developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; |
| 12 | compatible = "mediatek,mt7988a-dsa-10g-spim-snand", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0 0x40000000 0 0x10000000>; |
| 24 | }; |
| 25 | |
| 26 | nmbm_spim_nand { |
| 27 | compatible = "generic,nmbm"; |
| 28 | |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | |
| 32 | lower-mtd-device = <&spi_nand>; |
| 33 | forced-create; |
| 34 | |
| 35 | partitions { |
| 36 | compatible = "fixed-partitions"; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | |
| 40 | partition@0 { |
| 41 | label = "BL2"; |
| 42 | reg = <0x00000 0x0100000>; |
| 43 | read-only; |
| 44 | }; |
| 45 | |
| 46 | partition@100000 { |
| 47 | label = "u-boot-env"; |
| 48 | reg = <0x0100000 0x0080000>; |
| 49 | }; |
| 50 | |
| 51 | factory: partition@180000 { |
| 52 | label = "Factory"; |
| 53 | reg = <0x180000 0x0400000>; |
| 54 | }; |
| 55 | |
| 56 | partition@580000 { |
| 57 | label = "FIP"; |
| 58 | reg = <0x580000 0x0200000>; |
| 59 | }; |
| 60 | |
| 61 | partition@780000 { |
| 62 | label = "ubi"; |
developer | 22ccfc5 | 2022-11-22 13:46:27 +0800 | [diff] [blame] | 63 | reg = <0x780000 0x7880000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 64 | }; |
| 65 | }; |
| 66 | }; |
| 67 | |
| 68 | wsys_adie: wsys_adie@0 { |
| 69 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 70 | compatible = "mediatek,rebb-mt7988-adie"; |
| 71 | adie_id = <7976>; |
| 72 | sku_type = <3000>; |
| 73 | }; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 74 | |
| 75 | sound_wm8960 { |
| 76 | compatible = "mediatek,mt79xx-wm8960-machine"; |
| 77 | mediatek,platform = <&afe>; |
| 78 | audio-routing = "Headphone", "HP_L", |
| 79 | "Headphone", "HP_R", |
| 80 | "LINPUT1", "AMIC", |
| 81 | "RINPUT1", "AMIC"; |
| 82 | mediatek,audio-codec = <&wm8960>; |
| 83 | status = "disabled"; |
| 84 | }; |
| 85 | |
| 86 | sound_si3218x { |
| 87 | compatible = "mediatek,mt79xx-si3218x-machine"; |
| 88 | mediatek,platform = <&afe>; |
| 89 | mediatek,ext-codec = <&proslic_spi>; |
| 90 | status = "disabled"; |
| 91 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | &fan { |
| 95 | pwms = <&pwm 0 50000 0>; |
| 96 | status = "okay"; |
| 97 | }; |
| 98 | |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 99 | &afe { |
| 100 | pinctrl-names = "default"; |
| 101 | pinctrl-0 = <&pcm_pins>; |
| 102 | status = "okay"; |
| 103 | }; |
| 104 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 105 | &pwm { |
| 106 | status = "okay"; |
| 107 | }; |
| 108 | |
| 109 | &uart0 { |
| 110 | status = "okay"; |
| 111 | }; |
| 112 | |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 113 | &i2c1 { |
| 114 | pinctrl-names = "default"; |
| 115 | pinctrl-0 = <&i2c1_pins>; |
| 116 | status = "okay"; |
| 117 | |
| 118 | wm8960: wm8960@1a { |
| 119 | compatible = "wlf,wm8960"; |
| 120 | reg = <0x1a>; |
| 121 | }; |
| 122 | }; |
| 123 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 124 | &spi0 { |
| 125 | pinctrl-names = "default"; |
| 126 | pinctrl-0 = <&spi0_flash_pins>; |
| 127 | status = "okay"; |
| 128 | |
| 129 | spi_nand: spi_nand@0 { |
| 130 | #address-cells = <1>; |
| 131 | #size-cells = <1>; |
| 132 | compatible = "spi-nand"; |
| 133 | spi-cal-enable; |
| 134 | spi-cal-mode = "read-data"; |
| 135 | spi-cal-datalen = <7>; |
| 136 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 137 | spi-cal-addrlen = <5>; |
| 138 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 139 | reg = <0>; |
| 140 | spi-max-frequency = <52000000>; |
| 141 | spi-tx-buswidth = <4>; |
| 142 | spi-rx-buswidth = <4>; |
| 143 | }; |
| 144 | }; |
| 145 | |
| 146 | &spi1 { |
| 147 | pinctrl-names = "default"; |
| 148 | /* pin shared with snfi */ |
| 149 | pinctrl-0 = <&spic_pins>; |
| 150 | status = "disabled"; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 151 | |
| 152 | proslic_spi: proslic_spi@0 { |
| 153 | compatible = "silabs,proslic_spi"; |
| 154 | reg = <0>; |
| 155 | spi-max-frequency = <10000000>; |
| 156 | spi-cpha = <1>; |
| 157 | spi-cpol = <1>; |
| 158 | channel_count = <1>; |
| 159 | debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ |
| 160 | reset_gpio = <&pio 54 0>; |
| 161 | ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ |
| 162 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 163 | }; |
| 164 | |
| 165 | &pcie0 { |
| 166 | pinctrl-names = "default"; |
| 167 | pinctrl-0 = <&pcie0_pins>; |
| 168 | status = "okay"; |
| 169 | }; |
| 170 | |
| 171 | &pcie1 { |
| 172 | pinctrl-names = "default"; |
| 173 | pinctrl-0 = <&pcie1_pins>; |
| 174 | status = "okay"; |
| 175 | }; |
| 176 | |
| 177 | &pcie2 { |
| 178 | pinctrl-names = "default"; |
| 179 | pinctrl-0 = <&pcie2_pins>; |
| 180 | status = "disabled"; |
| 181 | }; |
| 182 | |
| 183 | &pcie3 { |
| 184 | pinctrl-names = "default"; |
| 185 | pinctrl-0 = <&pcie3_pins>; |
| 186 | status = "okay"; |
| 187 | }; |
| 188 | |
| 189 | &pio { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 190 | mdio0_pins: mdio0-pins { |
| 191 | mux { |
| 192 | function = "mdio"; |
| 193 | groups = "mdc_mdio0"; |
| 194 | }; |
| 195 | |
| 196 | conf { |
| 197 | groups = "mdc_mdio0"; |
| 198 | drive-strength = <MTK_DRIVE_8mA>; |
| 199 | }; |
| 200 | }; |
| 201 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 202 | pcie0_pins: pcie0-pins { |
| 203 | mux { |
| 204 | function = "pcie"; |
| 205 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 206 | "pcie_wake_n0_0"; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | pcie1_pins: pcie1-pins { |
| 211 | mux { |
| 212 | function = "pcie"; |
| 213 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 214 | "pcie_wake_n1_0"; |
| 215 | }; |
| 216 | }; |
| 217 | |
| 218 | pcie2_pins: pcie2-pins { |
| 219 | mux { |
| 220 | function = "pcie"; |
| 221 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 222 | "pcie_wake_n2_0"; |
| 223 | }; |
| 224 | }; |
| 225 | |
| 226 | pcie3_pins: pcie3-pins { |
| 227 | mux { |
| 228 | function = "pcie"; |
| 229 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 230 | "pcie_wake_n3_0"; |
| 231 | }; |
| 232 | }; |
| 233 | |
| 234 | spi0_flash_pins: spi0-pins { |
| 235 | mux { |
| 236 | function = "spi"; |
| 237 | groups = "spi0", "spi0_wp_hold"; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | spic_pins: spi1-pins { |
| 242 | mux { |
| 243 | function = "spi"; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 244 | groups = "spi1"; |
| 245 | }; |
| 246 | }; |
| 247 | |
| 248 | i2c1_pins: i2c1-pins { |
| 249 | mux { |
| 250 | function = "i2c"; |
| 251 | groups = "i2c1_0"; |
| 252 | }; |
| 253 | }; |
| 254 | |
| 255 | i2s_pins: i2s-pins { |
| 256 | mux { |
| 257 | function = "audio"; |
| 258 | groups = "i2s"; |
| 259 | }; |
| 260 | }; |
| 261 | |
| 262 | pcm_pins: pcm-pins { |
| 263 | mux { |
| 264 | function = "audio"; |
| 265 | groups = "pcm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 266 | }; |
| 267 | }; |
| 268 | }; |
| 269 | |
| 270 | &watchdog { |
| 271 | status = "disabled"; |
| 272 | }; |
| 273 | |
| 274 | ð { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 275 | pinctrl-names = "default"; |
| 276 | pinctrl-0 = <&mdio0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 277 | status = "okay"; |
| 278 | |
| 279 | gmac0: mac@0 { |
| 280 | compatible = "mediatek,eth-mac"; |
| 281 | reg = <0>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 282 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 283 | phy-mode = "10gbase-kr"; |
| 284 | |
| 285 | fixed-link { |
| 286 | speed = <2500>; |
| 287 | full-duplex; |
| 288 | pause; |
| 289 | }; |
| 290 | }; |
| 291 | |
| 292 | gmac1: mac@1 { |
| 293 | compatible = "mediatek,eth-mac"; |
| 294 | reg = <1>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 295 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 296 | phy-mode = "10gbase-kr"; |
| 297 | phy-handle = <&phy0>; |
| 298 | }; |
| 299 | |
| 300 | gmac2: mac@2 { |
| 301 | compatible = "mediatek,eth-mac"; |
| 302 | reg = <2>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 303 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 304 | phy-mode = "10gbase-kr"; |
| 305 | phy-handle = <&phy1>; |
| 306 | }; |
| 307 | |
| 308 | mdio: mdio-bus { |
| 309 | #address-cells = <1>; |
| 310 | #size-cells = <0>; |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 311 | mdc-max-frequency = <10500000>; |
| 312 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 313 | phy0: ethernet-phy@0 { |
| 314 | reg = <0>; |
| 315 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 316 | reset-gpios = <&pio 72 1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 317 | reset-assert-us = <1000000>; |
| 318 | reset-deassert-us = <1000000>; |
| 319 | }; |
| 320 | |
| 321 | phy1: ethernet-phy@8 { |
| 322 | reg = <8>; |
| 323 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 324 | reset-gpios = <&pio 71 1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 325 | reset-assert-us = <1000000>; |
| 326 | reset-deassert-us = <1000000>; |
| 327 | }; |
| 328 | |
| 329 | switch@0 { |
| 330 | compatible = "mediatek,mt7988"; |
| 331 | reg = <31>; |
| 332 | ports { |
| 333 | #address-cells = <1>; |
| 334 | #size-cells = <0>; |
| 335 | |
| 336 | port@0 { |
| 337 | reg = <0>; |
| 338 | label = "lan0"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 339 | phy-mode = "gmii"; |
| 340 | phy-handle = <&sphy0>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | port@1 { |
| 344 | reg = <1>; |
| 345 | label = "lan1"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 346 | phy-mode = "gmii"; |
| 347 | phy-handle = <&sphy1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | port@2 { |
| 351 | reg = <2>; |
| 352 | label = "lan2"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 353 | phy-mode = "gmii"; |
| 354 | phy-handle = <&sphy2>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 355 | }; |
| 356 | |
| 357 | port@3 { |
| 358 | reg = <3>; |
| 359 | label = "lan3"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 360 | phy-mode = "gmii"; |
| 361 | phy-handle = <&sphy3>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | port@6 { |
| 365 | reg = <6>; |
| 366 | label = "cpu"; |
| 367 | ethernet = <&gmac0>; |
| 368 | phy-mode = "10gbase-kr"; |
| 369 | |
| 370 | fixed-link { |
| 371 | speed = <10000>; |
| 372 | full-duplex; |
| 373 | pause; |
| 374 | }; |
| 375 | }; |
| 376 | }; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 377 | |
| 378 | mdio { |
| 379 | compatible = "mediatek,dsa-slave-mdio"; |
| 380 | #address-cells = <1>; |
| 381 | #size-cells = <0>; |
| 382 | |
| 383 | sphy0: switch_phy0@0 { |
| 384 | compatible = "ethernet-phy-id03a2.9481"; |
| 385 | reg = <0>; |
| 386 | phy-mode = "gmii"; |
| 387 | rext = "efuse"; |
| 388 | tx_r50 = "efuse"; |
| 389 | nvmem-cells = <&phy_calibration_p0>; |
| 390 | nvmem-cell-names = "phy-cal-data"; |
| 391 | }; |
| 392 | |
| 393 | sphy1: switch_phy1@1 { |
| 394 | compatible = "ethernet-phy-id03a2.9481"; |
| 395 | reg = <1>; |
| 396 | phy-mode = "gmii"; |
| 397 | rext = "efuse"; |
| 398 | tx_r50 = "efuse"; |
| 399 | nvmem-cells = <&phy_calibration_p1>; |
| 400 | nvmem-cell-names = "phy-cal-data"; |
| 401 | }; |
| 402 | |
| 403 | sphy2: switch_phy2@2 { |
| 404 | compatible = "ethernet-phy-id03a2.9481"; |
| 405 | reg = <2>; |
| 406 | phy-mode = "gmii"; |
| 407 | rext = "efuse"; |
| 408 | tx_r50 = "efuse"; |
| 409 | nvmem-cells = <&phy_calibration_p2>; |
| 410 | nvmem-cell-names = "phy-cal-data"; |
| 411 | }; |
| 412 | |
| 413 | sphy3: switch_phy3@3 { |
| 414 | compatible = "ethernet-phy-id03a2.9481"; |
| 415 | reg = <3>; |
| 416 | phy-mode = "gmii"; |
| 417 | rext = "efuse"; |
| 418 | tx_r50 = "efuse"; |
| 419 | nvmem-cells = <&phy_calibration_p3>; |
| 420 | nvmem-cell-names = "phy-cal-data"; |
| 421 | }; |
| 422 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 423 | }; |
| 424 | }; |
| 425 | }; |
| 426 | |
| 427 | &hnat { |
| 428 | mtketh-wan = "eth1"; |
| 429 | mtketh-lan = "lan"; |
| 430 | mtketh-lan2 = "eth2"; |
| 431 | mtketh-max-gmac = <3>; |
| 432 | status = "okay"; |
| 433 | }; |