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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / d34018d9d2007438551c6792d3003b4b5c15dd80 / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / package / kernel / mt76 / patches / 1000-wifi-mt76-mt7996-add-debug-tool.patch
blob: d29a90b93bb59c926813f582ec50776b212db1d8 [file] [log] [blame]
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]1From 393f2e0f06e9a6ead8ffd64c904b6e24ff6c92f1 Mon Sep 17 00:00:00 2001
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Fri, 24 Mar 2023 14:02:32 +0800
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]4Subject: [PATCH 33/98] wifi: mt76: mt7996: add debug tool
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]5
6Change-Id: Ie10390b01f17db893dbfbf3221bf63a4bd1fe38f
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]7Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]8---
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]9 mt7996/Makefile | 4 +
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]10 mt7996/coredump.c | 10 +-
11 mt7996/coredump.h | 7 +
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]12 mt7996/debugfs.c | 34 +-
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]13 mt7996/mt7996.h | 10 +
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]14 mt7996/mtk_debug.h | 2147 ++++++++++++++++++++++++++++++++++++++
15 mt7996/mtk_debugfs.c | 2379 ++++++++++++++++++++++++++++++++++++++++++
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]16 mt7996/mtk_mcu.c | 18 +
17 mt7996/mtk_mcu.h | 16 +
18 tools/fwlog.c | 25 +-
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]19 10 files changed, 4630 insertions(+), 20 deletions(-)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]20 create mode 100644 mt7996/mtk_debug.h
21 create mode 100644 mt7996/mtk_debugfs.c
22 create mode 100644 mt7996/mtk_mcu.c
23 create mode 100644 mt7996/mtk_mcu.h
24
25diff --git a/mt7996/Makefile b/mt7996/Makefile
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]26index 07c8b55..a056b40 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]27--- a/mt7996/Makefile
28+++ b/mt7996/Makefile
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]29@@ -1,4 +1,6 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]30 # SPDX-License-Identifier: ISC
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]31+EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]32+EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
33
34 obj-$(CONFIG_MT7996E) += mt7996e.o
35
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]36@@ -6,3 +8,5 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
37 debugfs.o mmio.o
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]38
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]39 mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]40+
41+mt7996e-y += mtk_debugfs.o mtk_mcu.o
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]42diff --git a/mt7996/coredump.c b/mt7996/coredump.c
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]43index 60b8808..a7f91b5 100644
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]44--- a/mt7996/coredump.c
45+++ b/mt7996/coredump.c
46@@ -195,7 +195,7 @@ mt7996_coredump_fw_stack(struct mt7996_dev *dev, u8 type, struct mt7996_coredump
47 }
48 }
49
50-static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type)
51+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
52 {
53 struct mt7996_crash_data *crash_data = dev->coredump.crash_data[type];
54 struct mt7996_coredump *dump;
55@@ -206,7 +206,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
56
57 len = hdr_len;
58
59- if (coredump_memdump && crash_data->memdump_buf_len)
60+ if (full_dump && coredump_memdump && crash_data->memdump_buf_len)
61 len += sizeof(*dump_mem) + crash_data->memdump_buf_len;
62
63 sofar += hdr_len;
64@@ -248,6 +248,9 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
65 mt7996_coredump_fw_state(dev, type, dump, &exception);
66 mt7996_coredump_fw_stack(dev, type, dump, exception);
67
68+ if (!full_dump)
69+ goto skip_dump_mem;
70+
71 /* gather memory content */
72 dump_mem = (struct mt7996_coredump_mem *)(buf + sofar);
73 dump_mem->len = crash_data->memdump_buf_len;
74@@ -255,6 +258,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
75 memcpy(dump_mem->data, crash_data->memdump_buf,
76 crash_data->memdump_buf_len);
77
78+skip_dump_mem:
79 mutex_unlock(&dev->dump_mutex);
80
81 return dump;
82@@ -264,7 +268,7 @@ int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
83 {
84 struct mt7996_coredump *dump;
85
86- dump = mt7996_coredump_build(dev, type);
87+ dump = mt7996_coredump_build(dev, type, true);
88 if (!dump) {
89 dev_warn(dev->mt76.dev, "no crash dump data found\n");
90 return -ENODATA;
91diff --git a/mt7996/coredump.h b/mt7996/coredump.h
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]92index 01ed373..93cd84a 100644
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]93--- a/mt7996/coredump.h
94+++ b/mt7996/coredump.h
95@@ -75,6 +75,7 @@ struct mt7996_mem_region {
96 const struct mt7996_mem_region *
97 mt7996_coredump_get_mem_layout(struct mt7996_dev *dev, u8 type, u32 *num);
98 struct mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type);
99+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump);
100 int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type);
101 int mt7996_coredump_register(struct mt7996_dev *dev);
102 void mt7996_coredump_unregister(struct mt7996_dev *dev);
103@@ -92,6 +93,12 @@ static inline int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
104 return 0;
105 }
106
107+static inline struct
108+mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
109+{
110+ return NULL;
111+}
112+
113 static inline struct
114 mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type)
115 {
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]116diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]117index 9bd9535..92aa164 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]118--- a/mt7996/debugfs.c
119+++ b/mt7996/debugfs.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]120@@ -290,11 +290,20 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
121 DEBUG_SPL,
122 DEBUG_RPT_RX,
123 DEBUG_RPT_RA = 68,
124+ DEBUG_IDS_PP = 93,
125+ DEBUG_IDS_RA = 94,
126+ DEBUG_IDS_BF = 95,
127+ DEBUG_IDS_SR = 96,
128+ DEBUG_IDS_RU = 97,
129+ DEBUG_IDS_MUMIMO = 98,
130 } debug;
131 bool tx, rx, en;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]132 int ret;
133
134 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
135+#ifdef CONFIG_MTK_DEBUG
136+ dev->fw_debug_wm = val;
137+#endif
138
139 if (dev->fw_debug_bin)
140 val = MCU_FW_LOG_RELAY;
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]141@@ -309,8 +318,8 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
142 if (ret)
143 return ret;
144
145- for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) {
146- if (debug == 67)
147+ for (debug = DEBUG_TXCMD; debug <= DEBUG_IDS_MUMIMO; debug++) {
148+ if (debug == 67 || (debug > DEBUG_RPT_RA && debug < DEBUG_IDS_PP))
149 continue;
150
151 if (debug == DEBUG_RPT_RX)
152@@ -401,11 +410,12 @@ mt7996_fw_debug_bin_set(void *data, u64 val)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]153 };
154 struct mt7996_dev *dev = data;
155
156- if (!dev->relay_fwlog)
157+ if (!dev->relay_fwlog) {
158 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
159 1500, 512, &relay_cb, NULL);
160- if (!dev->relay_fwlog)
161- return -ENOMEM;
162+ if (!dev->relay_fwlog)
163+ return -ENOMEM;
164+ }
165
166 dev->fw_debug_bin = val;
167
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]168@@ -819,6 +829,11 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]169 if (phy == &dev->phy)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]170 dev->debugfs_dir = dir;
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]171
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]172+#ifdef CONFIG_MTK_DEBUG
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]173+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
174+ mt7996_mtk_init_debugfs(phy, dir);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]175+#endif
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]176+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]177 return 0;
178 }
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]179
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]180@@ -831,6 +846,12 @@ mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]181 void *dest;
182
183 spin_lock_irqsave(&lock, flags);
184+
185+ if (!dev->relay_fwlog) {
186+ spin_unlock_irqrestore(&lock, flags);
187+ return;
188+ }
189+
190 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
191 if (dest) {
192 *(u32 *)dest = hdrlen + len;
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]193@@ -863,9 +884,6 @@ void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]194 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
195 };
196
197- if (!dev->relay_fwlog)
198- return;
199-
200 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);
201 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
202 hdr.len = *(__le16 *)data;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]203diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]204index c4d74a0..8801956 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]205--- a/mt7996/mt7996.h
206+++ b/mt7996/mt7996.h
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]207@@ -317,6 +317,16 @@ struct mt7996_dev {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]208 spinlock_t reg_lock;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]209
210 u8 wtbl_size_group;
211+
212+#ifdef CONFIG_MTK_DEBUG
213+ u16 wlan_idx;
214+ struct {
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]215+ u8 sku_disable;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]216+ u32 fw_dbg_module;
217+ u8 fw_dbg_lv;
218+ u32 bcn_total_cnt[__MT_MAX_BAND];
219+ } dbg;
220+#endif
221 };
222
223 enum {
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]224diff --git a/mt7996/mtk_debug.h b/mt7996/mtk_debug.h
225new file mode 100644
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]226index 0000000..368f0bc
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]227--- /dev/null
228+++ b/mt7996/mtk_debug.h
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]229@@ -0,0 +1,2147 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]230+#ifndef __MTK_DEBUG_H
231+#define __MTK_DEBUG_H
232+
233+#ifdef CONFIG_MTK_DEBUG
234+#define NO_SHIFT_DEFINE 0xFFFFFFFF
235+#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
236+
237+#define GET_FIELD(_field, _reg) \
238+ ({ \
239+ (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \
240+ })
241+
242+/* AGG */
243+#define BN0_WF_AGG_TOP_BASE 0x820e2000
244+#define BN1_WF_AGG_TOP_BASE 0x820f2000
245+#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000
246+
247+#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000
248+#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004
249+#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008
250+#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C
251+#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010
252+#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014
253+#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018
254+#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C
255+#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020
256+#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024
257+#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028
258+#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C
259+#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030
260+#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034
261+#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038
262+#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C
263+#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040
264+#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044
265+#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C
266+#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050
267+#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054
268+#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058
269+#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C
270+#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060
271+#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064
272+#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068
273+#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C
274+#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070
275+#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074
276+#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078
277+#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C
278+#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080
279+#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084
280+#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088
281+#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C
282+#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090
283+#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094
284+#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098
285+#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C
286+#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0
287+#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4
288+#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8
289+#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC
290+#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0
291+#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4
292+#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8
293+#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC
294+#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0
295+#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4
296+#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8
297+#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC
298+#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0
299+#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4
300+#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8
301+#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC
302+#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0
303+#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4
304+#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8
305+#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]306+#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108
307+#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C
308+#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110
309+#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114
310+#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118
311+#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]312+#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x128) // 2128
313+#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x12c) // 212C
314+#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x130) // 2130
315+#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x134) // 2134
316+#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x138) // 2138
317+#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + 0x13c) // 213C
318+#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x150) // 2150
319+#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x154) // 2154
320+#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x158) // 2158
321+#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x15c) // 215C
322+#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x160) // 2160
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]323+#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178
324+#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198
325+#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8
326+#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC
327+#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0
328+#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4
329+#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8
330+#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4
331+#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8
332+#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC
333+#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0
334+#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4
335+#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8
336+#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC
337+
338+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
339+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16]
340+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16
341+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
342+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0]
343+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0
344+
345+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
346+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16]
347+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16
348+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
349+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0]
350+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0
351+
352+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
353+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16]
354+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16
355+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
356+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0]
357+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0
358+
359+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
360+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16]
361+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16
362+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
363+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0]
364+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0
365+
366+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
367+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16]
368+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16
369+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
370+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0]
371+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0
372+
373+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
374+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16]
375+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16
376+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
377+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0]
378+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0
379+
380+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
381+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16]
382+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16
383+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
384+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0]
385+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0
386+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
387+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16]
388+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16
389+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
390+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0]
391+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0
392+
393+/* DMA */
394+struct queue_desc {
395+ u32 hw_desc_base;
396+ u16 ring_size;
397+ char *const ring_info;
398+};
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]399+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]400+// HOST DMA
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]401+#define WF_WFDMA_HOST_DMA0_BASE 0xd4000
402+
403+#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
404+ (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
405+#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
406+ (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
407+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
408+ (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
409+
410+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \
411+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
412+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \
413+ 0x00000008 /* RX_DMA_BUSY[3] */
414+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
415+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \
416+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
417+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \
418+ 0x00000004 /* RX_DMA_EN[2] */
419+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
420+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \
421+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
422+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \
423+ 0x00000002 /* TX_DMA_BUSY[1] */
424+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
425+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \
426+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
427+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \
428+ 0x00000001 /* TX_DMA_EN[0] */
429+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
430+
431+
432+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
433+ (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
434+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
435+ (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
436+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
437+ (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
438+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
439+ (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
440+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
441+ (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
442+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
443+ (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
444+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
445+ (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
446+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
447+ (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
448+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
449+ (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
450+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
451+ (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
452+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
453+ (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
454+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
455+ (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
456+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
457+ (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
458+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
459+ (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
460+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
461+ (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
462+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
463+ (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
464+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
465+ (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
466+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
467+ (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
468+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
469+ (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
470+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
471+ (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
472+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
473+ (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
474+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
475+ (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
476+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
477+ (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
478+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
479+ (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
480+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
481+ (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
482+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
483+ (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
484+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
485+ (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
486+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
487+ (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
488+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
489+ (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
490+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
491+ (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
492+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
493+ (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
494+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
495+ (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
496+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
497+ (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
498+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
499+ (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
500+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
501+ (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
502+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
503+ (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
504+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
505+ (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
506+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
507+ (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
508+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
509+ (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
510+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
511+ (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
512+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
513+ (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
514+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
515+ (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
516+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
517+ (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
518+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
519+ (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
520+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
521+ (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
522+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
523+ (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
524+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
525+ (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
526+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
527+ (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
528+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \
529+ (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */
530+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \
531+ (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */
532+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \
533+ (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */
534+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \
535+ (WF_WFDMA_HOST_DMA0_BASE + 0x45c) /* 445c */
536+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x460) // 4460
537+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x464) // 4464
538+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x468) // 4468
539+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x46c) // 446C
540+
541+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
542+ (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
543+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
544+ (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
545+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
546+ (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
547+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
548+ (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
549+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
550+ (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
551+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
552+ (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
553+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
554+ (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
555+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
556+ (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
557+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
558+ (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
559+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
560+ (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
561+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
562+ (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
563+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
564+ (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
565+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
566+ (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
567+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
568+ (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
569+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
570+ (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
571+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
572+ (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
573+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
574+ (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
575+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
576+ (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
577+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
578+ (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
579+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
580+ (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
581+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
582+ (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
583+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
584+ (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
585+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
586+ (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
587+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
588+ (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
589+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
590+ (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
591+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
592+ (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
593+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
594+ (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
595+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
596+ (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
597+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
598+ (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
599+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
600+ (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
601+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
602+ (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
603+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
604+ (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
605+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
606+ (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
607+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
608+ (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
609+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
610+ (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
611+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
612+ (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
613+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
614+ (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
615+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
616+ (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
617+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
618+ (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
619+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
620+ (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
621+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a0) // 45A0
622+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a4) // 45A4
623+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a8) // 45A8
624+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5ac) // 45AC
625+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b0) // 45B0
626+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b4) // 45B4
627+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b8) // 45B8
628+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5bc) // 45BC
629+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C0) // 45C0
630+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C4) // 45C4
631+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C8) // 45C8
632+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5CC) // 45CC
633+
634+// HOST PCIE1 DMA
635+#define WF_WFDMA_HOST_DMA0_PCIE1_BASE 0xd8000
636+
637+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x200) // 8200
638+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0X204) // 8204
639+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x208) // 8208
640+
641+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_PDMA_BT_SIZE_SHFT 4
642+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008
643+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
644+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004
645+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
646+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002
647+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
648+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001
649+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
650+
651+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x450) // 8450
652+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x454) // 8454
653+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x458) // 8458
654+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x45c) // 845C
655+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x460) // 8460
656+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x464) // 8464
657+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x468) // 8468
658+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x46c) // 846C
659+
660+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x530) // 8530
661+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x534) // 8534
662+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x538) // 8538
663+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x53C) // 853C
664+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x550) // 8550
665+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x554) // 8554
666+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x558) // 8558
667+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x55c) // 855C
668+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x560) // 8560
669+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x564) // 8564
670+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x568) // 8568
671+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x56c) // 856C
672+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x570) // 8570
673+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x574) // 8574
674+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x578) // 8578
675+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x57c) // 857C
676+//MCU DMA
677+//#define WF_WFDMA_MCU_DMA0_BASE 0x02000
678+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
679+
680+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
681+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
682+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
683+
684+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
685+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
686+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
687+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
688+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
689+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
690+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
691+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
692+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
693+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
694+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
695+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
696+
697+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
698+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304
699+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308
700+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C
701+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
702+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314
703+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318
704+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C
705+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
706+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324
707+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328
708+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C
709+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
710+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334
711+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338
712+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C
713+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
714+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344
715+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348
716+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C
717+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
718+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354
719+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358
720+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C
721+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
722+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364
723+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368
724+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C
725+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370
726+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374
727+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378
728+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C
729+
730+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
731+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504
732+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508
733+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C
734+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
735+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514
736+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518
737+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C
738+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
739+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524
740+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528
741+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C
742+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
743+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534
744+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538
745+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C
746+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
747+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544
748+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548
749+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C
750+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
751+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554
752+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558
753+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C
754+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
755+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564
756+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568
757+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C
758+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
759+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574
760+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578
761+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C
762+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
763+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584
764+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588
765+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C
766+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
767+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594
768+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598
769+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C
770+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0
771+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4
772+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8
773+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC
774+
775+// MEM DMA
776+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
777+
778+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
779+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
780+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
781+
782+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
783+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
784+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
785+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
786+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
787+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
788+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
789+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
790+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
791+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
792+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
793+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
794+
795+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
796+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304
797+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308
798+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C
799+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
800+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314
801+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318
802+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C
803+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320
804+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324
805+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328
806+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C
807+
808+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
809+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504
810+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508
811+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C
812+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
813+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514
814+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518
815+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C
816+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520
817+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524
818+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528
819+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C
820+
821+/* MIB */
822+#define WF_UMIB_TOP_BASE 0x820cd000
823+#define BN0_WF_MIB_TOP_BASE 0x820ed000
824+#define BN1_WF_MIB_TOP_BASE 0x820fd000
825+#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000
826+
827+#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x484) // D484
828+#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D4) // D4D4
829+#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x524) // D524
830+#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5E8) // D5E8
831+#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x74C) // D74C
832+
833+#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000
834+#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020
835+#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024
836+#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030
837+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
838+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x450) // D450
839+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x590) // D590
840+#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5A0) // D5A0
841+#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x720) // D720
842+
843+#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0
844+#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC
845+#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C0) // D6C0
846+#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C4) // D6C4
847+#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C8) // D6C8
848+#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D0) // D6D0
849+#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x6CC) // D6CC
850+
851+#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC
852+#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F0) // D6F0
853+#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F4) // D6F4
854+#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F8) // D6F8
855+#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6FC) // D6FC
856+
857+#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x728) // D728
858+#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x72C) // D72C
859+#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x730) // D730
860+#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x734) // D734
861+#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x738) // D738
862+
863+#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
864+#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0
865+#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600
866+#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610
867+#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620
868+#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x788) // D788
869+#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x798) // D798
870+
871+#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x7AC) // D7AC
872+#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4
873+#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0xA1C) // DA1C
874+
875+#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA64) // DA64
876+#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA68) // DA68
877+#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0xA6C) // DA6C
878+#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA70) // DA70
879+#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA74) // DA74
880+
881+#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x950) // D950
882+#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x954) // D954
883+#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x958) // D958
884+#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964
885+#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x96C) // D96C
886+#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x974) // D974
887+#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x978) // D978
888+
889+#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0]
890+#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0]
891+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
892+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
893+#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0]
894+#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0]
895+#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0]
896+#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0]
897+#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0]
898+#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0]
899+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
900+#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0]
901+#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0]
902+#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0]
903+#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0]
904+#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0]
905+#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0]
906+#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0]
907+#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0]
908+#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0]
909+#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0]
910+#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0]
911+#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0]
912+#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
913+#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0]
914+#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0]
915+#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0]
916+#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0]
917+#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0]
918+#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0]
919+#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0]
920+#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0
921+#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4
922+#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8
923+#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC
924+#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0
925+#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4
926+#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8
927+#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC
928+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]929+#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA24) // DA24
930+#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA28) // DA28
931+#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0xA2C) // DA2C
932+#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0xA30) // DA30
933+#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0xA34) // DA34
934+#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA38) // DA38
935+#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA3C) // DA3C
936+#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0xA40) // DA40
937+#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0xA44) // DA44
938+#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0xA48) // DA48
939+#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0xA4C) // DA4C
940+#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0xA50) // DA50
941+#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0xA54) // DA54
942+#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + 0xA58) // DA58
943+#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0xA5C) // DA5C
944+#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0xA60) // DA60
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]945+
946+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
947+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16]
948+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16
949+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
950+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0]
951+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0
952+
953+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
954+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16]
955+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16
956+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
957+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0]
958+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0
959+
960+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
961+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16]
962+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16
963+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
964+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0]
965+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0
966+
967+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
968+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16]
969+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16
970+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
971+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0]
972+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0
973+
974+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
975+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16]
976+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16
977+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
978+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0]
979+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0
980+
981+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
982+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16]
983+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16
984+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
985+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0]
986+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0
987+
988+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
989+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16]
990+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16
991+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
992+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0]
993+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0
994+
995+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR
996+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0]
997+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0
998+
999+/* RRO TOP */
1000+#define WF_RRO_TOP_BASE 0xA000 /*0x820C2000 */
1001+#define WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR (WF_RRO_TOP_BASE + 0x40) // 2040
1002+ //
1003+/* WTBL */
1004+enum mt7996_wtbl_type {
1005+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1006+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1007+ WTBL_TYPE_KEY, /* Key Table */
1008+ MAX_NUM_WTBL_TYPE
1009+};
1010+
1011+struct berse_wtbl_parse {
1012+ u8 *name;
1013+ u32 mask;
1014+ u32 shift;
1015+ u8 new_line;
1016+};
1017+
1018+enum muar_idx {
1019+ MUAR_INDEX_OWN_MAC_ADDR_0 = 0,
1020+ MUAR_INDEX_OWN_MAC_ADDR_1,
1021+ MUAR_INDEX_OWN_MAC_ADDR_2,
1022+ MUAR_INDEX_OWN_MAC_ADDR_3,
1023+ MUAR_INDEX_OWN_MAC_ADDR_4,
1024+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE,
1025+ MUAR_INDEX_UNMATCHED = 0xF,
1026+ MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11,
1027+ MUAR_INDEX_OWN_MAC_ADDR_12,
1028+ MUAR_INDEX_OWN_MAC_ADDR_13,
1029+ MUAR_INDEX_OWN_MAC_ADDR_14,
1030+ MUAR_INDEX_OWN_MAC_ADDR_15,
1031+ MUAR_INDEX_OWN_MAC_ADDR_16,
1032+ MUAR_INDEX_OWN_MAC_ADDR_17,
1033+ MUAR_INDEX_OWN_MAC_ADDR_18,
1034+ MUAR_INDEX_OWN_MAC_ADDR_19,
1035+ MUAR_INDEX_OWN_MAC_ADDR_1A,
1036+ MUAR_INDEX_OWN_MAC_ADDR_1B,
1037+ MUAR_INDEX_OWN_MAC_ADDR_1C,
1038+ MUAR_INDEX_OWN_MAC_ADDR_1D,
1039+ MUAR_INDEX_OWN_MAC_ADDR_1E,
1040+ MUAR_INDEX_OWN_MAC_ADDR_1F,
1041+ MUAR_INDEX_OWN_MAC_ADDR_20,
1042+ MUAR_INDEX_OWN_MAC_ADDR_21,
1043+ MUAR_INDEX_OWN_MAC_ADDR_22,
1044+ MUAR_INDEX_OWN_MAC_ADDR_23,
1045+ MUAR_INDEX_OWN_MAC_ADDR_24,
1046+ MUAR_INDEX_OWN_MAC_ADDR_25,
1047+ MUAR_INDEX_OWN_MAC_ADDR_26,
1048+ MUAR_INDEX_OWN_MAC_ADDR_27,
1049+ MUAR_INDEX_OWN_MAC_ADDR_28,
1050+ MUAR_INDEX_OWN_MAC_ADDR_29,
1051+ MUAR_INDEX_OWN_MAC_ADDR_2A,
1052+ MUAR_INDEX_OWN_MAC_ADDR_2B,
1053+ MUAR_INDEX_OWN_MAC_ADDR_2C,
1054+ MUAR_INDEX_OWN_MAC_ADDR_2D,
1055+ MUAR_INDEX_OWN_MAC_ADDR_2E,
1056+ MUAR_INDEX_OWN_MAC_ADDR_2F
1057+};
1058+
1059+enum cipher_suit {
1060+ IGTK_CIPHER_SUIT_NONE = 0,
1061+ IGTK_CIPHER_SUIT_BIP,
1062+ IGTK_CIPHER_SUIT_BIP_256
1063+};
1064+
1065+#define LWTBL_LEN_IN_DW 36
1066+#define UWTBL_LEN_IN_DW 10
1067+
1068+#define MT_DBG_WTBL_BASE 0x820D8000
1069+
1070+#define MT_DBG_WTBLON_TOP_BASE 0x820d4000
1071+#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370
1072+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
1073+
1074+#define MT_DBG_UWTBL_TOP_BASE 0x820c4000
1075+#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104
1076+#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0)
1077+#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31)
1078+
1079+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1080+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1081+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1082+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1083+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1084+
1085+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1086+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1087+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1088+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1089+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1090+
1091+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1092+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1093+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1094+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1095+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1096+
1097+// UMAC WTBL
1098+// DW0
1099+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0
1100+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0
1101+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0
1102+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0
1103+#define WF_UWTBL_OWN_MLD_ID_DW 0
1104+#define WF_UWTBL_OWN_MLD_ID_ADDR 0
1105+#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16
1106+#define WF_UWTBL_OWN_MLD_ID_SHIFT 16
1107+// DW1
1108+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1
1109+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4
1110+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0
1111+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0
1112+// DW2
1113+#define WF_UWTBL_PN_31_0__DW 2
1114+#define WF_UWTBL_PN_31_0__ADDR 8
1115+#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0
1116+#define WF_UWTBL_PN_31_0__SHIFT 0
1117+// DW3
1118+#define WF_UWTBL_PN_47_32__DW 3
1119+#define WF_UWTBL_PN_47_32__ADDR 12
1120+#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0
1121+#define WF_UWTBL_PN_47_32__SHIFT 0
1122+#define WF_UWTBL_COM_SN_DW 3
1123+#define WF_UWTBL_COM_SN_ADDR 12
1124+#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16
1125+#define WF_UWTBL_COM_SN_SHIFT 16
1126+// DW4
1127+#define WF_UWTBL_TID0_SN_DW 4
1128+#define WF_UWTBL_TID0_SN_ADDR 16
1129+#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0
1130+#define WF_UWTBL_TID0_SN_SHIFT 0
1131+#define WF_UWTBL_RX_BIPN_31_0__DW 4
1132+#define WF_UWTBL_RX_BIPN_31_0__ADDR 16
1133+#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0
1134+#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0
1135+#define WF_UWTBL_TID1_SN_DW 4
1136+#define WF_UWTBL_TID1_SN_ADDR 16
1137+#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12
1138+#define WF_UWTBL_TID1_SN_SHIFT 12
1139+#define WF_UWTBL_TID2_SN_7_0__DW 4
1140+#define WF_UWTBL_TID2_SN_7_0__ADDR 16
1141+#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24
1142+#define WF_UWTBL_TID2_SN_7_0__SHIFT 24
1143+// DW5
1144+#define WF_UWTBL_TID2_SN_11_8__DW 5
1145+#define WF_UWTBL_TID2_SN_11_8__ADDR 20
1146+#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0
1147+#define WF_UWTBL_TID2_SN_11_8__SHIFT 0
1148+#define WF_UWTBL_RX_BIPN_47_32__DW 5
1149+#define WF_UWTBL_RX_BIPN_47_32__ADDR 20
1150+#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0
1151+#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0
1152+#define WF_UWTBL_TID3_SN_DW 5
1153+#define WF_UWTBL_TID3_SN_ADDR 20
1154+#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4
1155+#define WF_UWTBL_TID3_SN_SHIFT 4
1156+#define WF_UWTBL_TID4_SN_DW 5
1157+#define WF_UWTBL_TID4_SN_ADDR 20
1158+#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16
1159+#define WF_UWTBL_TID4_SN_SHIFT 16
1160+#define WF_UWTBL_TID5_SN_3_0__DW 5
1161+#define WF_UWTBL_TID5_SN_3_0__ADDR 20
1162+#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28
1163+#define WF_UWTBL_TID5_SN_3_0__SHIFT 28
1164+// DW6
1165+#define WF_UWTBL_TID5_SN_11_4__DW 6
1166+#define WF_UWTBL_TID5_SN_11_4__ADDR 24
1167+#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0
1168+#define WF_UWTBL_TID5_SN_11_4__SHIFT 0
1169+#define WF_UWTBL_KEY_LOC2_DW 6
1170+#define WF_UWTBL_KEY_LOC2_ADDR 24
1171+#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0
1172+#define WF_UWTBL_KEY_LOC2_SHIFT 0
1173+#define WF_UWTBL_TID6_SN_DW 6
1174+#define WF_UWTBL_TID6_SN_ADDR 24
1175+#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8
1176+#define WF_UWTBL_TID6_SN_SHIFT 8
1177+#define WF_UWTBL_TID7_SN_DW 6
1178+#define WF_UWTBL_TID7_SN_ADDR 24
1179+#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20
1180+#define WF_UWTBL_TID7_SN_SHIFT 20
1181+// DW7
1182+#define WF_UWTBL_KEY_LOC0_DW 7
1183+#define WF_UWTBL_KEY_LOC0_ADDR 28
1184+#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0
1185+#define WF_UWTBL_KEY_LOC0_SHIFT 0
1186+#define WF_UWTBL_KEY_LOC1_DW 7
1187+#define WF_UWTBL_KEY_LOC1_ADDR 28
1188+#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16
1189+#define WF_UWTBL_KEY_LOC1_SHIFT 16
1190+// DW8
1191+#define WF_UWTBL_AMSDU_CFG_DW 8
1192+#define WF_UWTBL_AMSDU_CFG_ADDR 32
1193+#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0
1194+#define WF_UWTBL_AMSDU_CFG_SHIFT 0
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1195+#define WF_UWTBL_SEC_ADDR_MODE_DW 8
1196+#define WF_UWTBL_SEC_ADDR_MODE_ADDR 32
1197+#define WF_UWTBL_SEC_ADDR_MODE_MASK 0x00300000 // 21-20
1198+#define WF_UWTBL_SEC_ADDR_MODE_SHIFT 20
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1199+#define WF_UWTBL_WMM_Q_DW 8
1200+#define WF_UWTBL_WMM_Q_ADDR 32
1201+#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25
1202+#define WF_UWTBL_WMM_Q_SHIFT 25
1203+#define WF_UWTBL_QOS_DW 8
1204+#define WF_UWTBL_QOS_ADDR 32
1205+#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27
1206+#define WF_UWTBL_QOS_SHIFT 27
1207+#define WF_UWTBL_HT_DW 8
1208+#define WF_UWTBL_HT_ADDR 32
1209+#define WF_UWTBL_HT_MASK 0x10000000 // 28-28
1210+#define WF_UWTBL_HT_SHIFT 28
1211+#define WF_UWTBL_HDRT_MODE_DW 8
1212+#define WF_UWTBL_HDRT_MODE_ADDR 32
1213+#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29
1214+#define WF_UWTBL_HDRT_MODE_SHIFT 29
1215+// DW9
1216+#define WF_UWTBL_RELATED_IDX0_DW 9
1217+#define WF_UWTBL_RELATED_IDX0_ADDR 36
1218+#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0
1219+#define WF_UWTBL_RELATED_IDX0_SHIFT 0
1220+#define WF_UWTBL_RELATED_BAND0_DW 9
1221+#define WF_UWTBL_RELATED_BAND0_ADDR 36
1222+#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12
1223+#define WF_UWTBL_RELATED_BAND0_SHIFT 12
1224+#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9
1225+#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36
1226+#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14
1227+#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14
1228+#define WF_UWTBL_RELATED_IDX1_DW 9
1229+#define WF_UWTBL_RELATED_IDX1_ADDR 36
1230+#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16
1231+#define WF_UWTBL_RELATED_IDX1_SHIFT 16
1232+#define WF_UWTBL_RELATED_BAND1_DW 9
1233+#define WF_UWTBL_RELATED_BAND1_ADDR 36
1234+#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28
1235+#define WF_UWTBL_RELATED_BAND1_SHIFT 28
1236+#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9
1237+#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36
1238+#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30
1239+#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30
1240+
1241+/* LMAC WTBL */
1242+// DW0
1243+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0
1244+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0
1245+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \
1246+ 0x0000ffff // 15- 0
1247+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0
1248+#define WF_LWTBL_MUAR_DW 0
1249+#define WF_LWTBL_MUAR_ADDR 0
1250+#define WF_LWTBL_MUAR_MASK \
1251+ 0x003f0000 // 21-16
1252+#define WF_LWTBL_MUAR_SHIFT 16
1253+#define WF_LWTBL_RCA1_DW 0
1254+#define WF_LWTBL_RCA1_ADDR 0
1255+#define WF_LWTBL_RCA1_MASK \
1256+ 0x00400000 // 22-22
1257+#define WF_LWTBL_RCA1_SHIFT 22
1258+#define WF_LWTBL_KID_DW 0
1259+#define WF_LWTBL_KID_ADDR 0
1260+#define WF_LWTBL_KID_MASK \
1261+ 0x01800000 // 24-23
1262+#define WF_LWTBL_KID_SHIFT 23
1263+#define WF_LWTBL_RCID_DW 0
1264+#define WF_LWTBL_RCID_ADDR 0
1265+#define WF_LWTBL_RCID_MASK \
1266+ 0x02000000 // 25-25
1267+#define WF_LWTBL_RCID_SHIFT 25
1268+#define WF_LWTBL_BAND_DW 0
1269+#define WF_LWTBL_BAND_ADDR 0
1270+#define WF_LWTBL_BAND_MASK \
1271+ 0x0c000000 // 27-26
1272+#define WF_LWTBL_BAND_SHIFT 26
1273+#define WF_LWTBL_RV_DW 0
1274+#define WF_LWTBL_RV_ADDR 0
1275+#define WF_LWTBL_RV_MASK \
1276+ 0x10000000 // 28-28
1277+#define WF_LWTBL_RV_SHIFT 28
1278+#define WF_LWTBL_RCA2_DW 0
1279+#define WF_LWTBL_RCA2_ADDR 0
1280+#define WF_LWTBL_RCA2_MASK \
1281+ 0x20000000 // 29-29
1282+#define WF_LWTBL_RCA2_SHIFT 29
1283+#define WF_LWTBL_WPI_FLAG_DW 0
1284+#define WF_LWTBL_WPI_FLAG_ADDR 0
1285+#define WF_LWTBL_WPI_FLAG_MASK \
1286+ 0x40000000 // 30-30
1287+#define WF_LWTBL_WPI_FLAG_SHIFT 30
1288+// DW1
1289+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1
1290+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4
1291+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \
1292+ 0xffffffff // 31- 0
1293+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0
1294+// DW2
1295+#define WF_LWTBL_AID_DW 2
1296+#define WF_LWTBL_AID_ADDR 8
1297+#define WF_LWTBL_AID_MASK \
1298+ 0x00000fff // 11- 0
1299+#define WF_LWTBL_AID_SHIFT 0
1300+#define WF_LWTBL_GID_SU_DW 2
1301+#define WF_LWTBL_GID_SU_ADDR 8
1302+#define WF_LWTBL_GID_SU_MASK \
1303+ 0x00001000 // 12-12
1304+#define WF_LWTBL_GID_SU_SHIFT 12
1305+#define WF_LWTBL_SPP_EN_DW 2
1306+#define WF_LWTBL_SPP_EN_ADDR 8
1307+#define WF_LWTBL_SPP_EN_MASK \
1308+ 0x00002000 // 13-13
1309+#define WF_LWTBL_SPP_EN_SHIFT 13
1310+#define WF_LWTBL_WPI_EVEN_DW 2
1311+#define WF_LWTBL_WPI_EVEN_ADDR 8
1312+#define WF_LWTBL_WPI_EVEN_MASK \
1313+ 0x00004000 // 14-14
1314+#define WF_LWTBL_WPI_EVEN_SHIFT 14
1315+#define WF_LWTBL_AAD_OM_DW 2
1316+#define WF_LWTBL_AAD_OM_ADDR 8
1317+#define WF_LWTBL_AAD_OM_MASK \
1318+ 0x00008000 // 15-15
1319+#define WF_LWTBL_AAD_OM_SHIFT 15
1320+#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2
1321+#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8
1322+#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \
1323+ 0x001f0000 // 20-16
1324+#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16
1325+#define WF_LWTBL_FD_DW 2
1326+#define WF_LWTBL_FD_ADDR 8
1327+#define WF_LWTBL_FD_MASK \
1328+ 0x00200000 // 21-21
1329+#define WF_LWTBL_FD_SHIFT 21
1330+#define WF_LWTBL_TD_DW 2
1331+#define WF_LWTBL_TD_ADDR 8
1332+#define WF_LWTBL_TD_MASK \
1333+ 0x00400000 // 22-22
1334+#define WF_LWTBL_TD_SHIFT 22
1335+#define WF_LWTBL_SW_DW 2
1336+#define WF_LWTBL_SW_ADDR 8
1337+#define WF_LWTBL_SW_MASK \
1338+ 0x00800000 // 23-23
1339+#define WF_LWTBL_SW_SHIFT 23
1340+#define WF_LWTBL_UL_DW 2
1341+#define WF_LWTBL_UL_ADDR 8
1342+#define WF_LWTBL_UL_MASK \
1343+ 0x01000000 // 24-24
1344+#define WF_LWTBL_UL_SHIFT 24
1345+#define WF_LWTBL_TX_PS_DW 2
1346+#define WF_LWTBL_TX_PS_ADDR 8
1347+#define WF_LWTBL_TX_PS_MASK \
1348+ 0x02000000 // 25-25
1349+#define WF_LWTBL_TX_PS_SHIFT 25
1350+#define WF_LWTBL_QOS_DW 2
1351+#define WF_LWTBL_QOS_ADDR 8
1352+#define WF_LWTBL_QOS_MASK \
1353+ 0x04000000 // 26-26
1354+#define WF_LWTBL_QOS_SHIFT 26
1355+#define WF_LWTBL_HT_DW 2
1356+#define WF_LWTBL_HT_ADDR 8
1357+#define WF_LWTBL_HT_MASK \
1358+ 0x08000000 // 27-27
1359+#define WF_LWTBL_HT_SHIFT 27
1360+#define WF_LWTBL_VHT_DW 2
1361+#define WF_LWTBL_VHT_ADDR 8
1362+#define WF_LWTBL_VHT_MASK \
1363+ 0x10000000 // 28-28
1364+#define WF_LWTBL_VHT_SHIFT 28
1365+#define WF_LWTBL_HE_DW 2
1366+#define WF_LWTBL_HE_ADDR 8
1367+#define WF_LWTBL_HE_MASK \
1368+ 0x20000000 // 29-29
1369+#define WF_LWTBL_HE_SHIFT 29
1370+#define WF_LWTBL_EHT_DW 2
1371+#define WF_LWTBL_EHT_ADDR 8
1372+#define WF_LWTBL_EHT_MASK \
1373+ 0x40000000 // 30-30
1374+#define WF_LWTBL_EHT_SHIFT 30
1375+#define WF_LWTBL_MESH_DW 2
1376+#define WF_LWTBL_MESH_ADDR 8
1377+#define WF_LWTBL_MESH_MASK \
1378+ 0x80000000 // 31-31
1379+#define WF_LWTBL_MESH_SHIFT 31
1380+// DW3
1381+#define WF_LWTBL_WMM_Q_DW 3
1382+#define WF_LWTBL_WMM_Q_ADDR 12
1383+#define WF_LWTBL_WMM_Q_MASK \
1384+ 0x00000003 // 1- 0
1385+#define WF_LWTBL_WMM_Q_SHIFT 0
1386+#define WF_LWTBL_EHT_SIG_MCS_DW 3
1387+#define WF_LWTBL_EHT_SIG_MCS_ADDR 12
1388+#define WF_LWTBL_EHT_SIG_MCS_MASK \
1389+ 0x0000000c // 3- 2
1390+#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2
1391+#define WF_LWTBL_HDRT_MODE_DW 3
1392+#define WF_LWTBL_HDRT_MODE_ADDR 12
1393+#define WF_LWTBL_HDRT_MODE_MASK \
1394+ 0x00000010 // 4- 4
1395+#define WF_LWTBL_HDRT_MODE_SHIFT 4
1396+#define WF_LWTBL_BEAM_CHG_DW 3
1397+#define WF_LWTBL_BEAM_CHG_ADDR 12
1398+#define WF_LWTBL_BEAM_CHG_MASK \
1399+ 0x00000020 // 5- 5
1400+#define WF_LWTBL_BEAM_CHG_SHIFT 5
1401+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3
1402+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12
1403+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \
1404+ 0x000000c0 // 7- 6
1405+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6
1406+#define WF_LWTBL_PFMU_IDX_DW 3
1407+#define WF_LWTBL_PFMU_IDX_ADDR 12
1408+#define WF_LWTBL_PFMU_IDX_MASK \
1409+ 0x0000ff00 // 15- 8
1410+#define WF_LWTBL_PFMU_IDX_SHIFT 8
1411+#define WF_LWTBL_ULPF_IDX_DW 3
1412+#define WF_LWTBL_ULPF_IDX_ADDR 12
1413+#define WF_LWTBL_ULPF_IDX_MASK \
1414+ 0x00ff0000 // 23-16
1415+#define WF_LWTBL_ULPF_IDX_SHIFT 16
1416+#define WF_LWTBL_RIBF_DW 3
1417+#define WF_LWTBL_RIBF_ADDR 12
1418+#define WF_LWTBL_RIBF_MASK \
1419+ 0x01000000 // 24-24
1420+#define WF_LWTBL_RIBF_SHIFT 24
1421+#define WF_LWTBL_ULPF_DW 3
1422+#define WF_LWTBL_ULPF_ADDR 12
1423+#define WF_LWTBL_ULPF_MASK \
1424+ 0x02000000 // 25-25
1425+#define WF_LWTBL_ULPF_SHIFT 25
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1426+#define WF_LWTBL_BYPASS_TXSMM_DW 3
1427+#define WF_LWTBL_BYPASS_TXSMM_ADDR 12
1428+#define WF_LWTBL_BYPASS_TXSMM_MASK \
1429+ 0x04000000 // 26-26
1430+#define WF_LWTBL_BYPASS_TXSMM_SHIFT 26
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1431+#define WF_LWTBL_TBF_HT_DW 3
1432+#define WF_LWTBL_TBF_HT_ADDR 12
1433+#define WF_LWTBL_TBF_HT_MASK \
1434+ 0x08000000 // 27-27
1435+#define WF_LWTBL_TBF_HT_SHIFT 27
1436+#define WF_LWTBL_TBF_VHT_DW 3
1437+#define WF_LWTBL_TBF_VHT_ADDR 12
1438+#define WF_LWTBL_TBF_VHT_MASK \
1439+ 0x10000000 // 28-28
1440+#define WF_LWTBL_TBF_VHT_SHIFT 28
1441+#define WF_LWTBL_TBF_HE_DW 3
1442+#define WF_LWTBL_TBF_HE_ADDR 12
1443+#define WF_LWTBL_TBF_HE_MASK \
1444+ 0x20000000 // 29-29
1445+#define WF_LWTBL_TBF_HE_SHIFT 29
1446+#define WF_LWTBL_TBF_EHT_DW 3
1447+#define WF_LWTBL_TBF_EHT_ADDR 12
1448+#define WF_LWTBL_TBF_EHT_MASK \
1449+ 0x40000000 // 30-30
1450+#define WF_LWTBL_TBF_EHT_SHIFT 30
1451+#define WF_LWTBL_IGN_FBK_DW 3
1452+#define WF_LWTBL_IGN_FBK_ADDR 12
1453+#define WF_LWTBL_IGN_FBK_MASK \
1454+ 0x80000000 // 31-31
1455+#define WF_LWTBL_IGN_FBK_SHIFT 31
1456+// DW4
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1457+#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 4
1458+#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 16
1459+#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1460+ 0x00000007 // 2- 0
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1461+#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0
1462+#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 4
1463+#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 16
1464+#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1465+ 0x00000038 // 5- 3
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1466+#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3
1467+#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 4
1468+#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 16
1469+#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1470+ 0x000001c0 // 8- 6
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1471+#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6
1472+#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 4
1473+#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 16
1474+#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1475+ 0x00000e00 // 11- 9
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1476+#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9
1477+#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 4
1478+#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 16
1479+#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1480+ 0x00007000 // 14-12
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1481+#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12
1482+#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 4
1483+#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 16
1484+#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1485+ 0x00038000 // 17-15
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1486+#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15
1487+#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 4
1488+#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 16
1489+#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1490+ 0x001c0000 // 20-18
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1491+#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18
1492+#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 4
1493+#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 16
1494+#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1495+ 0x00e00000 // 23-21
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1496+#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1497+#define WF_LWTBL_PE_DW 4
1498+#define WF_LWTBL_PE_ADDR 16
1499+#define WF_LWTBL_PE_MASK \
1500+ 0x03000000 // 25-24
1501+#define WF_LWTBL_PE_SHIFT 24
1502+#define WF_LWTBL_DIS_RHTR_DW 4
1503+#define WF_LWTBL_DIS_RHTR_ADDR 16
1504+#define WF_LWTBL_DIS_RHTR_MASK \
1505+ 0x04000000 // 26-26
1506+#define WF_LWTBL_DIS_RHTR_SHIFT 26
1507+#define WF_LWTBL_LDPC_HT_DW 4
1508+#define WF_LWTBL_LDPC_HT_ADDR 16
1509+#define WF_LWTBL_LDPC_HT_MASK \
1510+ 0x08000000 // 27-27
1511+#define WF_LWTBL_LDPC_HT_SHIFT 27
1512+#define WF_LWTBL_LDPC_VHT_DW 4
1513+#define WF_LWTBL_LDPC_VHT_ADDR 16
1514+#define WF_LWTBL_LDPC_VHT_MASK \
1515+ 0x10000000 // 28-28
1516+#define WF_LWTBL_LDPC_VHT_SHIFT 28
1517+#define WF_LWTBL_LDPC_HE_DW 4
1518+#define WF_LWTBL_LDPC_HE_ADDR 16
1519+#define WF_LWTBL_LDPC_HE_MASK \
1520+ 0x20000000 // 29-29
1521+#define WF_LWTBL_LDPC_HE_SHIFT 29
1522+#define WF_LWTBL_LDPC_EHT_DW 4
1523+#define WF_LWTBL_LDPC_EHT_ADDR 16
1524+#define WF_LWTBL_LDPC_EHT_MASK \
1525+ 0x40000000 // 30-30
1526+#define WF_LWTBL_LDPC_EHT_SHIFT 30
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1527+#define WF_LWTBL_BA_MODE_DW 4
1528+#define WF_LWTBL_BA_MODE_ADDR 16
1529+#define WF_LWTBL_BA_MODE_MASK \
1530+ 0x80000000 // 31-31
1531+#define WF_LWTBL_BA_MODE_SHIFT 31
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1532+// DW5
1533+#define WF_LWTBL_AF_DW 5
1534+#define WF_LWTBL_AF_ADDR 20
1535+#define WF_LWTBL_AF_MASK \
1536+ 0x00000007 // 2- 0
1537+#define WF_LWTBL_AF_SHIFT 0
1538+#define WF_LWTBL_AF_HE_DW 5
1539+#define WF_LWTBL_AF_HE_ADDR 20
1540+#define WF_LWTBL_AF_HE_MASK \
1541+ 0x00000018 // 4- 3
1542+#define WF_LWTBL_AF_HE_SHIFT 3
1543+#define WF_LWTBL_RTS_DW 5
1544+#define WF_LWTBL_RTS_ADDR 20
1545+#define WF_LWTBL_RTS_MASK \
1546+ 0x00000020 // 5- 5
1547+#define WF_LWTBL_RTS_SHIFT 5
1548+#define WF_LWTBL_SMPS_DW 5
1549+#define WF_LWTBL_SMPS_ADDR 20
1550+#define WF_LWTBL_SMPS_MASK \
1551+ 0x00000040 // 6- 6
1552+#define WF_LWTBL_SMPS_SHIFT 6
1553+#define WF_LWTBL_DYN_BW_DW 5
1554+#define WF_LWTBL_DYN_BW_ADDR 20
1555+#define WF_LWTBL_DYN_BW_MASK \
1556+ 0x00000080 // 7- 7
1557+#define WF_LWTBL_DYN_BW_SHIFT 7
1558+#define WF_LWTBL_MMSS_DW 5
1559+#define WF_LWTBL_MMSS_ADDR 20
1560+#define WF_LWTBL_MMSS_MASK \
1561+ 0x00000700 // 10- 8
1562+#define WF_LWTBL_MMSS_SHIFT 8
1563+#define WF_LWTBL_USR_DW 5
1564+#define WF_LWTBL_USR_ADDR 20
1565+#define WF_LWTBL_USR_MASK \
1566+ 0x00000800 // 11-11
1567+#define WF_LWTBL_USR_SHIFT 11
1568+#define WF_LWTBL_SR_R_DW 5
1569+#define WF_LWTBL_SR_R_ADDR 20
1570+#define WF_LWTBL_SR_R_MASK \
1571+ 0x00007000 // 14-12
1572+#define WF_LWTBL_SR_R_SHIFT 12
1573+#define WF_LWTBL_SR_ABORT_DW 5
1574+#define WF_LWTBL_SR_ABORT_ADDR 20
1575+#define WF_LWTBL_SR_ABORT_MASK \
1576+ 0x00008000 // 15-15
1577+#define WF_LWTBL_SR_ABORT_SHIFT 15
1578+#define WF_LWTBL_TX_POWER_OFFSET_DW 5
1579+#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20
1580+#define WF_LWTBL_TX_POWER_OFFSET_MASK \
1581+ 0x003f0000 // 21-16
1582+#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16
1583+#define WF_LWTBL_LTF_EHT_DW 5
1584+#define WF_LWTBL_LTF_EHT_ADDR 20
1585+#define WF_LWTBL_LTF_EHT_MASK \
1586+ 0x00c00000 // 23-22
1587+#define WF_LWTBL_LTF_EHT_SHIFT 22
1588+#define WF_LWTBL_GI_EHT_DW 5
1589+#define WF_LWTBL_GI_EHT_ADDR 20
1590+#define WF_LWTBL_GI_EHT_MASK \
1591+ 0x03000000 // 25-24
1592+#define WF_LWTBL_GI_EHT_SHIFT 24
1593+#define WF_LWTBL_DOPPL_DW 5
1594+#define WF_LWTBL_DOPPL_ADDR 20
1595+#define WF_LWTBL_DOPPL_MASK \
1596+ 0x04000000 // 26-26
1597+#define WF_LWTBL_DOPPL_SHIFT 26
1598+#define WF_LWTBL_TXOP_PS_CAP_DW 5
1599+#define WF_LWTBL_TXOP_PS_CAP_ADDR 20
1600+#define WF_LWTBL_TXOP_PS_CAP_MASK \
1601+ 0x08000000 // 27-27
1602+#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27
1603+#define WF_LWTBL_DU_I_PSM_DW 5
1604+#define WF_LWTBL_DU_I_PSM_ADDR 20
1605+#define WF_LWTBL_DU_I_PSM_MASK \
1606+ 0x10000000 // 28-28
1607+#define WF_LWTBL_DU_I_PSM_SHIFT 28
1608+#define WF_LWTBL_I_PSM_DW 5
1609+#define WF_LWTBL_I_PSM_ADDR 20
1610+#define WF_LWTBL_I_PSM_MASK \
1611+ 0x20000000 // 29-29
1612+#define WF_LWTBL_I_PSM_SHIFT 29
1613+#define WF_LWTBL_PSM_DW 5
1614+#define WF_LWTBL_PSM_ADDR 20
1615+#define WF_LWTBL_PSM_MASK \
1616+ 0x40000000 // 30-30
1617+#define WF_LWTBL_PSM_SHIFT 30
1618+#define WF_LWTBL_SKIP_TX_DW 5
1619+#define WF_LWTBL_SKIP_TX_ADDR 20
1620+#define WF_LWTBL_SKIP_TX_MASK \
1621+ 0x80000000 // 31-31
1622+#define WF_LWTBL_SKIP_TX_SHIFT 31
1623+// DW6
1624+#define WF_LWTBL_CBRN_DW 6
1625+#define WF_LWTBL_CBRN_ADDR 24
1626+#define WF_LWTBL_CBRN_MASK \
1627+ 0x00000007 // 2- 0
1628+#define WF_LWTBL_CBRN_SHIFT 0
1629+#define WF_LWTBL_DBNSS_EN_DW 6
1630+#define WF_LWTBL_DBNSS_EN_ADDR 24
1631+#define WF_LWTBL_DBNSS_EN_MASK \
1632+ 0x00000008 // 3- 3
1633+#define WF_LWTBL_DBNSS_EN_SHIFT 3
1634+#define WF_LWTBL_BAF_EN_DW 6
1635+#define WF_LWTBL_BAF_EN_ADDR 24
1636+#define WF_LWTBL_BAF_EN_MASK \
1637+ 0x00000010 // 4- 4
1638+#define WF_LWTBL_BAF_EN_SHIFT 4
1639+#define WF_LWTBL_RDGBA_DW 6
1640+#define WF_LWTBL_RDGBA_ADDR 24
1641+#define WF_LWTBL_RDGBA_MASK \
1642+ 0x00000020 // 5- 5
1643+#define WF_LWTBL_RDGBA_SHIFT 5
1644+#define WF_LWTBL_R_DW 6
1645+#define WF_LWTBL_R_ADDR 24
1646+#define WF_LWTBL_R_MASK \
1647+ 0x00000040 // 6- 6
1648+#define WF_LWTBL_R_SHIFT 6
1649+#define WF_LWTBL_SPE_IDX_DW 6
1650+#define WF_LWTBL_SPE_IDX_ADDR 24
1651+#define WF_LWTBL_SPE_IDX_MASK \
1652+ 0x00000f80 // 11- 7
1653+#define WF_LWTBL_SPE_IDX_SHIFT 7
1654+#define WF_LWTBL_G2_DW 6
1655+#define WF_LWTBL_G2_ADDR 24
1656+#define WF_LWTBL_G2_MASK \
1657+ 0x00001000 // 12-12
1658+#define WF_LWTBL_G2_SHIFT 12
1659+#define WF_LWTBL_G4_DW 6
1660+#define WF_LWTBL_G4_ADDR 24
1661+#define WF_LWTBL_G4_MASK \
1662+ 0x00002000 // 13-13
1663+#define WF_LWTBL_G4_SHIFT 13
1664+#define WF_LWTBL_G8_DW 6
1665+#define WF_LWTBL_G8_ADDR 24
1666+#define WF_LWTBL_G8_MASK \
1667+ 0x00004000 // 14-14
1668+#define WF_LWTBL_G8_SHIFT 14
1669+#define WF_LWTBL_G16_DW 6
1670+#define WF_LWTBL_G16_ADDR 24
1671+#define WF_LWTBL_G16_MASK \
1672+ 0x00008000 // 15-15
1673+#define WF_LWTBL_G16_SHIFT 15
1674+#define WF_LWTBL_G2_LTF_DW 6
1675+#define WF_LWTBL_G2_LTF_ADDR 24
1676+#define WF_LWTBL_G2_LTF_MASK \
1677+ 0x00030000 // 17-16
1678+#define WF_LWTBL_G2_LTF_SHIFT 16
1679+#define WF_LWTBL_G4_LTF_DW 6
1680+#define WF_LWTBL_G4_LTF_ADDR 24
1681+#define WF_LWTBL_G4_LTF_MASK \
1682+ 0x000c0000 // 19-18
1683+#define WF_LWTBL_G4_LTF_SHIFT 18
1684+#define WF_LWTBL_G8_LTF_DW 6
1685+#define WF_LWTBL_G8_LTF_ADDR 24
1686+#define WF_LWTBL_G8_LTF_MASK \
1687+ 0x00300000 // 21-20
1688+#define WF_LWTBL_G8_LTF_SHIFT 20
1689+#define WF_LWTBL_G16_LTF_DW 6
1690+#define WF_LWTBL_G16_LTF_ADDR 24
1691+#define WF_LWTBL_G16_LTF_MASK \
1692+ 0x00c00000 // 23-22
1693+#define WF_LWTBL_G16_LTF_SHIFT 22
1694+#define WF_LWTBL_G2_HE_DW 6
1695+#define WF_LWTBL_G2_HE_ADDR 24
1696+#define WF_LWTBL_G2_HE_MASK \
1697+ 0x03000000 // 25-24
1698+#define WF_LWTBL_G2_HE_SHIFT 24
1699+#define WF_LWTBL_G4_HE_DW 6
1700+#define WF_LWTBL_G4_HE_ADDR 24
1701+#define WF_LWTBL_G4_HE_MASK \
1702+ 0x0c000000 // 27-26
1703+#define WF_LWTBL_G4_HE_SHIFT 26
1704+#define WF_LWTBL_G8_HE_DW 6
1705+#define WF_LWTBL_G8_HE_ADDR 24
1706+#define WF_LWTBL_G8_HE_MASK \
1707+ 0x30000000 // 29-28
1708+#define WF_LWTBL_G8_HE_SHIFT 28
1709+#define WF_LWTBL_G16_HE_DW 6
1710+#define WF_LWTBL_G16_HE_ADDR 24
1711+#define WF_LWTBL_G16_HE_MASK \
1712+ 0xc0000000 // 31-30
1713+#define WF_LWTBL_G16_HE_SHIFT 30
1714+// DW7
1715+#define WF_LWTBL_BA_WIN_SIZE0_DW 7
1716+#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28
1717+#define WF_LWTBL_BA_WIN_SIZE0_MASK \
1718+ 0x0000000f // 3- 0
1719+#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0
1720+#define WF_LWTBL_BA_WIN_SIZE1_DW 7
1721+#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28
1722+#define WF_LWTBL_BA_WIN_SIZE1_MASK \
1723+ 0x000000f0 // 7- 4
1724+#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4
1725+#define WF_LWTBL_BA_WIN_SIZE2_DW 7
1726+#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28
1727+#define WF_LWTBL_BA_WIN_SIZE2_MASK \
1728+ 0x00000f00 // 11- 8
1729+#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8
1730+#define WF_LWTBL_BA_WIN_SIZE3_DW 7
1731+#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28
1732+#define WF_LWTBL_BA_WIN_SIZE3_MASK \
1733+ 0x0000f000 // 15-12
1734+#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12
1735+#define WF_LWTBL_BA_WIN_SIZE4_DW 7
1736+#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28
1737+#define WF_LWTBL_BA_WIN_SIZE4_MASK \
1738+ 0x000f0000 // 19-16
1739+#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16
1740+#define WF_LWTBL_BA_WIN_SIZE5_DW 7
1741+#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28
1742+#define WF_LWTBL_BA_WIN_SIZE5_MASK \
1743+ 0x00f00000 // 23-20
1744+#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20
1745+#define WF_LWTBL_BA_WIN_SIZE6_DW 7
1746+#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28
1747+#define WF_LWTBL_BA_WIN_SIZE6_MASK \
1748+ 0x0f000000 // 27-24
1749+#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24
1750+#define WF_LWTBL_BA_WIN_SIZE7_DW 7
1751+#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28
1752+#define WF_LWTBL_BA_WIN_SIZE7_MASK \
1753+ 0xf0000000 // 31-28
1754+#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28
1755+// DW8
1756+#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8
1757+#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32
1758+#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \
1759+ 0x0000001f // 4- 0
1760+#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0
1761+#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8
1762+#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32
1763+#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \
1764+ 0x000003e0 // 9- 5
1765+#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5
1766+#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8
1767+#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32
1768+#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \
1769+ 0x00007c00 // 14-10
1770+#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10
1771+#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8
1772+#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32
1773+#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \
1774+ 0x000f8000 // 19-15
1775+#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15
1776+#define WF_LWTBL_PARTIAL_AID_DW 8
1777+#define WF_LWTBL_PARTIAL_AID_ADDR 32
1778+#define WF_LWTBL_PARTIAL_AID_MASK \
1779+ 0x1ff00000 // 28-20
1780+#define WF_LWTBL_PARTIAL_AID_SHIFT 20
1781+#define WF_LWTBL_CHK_PER_DW 8
1782+#define WF_LWTBL_CHK_PER_ADDR 32
1783+#define WF_LWTBL_CHK_PER_MASK \
1784+ 0x80000000 // 31-31
1785+#define WF_LWTBL_CHK_PER_SHIFT 31
1786+// DW9
1787+#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9
1788+#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36
1789+#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \
1790+ 0x00003fff // 13- 0
1791+#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0
1792+#define WF_LWTBL_PRITX_SW_MODE_DW 9
1793+#define WF_LWTBL_PRITX_SW_MODE_ADDR 36
1794+#define WF_LWTBL_PRITX_SW_MODE_MASK \
1795+ 0x00008000 // 15-15
1796+#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15
1797+#define WF_LWTBL_PRITX_ERSU_DW 9
1798+#define WF_LWTBL_PRITX_ERSU_ADDR 36
1799+#define WF_LWTBL_PRITX_ERSU_MASK \
1800+ 0x00010000 // 16-16
1801+#define WF_LWTBL_PRITX_ERSU_SHIFT 16
1802+#define WF_LWTBL_PRITX_PLR_DW 9
1803+#define WF_LWTBL_PRITX_PLR_ADDR 36
1804+#define WF_LWTBL_PRITX_PLR_MASK \
1805+ 0x00020000 // 17-17
1806+#define WF_LWTBL_PRITX_PLR_SHIFT 17
1807+#define WF_LWTBL_PRITX_DCM_DW 9
1808+#define WF_LWTBL_PRITX_DCM_ADDR 36
1809+#define WF_LWTBL_PRITX_DCM_MASK \
1810+ 0x00040000 // 18-18
1811+#define WF_LWTBL_PRITX_DCM_SHIFT 18
1812+#define WF_LWTBL_PRITX_ER106T_DW 9
1813+#define WF_LWTBL_PRITX_ER106T_ADDR 36
1814+#define WF_LWTBL_PRITX_ER106T_MASK \
1815+ 0x00080000 // 19-19
1816+#define WF_LWTBL_PRITX_ER106T_SHIFT 19
1817+#define WF_LWTBL_FCAP_DW 9
1818+#define WF_LWTBL_FCAP_ADDR 36
1819+#define WF_LWTBL_FCAP_MASK \
1820+ 0x00700000 // 22-20
1821+#define WF_LWTBL_FCAP_SHIFT 20
1822+#define WF_LWTBL_MPDU_FAIL_CNT_DW 9
1823+#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36
1824+#define WF_LWTBL_MPDU_FAIL_CNT_MASK \
1825+ 0x03800000 // 25-23
1826+#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23
1827+#define WF_LWTBL_MPDU_OK_CNT_DW 9
1828+#define WF_LWTBL_MPDU_OK_CNT_ADDR 36
1829+#define WF_LWTBL_MPDU_OK_CNT_MASK \
1830+ 0x1c000000 // 28-26
1831+#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26
1832+#define WF_LWTBL_RATE_IDX_DW 9
1833+#define WF_LWTBL_RATE_IDX_ADDR 36
1834+#define WF_LWTBL_RATE_IDX_MASK \
1835+ 0xe0000000 // 31-29
1836+#define WF_LWTBL_RATE_IDX_SHIFT 29
1837+// DW10
1838+#define WF_LWTBL_RATE1_DW 10
1839+#define WF_LWTBL_RATE1_ADDR 40
1840+#define WF_LWTBL_RATE1_MASK \
1841+ 0x00007fff // 14- 0
1842+#define WF_LWTBL_RATE1_SHIFT 0
1843+#define WF_LWTBL_RATE2_DW 10
1844+#define WF_LWTBL_RATE2_ADDR 40
1845+#define WF_LWTBL_RATE2_MASK \
1846+ 0x7fff0000 // 30-16
1847+#define WF_LWTBL_RATE2_SHIFT 16
1848+// DW11
1849+#define WF_LWTBL_RATE3_DW 11
1850+#define WF_LWTBL_RATE3_ADDR 44
1851+#define WF_LWTBL_RATE3_MASK \
1852+ 0x00007fff // 14- 0
1853+#define WF_LWTBL_RATE3_SHIFT 0
1854+#define WF_LWTBL_RATE4_DW 11
1855+#define WF_LWTBL_RATE4_ADDR 44
1856+#define WF_LWTBL_RATE4_MASK \
1857+ 0x7fff0000 // 30-16
1858+#define WF_LWTBL_RATE4_SHIFT 16
1859+// DW12
1860+#define WF_LWTBL_RATE5_DW 12
1861+#define WF_LWTBL_RATE5_ADDR 48
1862+#define WF_LWTBL_RATE5_MASK \
1863+ 0x00007fff // 14- 0
1864+#define WF_LWTBL_RATE5_SHIFT 0
1865+#define WF_LWTBL_RATE6_DW 12
1866+#define WF_LWTBL_RATE6_ADDR 48
1867+#define WF_LWTBL_RATE6_MASK \
1868+ 0x7fff0000 // 30-16
1869+#define WF_LWTBL_RATE6_SHIFT 16
1870+// DW13
1871+#define WF_LWTBL_RATE7_DW 13
1872+#define WF_LWTBL_RATE7_ADDR 52
1873+#define WF_LWTBL_RATE7_MASK \
1874+ 0x00007fff // 14- 0
1875+#define WF_LWTBL_RATE7_SHIFT 0
1876+#define WF_LWTBL_RATE8_DW 13
1877+#define WF_LWTBL_RATE8_ADDR 52
1878+#define WF_LWTBL_RATE8_MASK \
1879+ 0x7fff0000 // 30-16
1880+#define WF_LWTBL_RATE8_SHIFT 16
1881+// DW14
1882+#define WF_LWTBL_RATE1_TX_CNT_DW 14
1883+#define WF_LWTBL_RATE1_TX_CNT_ADDR 56
1884+#define WF_LWTBL_RATE1_TX_CNT_MASK \
1885+ 0x0000ffff // 15- 0
1886+#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0
1887+#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14
1888+#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56
1889+#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \
1890+ 0x00003000 // 13-12
1891+#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12
1892+#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14
1893+#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56
1894+#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \
1895+ 0x0000c000 // 15-14
1896+#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14
1897+#define WF_LWTBL_RATE1_FAIL_CNT_DW 14
1898+#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56
1899+#define WF_LWTBL_RATE1_FAIL_CNT_MASK \
1900+ 0xffff0000 // 31-16
1901+#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16
1902+// DW15
1903+#define WF_LWTBL_RATE2_OK_CNT_DW 15
1904+#define WF_LWTBL_RATE2_OK_CNT_ADDR 60
1905+#define WF_LWTBL_RATE2_OK_CNT_MASK \
1906+ 0x0000ffff // 15- 0
1907+#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0
1908+#define WF_LWTBL_RATE3_OK_CNT_DW 15
1909+#define WF_LWTBL_RATE3_OK_CNT_ADDR 60
1910+#define WF_LWTBL_RATE3_OK_CNT_MASK \
1911+ 0xffff0000 // 31-16
1912+#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16
1913+// DW16
1914+#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16
1915+#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64
1916+#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \
1917+ 0x0000ffff // 15- 0
1918+#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0
1919+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16
1920+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64
1921+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \
1922+ 0xffff0000 // 31-16
1923+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16
1924+// DW17
1925+#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17
1926+#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68
1927+#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \
1928+ 0x0000ffff // 15- 0
1929+#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0
1930+#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17
1931+#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68
1932+#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \
1933+ 0xffff0000 // 31-16
1934+#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16
1935+// DW18
1936+#define WF_LWTBL_RTS_OK_CNT_DW 18
1937+#define WF_LWTBL_RTS_OK_CNT_ADDR 72
1938+#define WF_LWTBL_RTS_OK_CNT_MASK \
1939+ 0x0000ffff // 15- 0
1940+#define WF_LWTBL_RTS_OK_CNT_SHIFT 0
1941+#define WF_LWTBL_RTS_FAIL_CNT_DW 18
1942+#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72
1943+#define WF_LWTBL_RTS_FAIL_CNT_MASK \
1944+ 0xffff0000 // 31-16
1945+#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16
1946+// DW19
1947+#define WF_LWTBL_DATA_RETRY_CNT_DW 19
1948+#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76
1949+#define WF_LWTBL_DATA_RETRY_CNT_MASK \
1950+ 0x0000ffff // 15- 0
1951+#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0
1952+#define WF_LWTBL_MGNT_RETRY_CNT_DW 19
1953+#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76
1954+#define WF_LWTBL_MGNT_RETRY_CNT_MASK \
1955+ 0xffff0000 // 31-16
1956+#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16
1957+// DW20
1958+#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20
1959+#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80
1960+#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \
1961+ 0xffffffff // 31- 0
1962+#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0
1963+// DW21
1964+// DO NOT process repeat field(adm[0])
1965+// DW22
1966+#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22
1967+#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88
1968+#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \
1969+ 0xffffffff // 31- 0
1970+#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0
1971+// DW23
1972+// DO NOT process repeat field(adm[1])
1973+// DW24
1974+#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24
1975+#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96
1976+#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \
1977+ 0xffffffff // 31- 0
1978+#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0
1979+// DW25
1980+// DO NOT process repeat field(adm[2])
1981+// DW26
1982+#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26
1983+#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104
1984+#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \
1985+ 0xffffffff // 31- 0
1986+#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0
1987+// DW27
1988+// DO NOT process repeat field(adm[3])
1989+// DW28
1990+#define WF_LWTBL_RELATED_IDX0_DW 28
1991+#define WF_LWTBL_RELATED_IDX0_ADDR 112
1992+#define WF_LWTBL_RELATED_IDX0_MASK \
1993+ 0x00000fff // 11- 0
1994+#define WF_LWTBL_RELATED_IDX0_SHIFT 0
1995+#define WF_LWTBL_RELATED_BAND0_DW 28
1996+#define WF_LWTBL_RELATED_BAND0_ADDR 112
1997+#define WF_LWTBL_RELATED_BAND0_MASK \
1998+ 0x00003000 // 13-12
1999+#define WF_LWTBL_RELATED_BAND0_SHIFT 12
2000+#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28
2001+#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112
2002+#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \
2003+ 0x0000c000 // 15-14
2004+#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14
2005+#define WF_LWTBL_RELATED_IDX1_DW 28
2006+#define WF_LWTBL_RELATED_IDX1_ADDR 112
2007+#define WF_LWTBL_RELATED_IDX1_MASK \
2008+ 0x0fff0000 // 27-16
2009+#define WF_LWTBL_RELATED_IDX1_SHIFT 16
2010+#define WF_LWTBL_RELATED_BAND1_DW 28
2011+#define WF_LWTBL_RELATED_BAND1_ADDR 112
2012+#define WF_LWTBL_RELATED_BAND1_MASK \
2013+ 0x30000000 // 29-28
2014+#define WF_LWTBL_RELATED_BAND1_SHIFT 28
2015+#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28
2016+#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112
2017+#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \
2018+ 0xc0000000 // 31-30
2019+#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30
2020+// DW29
2021+#define WF_LWTBL_DISPATCH_POLICY0_DW 29
2022+#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116
2023+#define WF_LWTBL_DISPATCH_POLICY0_MASK \
2024+ 0x00000003 // 1- 0
2025+#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0
2026+#define WF_LWTBL_DISPATCH_POLICY1_DW 29
2027+#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116
2028+#define WF_LWTBL_DISPATCH_POLICY1_MASK \
2029+ 0x0000000c // 3- 2
2030+#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2
2031+#define WF_LWTBL_DISPATCH_POLICY2_DW 29
2032+#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116
2033+#define WF_LWTBL_DISPATCH_POLICY2_MASK \
2034+ 0x00000030 // 5- 4
2035+#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4
2036+#define WF_LWTBL_DISPATCH_POLICY3_DW 29
2037+#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116
2038+#define WF_LWTBL_DISPATCH_POLICY3_MASK \
2039+ 0x000000c0 // 7- 6
2040+#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6
2041+#define WF_LWTBL_DISPATCH_POLICY4_DW 29
2042+#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116
2043+#define WF_LWTBL_DISPATCH_POLICY4_MASK \
2044+ 0x00000300 // 9- 8
2045+#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8
2046+#define WF_LWTBL_DISPATCH_POLICY5_DW 29
2047+#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116
2048+#define WF_LWTBL_DISPATCH_POLICY5_MASK \
2049+ 0x00000c00 // 11-10
2050+#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10
2051+#define WF_LWTBL_DISPATCH_POLICY6_DW 29
2052+#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116
2053+#define WF_LWTBL_DISPATCH_POLICY6_MASK \
2054+ 0x00003000 // 13-12
2055+#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12
2056+#define WF_LWTBL_DISPATCH_POLICY7_DW 29
2057+#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116
2058+#define WF_LWTBL_DISPATCH_POLICY7_MASK \
2059+ 0x0000c000 // 15-14
2060+#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14
2061+#define WF_LWTBL_OWN_MLD_ID_DW 29
2062+#define WF_LWTBL_OWN_MLD_ID_ADDR 116
2063+#define WF_LWTBL_OWN_MLD_ID_MASK \
2064+ 0x003f0000 // 21-16
2065+#define WF_LWTBL_OWN_MLD_ID_SHIFT 16
2066+#define WF_LWTBL_EMLSR0_DW 29
2067+#define WF_LWTBL_EMLSR0_ADDR 116
2068+#define WF_LWTBL_EMLSR0_MASK \
2069+ 0x00400000 // 22-22
2070+#define WF_LWTBL_EMLSR0_SHIFT 22
2071+#define WF_LWTBL_EMLMR0_DW 29
2072+#define WF_LWTBL_EMLMR0_ADDR 116
2073+#define WF_LWTBL_EMLMR0_MASK \
2074+ 0x00800000 // 23-23
2075+#define WF_LWTBL_EMLMR0_SHIFT 23
2076+#define WF_LWTBL_EMLSR1_DW 29
2077+#define WF_LWTBL_EMLSR1_ADDR 116
2078+#define WF_LWTBL_EMLSR1_MASK \
2079+ 0x01000000 // 24-24
2080+#define WF_LWTBL_EMLSR1_SHIFT 24
2081+#define WF_LWTBL_EMLMR1_DW 29
2082+#define WF_LWTBL_EMLMR1_ADDR 116
2083+#define WF_LWTBL_EMLMR1_MASK \
2084+ 0x02000000 // 25-25
2085+#define WF_LWTBL_EMLMR1_SHIFT 25
2086+#define WF_LWTBL_EMLSR2_DW 29
2087+#define WF_LWTBL_EMLSR2_ADDR 116
2088+#define WF_LWTBL_EMLSR2_MASK \
2089+ 0x04000000 // 26-26
2090+#define WF_LWTBL_EMLSR2_SHIFT 26
2091+#define WF_LWTBL_EMLMR2_DW 29
2092+#define WF_LWTBL_EMLMR2_ADDR 116
2093+#define WF_LWTBL_EMLMR2_MASK \
2094+ 0x08000000 // 27-27
2095+#define WF_LWTBL_EMLMR2_SHIFT 27
2096+#define WF_LWTBL_STR_BITMAP_DW 29
2097+#define WF_LWTBL_STR_BITMAP_ADDR 116
2098+#define WF_LWTBL_STR_BITMAP_MASK \
2099+ 0xe0000000 // 31-29
2100+#define WF_LWTBL_STR_BITMAP_SHIFT 29
2101+// DW30
2102+#define WF_LWTBL_DISPATCH_ORDER_DW 30
2103+#define WF_LWTBL_DISPATCH_ORDER_ADDR 120
2104+#define WF_LWTBL_DISPATCH_ORDER_MASK \
2105+ 0x0000007f // 6- 0
2106+#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0
2107+#define WF_LWTBL_DISPATCH_RATIO_DW 30
2108+#define WF_LWTBL_DISPATCH_RATIO_ADDR 120
2109+#define WF_LWTBL_DISPATCH_RATIO_MASK \
2110+ 0x00003f80 // 13- 7
2111+#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7
2112+#define WF_LWTBL_LINK_MGF_DW 30
2113+#define WF_LWTBL_LINK_MGF_ADDR 120
2114+#define WF_LWTBL_LINK_MGF_MASK \
2115+ 0xffff0000 // 31-16
2116+#define WF_LWTBL_LINK_MGF_SHIFT 16
2117+// DW31
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2118+#define WF_LWTBL_BFTX_TB_DW 31
2119+#define WF_LWTBL_BFTX_TB_ADDR 124
2120+#define WF_LWTBL_BFTX_TB_MASK \
2121+ 0x00800000 // 23-23
2122+#define WF_LWTBL_DROP_DW 31
2123+#define WF_LWTBL_DROP_ADDR 124
2124+#define WF_LWTBL_DROP_MASK \
2125+ 0x01000000 // 24-24
2126+#define WF_LWTBL_DROP_SHIFT 24
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2127+#define WF_LWTBL_CASCAD_DW 31
2128+#define WF_LWTBL_CASCAD_ADDR 124
2129+#define WF_LWTBL_CASCAD_MASK \
2130+ 0x02000000 // 25-25
2131+#define WF_LWTBL_CASCAD_SHIFT 25
2132+#define WF_LWTBL_ALL_ACK_DW 31
2133+#define WF_LWTBL_ALL_ACK_ADDR 124
2134+#define WF_LWTBL_ALL_ACK_MASK \
2135+ 0x04000000 // 26-26
2136+#define WF_LWTBL_ALL_ACK_SHIFT 26
2137+#define WF_LWTBL_MPDU_SIZE_DW 31
2138+#define WF_LWTBL_MPDU_SIZE_ADDR 124
2139+#define WF_LWTBL_MPDU_SIZE_MASK \
2140+ 0x18000000 // 28-27
2141+#define WF_LWTBL_MPDU_SIZE_SHIFT 27
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2142+#define WF_LWTBL_RXD_DUP_MODE_DW 31
2143+#define WF_LWTBL_RXD_DUP_MODE_ADDR 124
2144+#define WF_LWTBL_RXD_DUP_MODE_MASK \
2145+ 0x60000000 // 30-29
2146+#define WF_LWTBL_RXD_DUP_MODE_SHIFT 29
2147+#define WF_LWTBL_ACK_EN_DW 31
2148+#define WF_LWTBL_ACK_EN_ADDR 128
2149+#define WF_LWTBL_ACK_EN_MASK \
2150+ 0x80000000 // 31-31
2151+#define WF_LWTBL_ACK_EN_SHIFT 31
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2152+// DW32
2153+#define WF_LWTBL_OM_INFO_DW 32
2154+#define WF_LWTBL_OM_INFO_ADDR 128
2155+#define WF_LWTBL_OM_INFO_MASK \
2156+ 0x00000fff // 11- 0
2157+#define WF_LWTBL_OM_INFO_SHIFT 0
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2158+#define WF_LWTBL_OM_INFO_EHT_DW 32
2159+#define WF_LWTBL_OM_INFO_EHT_ADDR 128
2160+#define WF_LWTBL_OM_INFO_EHT_MASK \
2161+ 0x0000f000 // 15-12
2162+#define WF_LWTBL_OM_INFO_EHT_SHIFT 12
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2163+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32
2164+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128
2165+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2166+ 0x00010000 // 16-16
2167+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 16
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2168+#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32
2169+#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128
2170+#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2171+ 0x1ffe0000 // 28-17
2172+#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 17
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2173+// DW33
2174+#define WF_LWTBL_USER_RSSI_DW 33
2175+#define WF_LWTBL_USER_RSSI_ADDR 132
2176+#define WF_LWTBL_USER_RSSI_MASK \
2177+ 0x000001ff // 8- 0
2178+#define WF_LWTBL_USER_RSSI_SHIFT 0
2179+#define WF_LWTBL_USER_SNR_DW 33
2180+#define WF_LWTBL_USER_SNR_ADDR 132
2181+#define WF_LWTBL_USER_SNR_MASK \
2182+ 0x00007e00 // 14- 9
2183+#define WF_LWTBL_USER_SNR_SHIFT 9
2184+#define WF_LWTBL_RAPID_REACTION_RATE_DW 33
2185+#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132
2186+#define WF_LWTBL_RAPID_REACTION_RATE_MASK \
2187+ 0x0fff0000 // 27-16
2188+#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16
2189+#define WF_LWTBL_HT_AMSDU_DW 33
2190+#define WF_LWTBL_HT_AMSDU_ADDR 132
2191+#define WF_LWTBL_HT_AMSDU_MASK \
2192+ 0x40000000 // 30-30
2193+#define WF_LWTBL_HT_AMSDU_SHIFT 30
2194+#define WF_LWTBL_AMSDU_CROSS_LG_DW 33
2195+#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132
2196+#define WF_LWTBL_AMSDU_CROSS_LG_MASK \
2197+ 0x80000000 // 31-31
2198+#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31
2199+// DW34
2200+#define WF_LWTBL_RESP_RCPI0_DW 34
2201+#define WF_LWTBL_RESP_RCPI0_ADDR 136
2202+#define WF_LWTBL_RESP_RCPI0_MASK \
2203+ 0x000000ff // 7- 0
2204+#define WF_LWTBL_RESP_RCPI0_SHIFT 0
2205+#define WF_LWTBL_RESP_RCPI1_DW 34
2206+#define WF_LWTBL_RESP_RCPI1_ADDR 136
2207+#define WF_LWTBL_RESP_RCPI1_MASK \
2208+ 0x0000ff00 // 15- 8
2209+#define WF_LWTBL_RESP_RCPI1_SHIFT 8
2210+#define WF_LWTBL_RESP_RCPI2_DW 34
2211+#define WF_LWTBL_RESP_RCPI2_ADDR 136
2212+#define WF_LWTBL_RESP_RCPI2_MASK \
2213+ 0x00ff0000 // 23-16
2214+#define WF_LWTBL_RESP_RCPI2_SHIFT 16
2215+#define WF_LWTBL_RESP_RCPI3_DW 34
2216+#define WF_LWTBL_RESP_RCPI3_ADDR 136
2217+#define WF_LWTBL_RESP_RCPI3_MASK \
2218+ 0xff000000 // 31-24
2219+#define WF_LWTBL_RESP_RCPI3_SHIFT 24
2220+// DW35
2221+#define WF_LWTBL_SNR_RX0_DW 35
2222+#define WF_LWTBL_SNR_RX0_ADDR 140
2223+#define WF_LWTBL_SNR_RX0_MASK \
2224+ 0x0000003f // 5- 0
2225+#define WF_LWTBL_SNR_RX0_SHIFT 0
2226+#define WF_LWTBL_SNR_RX1_DW 35
2227+#define WF_LWTBL_SNR_RX1_ADDR 140
2228+#define WF_LWTBL_SNR_RX1_MASK \
2229+ 0x00000fc0 // 11- 6
2230+#define WF_LWTBL_SNR_RX1_SHIFT 6
2231+#define WF_LWTBL_SNR_RX2_DW 35
2232+#define WF_LWTBL_SNR_RX2_ADDR 140
2233+#define WF_LWTBL_SNR_RX2_MASK \
2234+ 0x0003f000 // 17-12
2235+#define WF_LWTBL_SNR_RX2_SHIFT 12
2236+#define WF_LWTBL_SNR_RX3_DW 35
2237+#define WF_LWTBL_SNR_RX3_ADDR 140
2238+#define WF_LWTBL_SNR_RX3_MASK \
2239+ 0x00fc0000 // 23-18
2240+#define WF_LWTBL_SNR_RX3_SHIFT 18
2241+
2242+/* WTBL Group - Packet Number */
2243+/* DW 2 */
2244+#define WTBL_PN0_MASK BITS(0, 7)
2245+#define WTBL_PN0_OFFSET 0
2246+#define WTBL_PN1_MASK BITS(8, 15)
2247+#define WTBL_PN1_OFFSET 8
2248+#define WTBL_PN2_MASK BITS(16, 23)
2249+#define WTBL_PN2_OFFSET 16
2250+#define WTBL_PN3_MASK BITS(24, 31)
2251+#define WTBL_PN3_OFFSET 24
2252+
2253+/* DW 3 */
2254+#define WTBL_PN4_MASK BITS(0, 7)
2255+#define WTBL_PN4_OFFSET 0
2256+#define WTBL_PN5_MASK BITS(8, 15)
2257+#define WTBL_PN5_OFFSET 8
2258+
2259+/* DW 4 */
2260+#define WTBL_BIPN0_MASK BITS(0, 7)
2261+#define WTBL_BIPN0_OFFSET 0
2262+#define WTBL_BIPN1_MASK BITS(8, 15)
2263+#define WTBL_BIPN1_OFFSET 8
2264+#define WTBL_BIPN2_MASK BITS(16, 23)
2265+#define WTBL_BIPN2_OFFSET 16
2266+#define WTBL_BIPN3_MASK BITS(24, 31)
2267+#define WTBL_BIPN3_OFFSET 24
2268+
2269+/* DW 5 */
2270+#define WTBL_BIPN4_MASK BITS(0, 7)
2271+#define WTBL_BIPN4_OFFSET 0
2272+#define WTBL_BIPN5_MASK BITS(8, 15)
2273+#define WTBL_BIPN5_OFFSET 8
2274+
2275+/* UWTBL DW 6 */
2276+#define WTBL_AMSDU_LEN_MASK BITS(0, 5)
2277+#define WTBL_AMSDU_LEN_OFFSET 0
2278+#define WTBL_AMSDU_NUM_MASK BITS(6, 10)
2279+#define WTBL_AMSDU_NUM_OFFSET 6
2280+#define WTBL_AMSDU_EN_MASK BIT(11)
2281+#define WTBL_AMSDU_EN_OFFSET 11
2282+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2283+/* UWTBL DW 8 */
2284+#define WTBL_SEC_ADDR_MODE_MASK BITS(20, 21)
2285+#define WTBL_SEC_ADDR_MODE_OFFSET 20
2286+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2287+/* LWTBL Rate field */
2288+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2289+#define WTBL_RATE_TX_RATE_OFFSET 0
2290+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2291+#define WTBL_RATE_TX_MODE_OFFSET 6
2292+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2293+#define WTBL_RATE_NSTS_OFFSET 10
2294+#define WTBL_RATE_STBC_MASK BIT(14)
2295+#define WTBL_RATE_STBC_OFFSET 14
2296+
2297+/***** WTBL(LMAC) DW Offset *****/
2298+/* LMAC WTBL Group - Peer Unique Information */
2299+#define WTBL_GROUP_PEER_INFO_DW_0 0
2300+#define WTBL_GROUP_PEER_INFO_DW_1 1
2301+
2302+/* WTBL Group - TxRx Capability/Information */
2303+#define WTBL_GROUP_TRX_CAP_DW_2 2
2304+#define WTBL_GROUP_TRX_CAP_DW_3 3
2305+#define WTBL_GROUP_TRX_CAP_DW_4 4
2306+#define WTBL_GROUP_TRX_CAP_DW_5 5
2307+#define WTBL_GROUP_TRX_CAP_DW_6 6
2308+#define WTBL_GROUP_TRX_CAP_DW_7 7
2309+#define WTBL_GROUP_TRX_CAP_DW_8 8
2310+#define WTBL_GROUP_TRX_CAP_DW_9 9
2311+
2312+/* WTBL Group - Auto Rate Table*/
2313+#define WTBL_GROUP_AUTO_RATE_1_2 10
2314+#define WTBL_GROUP_AUTO_RATE_3_4 11
2315+#define WTBL_GROUP_AUTO_RATE_5_6 12
2316+#define WTBL_GROUP_AUTO_RATE_7_8 13
2317+
2318+/* WTBL Group - Tx Counter */
2319+#define WTBL_GROUP_TX_CNT_LINE_1 14
2320+#define WTBL_GROUP_TX_CNT_LINE_2 15
2321+#define WTBL_GROUP_TX_CNT_LINE_3 16
2322+#define WTBL_GROUP_TX_CNT_LINE_4 17
2323+#define WTBL_GROUP_TX_CNT_LINE_5 18
2324+#define WTBL_GROUP_TX_CNT_LINE_6 19
2325+
2326+/* WTBL Group - Admission Control Counter */
2327+#define WTBL_GROUP_ADM_CNT_LINE_1 20
2328+#define WTBL_GROUP_ADM_CNT_LINE_2 21
2329+#define WTBL_GROUP_ADM_CNT_LINE_3 22
2330+#define WTBL_GROUP_ADM_CNT_LINE_4 23
2331+#define WTBL_GROUP_ADM_CNT_LINE_5 24
2332+#define WTBL_GROUP_ADM_CNT_LINE_6 25
2333+#define WTBL_GROUP_ADM_CNT_LINE_7 26
2334+#define WTBL_GROUP_ADM_CNT_LINE_8 27
2335+
2336+/* WTBL Group -MLO Info */
2337+#define WTBL_GROUP_MLO_INFO_LINE_1 28
2338+#define WTBL_GROUP_MLO_INFO_LINE_2 29
2339+#define WTBL_GROUP_MLO_INFO_LINE_3 30
2340+
2341+/* WTBL Group -RESP Info */
2342+#define WTBL_GROUP_RESP_INFO_DW_31 31
2343+
2344+/* WTBL Group -RX DUP Info */
2345+#define WTBL_GROUP_RX_DUP_INFO_DW_32 32
2346+
2347+/* WTBL Group - Rx Statistics Counter */
2348+#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33
2349+#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34
2350+#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35
2351+
2352+/* UWTBL Group - HW AMSDU */
2353+#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW
2354+
2355+/* LWTBL DW 4 */
2356+#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK
2357+
2358+/* UWTBL DW 5 */
2359+#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10)
2360+#define WTBL_PSM WF_LWTBL_PSM_MASK
2361+
2362+/* Need to sync with FW define */
2363+#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK
2364+
2365+// RATE
2366+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2367+#define WTBL_RATE_TX_RATE_OFFSET 0
2368+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2369+#define WTBL_RATE_TX_MODE_OFFSET 6
2370+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2371+#define WTBL_RATE_NSTS_OFFSET 10
2372+#define WTBL_RATE_STBC_MASK BIT(14)
2373+#define WTBL_RATE_STBC_OFFSET 14
2374+#endif
2375+
2376+#endif
2377diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c
2378new file mode 100644
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]2379index 0000000..5aa5c94
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2380--- /dev/null
2381+++ b/mt7996/mtk_debugfs.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2382@@ -0,0 +1,2379 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2383+// SPDX-License-Identifier: ISC
2384+/*
2385+ * Copyright (C) 2023 MediaTek Inc.
2386+ */
2387+#include "mt7996.h"
2388+#include "../mt76.h"
2389+#include "mcu.h"
2390+#include "mac.h"
2391+#include "eeprom.h"
2392+#include "mtk_debug.h"
2393+#include "mtk_mcu.h"
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2394+#include "coredump.h"
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2395+
2396+#ifdef CONFIG_MTK_DEBUG
2397+
2398+/* AGG INFO */
2399+static int
2400+mt7996_agginfo_read_per_band(struct seq_file *s, int band_idx)
2401+{
2402+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2403+ u64 total_burst, total_ampdu, ampdu_cnt[16];
2404+ u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0;
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2405+ u8 partial_str[16] = {}, full_str[64] = {};
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2406+
2407+ switch (band_idx) {
2408+ case 0:
2409+ band_offset = 0;
2410+ break;
2411+ case 1:
2412+ band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2413+ break;
2414+ case 2:
2415+ band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2416+ break;
2417+ default:
2418+ return 0;
2419+ }
2420+
2421+ seq_printf(s, "Band %d AGG Status\n", band_idx);
2422+ seq_printf(s, "===============================\n");
2423+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset);
2424+ seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT);
2425+ seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT);
2426+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset);
2427+ seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT);
2428+ seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT);
2429+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset);
2430+ seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT);
2431+ seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT);
2432+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset);
2433+ seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT);
2434+ seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT);
2435+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset);
2436+ seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT);
2437+ seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT);
2438+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset);
2439+ seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT);
2440+ seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT);
2441+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset);
2442+ seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT);
2443+ seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT);
2444+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset);
2445+ seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT);
2446+ seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT);
2447+
2448+ switch (band_idx) {
2449+ case 0:
2450+ band_offset = 0;
2451+ break;
2452+ case 1:
2453+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2454+ break;
2455+ case 2:
2456+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2457+ break;
2458+ default:
2459+ return 0;
2460+ }
2461+
2462+ seq_printf(s, "===AMPDU Related Counters===\n");
2463+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2464+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset);
2465+ agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT;
2466+ agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT;
2467+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset);
2468+ agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT;
2469+ agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT;
2470+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset);
2471+ agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT;
2472+ agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT;
2473+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset);
2474+ agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT;
2475+ agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT;
2476+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset);
2477+ agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT;
2478+ agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT;
2479+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset);
2480+ agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT;
2481+ agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT;
2482+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset);
2483+ agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT;
2484+ agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT;
2485+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset);
2486+ agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2487+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2488+ burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset);
2489+ burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset);
2490+ burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset);
2491+ burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset);
2492+ burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset);
2493+ burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset);
2494+ burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset);
2495+ burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset);
2496+ burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset);
2497+ burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset);
2498+ burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset);
2499+ burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset);
2500+ burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset);
2501+ burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset);
2502+ burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset);
2503+ burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2504+
2505+ start_range = 1;
2506+ total_burst = 0;
2507+ total_ampdu = 0;
2508+ agg_rang_sel[15] = 1023;
2509+
2510+ /* Need to add 1 after read from AGG_RANG_SEL CR */
2511+ for (idx = 0; idx < 16; idx++) {
2512+ agg_rang_sel[idx]++;
2513+ total_burst += burst_cnt[idx];
2514+
2515+ if (start_range == agg_rang_sel[idx])
2516+ ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx];
2517+ else
2518+ ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx];
2519+
2520+ start_range = agg_rang_sel[idx] + 1;
2521+ total_ampdu += ampdu_cnt[idx];
2522+ }
2523+
2524+ start_range = 1;
2525+ sprintf(full_str, "%13s ", "Tx Agg Range:");
2526+
2527+ for (row_idx = 0; row_idx < 4; row_idx++) {
2528+ for (col_idx = 0; col_idx < 4; col_idx++, idx++) {
2529+ idx = 4 * row_idx + col_idx;
2530+
2531+ if (start_range == agg_rang_sel[idx])
2532+ sprintf(partial_str, "%d", agg_rang_sel[idx]);
2533+ else
2534+ sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]);
2535+
2536+ start_range = agg_rang_sel[idx] + 1;
2537+ sprintf(full_str + strlen(full_str), "%-11s ", partial_str);
2538+ }
2539+
2540+ idx = 4 * row_idx;
2541+
2542+ seq_printf(s, "%s\n", full_str);
2543+ seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n",
2544+ row_idx ? "" : "Burst count:",
2545+ burst_cnt[idx], burst_cnt[idx + 1],
2546+ burst_cnt[idx + 2], burst_cnt[idx + 3]);
2547+
2548+ if (total_burst != 0) {
2549+ if (row_idx == 0)
2550+ sprintf(full_str, "%13s ",
2551+ "Burst ratio:");
2552+ else
2553+ sprintf(full_str, "%13s ", "");
2554+
2555+ for (col_idx = 0; col_idx < 4; col_idx++) {
2556+ u64 count = (u64) burst_cnt[idx + col_idx] * 100;
2557+
2558+ sprintf(partial_str, "(%llu%%)",
2559+ div64_u64(count, total_burst));
2560+ sprintf(full_str + strlen(full_str),
2561+ "%-11s ", partial_str);
2562+ }
2563+
2564+ seq_printf(s, "%s\n", full_str);
2565+
2566+ if (row_idx == 0)
2567+ sprintf(full_str, "%13s ",
2568+ "MDPU ratio:");
2569+ else
2570+ sprintf(full_str, "%13s ", "");
2571+
2572+ for (col_idx = 0; col_idx < 4; col_idx++) {
2573+ u64 count = ampdu_cnt[idx + col_idx] * 100;
2574+
2575+ sprintf(partial_str, "(%llu%%)",
2576+ div64_u64(count, total_ampdu));
2577+ sprintf(full_str + strlen(full_str),
2578+ "%-11s ", partial_str);
2579+ }
2580+
2581+ seq_printf(s, "%s\n", full_str);
2582+ }
2583+
2584+ sprintf(full_str, "%13s ", "");
2585+ }
2586+
2587+ return 0;
2588+}
2589+
2590+static int mt7996_agginfo_read_band0(struct seq_file *s, void *data)
2591+{
2592+ mt7996_agginfo_read_per_band(s, MT_BAND0);
2593+ return 0;
2594+}
2595+
2596+static int mt7996_agginfo_read_band1(struct seq_file *s, void *data)
2597+{
2598+ mt7996_agginfo_read_per_band(s, MT_BAND1);
2599+ return 0;
2600+}
2601+
2602+static int mt7996_agginfo_read_band2(struct seq_file *s, void *data)
2603+{
2604+ mt7996_agginfo_read_per_band(s, MT_BAND2);
2605+ return 0;
2606+}
2607+
2608+/* AMSDU INFO */
2609+static int mt7996_amsdu_result_read(struct seq_file *s, void *data)
2610+{
2611+#define HW_MSDU_CNT_ADDR 0xf400
2612+#define HW_MSDU_NUM_MAX 33
2613+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2614+ u32 ple_stat[HW_MSDU_NUM_MAX] = {0}, total_amsdu = 0;
2615+ u8 i;
2616+
2617+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2618+ ple_stat[i] = mt76_rr(dev, HW_MSDU_CNT_ADDR + i * 0x04);
2619+
2620+ seq_printf(s, "TXD counter status of MSDU:\n");
2621+
2622+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2623+ total_amsdu += ple_stat[i];
2624+
2625+ for (i = 0; i < HW_MSDU_NUM_MAX; i++) {
2626+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i, ple_stat[i]);
2627+ if (total_amsdu != 0)
2628+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
2629+ else
2630+ seq_printf(s, "\n");
2631+ }
2632+
2633+ return 0;
2634+}
2635+
2636+/* DBG MODLE */
2637+static int
2638+mt7996_fw_debug_module_set(void *data, u64 module)
2639+{
2640+ struct mt7996_dev *dev = data;
2641+
2642+ dev->dbg.fw_dbg_module = module;
2643+ return 0;
2644+}
2645+
2646+static int
2647+mt7996_fw_debug_module_get(void *data, u64 *module)
2648+{
2649+ struct mt7996_dev *dev = data;
2650+
2651+ *module = dev->dbg.fw_dbg_module;
2652+ return 0;
2653+}
2654+
2655+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7996_fw_debug_module_get,
2656+ mt7996_fw_debug_module_set, "%lld\n");
2657+
2658+static int
2659+mt7996_fw_debug_level_set(void *data, u64 level)
2660+{
2661+ struct mt7996_dev *dev = data;
2662+
2663+ dev->dbg.fw_dbg_lv = level;
2664+ mt7996_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2665+ return 0;
2666+}
2667+
2668+static int
2669+mt7996_fw_debug_level_get(void *data, u64 *level)
2670+{
2671+ struct mt7996_dev *dev = data;
2672+
2673+ *level = dev->dbg.fw_dbg_lv;
2674+ return 0;
2675+}
2676+
2677+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7996_fw_debug_level_get,
2678+ mt7996_fw_debug_level_set, "%lld\n");
2679+
2680+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
2681+static int
2682+mt7996_wa_set(void *data, u64 val)
2683+{
2684+ struct mt7996_dev *dev = data;
2685+ u32 arg1, arg2, arg3;
2686+
2687+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
2688+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
2689+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
2690+
2691+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
2692+ arg1, arg2, arg3);
2693+}
2694+
2695+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7996_wa_set,
2696+ "0x%llx\n");
2697+
2698+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
2699+static int
2700+mt7996_wa_query(void *data, u64 val)
2701+{
2702+ struct mt7996_dev *dev = data;
2703+ u32 arg1, arg2, arg3;
2704+
2705+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
2706+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
2707+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
2708+
2709+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
2710+ arg1, arg2, arg3);
2711+ return 0;
2712+}
2713+
2714+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7996_wa_query,
2715+ "0x%llx\n");
2716+
2717+static int mt7996_dump_version(struct seq_file *s, void *data)
2718+{
2719+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]2720+ seq_printf(s, "Version: 3.3.10.0\n");
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2721+
2722+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
2723+ return 0;
2724+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2725+ seq_printf(s, "Rom Patch Build Time: %.16s\n", dev->patch_build_date);
2726+ seq_printf(s, "WM Patch Build Time: %.15s, Mode: %s\n",
2727+ dev->ram_build_date[MT7996_RAM_TYPE_WM],
2728+ dev->testmode_enable ? "Testmode" : "Normal mode");
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2729+ seq_printf(s, "WA Patch Build Time: %.15s\n",
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2730+ dev->ram_build_date[MT7996_RAM_TYPE_WA]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2731+ seq_printf(s, "DSP Patch Build Time: %.15s\n",
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2732+ dev->ram_build_date[MT7996_RAM_TYPE_DSP]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2733+ return 0;
2734+}
2735+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2736+/* fw wm call trace info dump */
2737+void mt7996_show_lp_history(struct seq_file *s, u32 type)
2738+{
2739+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2740+ struct mt7996_crash_data *crash_data;
2741+ struct mt7996_coredump *dump;
2742+ u64 now = 0;
2743+ int i = 0;
2744+ u8 fw_type = !!type;
2745+
2746+ mutex_lock(&dev->dump_mutex);
2747+
2748+ crash_data = mt7996_coredump_new(dev, fw_type);
2749+ if (!crash_data) {
2750+ mutex_unlock(&dev->dump_mutex);
2751+ seq_printf(s, "the coredump is disable!\n");
2752+ return;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2753+ }
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2754+ mutex_unlock(&dev->dump_mutex);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2755+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2756+ dump = mt7996_coredump_build(dev, fw_type, false);
2757+ if (!dump) {
2758+ seq_printf(s, "no call stack data found!\n");
2759+ return;
2760+ }
2761+
2762+ seq_printf(s, "\x1b[32m%s log output\x1b[0m\n", dump->fw_type);
2763+ seq_printf(s, "\x1b[32mfw status: %s\n", dump->fw_state);
2764+ mt7996_dump_version(s, NULL);
2765+ /* PC log */
2766+ now = jiffies;
2767+ for (i = 0; i < 10; i++)
2768+ seq_printf(s, "\tCurrent PC=%x\n", dump->pc_cur[i]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2769+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2770+ seq_printf(s, "PC log contorl=0x%x(T=%llu)(latest PC index = 0x%x)\n",
2771+ dump->pc_dbg_ctrl, now, dump->pc_cur_idx);
2772+ for (i = 0; i < 32; i++)
2773+ seq_printf(s, "\tPC log(%d)=0x%08x\n", i, dump->pc_stack[i]);
2774+
2775+ /* LR log */
2776+ now = jiffies;
2777+ seq_printf(s, "\nLR log contorl=0x%x(T=%llu)(latest LR index = 0x%x)\n",
2778+ dump->lr_dbg_ctrl, now, dump->lr_cur_idx);
2779+ for (i = 0; i < 32; i++)
2780+ seq_printf(s, "\tLR log(%d)=0x%08x\n", i, dump->lr_stack[i]);
2781+
2782+ vfree(dump);
2783+}
2784+
2785+static int mt7996_fw_wa_info_read(struct seq_file *s, void *data)
2786+{
2787+ seq_printf(s, "======[ShowPcLpHistory]======\n");
2788+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WA);
2789+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
2790+
2791+ return 0;
2792+}
2793+
2794+static int mt7996_fw_wm_info_read(struct seq_file *s, void *data)
2795+{
2796+ seq_printf(s, "======[ShowPcLpHistory]======\n");
2797+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WM);
2798+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
2799+
2800+ return 0;
2801+}
2802+
2803+/* dma info dump */
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2804+static void
2805+dump_dma_tx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
2806+{
2807+ u32 base, cnt, cidx, didx, queue_cnt;
2808+
2809+ base= mt76_rr(dev, ring_base);
2810+ cnt = mt76_rr(dev, ring_base + 4);
2811+ cidx = mt76_rr(dev, ring_base + 8);
2812+ didx = mt76_rr(dev, ring_base + 12);
2813+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2814+
2815+ seq_printf(s, "%20s %6s %10x %15x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt);
2816+}
2817+
2818+static void
2819+dump_dma_rx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
2820+{
2821+ u32 base, ctrl1, cnt, cidx, didx, queue_cnt;
2822+
2823+ base= mt76_rr(dev, ring_base);
2824+ ctrl1 = mt76_rr(dev, ring_base + 4);
2825+ cidx = mt76_rr(dev, ring_base + 8) & 0xfff;
2826+ didx = mt76_rr(dev, ring_base + 12) & 0xfff;
2827+ cnt = ctrl1 & 0xfff;
2828+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2829+
2830+ seq_printf(s, "%20s %6s %10x %10x(%3x) %10x %10x %10x\n",
2831+ str1, str2, base, ctrl1, cnt, cidx, didx, queue_cnt);
2832+}
2833+
2834+static void
2835+mt7996_show_dma_info(struct seq_file *s, struct mt7996_dev *dev)
2836+{
2837+ u32 sys_ctrl[10];
2838+
2839+ /* HOST DMA0 information */
2840+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR);
2841+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR);
2842+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR);
2843+
2844+ seq_printf(s, "HOST_DMA Configuration\n");
2845+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2846+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2847+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2848+ "DMA0", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
2849+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2850+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2851+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2852+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2853+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2854+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2855+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2856+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2857+
2858+ if (dev->hif2) {
2859+ /* HOST DMA1 information */
2860+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR);
2861+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR);
2862+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR);
2863+
2864+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2865+ "DMA0P1", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
2866+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2867+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2868+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2869+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2870+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2871+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2872+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2873+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2874+ }
2875+
2876+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2877+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2878+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
2879+ dump_dma_tx_ring_info(s, dev, "T0:TXD0(H2MAC)", "STA",
2880+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2881+ dump_dma_tx_ring_info(s, dev, "T1:TXD1(H2MAC)", "STA",
2882+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2883+ dump_dma_tx_ring_info(s, dev, "T2:TXD2(H2MAC)", "STA",
2884+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2885+ dump_dma_tx_ring_info(s, dev, "T3:", "STA",
2886+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2887+ dump_dma_tx_ring_info(s, dev, "T4:", "STA",
2888+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2889+ dump_dma_tx_ring_info(s, dev, "T5:", "STA",
2890+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2891+ dump_dma_tx_ring_info(s, dev, "T6:", "STA",
2892+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2893+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", "Both",
2894+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR);
2895+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", "Both",
2896+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR);
2897+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", "AP",
2898+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR);
2899+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", "AP",
2900+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR);
2901+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", "AP",
2902+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR);
2903+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
2904+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR);
2905+ dump_dma_tx_ring_info(s, dev, "T22:TXD3(H2WA)", "AP",
2906+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR);
2907+
2908+
2909+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", "Both",
2910+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2911+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", "AP",
2912+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2913+ dump_dma_rx_ring_info(s, dev, "R2:TxDone0(WA2H)", "AP",
2914+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2915+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
2916+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2917+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", "Both",
2918+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2919+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
2920+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2921+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
2922+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2923+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
2924+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2925+ dump_dma_rx_ring_info(s, dev, "R8:BUF0(MAC2H)", "Both",
2926+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2927+ dump_dma_rx_ring_info(s, dev, "R9:TxDone0(MAC2H)", "Both",
2928+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2929+ dump_dma_rx_ring_info(s, dev, "R10:MSDU_PG0(MAC2H)", "Both",
2930+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
2931+ dump_dma_rx_ring_info(s, dev, "R11:MSDU_PG1(MAC2H)", "Both",
2932+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR);
2933+ dump_dma_rx_ring_info(s, dev, "R12:MSDU_PG2(MAC2H)", "Both",
2934+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR);
2935+ dump_dma_rx_ring_info(s, dev, "IND:IND_CMD(MAC2H)", "Both",
2936+ WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR);
2937+
2938+ if (dev->hif2) {
2939+ seq_printf(s, "HOST_DMA0 PCIe1 Ring Configuration\n");
2940+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2941+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
2942+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
2943+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR);
2944+ dump_dma_tx_ring_info(s, dev, "T22:TXD?(H2WA)", "AP",
2945+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR);
2946+
2947+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
2948+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2949+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
2950+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR);
2951+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
2952+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR);
2953+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
2954+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR);
2955+ }
2956+
2957+ /* MCU DMA information */
2958+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2959+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2960+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2961+
2962+ seq_printf(s, "MCU_DMA Configuration\n");
2963+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2964+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2965+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2966+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2967+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2968+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2969+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2970+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2971+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2972+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2973+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2974+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2975+
2976+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2977+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2978+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2979+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", "Both",
2980+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2981+ dump_dma_tx_ring_info(s, dev, "T1:Event(WA2H)", "AP",
2982+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2983+ dump_dma_tx_ring_info(s, dev, "T2:TxDone0(WA2H)", "AP",
2984+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2985+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1(WA2H)", "AP",
2986+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2987+ dump_dma_tx_ring_info(s, dev, "T4:TXD(WM2MAC)", "Both",
2988+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2989+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD(WM2MAC)", "Both",
2990+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2991+ dump_dma_tx_ring_info(s, dev, "T6:TXD(WA2MAC)", "AP",
2992+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2993+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", "Both",
2994+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2995+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", "Both",
2996+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2997+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", "AP",
2998+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2999+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", "AP",
3000+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
3001+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", "AP",
3002+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
3003+ dump_dma_rx_ring_info(s, dev, "R5:Data0(MAC2WM)", "Both",
3004+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
3005+ dump_dma_rx_ring_info(s, dev, "R6:TxDone(MAC2WM)", "Both",
3006+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
3007+ dump_dma_rx_ring_info(s, dev, "R7:SPL/RPT(MAC2WM)", "Both",
3008+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
3009+ dump_dma_rx_ring_info(s, dev, "R8:TxDone(MAC2WA)", "AP",
3010+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
3011+ dump_dma_rx_ring_info(s, dev, "R9:Data1(MAC2WM)", "Both",
3012+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
3013+ dump_dma_rx_ring_info(s, dev, "R10:TXD2(H2WA)", "AP",
3014+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
3015+
3016+ /* MEM DMA information */
3017+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
3018+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
3019+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
3020+
3021+ seq_printf(s, "MEM_DMA Configuration\n");
3022+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
3023+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
3024+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3025+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
3026+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3027+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3028+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3029+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3030+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3031+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3032+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3033+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3034+
3035+ seq_printf(s, "MEM_DMA Ring Configuration\n");
3036+ seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n",
3037+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
3038+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", "AP",
3039+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
3040+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", "AP",
3041+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
3042+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", "AP",
3043+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
3044+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", "AP",
3045+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
3046+}
3047+
3048+static int mt7996_trinfo_read(struct seq_file *s, void *data)
3049+{
3050+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3051+ mt7996_show_dma_info(s, dev);
3052+ return 0;
3053+}
3054+
3055+/* MIB INFO */
3056+static int mt7996_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3057+{
3058+#define BSS_NUM 4
3059+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3060+ u8 bss_nums = BSS_NUM;
3061+ u32 idx;
3062+ u32 mac_val, band_offset = 0, band_offset_umib = 0;
3063+ u32 msdr6, msdr9, msdr18;
3064+ u32 rvsr0, rscr26, rscr35, mctr5, mctr6, msr0, msr1, msr2;
3065+ u32 tbcr0, tbcr1, tbcr2, tbcr3, tbcr4;
3066+ u32 btscr[7];
3067+ u32 tdrcr[5];
3068+ u32 mbtocr[16], mbtbcr[16], mbrocr[16], mbrbcr[16];
3069+ u32 btcr, btbcr, brocr, brbcr, btdcr, brdcr;
3070+ u32 mu_cnt[5];
3071+ u32 ampdu_cnt[3];
3072+ u64 per;
3073+
3074+ switch (band_idx) {
3075+ case 0:
3076+ band_offset = 0;
3077+ band_offset_umib = 0;
3078+ break;
3079+ case 1:
3080+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3081+ band_offset_umib = WF_UMIB_TOP_B1BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3082+ break;
3083+ case 2:
3084+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3085+ band_offset_umib = WF_UMIB_TOP_B2BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3086+ break;
3087+ default:
3088+ return true;
3089+ }
3090+
3091+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3092+ seq_printf(s, "===============================\n");
3093+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset);
3094+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3095+
3096+ msdr6 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset);
3097+ rvsr0 = mt76_rr(dev, BN0_WF_MIB_TOP_RVSR0_ADDR + band_offset);
3098+ rscr35 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR35_ADDR + band_offset);
3099+ msdr9 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset);
3100+ rscr26 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR26_ADDR + band_offset);
3101+ mctr5 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR5_ADDR + band_offset);
3102+ mctr6 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR6_ADDR + band_offset);
3103+ msdr18 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset);
3104+ msr0 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR0_ADDR + band_offset);
3105+ msr1 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR1_ADDR + band_offset);
3106+ msr2 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR2_ADDR + band_offset);
3107+ ampdu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR0_ADDR + band_offset);
3108+ ampdu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR3_ADDR + band_offset);
3109+ ampdu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR4_ADDR + band_offset);
3110+ ampdu_cnt[1] &= BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK;
3111+ ampdu_cnt[2] &= BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK;
3112+
3113+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3114+ seq_printf(s, "\tChannelIdleCnt=0x%x\n",
3115+ msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3116+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n",
3117+ msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3118+ seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n",
3119+ rscr26 & BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK);
3120+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x",
3121+ msr0 & BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK,
3122+ msr1 & BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK);
3123+ seq_printf(s, ", OFDM_GREEN_MDRDY_TIME=0x%x\n",
3124+ msr2 & BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK);
3125+ seq_printf(s, "\tPrim CCA Time=0x%x\n",
3126+ mctr5 & BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK);
3127+ seq_printf(s, "\tSec CCA Time=0x%x\n",
3128+ mctr6 & BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK);
3129+ seq_printf(s, "\tPrim ED Time=0x%x\n",
3130+ msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3131+
3132+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3133+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR18_ADDR + band_offset);
3134+ dev->dbg.bcn_total_cnt[band_idx] +=
3135+ (mac_val & BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK);
3136+ seq_printf(s, "\tBeaconTxCnt=0x%x\n", dev->dbg.bcn_total_cnt[band_idx]);
3137+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3138+
3139+ tbcr0 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR0_ADDR + band_offset);
3140+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n",
3141+ tbcr0 & BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK);
3142+ tbcr1 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR1_ADDR + band_offset);
3143+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n",
3144+ tbcr1 & BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK);
3145+ tbcr2 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR2_ADDR + band_offset);
3146+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n",
3147+ tbcr2 & BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK);
3148+ tbcr3 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR3_ADDR + band_offset);
3149+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n",
3150+ tbcr3 & BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK);
3151+ tbcr4 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR4_ADDR + band_offset);
3152+ seq_printf(s, "\tTx 320MHz Cnt=0x%x\n",
3153+ tbcr4 & BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK);
3154+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3155+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3156+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3157+ per = (ampdu_cnt[2] == 0 ?
3158+ 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3159+ seq_printf(s, "\tAMPDU MPDU PER=%llu.%1llu%%\n", per / 10, per % 10);
3160+
3161+ seq_printf(s, "===MU Related Counters===\n");
3162+ mu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSCR2_ADDR + band_offset);
3163+ mu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR5_ADDR + band_offset);
3164+ mu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR6_ADDR + band_offset);
3165+ mu_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR8_ADDR + band_offset);
3166+ mu_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR7_ADDR + band_offset);
3167+
3168+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n",
3169+ mu_cnt[0] & BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK);
3170+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3171+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3172+ seq_printf(s, "\tMU_TO_MU_FAIL_PPDU_COUNT=0x%x\n", mu_cnt[3]);
3173+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3174+
3175+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3176+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n",
3177+ rvsr0 & BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK);
3178+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n",
3179+ rscr35 & BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK);
3180+
3181+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR1_ADDR + band_offset);
3182+ seq_printf(s, "\tRxFCSErrCnt=0x%x\n",
3183+ (mac_val & BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK));
3184+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR33_ADDR + band_offset);
3185+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n",
3186+ (mac_val & BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK));
3187+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR36_ADDR + band_offset);
3188+ seq_printf(s, "\tRxLenMismatch=0x%x\n",
3189+ (mac_val & BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK));
3190+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR31_ADDR + band_offset);
3191+ seq_printf(s, "\tRxMPDUCnt=0x%x\n",
3192+ (mac_val & BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK));
3193+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR27_ADDR + band_offset);
3194+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3195+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR28_ADDR + band_offset);
3196+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3197+
3198+
3199+ /* Per-BSS T/RX Counters */
3200+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3201+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxOkCnt/DataCnt RxByteCnt\n");
3202+ for (idx = 0; idx < bss_nums; idx++) {
3203+ btcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTCR_ADDR + band_offset + idx * 4);
3204+ btdcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + idx * 4);
3205+ btbcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + idx * 4);
3206+
3207+ brocr = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + idx * 4);
3208+ brdcr = mt76_rr(dev, WF_UMIB_TOP_B0BRDCR_ADDR + band_offset_umib + idx * 4);
3209+ brbcr = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + idx * 4);
3210+
3211+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3212+ idx, btcr, btdcr, btbcr, brocr, brdcr, brbcr);
3213+ }
3214+
3215+ seq_printf(s, "===Per-BSS Related MIB Counters===\n");
3216+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3217+
3218+ /* Per-BSS TX Status */
3219+ for (idx = 0; idx < bss_nums; idx++) {
3220+ btscr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR5_ADDR + band_offset + idx * 4);
3221+ btscr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR6_ADDR + band_offset + idx * 4);
3222+ btscr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR0_ADDR + band_offset + idx * 4);
3223+ btscr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR1_ADDR + band_offset + idx * 4);
3224+ btscr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR2_ADDR + band_offset + idx * 4);
3225+ btscr[5] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR3_ADDR + band_offset + idx * 4);
3226+ btscr[6] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR4_ADDR + band_offset + idx * 4);
3227+
3228+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3229+ idx, (btscr[0] & BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK),
3230+ (btscr[1] & BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK),
3231+ (btscr[2] & BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK),
3232+ (btscr[3] & BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK),
3233+ (btscr[4] & BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK),
3234+ (btscr[5] & BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK),
3235+ (btscr[6] & BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK));
3236+ }
3237+
3238+ /* Dummy delimiter insertion result */
3239+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3240+ tdrcr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR0_ADDR + band_offset);
3241+ tdrcr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR1_ADDR + band_offset);
3242+ tdrcr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR2_ADDR + band_offset);
3243+ tdrcr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR3_ADDR + band_offset);
3244+ tdrcr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR4_ADDR + band_offset);
3245+
3246+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3247+ tdrcr[0],
3248+ tdrcr[1],
3249+ tdrcr[2],
3250+ tdrcr[3],
3251+ tdrcr[4]);
3252+
3253+ /* Per-MBSS T/RX Counters */
3254+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3255+ seq_printf(s, "MBSSIdx TxOkCnt TxByteCnt RxOkCnt RxByteCnt\n");
3256+
3257+ for (idx = 0; idx < 16; idx++) {
3258+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (bss_nums + idx) * 4);
3259+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (bss_nums + idx) * 4);
3260+
3261+ mbrocr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3262+ mbrbcr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3263+ }
3264+
3265+ for (idx = 0; idx < 16; idx++) {
3266+ seq_printf(s, "%d\t 0x%x\t 0x%x \t 0x%x \t 0x%x\n",
3267+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3268+ }
3269+
3270+ return 0;
3271+}
3272+
3273+static int mt7996_mibinfo_band0(struct seq_file *s, void *data)
3274+{
3275+ mt7996_mibinfo_read_per_band(s, MT_BAND0);
3276+ return 0;
3277+}
3278+
3279+static int mt7996_mibinfo_band1(struct seq_file *s, void *data)
3280+{
3281+ mt7996_mibinfo_read_per_band(s, MT_BAND1);
3282+ return 0;
3283+}
3284+
3285+static int mt7996_mibinfo_band2(struct seq_file *s, void *data)
3286+{
3287+ mt7996_mibinfo_read_per_band(s, MT_BAND2);
3288+ return 0;
3289+}
3290+
3291+/* WTBL INFO */
3292+static int
3293+mt7996_wtbl_read_raw(struct mt7996_dev *dev, u16 idx,
3294+ enum mt7996_wtbl_type type, u16 start_dw,
3295+ u16 len, void *buf)
3296+{
3297+ u32 *dest_cpy = (u32 *)buf;
3298+ u32 size_dw = len;
3299+ u32 src = 0;
3300+
3301+ if (!buf)
3302+ return 0xFF;
3303+
3304+ if (type == WTBL_TYPE_LMAC) {
3305+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3306+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3307+ src = LWTBL_IDX2BASE(idx, start_dw);
3308+ } else if (type == WTBL_TYPE_UMAC) {
3309+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3310+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3311+ src = UWTBL_IDX2BASE(idx, start_dw);
3312+ } else if (type == WTBL_TYPE_KEY) {
3313+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3314+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3315+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3316+ src = KEYTBL_IDX2BASE(idx, start_dw);
3317+ }
3318+
3319+ while (size_dw--) {
3320+ *dest_cpy++ = mt76_rr(dev, src);
3321+ src += 4;
3322+ };
3323+
3324+ return 0;
3325+}
3326+
3327+#if 0
3328+static int
3329+mt7996_wtbl_write_raw(struct mt7996_dev *dev, u16 idx,
3330+ enum mt7996_wtbl_type type, u16 start_dw,
3331+ u32 val)
3332+{
3333+ u32 addr = 0;
3334+
3335+ if (type == WTBL_TYPE_LMAC) {
3336+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3337+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3338+ addr = LWTBL_IDX2BASE(idx, start_dw);
3339+ } else if (type == WTBL_TYPE_UMAC) {
3340+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3341+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3342+ addr = UWTBL_IDX2BASE(idx, start_dw);
3343+ } else if (type == WTBL_TYPE_KEY) {
3344+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3345+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3346+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3347+ addr = KEYTBL_IDX2BASE(idx, start_dw);
3348+ }
3349+
3350+ mt76_wr(dev, addr, val);
3351+
3352+ return 0;
3353+}
3354+#endif
3355+
3356+static const struct berse_wtbl_parse WTBL_LMAC_DW0[] = {
3357+ {"MUAR_IDX", WF_LWTBL_MUAR_MASK, WF_LWTBL_MUAR_SHIFT,false},
3358+ {"RCA1", WF_LWTBL_RCA1_MASK, NO_SHIFT_DEFINE, false},
3359+ {"KID", WF_LWTBL_KID_MASK, WF_LWTBL_KID_SHIFT, false},
3360+ {"RCID", WF_LWTBL_RCID_MASK, NO_SHIFT_DEFINE, false},
3361+ {"BAND", WF_LWTBL_BAND_MASK, WF_LWTBL_BAND_SHIFT,false},
3362+ {"RV", WF_LWTBL_RV_MASK, NO_SHIFT_DEFINE, false},
3363+ {"RCA2", WF_LWTBL_RCA2_MASK, NO_SHIFT_DEFINE, false},
3364+ {"WPI_FLAG", WF_LWTBL_WPI_FLAG_MASK, NO_SHIFT_DEFINE,true},
3365+ {NULL,}
3366+};
3367+
3368+static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl)
3369+{
3370+ u32 *addr = 0;
3371+ u32 dw_value = 0;
3372+ u16 i = 0;
3373+
3374+ seq_printf(s, "\t\n");
3375+ seq_printf(s, "LinkAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
3376+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
3377+
3378+ /* LMAC WTBL DW 0 */
3379+ seq_printf(s, "\t\n");
3380+ seq_printf(s, "LWTBL DW 0/1\n");
3381+ addr = (u32 *)&(lwtbl[WTBL_GROUP_PEER_INFO_DW_0*4]);
3382+ dw_value = *addr;
3383+
3384+ while (WTBL_LMAC_DW0[i].name) {
3385+
3386+ if (WTBL_LMAC_DW0[i].shift == NO_SHIFT_DEFINE)
3387+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW0[i].name,
3388+ (dw_value & WTBL_LMAC_DW0[i].mask) ? 1 : 0);
3389+ else
3390+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW0[i].name,
3391+ (dw_value & WTBL_LMAC_DW0[i].mask) >> WTBL_LMAC_DW0[i].shift);
3392+ i++;
3393+ }
3394+}
3395+
3396+static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = {
3397+ {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false},
3398+ {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false},
3399+ {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false},
3400+ {"WPI_EVEN", WF_LWTBL_WPI_EVEN_MASK, NO_SHIFT_DEFINE, false},
3401+ {"AAD_OM", WF_LWTBL_AAD_OM_MASK, NO_SHIFT_DEFINE, false},
3402+ {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true},
3403+ {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false},
3404+ {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false},
3405+ {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false},
3406+ {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false},
3407+ {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true},
3408+ {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
3409+ {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
3410+ {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false},
3411+ {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false},
3412+ {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false},
3413+ {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true},
3414+ {NULL,}
3415+};
3416+
3417+static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl)
3418+{
3419+ u32 *addr = 0;
3420+ u32 dw_value = 0;
3421+ u16 i = 0;
3422+
3423+ /* LMAC WTBL DW 2 */
3424+ seq_printf(s, "\t\n");
3425+ seq_printf(s, "LWTBL DW 2\n");
3426+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
3427+ dw_value = *addr;
3428+
3429+ while (WTBL_LMAC_DW2[i].name) {
3430+
3431+ if (WTBL_LMAC_DW2[i].shift == NO_SHIFT_DEFINE)
3432+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW2[i].name,
3433+ (dw_value & WTBL_LMAC_DW2[i].mask) ? 1 : 0);
3434+ else
3435+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[i].name,
3436+ (dw_value & WTBL_LMAC_DW2[i].mask) >> WTBL_LMAC_DW2[i].shift);
3437+ i++;
3438+ }
3439+}
3440+
3441+static const struct berse_wtbl_parse WTBL_LMAC_DW3[] = {
3442+ {"WMM_Q", WF_LWTBL_WMM_Q_MASK, WF_LWTBL_WMM_Q_SHIFT, false},
3443+ {"EHT_SIG_MCS", WF_LWTBL_EHT_SIG_MCS_MASK, WF_LWTBL_EHT_SIG_MCS_SHIFT, false},
3444+ {"HDRT_MODE", WF_LWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, false},
3445+ {"BEAM_CHG", WF_LWTBL_BEAM_CHG_MASK, NO_SHIFT_DEFINE, false},
3446+ {"EHT_LTF_SYM_NUM", WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK, WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT, true},
3447+ {"PFMU_IDX", WF_LWTBL_PFMU_IDX_MASK, WF_LWTBL_PFMU_IDX_SHIFT, false},
3448+ {"ULPF_IDX", WF_LWTBL_ULPF_IDX_MASK, WF_LWTBL_ULPF_IDX_SHIFT, false},
3449+ {"RIBF", WF_LWTBL_RIBF_MASK, NO_SHIFT_DEFINE, false},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3450+ {"ULPF", WF_LWTBL_ULPF_MASK, NO_SHIFT_DEFINE, false},
3451+ {"BYPASS_TXSMM", WF_LWTBL_BYPASS_TXSMM_MASK, NO_SHIFT_DEFINE, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3452+ {"TBF_HT", WF_LWTBL_TBF_HT_MASK, NO_SHIFT_DEFINE, false},
3453+ {"TBF_VHT", WF_LWTBL_TBF_VHT_MASK, NO_SHIFT_DEFINE, false},
3454+ {"TBF_HE", WF_LWTBL_TBF_HE_MASK, NO_SHIFT_DEFINE, false},
3455+ {"TBF_EHT", WF_LWTBL_TBF_EHT_MASK, NO_SHIFT_DEFINE, false},
3456+ {"IGN_FBK", WF_LWTBL_IGN_FBK_MASK, NO_SHIFT_DEFINE, true},
3457+ {NULL,}
3458+};
3459+
3460+static void parse_fmac_lwtbl_dw3(struct seq_file *s, u8 *lwtbl)
3461+{
3462+ u32 *addr = 0;
3463+ u32 dw_value = 0;
3464+ u16 i = 0;
3465+
3466+ /* LMAC WTBL DW 3 */
3467+ seq_printf(s, "\t\n");
3468+ seq_printf(s, "LWTBL DW 3\n");
3469+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_3*4]);
3470+ dw_value = *addr;
3471+
3472+ while (WTBL_LMAC_DW3[i].name) {
3473+
3474+ if (WTBL_LMAC_DW3[i].shift == NO_SHIFT_DEFINE)
3475+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW3[i].name,
3476+ (dw_value & WTBL_LMAC_DW3[i].mask) ? 1 : 0);
3477+ else
3478+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW3[i].name,
3479+ (dw_value & WTBL_LMAC_DW3[i].mask) >> WTBL_LMAC_DW3[i].shift);
3480+ i++;
3481+ }
3482+}
3483+
3484+static const struct berse_wtbl_parse WTBL_LMAC_DW4[] = {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3485+ {"NEGOTIATED_WINSIZE0", WF_LWTBL_NEGOTIATED_WINSIZE0_MASK, WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT, false},
3486+ {"WINSIZE1", WF_LWTBL_NEGOTIATED_WINSIZE1_MASK, WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT, false},
3487+ {"WINSIZE2", WF_LWTBL_NEGOTIATED_WINSIZE2_MASK, WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT, false},
3488+ {"WINSIZE3", WF_LWTBL_NEGOTIATED_WINSIZE3_MASK, WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT, true},
3489+ {"WINSIZE4", WF_LWTBL_NEGOTIATED_WINSIZE4_MASK, WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT, false},
3490+ {"WINSIZE5", WF_LWTBL_NEGOTIATED_WINSIZE5_MASK, WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT, false},
3491+ {"WINSIZE6", WF_LWTBL_NEGOTIATED_WINSIZE6_MASK, WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT, false},
3492+ {"WINSIZE7", WF_LWTBL_NEGOTIATED_WINSIZE7_MASK, WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3493+ {"PE", WF_LWTBL_PE_MASK, WF_LWTBL_PE_SHIFT, false},
3494+ {"DIS_RHTR", WF_LWTBL_DIS_RHTR_MASK, NO_SHIFT_DEFINE, false},
3495+ {"LDPC_HT", WF_LWTBL_LDPC_HT_MASK, NO_SHIFT_DEFINE, false},
3496+ {"LDPC_VHT", WF_LWTBL_LDPC_VHT_MASK, NO_SHIFT_DEFINE, false},
3497+ {"LDPC_HE", WF_LWTBL_LDPC_HE_MASK, NO_SHIFT_DEFINE, false},
3498+ {"LDPC_EHT", WF_LWTBL_LDPC_EHT_MASK, NO_SHIFT_DEFINE, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3499+ {"BA_MODE", WF_LWTBL_BA_MODE_MASK, NO_SHIFT_DEFINE, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3500+ {NULL,}
3501+};
3502+
3503+static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl)
3504+{
3505+ u32 *addr = 0;
3506+ u32 dw_value = 0;
3507+ u16 i = 0;
3508+
3509+ /* LMAC WTBL DW 4 */
3510+ seq_printf(s, "\t\n");
3511+ seq_printf(s, "LWTBL DW 4\n");
3512+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_4*4]);
3513+ dw_value = *addr;
3514+
3515+ while (WTBL_LMAC_DW4[i].name) {
3516+ if (WTBL_LMAC_DW4[i].shift == NO_SHIFT_DEFINE)
3517+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW4[i].name,
3518+ (dw_value & WTBL_LMAC_DW4[i].mask) ? 1 : 0);
3519+ else
3520+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW4[i].name,
3521+ (dw_value & WTBL_LMAC_DW4[i].mask) >> WTBL_LMAC_DW4[i].shift);
3522+ i++;
3523+ }
3524+}
3525+
3526+static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = {
3527+ {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false},
3528+ {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false},
3529+ {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false},
3530+ {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false},
3531+ {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true},
3532+ {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false},
3533+ {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false},
3534+ {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false},
3535+ {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true},
3536+ {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false},
3537+ {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false},
3538+ {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false},
3539+ {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false},
3540+ {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false},
3541+ {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true},
3542+ {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false},
3543+ {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false},
3544+ {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true},
3545+ {NULL,}
3546+};
3547+
3548+static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl)
3549+{
3550+ u32 *addr = 0;
3551+ u32 dw_value = 0;
3552+ u16 i = 0;
3553+
3554+ /* LMAC WTBL DW 5 */
3555+ seq_printf(s, "\t\n");
3556+ seq_printf(s, "LWTBL DW 5\n");
3557+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]);
3558+ dw_value = *addr;
3559+
3560+ while (WTBL_LMAC_DW5[i].name) {
3561+ if (WTBL_LMAC_DW5[i].shift == NO_SHIFT_DEFINE)
3562+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW5[i].name,
3563+ (dw_value & WTBL_LMAC_DW5[i].mask) ? 1 : 0);
3564+ else
3565+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW5[i].name,
3566+ (dw_value & WTBL_LMAC_DW5[i].mask) >> WTBL_LMAC_DW5[i].shift);
3567+ i++;
3568+ }
3569+}
3570+
3571+static const struct berse_wtbl_parse WTBL_LMAC_DW6[] = {
3572+ {"CBRN", WF_LWTBL_CBRN_MASK, WF_LWTBL_CBRN_SHIFT, false},
3573+ {"DBNSS_EN", WF_LWTBL_DBNSS_EN_MASK, NO_SHIFT_DEFINE, false},
3574+ {"BAF_EN", WF_LWTBL_BAF_EN_MASK, NO_SHIFT_DEFINE, false},
3575+ {"RDGBA", WF_LWTBL_RDGBA_MASK, NO_SHIFT_DEFINE, false},
3576+ {"RDG", WF_LWTBL_R_MASK, NO_SHIFT_DEFINE, false},
3577+ {"SPE_IDX", WF_LWTBL_SPE_IDX_MASK, WF_LWTBL_SPE_IDX_SHIFT, true},
3578+ {"G2", WF_LWTBL_G2_MASK, NO_SHIFT_DEFINE, false},
3579+ {"G4", WF_LWTBL_G4_MASK, NO_SHIFT_DEFINE, false},
3580+ {"G8", WF_LWTBL_G8_MASK, NO_SHIFT_DEFINE, false},
3581+ {"G16", WF_LWTBL_G16_MASK, NO_SHIFT_DEFINE, true},
3582+ {"G2_LTF", WF_LWTBL_G2_LTF_MASK, WF_LWTBL_G2_LTF_SHIFT, false},
3583+ {"G4_LTF", WF_LWTBL_G4_LTF_MASK, WF_LWTBL_G4_LTF_SHIFT, false},
3584+ {"G8_LTF", WF_LWTBL_G8_LTF_MASK, WF_LWTBL_G8_LTF_SHIFT, false},
3585+ {"G16_LTF", WF_LWTBL_G16_LTF_MASK, WF_LWTBL_G16_LTF_SHIFT, true},
3586+ {"G2_HE", WF_LWTBL_G2_HE_MASK, WF_LWTBL_G2_HE_SHIFT, false},
3587+ {"G4_HE", WF_LWTBL_G4_HE_MASK, WF_LWTBL_G4_HE_SHIFT, false},
3588+ {"G8_HE", WF_LWTBL_G8_HE_MASK, WF_LWTBL_G8_HE_SHIFT, false},
3589+ {"G16_HE", WF_LWTBL_G16_HE_MASK, WF_LWTBL_G16_HE_SHIFT, true},
3590+ {NULL,}
3591+};
3592+
3593+static void parse_fmac_lwtbl_dw6(struct seq_file *s, u8 *lwtbl)
3594+{
3595+ u32 *addr = 0;
3596+ u32 dw_value = 0;
3597+ u16 i = 0;
3598+
3599+ /* LMAC WTBL DW 6 */
3600+ seq_printf(s, "\t\n");
3601+ seq_printf(s, "LWTBL DW 6\n");
3602+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_6*4]);
3603+ dw_value = *addr;
3604+
3605+ while (WTBL_LMAC_DW6[i].name) {
3606+ if (WTBL_LMAC_DW6[i].shift == NO_SHIFT_DEFINE)
3607+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW6[i].name,
3608+ (dw_value & WTBL_LMAC_DW6[i].mask) ? 1 : 0);
3609+ else
3610+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW6[i].name,
3611+ (dw_value & WTBL_LMAC_DW6[i].mask) >> WTBL_LMAC_DW6[i].shift);
3612+ i++;
3613+ }
3614+}
3615+
3616+static void parse_fmac_lwtbl_dw7(struct seq_file *s, u8 *lwtbl)
3617+{
3618+ u32 *addr = 0;
3619+ u32 dw_value = 0;
3620+ int i = 0;
3621+
3622+ /* LMAC WTBL DW 7 */
3623+ seq_printf(s, "\t\n");
3624+ seq_printf(s, "LWTBL DW 7\n");
3625+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_7*4]);
3626+ dw_value = *addr;
3627+
3628+ for (i = 0; i < 8; i++) {
3629+ seq_printf(s, "\tBA_WIN_SIZE%u:%lu\n", i, ((dw_value & BITS(i*4, i*4+3)) >> i*4));
3630+ }
3631+}
3632+
3633+static const struct berse_wtbl_parse WTBL_LMAC_DW8[] = {
3634+ {"RTS_FAIL_CNT_AC0", WF_LWTBL_AC0_RTS_FAIL_CNT_MASK, WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT, false},
3635+ {"AC1", WF_LWTBL_AC1_RTS_FAIL_CNT_MASK, WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT, false},
3636+ {"AC2", WF_LWTBL_AC2_RTS_FAIL_CNT_MASK, WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT, false},
3637+ {"AC3", WF_LWTBL_AC3_RTS_FAIL_CNT_MASK, WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT, true},
3638+ {"PARTIAL_AID", WF_LWTBL_PARTIAL_AID_MASK, WF_LWTBL_PARTIAL_AID_SHIFT, false},
3639+ {"CHK_PER", WF_LWTBL_CHK_PER_MASK, NO_SHIFT_DEFINE, true},
3640+ {NULL,}
3641+};
3642+
3643+static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl)
3644+{
3645+ u32 *addr = 0;
3646+ u32 dw_value = 0;
3647+ u16 i = 0;
3648+
3649+ /* LMAC WTBL DW 8 */
3650+ seq_printf(s, "\t\n");
3651+ seq_printf(s, "LWTBL DW 8\n");
3652+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_8*4]);
3653+ dw_value = *addr;
3654+
3655+ while (WTBL_LMAC_DW8[i].name) {
3656+ if (WTBL_LMAC_DW8[i].shift == NO_SHIFT_DEFINE)
3657+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW8[i].name,
3658+ (dw_value & WTBL_LMAC_DW8[i].mask) ? 1 : 0);
3659+ else
3660+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW8[i].name,
3661+ (dw_value & WTBL_LMAC_DW8[i].mask) >> WTBL_LMAC_DW8[i].shift);
3662+ i++;
3663+ }
3664+}
3665+
3666+static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = {
3667+ {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false},
3668+ {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false},
3669+ {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false},
3670+ {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK, NO_SHIFT_DEFINE, true},
3671+ {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false},
3672+ {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true},
3673+ /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */
3674+ {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false},
3675+ {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false},
3676+ {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true},
3677+ {NULL,}
3678+};
3679+
3680+char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"};
3681+
3682+static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl)
3683+{
3684+ u32 *addr = 0;
3685+ u32 dw_value = 0;
3686+ u16 i = 0;
3687+
3688+ /* LMAC WTBL DW 9 */
3689+ seq_printf(s, "\t\n");
3690+ seq_printf(s, "LWTBL DW 9\n");
3691+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_9*4]);
3692+ dw_value = *addr;
3693+
3694+ while (WTBL_LMAC_DW9[i].name) {
3695+ if (WTBL_LMAC_DW9[i].shift == NO_SHIFT_DEFINE)
3696+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW9[i].name,
3697+ (dw_value & WTBL_LMAC_DW9[i].mask) ? 1 : 0);
3698+ else
3699+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW9[i].name,
3700+ (dw_value & WTBL_LMAC_DW9[i].mask) >> WTBL_LMAC_DW9[i].shift);
3701+ i++;
3702+ }
3703+
3704+ /* FCAP parser */
3705+ seq_printf(s, "\t\n");
3706+ seq_printf(s, "FCAP:%s\n", fcap_name[(dw_value & WF_LWTBL_FCAP_MASK) >> WF_LWTBL_FCAP_SHIFT]);
3707+}
3708+
3709+#define HW_TX_RATE_TO_MODE(_x) (((_x) & WTBL_RATE_TX_MODE_MASK) >> WTBL_RATE_TX_MODE_OFFSET)
3710+#define HW_TX_RATE_TO_MCS(_x, _mode) ((_x) & WTBL_RATE_TX_RATE_MASK >> WTBL_RATE_TX_RATE_OFFSET)
3711+#define HW_TX_RATE_TO_NSS(_x) (((_x) & WTBL_RATE_NSTS_MASK) >> WTBL_RATE_NSTS_OFFSET)
3712+#define HW_TX_RATE_TO_STBC(_x) (((_x) & WTBL_RATE_STBC_MASK) >> WTBL_RATE_STBC_OFFSET)
3713+
3714+#define MAX_TX_MODE 16
3715+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
3716+ "N/A", "N/A", "N/A",
3717+ "HE_SU", "HE_EXT_SU", "HE_TRIG", "HE_MU",
3718+ "N/A",
3719+ "EHT_EXT_SU", "EHT_TRIG", "EHT_MU",
3720+ "N/A"};
3721+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong", "N/A", "2Mshort", "5.5Mshort", "11Mshort", "N/A"};
3722+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", "N/A"};
3723+
3724+static char *hw_rate_ofdm_str(uint16_t ofdm_idx)
3725+{
3726+ switch (ofdm_idx) {
3727+ case 11: /* 6M */
3728+ return HW_TX_RATE_OFDM_STR[0];
3729+
3730+ case 15: /* 9M */
3731+ return HW_TX_RATE_OFDM_STR[1];
3732+
3733+ case 10: /* 12M */
3734+ return HW_TX_RATE_OFDM_STR[2];
3735+
3736+ case 14: /* 18M */
3737+ return HW_TX_RATE_OFDM_STR[3];
3738+
3739+ case 9: /* 24M */
3740+ return HW_TX_RATE_OFDM_STR[4];
3741+
3742+ case 13: /* 36M */
3743+ return HW_TX_RATE_OFDM_STR[5];
3744+
3745+ case 8: /* 48M */
3746+ return HW_TX_RATE_OFDM_STR[6];
3747+
3748+ case 12: /* 54M */
3749+ return HW_TX_RATE_OFDM_STR[7];
3750+
3751+ default:
3752+ return HW_TX_RATE_OFDM_STR[8];
3753+ }
3754+}
3755+
3756+static char *hw_rate_str(u8 mode, uint16_t rate_idx)
3757+{
3758+ if (mode == 0)
3759+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
3760+ else if (mode == 1)
3761+ return hw_rate_ofdm_str(rate_idx);
3762+ else
3763+ return "MCS";
3764+}
3765+
3766+static void
3767+parse_rate(struct seq_file *s, uint16_t rate_idx, uint16_t txrate)
3768+{
3769+ uint16_t txmode, mcs, nss, stbc;
3770+
3771+ txmode = HW_TX_RATE_TO_MODE(txrate);
3772+ mcs = HW_TX_RATE_TO_MCS(txrate, txmode);
3773+ nss = HW_TX_RATE_TO_NSS(txrate);
3774+ stbc = HW_TX_RATE_TO_STBC(txrate);
3775+
3776+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
3777+ rate_idx + 1, txrate,
3778+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
3779+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
3780+}
3781+
3782+
3783+static const struct berse_wtbl_parse WTBL_LMAC_DW10[] = {
3784+ {"RATE1", WF_LWTBL_RATE1_MASK, WF_LWTBL_RATE1_SHIFT},
3785+ {"RATE2", WF_LWTBL_RATE2_MASK, WF_LWTBL_RATE2_SHIFT},
3786+ {NULL,}
3787+};
3788+
3789+static void parse_fmac_lwtbl_dw10(struct seq_file *s, u8 *lwtbl)
3790+{
3791+ u32 *addr = 0;
3792+ u32 dw_value = 0;
3793+ u16 i = 0;
3794+
3795+ /* LMAC WTBL DW 10 */
3796+ seq_printf(s, "\t\n");
3797+ seq_printf(s, "LWTBL DW 10\n");
3798+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_1_2*4]);
3799+ dw_value = *addr;
3800+
3801+ while (WTBL_LMAC_DW10[i].name) {
3802+ parse_rate(s, i, (dw_value & WTBL_LMAC_DW10[i].mask) >> WTBL_LMAC_DW10[i].shift);
3803+ i++;
3804+ }
3805+}
3806+
3807+static const struct berse_wtbl_parse WTBL_LMAC_DW11[] = {
3808+ {"RATE3", WF_LWTBL_RATE3_MASK, WF_LWTBL_RATE3_SHIFT},
3809+ {"RATE4", WF_LWTBL_RATE4_MASK, WF_LWTBL_RATE4_SHIFT},
3810+ {NULL,}
3811+};
3812+
3813+static void parse_fmac_lwtbl_dw11(struct seq_file *s, u8 *lwtbl)
3814+{
3815+ u32 *addr = 0;
3816+ u32 dw_value = 0;
3817+ u16 i = 0;
3818+
3819+ /* LMAC WTBL DW 11 */
3820+ seq_printf(s, "\t\n");
3821+ seq_printf(s, "LWTBL DW 11\n");
3822+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_3_4*4]);
3823+ dw_value = *addr;
3824+
3825+ while (WTBL_LMAC_DW11[i].name) {
3826+ parse_rate(s, i+2, (dw_value & WTBL_LMAC_DW11[i].mask) >> WTBL_LMAC_DW11[i].shift);
3827+ i++;
3828+ }
3829+}
3830+
3831+static const struct berse_wtbl_parse WTBL_LMAC_DW12[] = {
3832+ {"RATE5", WF_LWTBL_RATE5_MASK, WF_LWTBL_RATE5_SHIFT},
3833+ {"RATE6", WF_LWTBL_RATE6_MASK, WF_LWTBL_RATE6_SHIFT},
3834+ {NULL,}
3835+};
3836+
3837+static void parse_fmac_lwtbl_dw12(struct seq_file *s, u8 *lwtbl)
3838+{
3839+ u32 *addr = 0;
3840+ u32 dw_value = 0;
3841+ u16 i = 0;
3842+
3843+ /* LMAC WTBL DW 12 */
3844+ seq_printf(s, "\t\n");
3845+ seq_printf(s, "LWTBL DW 12\n");
3846+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_5_6*4]);
3847+ dw_value = *addr;
3848+
3849+ while (WTBL_LMAC_DW12[i].name) {
3850+ parse_rate(s, i+4, (dw_value & WTBL_LMAC_DW12[i].mask) >> WTBL_LMAC_DW12[i].shift);
3851+ i++;
3852+ }
3853+}
3854+
3855+static const struct berse_wtbl_parse WTBL_LMAC_DW13[] = {
3856+ {"RATE7", WF_LWTBL_RATE7_MASK, WF_LWTBL_RATE7_SHIFT},
3857+ {"RATE8", WF_LWTBL_RATE8_MASK, WF_LWTBL_RATE8_SHIFT},
3858+ {NULL,}
3859+};
3860+
3861+static void parse_fmac_lwtbl_dw13(struct seq_file *s, u8 *lwtbl)
3862+{
3863+ u32 *addr = 0;
3864+ u32 dw_value = 0;
3865+ u16 i = 0;
3866+
3867+ /* LMAC WTBL DW 13 */
3868+ seq_printf(s, "\t\n");
3869+ seq_printf(s, "LWTBL DW 13\n");
3870+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_7_8*4]);
3871+ dw_value = *addr;
3872+
3873+ while (WTBL_LMAC_DW13[i].name) {
3874+ parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW13[i].mask) >> WTBL_LMAC_DW13[i].shift);
3875+ i++;
3876+ }
3877+}
3878+
3879+static const struct berse_wtbl_parse WTBL_LMAC_DW14_BMC[] = {
3880+ {"CIPHER_IGTK", WF_LWTBL_CIPHER_SUIT_IGTK_MASK, WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT, false},
3881+ {"CIPHER_BIGTK", WF_LWTBL_CIPHER_SUIT_BIGTK_MASK, WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT, true},
3882+ {NULL,}
3883+};
3884+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3885+static const struct berse_wtbl_parse WTBL_LMAC_DW14[] = {
3886+ {"RATE1_TX_CNT", WF_LWTBL_RATE1_TX_CNT_MASK, WF_LWTBL_RATE1_TX_CNT_SHIFT, false},
3887+ {"RATE1_FAIL_CNT", WF_LWTBL_RATE1_FAIL_CNT_MASK, WF_LWTBL_RATE1_FAIL_CNT_SHIFT, true},
3888+ {NULL,}
3889+};
3890+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3891+static void parse_fmac_lwtbl_dw14(struct seq_file *s, u8 *lwtbl)
3892+{
3893+ u32 *addr, *muar_addr = 0;
3894+ u32 dw_value, muar_dw_value = 0;
3895+ u16 i = 0;
3896+
3897+ /* DUMP DW14 for BMC entry only */
3898+ muar_addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
3899+ muar_dw_value = *muar_addr;
3900+ if (((muar_dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT)
3901+ == MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
3902+ /* LMAC WTBL DW 14 */
3903+ seq_printf(s, "\t\n");
3904+ seq_printf(s, "LWTBL DW 14\n");
3905+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
3906+ dw_value = *addr;
3907+
3908+ while (WTBL_LMAC_DW14_BMC[i].name) {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3909+ if (WTBL_LMAC_DW14_BMC[i].shift == NO_SHIFT_DEFINE)
3910+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW14_BMC[i].name,
3911+ (dw_value & WTBL_LMAC_DW14_BMC[i].mask) ? 1 : 0);
3912+ else
3913+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW14_BMC[i].name,
3914+ (dw_value & WTBL_LMAC_DW14_BMC[i].mask) >> WTBL_LMAC_DW14_BMC[i].shift);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3915+ i++;
3916+ }
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3917+ } else {
3918+ seq_printf(s, "\t\n");
3919+ seq_printf(s, "LWTBL DW 14\n");
3920+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
3921+ dw_value = *addr;
3922+
3923+ while (WTBL_LMAC_DW14[i].name) {
3924+ if (WTBL_LMAC_DW14[i].shift == NO_SHIFT_DEFINE)
3925+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW14[i].name,
3926+ (dw_value & WTBL_LMAC_DW14[i].mask) ? 1 : 0);
3927+ else
3928+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW14[i].name,
3929+ (dw_value & WTBL_LMAC_DW14[i].mask) >> WTBL_LMAC_DW14[i].shift);
3930+ i++;
3931+ }
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3932+ }
3933+}
3934+
3935+static const struct berse_wtbl_parse WTBL_LMAC_DW28[] = {
3936+ {"RELATED_IDX0", WF_LWTBL_RELATED_IDX0_MASK, WF_LWTBL_RELATED_IDX0_SHIFT, false},
3937+ {"RELATED_BAND0", WF_LWTBL_RELATED_BAND0_MASK, WF_LWTBL_RELATED_BAND0_SHIFT, false},
3938+ {"PRI_MLD_BAND", WF_LWTBL_PRIMARY_MLD_BAND_MASK, WF_LWTBL_PRIMARY_MLD_BAND_SHIFT, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3939+ {"RELATED_IDX1", WF_LWTBL_RELATED_IDX1_MASK, WF_LWTBL_RELATED_IDX1_SHIFT, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3940+ {"RELATED_BAND1", WF_LWTBL_RELATED_BAND1_MASK, WF_LWTBL_RELATED_BAND1_SHIFT, false},
3941+ {"SEC_MLD_BAND", WF_LWTBL_SECONDARY_MLD_BAND_MASK, WF_LWTBL_SECONDARY_MLD_BAND_SHIFT, true},
3942+ {NULL,}
3943+};
3944+
3945+static void parse_fmac_lwtbl_dw28(struct seq_file *s, u8 *lwtbl)
3946+{
3947+ u32 *addr = 0;
3948+ u32 dw_value = 0;
3949+ u16 i = 0;
3950+
3951+ /* LMAC WTBL DW 28 */
3952+ seq_printf(s, "\t\n");
3953+ seq_printf(s, "LWTBL DW 28\n");
3954+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_1*4]);
3955+ dw_value = *addr;
3956+
3957+ while (WTBL_LMAC_DW28[i].name) {
3958+ if (WTBL_LMAC_DW28[i].shift == NO_SHIFT_DEFINE)
3959+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW28[i].name,
3960+ (dw_value & WTBL_LMAC_DW28[i].mask) ? 1 : 0);
3961+ else
3962+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW28[i].name,
3963+ (dw_value & WTBL_LMAC_DW28[i].mask) >>
3964+ WTBL_LMAC_DW28[i].shift);
3965+ i++;
3966+ }
3967+}
3968+
3969+static const struct berse_wtbl_parse WTBL_LMAC_DW29[] = {
3970+ {"DISPATCH_POLICY_MLD_TID0", WF_LWTBL_DISPATCH_POLICY0_MASK, WF_LWTBL_DISPATCH_POLICY0_SHIFT, false},
3971+ {"MLD_TID1", WF_LWTBL_DISPATCH_POLICY1_MASK, WF_LWTBL_DISPATCH_POLICY1_SHIFT, false},
3972+ {"MLD_TID2", WF_LWTBL_DISPATCH_POLICY2_MASK, WF_LWTBL_DISPATCH_POLICY2_SHIFT, false},
3973+ {"MLD_TID3", WF_LWTBL_DISPATCH_POLICY3_MASK, WF_LWTBL_DISPATCH_POLICY3_SHIFT, true},
3974+ {"MLD_TID4", WF_LWTBL_DISPATCH_POLICY4_MASK, WF_LWTBL_DISPATCH_POLICY4_SHIFT, false},
3975+ {"MLD_TID5", WF_LWTBL_DISPATCH_POLICY5_MASK, WF_LWTBL_DISPATCH_POLICY5_SHIFT, false},
3976+ {"MLD_TID6", WF_LWTBL_DISPATCH_POLICY6_MASK, WF_LWTBL_DISPATCH_POLICY6_SHIFT, false},
3977+ {"MLD_TID7", WF_LWTBL_DISPATCH_POLICY7_MASK, WF_LWTBL_DISPATCH_POLICY7_SHIFT, true},
3978+ {"OMLD_ID", WF_LWTBL_OWN_MLD_ID_MASK, WF_LWTBL_OWN_MLD_ID_SHIFT, false},
3979+ {"EMLSR0", WF_LWTBL_EMLSR0_MASK, NO_SHIFT_DEFINE, false},
3980+ {"EMLMR0", WF_LWTBL_EMLMR0_MASK, NO_SHIFT_DEFINE, false},
3981+ {"EMLSR1", WF_LWTBL_EMLSR1_MASK, NO_SHIFT_DEFINE, false},
3982+ {"EMLMR1", WF_LWTBL_EMLMR1_MASK, NO_SHIFT_DEFINE, true},
3983+ {"EMLSR2", WF_LWTBL_EMLSR2_MASK, NO_SHIFT_DEFINE, false},
3984+ {"EMLMR2", WF_LWTBL_EMLMR2_MASK, NO_SHIFT_DEFINE, false},
3985+ {"STR_BITMAP", WF_LWTBL_STR_BITMAP_MASK, WF_LWTBL_STR_BITMAP_SHIFT, true},
3986+ {NULL,}
3987+};
3988+
3989+static void parse_fmac_lwtbl_dw29(struct seq_file *s, u8 *lwtbl)
3990+{
3991+ u32 *addr = 0;
3992+ u32 dw_value = 0;
3993+ u16 i = 0;
3994+
3995+ /* LMAC WTBL DW 29 */
3996+ seq_printf(s, "\t\n");
3997+ seq_printf(s, "LWTBL DW 29\n");
3998+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_2*4]);
3999+ dw_value = *addr;
4000+
4001+ while (WTBL_LMAC_DW29[i].name) {
4002+ if (WTBL_LMAC_DW29[i].shift == NO_SHIFT_DEFINE)
4003+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW29[i].name,
4004+ (dw_value & WTBL_LMAC_DW29[i].mask) ? 1 : 0);
4005+ else
4006+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW29[i].name,
4007+ (dw_value & WTBL_LMAC_DW29[i].mask) >>
4008+ WTBL_LMAC_DW29[i].shift);
4009+ i++;
4010+ }
4011+}
4012+
4013+static const struct berse_wtbl_parse WTBL_LMAC_DW30[] = {
4014+ {"DISPATCH_ORDER", WF_LWTBL_DISPATCH_ORDER_MASK, WF_LWTBL_DISPATCH_ORDER_SHIFT, false},
4015+ {"DISPATCH_RATIO", WF_LWTBL_DISPATCH_RATIO_MASK, WF_LWTBL_DISPATCH_RATIO_SHIFT, false},
4016+ {"LINK_MGF", WF_LWTBL_LINK_MGF_MASK, WF_LWTBL_LINK_MGF_SHIFT, true},
4017+ {NULL,}
4018+};
4019+
4020+static void parse_fmac_lwtbl_dw30(struct seq_file *s, u8 *lwtbl)
4021+{
4022+ u32 *addr = 0;
4023+ u32 dw_value = 0;
4024+ u16 i = 0;
4025+
4026+ /* LMAC WTBL DW 30 */
4027+ seq_printf(s, "\t\n");
4028+ seq_printf(s, "LWTBL DW 30\n");
4029+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_3*4]);
4030+ dw_value = *addr;
4031+
4032+
4033+ while (WTBL_LMAC_DW30[i].name) {
4034+ if (WTBL_LMAC_DW30[i].shift == NO_SHIFT_DEFINE)
4035+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW30[i].name,
4036+ (dw_value & WTBL_LMAC_DW30[i].mask) ? 1 : 0);
4037+ else
4038+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW30[i].name,
4039+ (dw_value & WTBL_LMAC_DW30[i].mask) >> WTBL_LMAC_DW30[i].shift);
4040+ i++;
4041+ }
4042+}
4043+
4044+static const struct berse_wtbl_parse WTBL_LMAC_DW31[] = {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4045+ {"BFTX_TB", WF_LWTBL_BFTX_TB_MASK, NO_SHIFT_DEFINE, false},
4046+ {"DROP", WF_LWTBL_DROP_MASK, NO_SHIFT_DEFINE, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4047+ {"CASCAD", WF_LWTBL_CASCAD_MASK, NO_SHIFT_DEFINE, false},
4048+ {"ALL_ACK", WF_LWTBL_ALL_ACK_MASK, NO_SHIFT_DEFINE, false},
4049+ {"MPDU_SIZE", WF_LWTBL_MPDU_SIZE_MASK, WF_LWTBL_MPDU_SIZE_SHIFT, false},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4050+ {"RXD_DUP_MODE", WF_LWTBL_RXD_DUP_MODE_MASK, WF_LWTBL_RXD_DUP_MODE_SHIFT, true},
4051+ {"ACK_EN", WF_LWTBL_ACK_EN_MASK, NO_SHIFT_DEFINE, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4052+ {NULL,}
4053+};
4054+
4055+static void parse_fmac_lwtbl_dw31(struct seq_file *s, u8 *lwtbl)
4056+{
4057+ u32 *addr = 0;
4058+ u32 dw_value = 0;
4059+ u16 i = 0;
4060+
4061+ /* LMAC WTBL DW 31 */
4062+ seq_printf(s, "\t\n");
4063+ seq_printf(s, "LWTBL DW 31\n");
4064+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RESP_INFO_DW_31*4]);
4065+ dw_value = *addr;
4066+
4067+ while (WTBL_LMAC_DW31[i].name) {
4068+ if (WTBL_LMAC_DW31[i].shift == NO_SHIFT_DEFINE)
4069+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW31[i].name,
4070+ (dw_value & WTBL_LMAC_DW31[i].mask) ? 1 : 0);
4071+ else
4072+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW31[i].name,
4073+ (dw_value & WTBL_LMAC_DW31[i].mask) >>
4074+ WTBL_LMAC_DW31[i].shift);
4075+ i++;
4076+ }
4077+}
4078+
4079+static const struct berse_wtbl_parse WTBL_LMAC_DW32[] = {
4080+ {"OM_INFO", WF_LWTBL_OM_INFO_MASK, WF_LWTBL_OM_INFO_SHIFT, false},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4081+ {"OM_INFO_EHT", WF_LWTBL_OM_INFO_EHT_MASK, WF_LWTBL_OM_INFO_EHT_SHIFT, false},
4082+ {"RXD_DUP_FOR_OM_CHG", WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK, NO_SHIFT_DEFINE, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4083+ {"RXD_DUP_WHITE_LIST", WF_LWTBL_RXD_DUP_WHITE_LIST_MASK, WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4084+ {NULL,}
4085+};
4086+
4087+static void parse_fmac_lwtbl_dw32(struct seq_file *s, u8 *lwtbl)
4088+{
4089+ u32 *addr = 0;
4090+ u32 dw_value = 0;
4091+ u16 i = 0;
4092+
4093+ /* LMAC WTBL DW 32 */
4094+ seq_printf(s, "\t\n");
4095+ seq_printf(s, "LWTBL DW 32\n");
4096+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_DUP_INFO_DW_32*4]);
4097+ dw_value = *addr;
4098+
4099+ while (WTBL_LMAC_DW32[i].name) {
4100+ if (WTBL_LMAC_DW32[i].shift == NO_SHIFT_DEFINE)
4101+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW32[i].name,
4102+ (dw_value & WTBL_LMAC_DW32[i].mask) ? 1 : 0);
4103+ else
4104+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW32[i].name,
4105+ (dw_value & WTBL_LMAC_DW32[i].mask) >>
4106+ WTBL_LMAC_DW32[i].shift);
4107+ i++;
4108+ }
4109+}
4110+
4111+static const struct berse_wtbl_parse WTBL_LMAC_DW33[] = {
4112+ {"USER_RSSI", WF_LWTBL_USER_RSSI_MASK, WF_LWTBL_USER_RSSI_SHIFT, false},
4113+ {"USER_SNR", WF_LWTBL_USER_SNR_MASK, WF_LWTBL_USER_SNR_SHIFT, false},
4114+ {"RAPID_REACTION_RATE", WF_LWTBL_RAPID_REACTION_RATE_MASK, WF_LWTBL_RAPID_REACTION_RATE_SHIFT, true},
4115+ {"HT_AMSDU(Read Only)", WF_LWTBL_HT_AMSDU_MASK, NO_SHIFT_DEFINE, false},
4116+ {"AMSDU_CROSS_LG(Read Only)", WF_LWTBL_AMSDU_CROSS_LG_MASK, NO_SHIFT_DEFINE, true},
4117+ {NULL,}
4118+};
4119+
4120+static void parse_fmac_lwtbl_dw33(struct seq_file *s, u8 *lwtbl)
4121+{
4122+ u32 *addr = 0;
4123+ u32 dw_value = 0;
4124+ u16 i = 0;
4125+
4126+ /* LMAC WTBL DW 33 */
4127+ seq_printf(s, "\t\n");
4128+ seq_printf(s, "LWTBL DW 33\n");
4129+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_1*4]);
4130+ dw_value = *addr;
4131+
4132+ while (WTBL_LMAC_DW33[i].name) {
4133+ if (WTBL_LMAC_DW33[i].shift == NO_SHIFT_DEFINE)
4134+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW33[i].name,
4135+ (dw_value & WTBL_LMAC_DW33[i].mask) ? 1 : 0);
4136+ else
4137+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW33[i].name,
4138+ (dw_value & WTBL_LMAC_DW33[i].mask) >>
4139+ WTBL_LMAC_DW33[i].shift);
4140+ i++;
4141+ }
4142+}
4143+
4144+static const struct berse_wtbl_parse WTBL_LMAC_DW34[] = {
4145+ {"RESP_RCPI0", WF_LWTBL_RESP_RCPI0_MASK, WF_LWTBL_RESP_RCPI0_SHIFT, false},
4146+ {"RCPI1", WF_LWTBL_RESP_RCPI1_MASK, WF_LWTBL_RESP_RCPI1_SHIFT, false},
4147+ {"RCPI2", WF_LWTBL_RESP_RCPI2_MASK, WF_LWTBL_RESP_RCPI2_SHIFT, false},
4148+ {"RCPI3", WF_LWTBL_RESP_RCPI3_MASK, WF_LWTBL_RESP_RCPI3_SHIFT, true},
4149+ {NULL,}
4150+};
4151+
4152+static void parse_fmac_lwtbl_dw34(struct seq_file *s, u8 *lwtbl)
4153+{
4154+ u32 *addr = 0;
4155+ u32 dw_value = 0;
4156+ u16 i = 0;
4157+
4158+ /* LMAC WTBL DW 34 */
4159+ seq_printf(s, "\t\n");
4160+ seq_printf(s, "LWTBL DW 34\n");
4161+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_2*4]);
4162+ dw_value = *addr;
4163+
4164+
4165+ while (WTBL_LMAC_DW34[i].name) {
4166+ if (WTBL_LMAC_DW34[i].shift == NO_SHIFT_DEFINE)
4167+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW34[i].name,
4168+ (dw_value & WTBL_LMAC_DW34[i].mask) ? 1 : 0);
4169+ else
4170+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW34[i].name,
4171+ (dw_value & WTBL_LMAC_DW34[i].mask) >>
4172+ WTBL_LMAC_DW34[i].shift);
4173+ i++;
4174+ }
4175+}
4176+
4177+static const struct berse_wtbl_parse WTBL_LMAC_DW35[] = {
4178+ {"SNR 0", WF_LWTBL_SNR_RX0_MASK, WF_LWTBL_SNR_RX0_SHIFT, false},
4179+ {"SNR 1", WF_LWTBL_SNR_RX1_MASK, WF_LWTBL_SNR_RX1_SHIFT, false},
4180+ {"SNR 2", WF_LWTBL_SNR_RX2_MASK, WF_LWTBL_SNR_RX2_SHIFT, false},
4181+ {"SNR 3", WF_LWTBL_SNR_RX3_MASK, WF_LWTBL_SNR_RX3_SHIFT, true},
4182+ {NULL,}
4183+};
4184+
4185+static void parse_fmac_lwtbl_dw35(struct seq_file *s, u8 *lwtbl)
4186+{
4187+ u32 *addr = 0;
4188+ u32 dw_value = 0;
4189+ u16 i = 0;
4190+
4191+ /* LMAC WTBL DW 35 */
4192+ seq_printf(s, "\t\n");
4193+ seq_printf(s, "LWTBL DW 35\n");
4194+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_3*4]);
4195+ dw_value = *addr;
4196+
4197+
4198+ while (WTBL_LMAC_DW35[i].name) {
4199+ if (WTBL_LMAC_DW35[i].shift == NO_SHIFT_DEFINE)
4200+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW35[i].name,
4201+ (dw_value & WTBL_LMAC_DW35[i].mask) ? 1 : 0);
4202+ else
4203+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW35[i].name,
4204+ (dw_value & WTBL_LMAC_DW35[i].mask) >>
4205+ WTBL_LMAC_DW35[i].shift);
4206+ i++;
4207+ }
4208+}
4209+
4210+static void parse_fmac_lwtbl_rx_stats(struct seq_file *s, u8 *lwtbl)
4211+{
4212+ parse_fmac_lwtbl_dw33(s, lwtbl);
4213+ parse_fmac_lwtbl_dw34(s, lwtbl);
4214+ parse_fmac_lwtbl_dw35(s, lwtbl);
4215+}
4216+
4217+static void parse_fmac_lwtbl_mlo_info(struct seq_file *s, u8 *lwtbl)
4218+{
4219+ parse_fmac_lwtbl_dw28(s, lwtbl);
4220+ parse_fmac_lwtbl_dw29(s, lwtbl);
4221+ parse_fmac_lwtbl_dw30(s, lwtbl);
4222+}
4223+
4224+static const struct berse_wtbl_parse WTBL_UMAC_DW9[] = {
4225+ {"RELATED_IDX0", WF_UWTBL_RELATED_IDX0_MASK, WF_UWTBL_RELATED_IDX0_SHIFT, false},
4226+ {"RELATED_BAND0", WF_UWTBL_RELATED_BAND0_MASK, WF_UWTBL_RELATED_BAND0_SHIFT, false},
4227+ {"PRI_MLD_BAND", WF_UWTBL_PRIMARY_MLD_BAND_MASK, WF_UWTBL_PRIMARY_MLD_BAND_SHIFT, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4228+ {"RELATED_IDX1", WF_UWTBL_RELATED_IDX1_MASK, WF_UWTBL_RELATED_IDX1_SHIFT, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4229+ {"RELATED_BAND1", WF_UWTBL_RELATED_BAND1_MASK, WF_UWTBL_RELATED_BAND1_SHIFT, false},
4230+ {"SEC_MLD_BAND", WF_UWTBL_SECONDARY_MLD_BAND_MASK, WF_UWTBL_SECONDARY_MLD_BAND_SHIFT, true},
4231+ {NULL,}
4232+};
4233+
4234+static void parse_fmac_uwtbl_mlo_info(struct seq_file *s, u8 *uwtbl)
4235+{
4236+ u32 *addr = 0;
4237+ u32 dw_value = 0;
4238+ u16 i = 0;
4239+
4240+ seq_printf(s, "\t\n");
4241+ seq_printf(s, "MldAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
4242+ uwtbl[4], uwtbl[5], uwtbl[6], uwtbl[7], uwtbl[0], uwtbl[1]);
4243+
4244+ /* UMAC WTBL DW 0 */
4245+ seq_printf(s, "\t\n");
4246+ seq_printf(s, "UWTBL DW 0\n");
4247+ addr = (u32 *)&(uwtbl[WF_UWTBL_OWN_MLD_ID_DW*4]);
4248+ dw_value = *addr;
4249+
4250+ seq_printf(s, "\t%s:%u\n", "OMLD_ID",
4251+ (dw_value & WF_UWTBL_OWN_MLD_ID_MASK) >> WF_UWTBL_OWN_MLD_ID_SHIFT);
4252+
4253+ /* UMAC WTBL DW 9 */
4254+ seq_printf(s, "\t\n");
4255+ seq_printf(s, "UWTBL DW 9\n");
4256+ addr = (u32 *)&(uwtbl[WF_UWTBL_RELATED_IDX0_DW*4]);
4257+ dw_value = *addr;
4258+
4259+ while (WTBL_UMAC_DW9[i].name) {
4260+
4261+ if (WTBL_UMAC_DW9[i].shift == NO_SHIFT_DEFINE)
4262+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW9[i].name,
4263+ (dw_value & WTBL_UMAC_DW9[i].mask) ? 1 : 0);
4264+ else
4265+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW9[i].name,
4266+ (dw_value & WTBL_UMAC_DW9[i].mask) >>
4267+ WTBL_UMAC_DW9[i].shift);
4268+ i++;
4269+ }
4270+}
4271+
4272+static bool
4273+is_wtbl_bigtk_exist(u8 *lwtbl)
4274+{
4275+ u32 *addr = 0;
4276+ u32 dw_value = 0;
4277+
4278+ addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
4279+ dw_value = *addr;
4280+ if (((dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) ==
4281+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
4282+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_BIGTK_DW*4]);
4283+ dw_value = *addr;
4284+ if (((dw_value & WF_LWTBL_CIPHER_SUIT_BIGTK_MASK) >>
4285+ WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT) != IGTK_CIPHER_SUIT_NONE)
4286+ return true;
4287+ }
4288+
4289+ return false;
4290+}
4291+
4292+static const struct berse_wtbl_parse WTBL_UMAC_DW2[] = {
4293+ {"PN0", WTBL_PN0_MASK, WTBL_PN0_OFFSET, false},
4294+ {"PN1", WTBL_PN1_MASK, WTBL_PN1_OFFSET, false},
4295+ {"PN2", WTBL_PN2_MASK, WTBL_PN2_OFFSET, true},
4296+ {"PN3", WTBL_PN3_MASK, WTBL_PN3_OFFSET, false},
4297+ {NULL,}
4298+};
4299+
4300+static const struct berse_wtbl_parse WTBL_UMAC_DW3[] = {
4301+ {"PN4", WTBL_PN4_MASK, WTBL_PN4_OFFSET, false},
4302+ {"PN5", WTBL_PN5_MASK, WTBL_PN5_OFFSET, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4303+ {"COM_SN", WF_UWTBL_COM_SN_MASK, WF_UWTBL_COM_SN_SHIFT, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4304+ {NULL,}
4305+};
4306+
4307+static const struct berse_wtbl_parse WTBL_UMAC_DW4_BIPN[] = {
4308+ {"BIPN0", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false},
4309+ {"BIPN1", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, false},
4310+ {"BIPN2", WTBL_BIPN2_MASK, WTBL_BIPN2_OFFSET, true},
4311+ {"BIPN3", WTBL_BIPN3_MASK, WTBL_BIPN3_OFFSET, false},
4312+ {NULL,}
4313+};
4314+
4315+static const struct berse_wtbl_parse WTBL_UMAC_DW5_BIPN[] = {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4316+ {"BIPN4", WTBL_BIPN4_MASK, WTBL_BIPN4_OFFSET, false},
4317+ {"BIPN5", WTBL_BIPN5_MASK, WTBL_BIPN5_OFFSET, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4318+ {NULL,}
4319+};
4320+
4321+static void parse_fmac_uwtbl_pn(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4322+{
4323+ u32 *addr = 0;
4324+ u32 dw_value = 0;
4325+ u16 i = 0;
4326+
4327+ seq_printf(s, "\t\n");
4328+ seq_printf(s, "UWTBL PN\n");
4329+
4330+ /* UMAC WTBL DW 2/3 */
4331+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_31_0__DW*4]);
4332+ dw_value = *addr;
4333+
4334+ while (WTBL_UMAC_DW2[i].name) {
4335+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW2[i].name,
4336+ (dw_value & WTBL_UMAC_DW2[i].mask) >>
4337+ WTBL_UMAC_DW2[i].shift);
4338+ i++;
4339+ }
4340+
4341+ i = 0;
4342+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_47_32__DW*4]);
4343+ dw_value = *addr;
4344+
4345+ while (WTBL_UMAC_DW3[i].name) {
4346+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW3[i].name,
4347+ (dw_value & WTBL_UMAC_DW3[i].mask) >>
4348+ WTBL_UMAC_DW3[i].shift);
4349+ i++;
4350+ }
4351+
4352+
4353+ /* UMAC WTBL DW 4/5 for BIGTK */
4354+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
4355+ i = 0;
4356+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_31_0__DW*4]);
4357+ dw_value = *addr;
4358+
4359+ while (WTBL_UMAC_DW4_BIPN[i].name) {
4360+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW4_BIPN[i].name,
4361+ (dw_value & WTBL_UMAC_DW4_BIPN[i].mask) >>
4362+ WTBL_UMAC_DW4_BIPN[i].shift);
4363+ i++;
4364+ }
4365+
4366+ i = 0;
4367+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_47_32__DW*4]);
4368+ dw_value = *addr;
4369+
4370+ while (WTBL_UMAC_DW5_BIPN[i].name) {
4371+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW5_BIPN[i].name,
4372+ (dw_value & WTBL_UMAC_DW5_BIPN[i].mask) >>
4373+ WTBL_UMAC_DW5_BIPN[i].shift);
4374+ i++;
4375+ }
4376+ }
4377+}
4378+
4379+static void parse_fmac_uwtbl_sn(struct seq_file *s, u8 *uwtbl)
4380+{
4381+ u32 *addr = 0;
4382+ u32 u2SN = 0;
4383+
4384+ /* UMAC WTBL DW SN part */
4385+ seq_printf(s, "\t\n");
4386+ seq_printf(s, "UWTBL SN\n");
4387+
4388+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID0_SN_DW*4]);
4389+ u2SN = ((*addr) & WF_UWTBL_TID0_SN_MASK) >> WF_UWTBL_TID0_SN_SHIFT;
4390+ seq_printf(s, "\t%s:%u\n", "TID0_AC0_SN", u2SN);
4391+
4392+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID1_SN_DW*4]);
4393+ u2SN = ((*addr) & WF_UWTBL_TID1_SN_MASK) >> WF_UWTBL_TID1_SN_SHIFT;
4394+ seq_printf(s, "\t%s:%u\n", "TID1_AC1_SN", u2SN);
4395+
4396+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_7_0__DW*4]);
4397+ u2SN = ((*addr) & WF_UWTBL_TID2_SN_7_0__MASK) >>
4398+ WF_UWTBL_TID2_SN_7_0__SHIFT;
4399+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_11_8__DW*4]);
4400+ u2SN |= (((*addr) & WF_UWTBL_TID2_SN_11_8__MASK) >>
4401+ WF_UWTBL_TID2_SN_11_8__SHIFT) << 8;
4402+ seq_printf(s, "\t%s:%u\n", "TID2_AC2_SN", u2SN);
4403+
4404+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID3_SN_DW*4]);
4405+ u2SN = ((*addr) & WF_UWTBL_TID3_SN_MASK) >> WF_UWTBL_TID3_SN_SHIFT;
4406+ seq_printf(s, "\t%s:%u\n", "TID3_AC3_SN", u2SN);
4407+
4408+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID4_SN_DW*4]);
4409+ u2SN = ((*addr) & WF_UWTBL_TID4_SN_MASK) >> WF_UWTBL_TID4_SN_SHIFT;
4410+ seq_printf(s, "\t%s:%u\n", "TID4_SN", u2SN);
4411+
4412+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_3_0__DW*4]);
4413+ u2SN = ((*addr) & WF_UWTBL_TID5_SN_3_0__MASK) >>
4414+ WF_UWTBL_TID5_SN_3_0__SHIFT;
4415+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_11_4__DW*4]);
4416+ u2SN |= (((*addr) & WF_UWTBL_TID5_SN_11_4__MASK) >>
4417+ WF_UWTBL_TID5_SN_11_4__SHIFT) << 4;
4418+ seq_printf(s, "\t%s:%u\n", "TID5_SN", u2SN);
4419+
4420+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID6_SN_DW*4]);
4421+ u2SN = ((*addr) & WF_UWTBL_TID6_SN_MASK) >> WF_UWTBL_TID6_SN_SHIFT;
4422+ seq_printf(s, "\t%s:%u\n", "TID6_SN", u2SN);
4423+
4424+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID7_SN_DW*4]);
4425+ u2SN = ((*addr) & WF_UWTBL_TID7_SN_MASK) >> WF_UWTBL_TID7_SN_SHIFT;
4426+ seq_printf(s, "\t%s:%u\n", "TID7_SN", u2SN);
4427+
4428+ addr = (u32 *)&(uwtbl[WF_UWTBL_COM_SN_DW*4]);
4429+ u2SN = ((*addr) & WF_UWTBL_COM_SN_MASK) >> WF_UWTBL_COM_SN_SHIFT;
4430+ seq_printf(s, "\t%s:%u\n", "COM_SN", u2SN);
4431+}
4432+
4433+static void dump_key_table(
4434+ struct seq_file *s,
4435+ uint16_t keyloc0,
4436+ uint16_t keyloc1,
4437+ uint16_t keyloc2
4438+)
4439+{
4440+#define ONE_KEY_ENTRY_LEN_IN_DW 8
4441+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4442+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
4443+ uint16_t x;
4444+
4445+ seq_printf(s, "\t\n");
4446+ seq_printf(s, "\t%s:%d\n", "keyloc0", keyloc0);
4447+ if (keyloc0 != INVALID_KEY_ENTRY) {
4448+
4449+ /* Don't swap below two lines, halWtblReadRaw will
4450+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4451+ */
4452+ mt7996_wtbl_read_raw(dev, keyloc0,
4453+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4454+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4455+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4456+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4457+ KEYTBL_IDX2BASE(keyloc0, 0));
4458+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4459+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4460+ x,
4461+ keytbl[x * 4 + 3],
4462+ keytbl[x * 4 + 2],
4463+ keytbl[x * 4 + 1],
4464+ keytbl[x * 4]);
4465+ }
4466+ }
4467+
4468+ seq_printf(s, "\t%s:%d\n", "keyloc1", keyloc1);
4469+ if (keyloc1 != INVALID_KEY_ENTRY) {
4470+ /* Don't swap below two lines, halWtblReadRaw will
4471+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4472+ */
4473+ mt7996_wtbl_read_raw(dev, keyloc1,
4474+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4475+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4476+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4477+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4478+ KEYTBL_IDX2BASE(keyloc1, 0));
4479+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4480+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4481+ x,
4482+ keytbl[x * 4 + 3],
4483+ keytbl[x * 4 + 2],
4484+ keytbl[x * 4 + 1],
4485+ keytbl[x * 4]);
4486+ }
4487+ }
4488+
4489+ seq_printf(s, "\t%s:%d\n", "keyloc2", keyloc2);
4490+ if (keyloc2 != INVALID_KEY_ENTRY) {
4491+ /* Don't swap below two lines, halWtblReadRaw will
4492+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4493+ */
4494+ mt7996_wtbl_read_raw(dev, keyloc2,
4495+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4496+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4497+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4498+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4499+ KEYTBL_IDX2BASE(keyloc2, 0));
4500+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4501+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4502+ x,
4503+ keytbl[x * 4 + 3],
4504+ keytbl[x * 4 + 2],
4505+ keytbl[x * 4 + 1],
4506+ keytbl[x * 4]);
4507+ }
4508+ }
4509+}
4510+
4511+static void parse_fmac_uwtbl_key_info(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4512+{
4513+ u32 *addr = 0;
4514+ u32 dw_value = 0;
4515+ uint16_t keyloc0 = INVALID_KEY_ENTRY;
4516+ uint16_t keyloc1 = INVALID_KEY_ENTRY;
4517+ uint16_t keyloc2 = INVALID_KEY_ENTRY;
4518+
4519+ /* UMAC WTBL DW 7 */
4520+ seq_printf(s, "\t\n");
4521+ seq_printf(s, "UWTBL key info\n");
4522+
4523+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC0_DW*4]);
4524+ dw_value = *addr;
4525+ keyloc0 = (dw_value & WF_UWTBL_KEY_LOC0_MASK) >> WF_UWTBL_KEY_LOC0_SHIFT;
4526+ keyloc1 = (dw_value & WF_UWTBL_KEY_LOC1_MASK) >> WF_UWTBL_KEY_LOC1_SHIFT;
4527+
4528+ seq_printf(s, "\t%s:%u/%u\n", "Key Loc 0/1", keyloc0, keyloc1);
4529+
4530+ /* UMAC WTBL DW 6 for BIGTK */
4531+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4532+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC2_DW*4]);
4533+ dw_value = *addr;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4534+ keyloc2 = (dw_value & WF_UWTBL_KEY_LOC2_MASK) >>
4535+ WF_UWTBL_KEY_LOC2_SHIFT;
4536+ seq_printf(s, "\t%s:%u\n", "Key Loc 2", keyloc2);
4537+ }
4538+
4539+ /* Parse KEY link */
4540+ dump_key_table(s, keyloc0, keyloc1, keyloc2);
4541+}
4542+
4543+static const struct berse_wtbl_parse WTBL_UMAC_DW8[] = {
4544+ {"UWTBL_WMM_Q", WF_UWTBL_WMM_Q_MASK, WF_UWTBL_WMM_Q_SHIFT, false},
4545+ {"UWTBL_QOS", WF_UWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
4546+ {"UWTBL_HT_VHT_HE", WF_UWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
4547+ {"UWTBL_HDRT_MODE", WF_UWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, true},
4548+ {NULL,}
4549+};
4550+
4551+static void parse_fmac_uwtbl_msdu_info(struct seq_file *s, u8 *uwtbl)
4552+{
4553+ u32 *addr = 0;
4554+ u32 dw_value = 0;
4555+ u32 amsdu_len = 0;
4556+ u16 i = 0;
4557+
4558+ /* UMAC WTBL DW 8 */
4559+ seq_printf(s, "\t\n");
4560+ seq_printf(s, "UWTBL DW8\n");
4561+
4562+ addr = (u32 *)&(uwtbl[WF_UWTBL_AMSDU_CFG_DW*4]);
4563+ dw_value = *addr;
4564+
4565+ while (WTBL_UMAC_DW8[i].name) {
4566+
4567+ if (WTBL_UMAC_DW8[i].shift == NO_SHIFT_DEFINE)
4568+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW8[i].name,
4569+ (dw_value & WTBL_UMAC_DW8[i].mask) ? 1 : 0);
4570+ else
4571+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW8[i].name,
4572+ (dw_value & WTBL_UMAC_DW8[i].mask) >>
4573+ WTBL_UMAC_DW8[i].shift);
4574+ i++;
4575+ }
4576+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4577+ /* UMAC WTBL DW 8 - SEC_ADDR_MODE */
4578+ addr = (u32 *)&(uwtbl[WF_UWTBL_SEC_ADDR_MODE_DW*4]);
4579+ dw_value = *addr;
4580+ seq_printf(s, "\t%s:%lu\n", "SEC_ADDR_MODE",
4581+ (dw_value & WTBL_SEC_ADDR_MODE_MASK) >> WTBL_SEC_ADDR_MODE_OFFSET);
4582+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4583+ /* UMAC WTBL DW 8 - AMSDU_CFG */
4584+ seq_printf(s, "\t%s:%d\n", "HW AMSDU Enable",
4585+ (dw_value & WTBL_AMSDU_EN_MASK) ? 1 : 0);
4586+
4587+ amsdu_len = (dw_value & WTBL_AMSDU_LEN_MASK) >> WTBL_AMSDU_LEN_OFFSET;
4588+ if (amsdu_len == 0)
4589+ seq_printf(s, "\t%s:invalid (WTBL value=0x%x)\n", "HW AMSDU Len",
4590+ amsdu_len);
4591+ else if (amsdu_len == 1)
4592+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4593+ 1,
4594+ 255,
4595+ amsdu_len);
4596+ else if (amsdu_len == 2)
4597+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4598+ 256,
4599+ 511,
4600+ amsdu_len);
4601+ else if (amsdu_len == 3)
4602+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4603+ 512,
4604+ 767,
4605+ amsdu_len);
4606+ else
4607+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4608+ 256 * (amsdu_len - 1),
4609+ 256 * (amsdu_len - 1) + 255,
4610+ amsdu_len);
4611+
4612+ seq_printf(s, "\t%s:%lu (WTBL value=0x%lx)\n", "HW AMSDU Num",
4613+ ((dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET) + 1,
4614+ (dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET);
4615+}
4616+
4617+static int mt7996_wtbl_read(struct seq_file *s, void *data)
4618+{
4619+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4620+ u8 lwtbl[LWTBL_LEN_IN_DW * 4] = {0};
4621+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
4622+ int x;
4623+
4624+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
4625+ LWTBL_LEN_IN_DW, lwtbl);
4626+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
4627+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4628+ MT_DBG_WTBLON_TOP_WDUCR_ADDR,
4629+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR),
4630+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
4631+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
4632+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
4633+ x,
4634+ lwtbl[x * 4 + 3],
4635+ lwtbl[x * 4 + 2],
4636+ lwtbl[x * 4 + 1],
4637+ lwtbl[x * 4]);
4638+ }
4639+
4640+ /* Parse LWTBL */
4641+ parse_fmac_lwtbl_dw0_1(s, lwtbl);
4642+ parse_fmac_lwtbl_dw2(s, lwtbl);
4643+ parse_fmac_lwtbl_dw3(s, lwtbl);
4644+ parse_fmac_lwtbl_dw4(s, lwtbl);
4645+ parse_fmac_lwtbl_dw5(s, lwtbl);
4646+ parse_fmac_lwtbl_dw6(s, lwtbl);
4647+ parse_fmac_lwtbl_dw7(s, lwtbl);
4648+ parse_fmac_lwtbl_dw8(s, lwtbl);
4649+ parse_fmac_lwtbl_dw9(s, lwtbl);
4650+ parse_fmac_lwtbl_dw10(s, lwtbl);
4651+ parse_fmac_lwtbl_dw11(s, lwtbl);
4652+ parse_fmac_lwtbl_dw12(s, lwtbl);
4653+ parse_fmac_lwtbl_dw13(s, lwtbl);
4654+ parse_fmac_lwtbl_dw14(s, lwtbl);
4655+ parse_fmac_lwtbl_mlo_info(s, lwtbl);
4656+ parse_fmac_lwtbl_dw31(s, lwtbl);
4657+ parse_fmac_lwtbl_dw32(s, lwtbl);
4658+ parse_fmac_lwtbl_rx_stats(s, lwtbl);
4659+
4660+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
4661+ UWTBL_LEN_IN_DW, uwtbl);
4662+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
4663+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4664+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4665+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4666+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
4667+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
4668+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
4669+ x,
4670+ uwtbl[x * 4 + 3],
4671+ uwtbl[x * 4 + 2],
4672+ uwtbl[x * 4 + 1],
4673+ uwtbl[x * 4]);
4674+ }
4675+
4676+ /* Parse UWTBL */
4677+ parse_fmac_uwtbl_mlo_info(s, uwtbl);
4678+ parse_fmac_uwtbl_pn(s, uwtbl, lwtbl);
4679+ parse_fmac_uwtbl_sn(s, uwtbl);
4680+ parse_fmac_uwtbl_key_info(s, uwtbl, lwtbl);
4681+ parse_fmac_uwtbl_msdu_info(s, uwtbl);
4682+
4683+ return 0;
4684+}
4685+
4686+static int mt7996_sta_info(struct seq_file *s, void *data)
4687+{
4688+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4689+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
4690+ u16 i = 0;
4691+
4692+ for (i=0; i < mt7996_wtbl_size(dev); i++) {
4693+ mt7996_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
4694+ LWTBL_LEN_IN_DW, lwtbl);
4695+
4696+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1]) {
4697+ u32 *addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
4698+ u32 dw_value = *addr;
4699+
4700+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x",
4701+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
4702+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[0].name,
4703+ (dw_value & WTBL_LMAC_DW2[0].mask) >> WTBL_LMAC_DW2[0].shift);
4704+ }
4705+ }
4706+
4707+ return 0;
4708+}
4709+
4710+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir)
4711+{
4712+ struct mt7996_dev *dev = phy->dev;
4713+
4714+ mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4715+
4716+ /* agg */
4717+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4718+ mt7996_agginfo_read_band0);
4719+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4720+ mt7996_agginfo_read_band1);
4721+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info2", dir,
4722+ mt7996_agginfo_read_band2);
4723+ /* amsdu */
4724+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4725+ mt7996_amsdu_result_read);
4726+
4727+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4728+ &fops_fw_debug_module);
4729+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4730+ &fops_fw_debug_level);
4731+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4732+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4733+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
4734+ mt7996_dump_version);
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]4735+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wa_info", dir,
4736+ mt7996_fw_wa_info_read);
4737+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
4738+ mt7996_fw_wm_info_read);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4739+
4740+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4741+ mt7996_mibinfo_band0);
4742+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4743+ mt7996_mibinfo_band1);
4744+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info2", dir,
4745+ mt7996_mibinfo_band2);
4746+
4747+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
4748+ mt7996_sta_info);
4749+
4750+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4751+ mt7996_trinfo_read);
4752+
4753+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4754+ mt7996_wtbl_read);
4755+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]4756+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
4757+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4758+ return 0;
4759+}
4760+
4761+#endif
4762diff --git a/mt7996/mtk_mcu.c b/mt7996/mtk_mcu.c
4763new file mode 100644
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]4764index 0000000..e887016
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4765--- /dev/null
4766+++ b/mt7996/mtk_mcu.c
4767@@ -0,0 +1,18 @@
4768+// SPDX-License-Identifier: ISC
4769+/*
4770+ * Copyright (C) 2023 MediaTek Inc.
4771+ */
4772+
4773+#include <linux/firmware.h>
4774+#include <linux/fs.h>
4775+#include "mt7996.h"
4776+#include "mcu.h"
4777+#include "mac.h"
4778+#include "mtk_mcu.h"
4779+
4780+#ifdef CONFIG_MTK_DEBUG
4781+
4782+
4783+
4784+
4785+#endif
4786diff --git a/mt7996/mtk_mcu.h b/mt7996/mtk_mcu.h
4787new file mode 100644
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]4788index 0000000..e741aa2
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4789--- /dev/null
4790+++ b/mt7996/mtk_mcu.h
4791@@ -0,0 +1,16 @@
4792+/* SPDX-License-Identifier: ISC */
4793+/*
4794+ * Copyright (C) 2023 MediaTek Inc.
4795+ */
4796+
4797+#ifndef __MT7996_MTK_MCU_H
4798+#define __MT7996_MTK_MCU_H
4799+
4800+#include "../mt76_connac_mcu.h"
4801+
4802+#ifdef CONFIG_MTK_DEBUG
4803+
4804+
4805+#endif
4806+
4807+#endif
4808diff --git a/tools/fwlog.c b/tools/fwlog.c
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]4809index e5d4a10..3c6a61d 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4810--- a/tools/fwlog.c
4811+++ b/tools/fwlog.c
4812@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4813 return path;
4814 }
4815
4816-static int mt76_set_fwlog_en(const char *phyname, bool en)
4817+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4818 {
4819 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4820
4821@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4822 return 1;
4823 }
4824
4825- fprintf(f, "7");
4826+ if (en && val)
4827+ fprintf(f, "%s", val);
4828+ else if (en)
4829+ fprintf(f, "7");
4830+ else
4831+ fprintf(f, "0");
4832+
4833 fclose(f);
4834
4835 return 0;
4836@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4837
4838 int mt76_fwlog(const char *phyname, int argc, char **argv)
4839 {
4840+#define BUF_SIZE 1504
4841 struct sockaddr_in local = {
4842 .sin_family = AF_INET,
4843 .sin_addr.s_addr = INADDR_ANY,
4844@@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4845 .sin_family = AF_INET,
4846 .sin_port = htons(55688),
4847 };
4848- char buf[1504];
4849+ char *buf = calloc(BUF_SIZE, sizeof(char));
4850 int ret = 0;
4851- int yes = 1;
4852+ /* int yes = 1; */
4853 int s, fd;
4854
4855 if (argc < 1) {
4856@@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4857 return 1;
4858 }
4859
4860- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4861+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4862 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4863 perror("bind");
4864 return 1;
4865 }
4866
4867- if (mt76_set_fwlog_en(phyname, true))
4868+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4869 return 1;
4870
4871 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
4872@@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4873 if (!r)
4874 continue;
4875
4876- if (len > sizeof(buf)) {
4877- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4878+ if (len > BUF_SIZE) {
4879+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4880 ret = 1;
4881 break;
4882 }
4883@@ -171,7 +178,7 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4884 close(fd);
4885
4886 out:
4887- mt76_set_fwlog_en(phyname, false);
4888+ mt76_set_fwlog_en(phyname, false, NULL);
4889
4890 return ret;
4891 }
4892--
developer7e2761e2023-10-12 08:11:13 +0800[diff] [blame]48932.18.0
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4894