blob: 443dbb53ee43c7cebd6ff77d11baf436e8e8463c [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developerfd40db22021-04-29 10:08:25 +08005/ {
6 model = "MediaTek MT7986b RFB";
developer3395eb42021-06-15 16:01:34 +08007 compatible = "mediatek,mt7986b-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
developerfd40db22021-04-29 10:08:25 +080016};
developer298705c2021-06-05 18:48:19 +080017
developer565bacb2021-09-28 21:26:32 +080018&uart0 {
developerd45e4322021-06-17 10:41:47 +080019 status = "okay";
developer565bacb2021-09-28 21:26:32 +080020};
developer5b91be72021-09-27 14:03:07 +080021
developer565bacb2021-09-28 21:26:32 +080022/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
53
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 };
59 };
60
61 gmac1: mac@1 {
62 compatible = "mediatek,eth-mac";
63 reg = <1>;
64 phy-mode = "2500base-x";
65
66 fixed-link {
67 speed = <2500>;
68 full-duplex;
69 pause;
70 };
71 };
72
73 mdio: mdio-bus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy5: phy@5 {
78 compatible = "ethernet-phy-id67c9.de0a";
79 reg = <5>;
80 reset-gpios = <&pio 6 1>;
81 reset-deassert-us = <20000>;
82 phy-mode = "2500base-x";
83 };
84
85 phy6: phy@6 {
86 compatible = "ethernet-phy-id67c9.de0a";
87 reg = <6>;
88 phy-mode = "2500base-x";
89 };
90
91 switch@0 {
92 compatible = "mediatek,mt7531";
93 reg = <31>;
94 reset-gpios = <&pio 5 0>;
95
96 ports {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
100 port@0 {
101 reg = <0>;
102 label = "lan0";
103 };
104
105 port@1 {
106 reg = <1>;
107 label = "lan1";
108 };
109
110 port@2 {
111 reg = <2>;
112 label = "lan2";
113 };
114
115 port@3 {
116 reg = <3>;
117 label = "lan3";
118 };
119
120 port@6 {
121 reg = <6>;
122 label = "cpu";
123 ethernet = <&gmac0>;
124 phy-mode = "2500base-x";
125
126 fixed-link {
127 speed = <2500>;
128 full-duplex;
129 pause;
130 };
131 };
developer5b91be72021-09-27 14:03:07 +0800132 };
133 };
134 };
135};
136
developer565bacb2021-09-28 21:26:32 +0800137&hnat {
138 mtketh-wan = "eth1";
139 mtketh-lan = "lan";
140 mtketh-max-gmac = <2>;
141 status = "okay";
developer5b91be72021-09-27 14:03:07 +0800142};
143
developer565bacb2021-09-28 21:26:32 +0800144&spi0 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&spi_flash_pins>;
147 cs-gpios = <0>, <0>;
148 status = "okay";
149
150 spi_nor@0 {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "jedec,spi-nor";
154 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800155 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800156 spi-tx-buswidth = <4>;
157 spi-rx-buswidth = <4>;
158 };
159};
160
161/* Warning: pins shared with &uart2 */
162&spi1 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&spic_pins>;
165 status = "okay";
166};
167
168&wbsys {
169 mediatek,mtd-eeprom = <&factory 0x0000>;
170 status = "okay";
171};
172
173&pio {
174 spi_flash_pins: spi-flash-pins-33-to-38 {
175 mux {
176 function = "flash";
177 groups = "spi0", "spi0_wp_hold";
178 };
179 conf-pu {
180 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
181 drive-strength = <MTK_DRIVE_8mA>;
182 mediatek,pull-up-adv = <0>; /* bias-disable */
183 };
184 conf-pd {
185 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
186 drive-strength = <MTK_DRIVE_8mA>;
187 mediatek,pull-down-adv = <0>; /* bias-disable */
188 };
189
190 };
developer298705c2021-06-05 18:48:19 +0800191};