developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #include <linux/kernel.h> |
| 7 | #include <linux/module.h> |
| 8 | #include <linux/pci.h> |
| 9 | |
| 10 | #include "mt7996.h" |
| 11 | #include "mac.h" |
| 12 | #include "../trace.h" |
| 13 | |
| 14 | static const struct __base mt7996_reg_base[] = { |
| 15 | [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } }, |
| 16 | [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, |
| 17 | [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } }, |
| 18 | [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } }, |
| 19 | [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } }, |
| 20 | [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, |
| 21 | [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, |
| 22 | [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } }, |
| 23 | }; |
| 24 | |
| 25 | static const struct __map mt7996_reg_map[] = { |
| 26 | { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ |
| 27 | { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ |
| 28 | { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */ |
| 29 | { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */ |
| 30 | { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ |
| 31 | { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ |
| 32 | { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ |
| 33 | { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ |
| 34 | { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ |
| 35 | { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */ |
| 36 | { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ |
| 37 | { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ |
| 38 | { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ |
| 39 | { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ |
| 40 | { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ |
| 41 | { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ |
| 42 | { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ |
| 43 | { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ |
| 44 | { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ |
| 45 | { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ |
| 46 | { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ |
| 47 | { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ |
| 48 | { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ |
| 49 | { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ |
| 50 | { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ |
| 51 | { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ |
| 52 | { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ |
| 53 | { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ |
| 54 | { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ |
| 55 | { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ |
| 56 | { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ |
| 57 | { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ |
| 58 | { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ |
| 59 | { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ |
| 60 | { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ |
| 61 | { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ |
| 62 | { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ |
| 63 | { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ |
| 64 | { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ |
| 65 | { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ |
| 66 | { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ |
| 67 | { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ |
| 68 | { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ |
| 69 | { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */ |
| 70 | { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ |
| 71 | { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ |
| 72 | { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */ |
| 73 | { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ |
| 74 | { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ |
| 75 | { 0x0, 0x0, 0x0 }, /* imply end of search */ |
| 76 | }; |
| 77 | |
| 78 | static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr) |
| 79 | { |
| 80 | u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); |
| 81 | u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); |
| 82 | |
| 83 | dev->reg_l1_backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); |
| 84 | dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, |
| 85 | MT_HIF_REMAP_L1_MASK, |
| 86 | FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); |
| 87 | /* use read to push write */ |
| 88 | dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); |
| 89 | |
| 90 | return MT_HIF_REMAP_BASE_L1 + offset; |
| 91 | } |
| 92 | |
| 93 | static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr) |
| 94 | { |
| 95 | u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); |
| 96 | u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); |
| 97 | |
| 98 | dev->reg_l2_backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); |
| 99 | dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, |
| 100 | MT_HIF_REMAP_L2_MASK, |
| 101 | FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); |
| 102 | /* use read to push write */ |
| 103 | dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); |
| 104 | |
| 105 | return MT_HIF_REMAP_BASE_L2 + offset; |
| 106 | } |
| 107 | |
| 108 | static void mt7996_reg_remap_restore(struct mt7996_dev *dev) |
| 109 | { |
| 110 | /* remap to ori status */ |
| 111 | if (unlikely(dev->reg_l1_backup)) { |
| 112 | dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->reg_l1_backup); |
| 113 | dev->reg_l1_backup = 0; |
| 114 | } |
| 115 | |
| 116 | if (dev->reg_l2_backup) { |
| 117 | dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->reg_l2_backup); |
| 118 | dev->reg_l2_backup = 0; |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr) |
| 123 | { |
| 124 | int i; |
| 125 | |
| 126 | mt7996_reg_remap_restore(dev); |
| 127 | |
| 128 | if (addr < 0x100000) |
| 129 | return addr; |
| 130 | |
| 131 | for (i = 0; i < dev->reg.map_size; i++) { |
| 132 | u32 ofs; |
| 133 | |
| 134 | if (addr < dev->reg.map[i].phys) |
| 135 | continue; |
| 136 | |
| 137 | ofs = addr - dev->reg.map[i].phys; |
| 138 | if (ofs > dev->reg.map[i].size) |
| 139 | continue; |
| 140 | |
| 141 | return dev->reg.map[i].mapped + ofs; |
| 142 | } |
| 143 | |
| 144 | if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || |
| 145 | (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || |
| 146 | (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) |
| 147 | return mt7996_reg_map_l1(dev, addr); |
| 148 | |
| 149 | if (dev_is_pci(dev->mt76.dev) && |
| 150 | ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || |
| 151 | (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) |
| 152 | return mt7996_reg_map_l1(dev, addr); |
| 153 | |
| 154 | /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ |
| 155 | if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { |
| 156 | addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; |
| 157 | return mt7996_reg_map_l1(dev, addr); |
| 158 | } |
| 159 | |
| 160 | return mt7996_reg_map_l2(dev, addr); |
| 161 | } |
| 162 | |
| 163 | static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset) |
| 164 | { |
| 165 | struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); |
| 166 | |
| 167 | return dev->bus_ops->rr(mdev, __mt7996_reg_addr(dev, offset)); |
| 168 | } |
| 169 | |
| 170 | static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val) |
| 171 | { |
| 172 | struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); |
| 173 | |
| 174 | dev->bus_ops->wr(mdev, __mt7996_reg_addr(dev, offset), val); |
| 175 | } |
| 176 | |
| 177 | static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) |
| 178 | { |
| 179 | struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); |
| 180 | |
| 181 | return dev->bus_ops->rmw(mdev, __mt7996_reg_addr(dev, offset), mask, val); |
| 182 | } |
| 183 | |
| 184 | static int mt7996_mmio_init(struct mt76_dev *mdev, |
| 185 | void __iomem *mem_base, |
| 186 | u32 device_id) |
| 187 | { |
| 188 | struct mt76_bus_ops *bus_ops; |
| 189 | struct mt7996_dev *dev; |
| 190 | |
| 191 | dev = container_of(mdev, struct mt7996_dev, mt76); |
| 192 | mt76_mmio_init(&dev->mt76, mem_base); |
| 193 | |
| 194 | switch (device_id) { |
| 195 | case 0x7990: |
| 196 | dev->reg.base = mt7996_reg_base; |
| 197 | dev->reg.map = mt7996_reg_map; |
| 198 | dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); |
| 199 | break; |
| 200 | default: |
| 201 | return -EINVAL; |
| 202 | } |
| 203 | |
| 204 | dev->bus_ops = dev->mt76.bus; |
| 205 | bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), |
| 206 | GFP_KERNEL); |
| 207 | if (!bus_ops) |
| 208 | return -ENOMEM; |
| 209 | |
| 210 | bus_ops->rr = mt7996_rr; |
| 211 | bus_ops->wr = mt7996_wr; |
| 212 | bus_ops->rmw = mt7996_rmw; |
| 213 | dev->mt76.bus = bus_ops; |
| 214 | |
| 215 | mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff); |
| 216 | |
| 217 | dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, |
| 223 | u32 clear, u32 set) |
| 224 | { |
| 225 | struct mt76_dev *mdev = &dev->mt76; |
| 226 | unsigned long flags; |
| 227 | |
| 228 | spin_lock_irqsave(&mdev->mmio.irq_lock, flags); |
| 229 | |
| 230 | mdev->mmio.irqmask &= ~clear; |
| 231 | mdev->mmio.irqmask |= set; |
| 232 | |
| 233 | if (write_reg) { |
| 234 | mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); |
| 235 | mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); |
| 236 | } |
| 237 | |
| 238 | spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); |
| 239 | } |
| 240 | |
| 241 | |
| 242 | static void mt7996_rx_poll_complete(struct mt76_dev *mdev, |
| 243 | enum mt76_rxq_id q) |
| 244 | { |
| 245 | struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); |
| 246 | |
| 247 | mt7996_irq_enable(dev, MT_INT_RX(q)); |
| 248 | } |
| 249 | |
| 250 | /* TODO: support 2/4/6/8 MSI-X vectors */ |
| 251 | static void mt7996_irq_tasklet(struct tasklet_struct *t) |
| 252 | { |
| 253 | struct mt7996_dev *dev = from_tasklet(dev, t, irq_tasklet); |
| 254 | u32 i, intr, mask, intr1; |
| 255 | |
| 256 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 257 | if (dev->hif2) |
| 258 | mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 259 | |
| 260 | intr = mt76_rr(dev, MT_INT_SOURCE_CSR); |
| 261 | intr &= dev->mt76.mmio.irqmask; |
| 262 | mt76_wr(dev, MT_INT_SOURCE_CSR, intr); |
| 263 | |
| 264 | if (dev->hif2) { |
| 265 | intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); |
| 266 | intr1 &= dev->mt76.mmio.irqmask; |
| 267 | mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); |
| 268 | |
| 269 | intr |= intr1; |
| 270 | } |
| 271 | |
| 272 | trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); |
| 273 | |
| 274 | mask = intr & MT_INT_RX_DONE_ALL; |
| 275 | if (intr & MT_INT_TX_DONE_MCU) |
| 276 | mask |= MT_INT_TX_DONE_MCU; |
| 277 | mt7996_irq_disable(dev, mask); |
| 278 | |
| 279 | if (intr & MT_INT_TX_DONE_MCU) |
| 280 | napi_schedule(&dev->mt76.tx_napi); |
| 281 | |
| 282 | for (i = 0; i < __MT_RXQ_MAX; i++) { |
| 283 | if ((intr & MT_INT_RX(i))) |
| 284 | napi_schedule(&dev->mt76.napi[i]); |
| 285 | } |
| 286 | |
| 287 | if (intr & MT_INT_MCU_CMD) { |
| 288 | u32 val = mt76_rr(dev, MT_MCU_CMD); |
| 289 | |
| 290 | mt76_wr(dev, MT_MCU_CMD, val); |
| 291 | if (val & MT_MCU_CMD_ERROR_MASK) { |
| 292 | dev->reset_state = val; |
| 293 | ieee80211_queue_work(mt76_hw(dev), &dev->reset_work); |
| 294 | wake_up(&dev->reset_wait); |
| 295 | } |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | irqreturn_t mt7996_irq_handler(int irq, void *dev_instance) |
| 300 | { |
| 301 | struct mt7996_dev *dev = dev_instance; |
| 302 | |
| 303 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 304 | if (dev->hif2) |
| 305 | mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 306 | |
| 307 | if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) |
| 308 | return IRQ_NONE; |
| 309 | |
| 310 | tasklet_schedule(&dev->irq_tasklet); |
| 311 | |
| 312 | return IRQ_HANDLED; |
| 313 | } |
| 314 | |
| 315 | struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, |
| 316 | void __iomem *mem_base, u32 device_id) |
| 317 | { |
| 318 | static const struct mt76_driver_ops drv_ops = { |
| 319 | /* txwi_size = txd size + txp size */ |
| 320 | .txwi_size = MT_TXD_SIZE + sizeof(struct mt7996_txp), |
| 321 | .drv_flags = MT_DRV_TXWI_NO_FREE | |
| 322 | MT_DRV_HW_MGMT_TXQ, |
| 323 | .survey_flags = SURVEY_INFO_TIME_TX | |
| 324 | SURVEY_INFO_TIME_RX | |
| 325 | SURVEY_INFO_TIME_BSS_RX, |
| 326 | .token_size = MT7996_TOKEN_SIZE, |
| 327 | .tx_prepare_skb = mt7996_tx_prepare_skb, |
| 328 | .tx_complete_skb = mt7996_tx_complete_skb, |
| 329 | .rx_skb = mt7996_queue_rx_skb, |
| 330 | .rx_check = mt7996_rx_check, |
| 331 | .rx_poll_complete = mt7996_rx_poll_complete, |
| 332 | .sta_ps = mt7996_sta_ps, |
| 333 | .sta_add = mt7996_mac_sta_add, |
| 334 | .sta_remove = mt7996_mac_sta_remove, |
| 335 | .update_survey = mt7996_update_channel, |
| 336 | }; |
| 337 | struct mt7996_dev *dev; |
| 338 | struct mt76_dev *mdev; |
| 339 | int ret; |
| 340 | |
| 341 | mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops); |
| 342 | if (!mdev) |
| 343 | return ERR_PTR(-ENOMEM); |
| 344 | |
| 345 | dev = container_of(mdev, struct mt7996_dev, mt76); |
| 346 | |
| 347 | ret = mt7996_mmio_init(mdev, mem_base, device_id); |
| 348 | if (ret) |
| 349 | goto error; |
| 350 | |
| 351 | tasklet_setup(&dev->irq_tasklet, mt7996_irq_tasklet); |
| 352 | |
| 353 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 354 | |
| 355 | return dev; |
| 356 | |
| 357 | error: |
| 358 | mt76_free_device(&dev->mt76); |
| 359 | |
| 360 | return ERR_PTR(ret); |
| 361 | } |
| 362 | |
| 363 | static int __init mt7996_init(void) |
| 364 | { |
| 365 | int ret; |
| 366 | |
| 367 | ret = pci_register_driver(&mt7996_hif_driver); |
| 368 | if (ret) |
| 369 | return ret; |
| 370 | |
| 371 | ret = pci_register_driver(&mt7996_pci_driver); |
| 372 | if (ret) |
| 373 | pci_unregister_driver(&mt7996_hif_driver); |
| 374 | |
| 375 | return ret; |
| 376 | } |
| 377 | |
| 378 | static void __exit mt7996_exit(void) |
| 379 | { |
| 380 | pci_unregister_driver(&mt7996_pci_driver); |
| 381 | pci_unregister_driver(&mt7996_hif_driver); |
| 382 | } |
| 383 | |
| 384 | module_init(mt7996_init); |
| 385 | module_exit(mt7996_exit); |
| 386 | MODULE_LICENSE("Dual BSD/GPL"); |