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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / ce9e509d3d8e299873250682296510bebd165652 / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / package / kernel / mt76 / src / mt7915 / regs.h
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developer0f312e82022-11-01 12:31:52 +0800[diff] [blame]1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7915_REGS_H
5#define __MT7915_REGS_H
6
7/* used to differentiate between generations */
8struct mt7915_reg_desc {
9 const u32 *reg_rev;
10 const u32 *offs_rev;
11 const struct mt76_connac_reg_map *map;
12 u32 map_size;
13};
14
15enum reg_rev {
16 INT_SOURCE_CSR,
17 INT_MASK_CSR,
18 INT1_SOURCE_CSR,
19 INT1_MASK_CSR,
20 INT_MCU_CMD_SOURCE,
21 INT_MCU_CMD_EVENT,
22 WFDMA0_ADDR,
23 WFDMA0_PCIE1_ADDR,
24 WFDMA_EXT_CSR_ADDR,
25 CBTOP1_PHY_END,
26 INFRA_MCU_ADDR_END,
27 FW_EXCEPTION_ADDR,
28 SWDEF_BASE_ADDR,
29 TXQ_WED_RING_BASE,
30 RXQ_WED_RING_BASE,
31 __MT_REG_MAX,
32};
33
34enum offs_rev {
35 TMAC_CDTR,
36 TMAC_ODTR,
37 TMAC_ATCR,
38 TMAC_TRCR0,
39 TMAC_ICR0,
40 TMAC_ICR1,
41 TMAC_CTCR0,
42 TMAC_TFCR0,
43 MDP_BNRCFR0,
44 MDP_BNRCFR1,
45 ARB_DRNGR0,
46 ARB_SCR,
47 RMAC_MIB_AIRTIME14,
48 AGG_AWSCR0,
49 AGG_PCR0,
50 AGG_ACR0,
51 AGG_ACR4,
52 AGG_MRCR,
53 AGG_ATCR1,
54 AGG_ATCR3,
55 LPON_UTTR0,
56 LPON_UTTR1,
57 LPON_FRCR,
58 MIB_SDR3,
59 MIB_SDR4,
60 MIB_SDR5,
61 MIB_SDR7,
62 MIB_SDR8,
63 MIB_SDR9,
64 MIB_SDR10,
65 MIB_SDR11,
66 MIB_SDR12,
67 MIB_SDR13,
68 MIB_SDR14,
69 MIB_SDR15,
70 MIB_SDR16,
71 MIB_SDR17,
72 MIB_SDR18,
73 MIB_SDR19,
74 MIB_SDR20,
75 MIB_SDR21,
76 MIB_SDR22,
77 MIB_SDR23,
78 MIB_SDR24,
79 MIB_SDR25,
80 MIB_SDR27,
81 MIB_SDR28,
82 MIB_SDR29,
83 MIB_SDRVEC,
84 MIB_SDR31,
85 MIB_SDR32,
86 MIB_SDRMUBF,
87 MIB_DR8,
88 MIB_DR9,
89 MIB_DR11,
90 MIB_MB_SDR0,
91 MIB_MB_SDR1,
92 TX_AGG_CNT,
93 TX_AGG_CNT2,
94 MIB_ARNG,
95 WTBLON_TOP_WDUCR,
96 WTBL_UPDATE,
97 PLE_FL_Q_EMPTY,
98 PLE_FL_Q_CTRL,
99 PLE_AC_QEMPTY,
100 PLE_FREEPG_CNT,
101 PLE_FREEPG_HEAD_TAIL,
102 PLE_PG_HIF_GROUP,
103 PLE_HIF_PG_INFO,
104 AC_OFFSET,
105 ETBF_PAR_RPT0,
106 __MT_OFFS_MAX,
107};
108
109#define __REG(id) (dev->reg.reg_rev[(id)])
110#define __OFFS(id) (dev->reg.offs_rev[(id)])
111
112/* MCU WFDMA0 */
113#define MT_MCU_WFDMA0_BASE 0x2000
114#define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs))
115
116#define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
117
118/* MCU WFDMA1 */
119#define MT_MCU_WFDMA1_BASE 0x3000
120#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
121
122#define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT)
123#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
124#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
125#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
126#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
127
128/* PLE */
129#define MT_PLE_BASE 0x820c0000
130#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
131
132#define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY))
133#define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL))
134#define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
135#define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
136
137#define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT))
138#define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL))
139#define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP))
140#define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO))
141
142#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \
143 __OFFS(AC_OFFSET) * \
144 (ac) + ((n) << 2))
145#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
146
147#define MT_PSE_BASE 0x820c8000
148#define MT_PSE(ofs) (MT_PSE_BASE + (ofs))
149
150/* WF MDP TOP */
151#define MT_MDP_BASE 0x820cd000
152#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
153
154#define MT_MDP_DCR0 MT_MDP(0x000)
155#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
156
157#define MT_MDP_DCR1 MT_MDP(0x004)
158#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
159
160#define MT_MDP_DCR2 MT_MDP(0x0e8)
161#define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2)
162
163#define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \
164 ((_band) << 8))
165#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
166#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
167#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
168
169#define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \
170 ((_band) << 8))
171#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
172#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
173#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
174#define MT_MDP_TO_HIF 0
175#define MT_MDP_TO_WM 1
176
177/* TRB: band 0(0x820e1000), band 1(0x820f1000) */
178#define MT_WF_TRB_BASE(_band) ((_band) ? 0x820f1000 : 0x820e1000)
179#define MT_WF_TRB(_band, ofs) (MT_WF_TRB_BASE(_band) + (ofs))
180
181#define MT_TRB_RXPSR0(_band) MT_WF_TRB(_band, 0x03c)
182#define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
183#define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
184
185/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
186#define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
187#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
188
189#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
190#define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
191#define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
192
193#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
194 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
195#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
196#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
197
198#define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR))
199#define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0)
200
201#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0))
202#define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0)
203#define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
204
205#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0))
206#define MT_IFS_EIFS_OFDM GENMASK(8, 0)
207#define MT_IFS_RIFS GENMASK(14, 10)
208#define MT_IFS_SIFS GENMASK(22, 16)
209#define MT_IFS_SLOT GENMASK(30, 24)
210
211#define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1))
212#define MT_IFS_EIFS_CCK GENMASK(8, 0)
213
214#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0))
215#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
216#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
217#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
218
219#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0))
220
221/* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */
222#define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
223#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
224
225#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
226#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
227#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
228
229/* ETBF: band 0(0x820ea000), band 1(0x820fa000) */
230#define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000)
231#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))
232
233#define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040)
234#define MT_ETBF_TX_FB_CPL GENMASK(31, 16)
235#define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
236
237#define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0))
238#define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6)
239#define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3)
240#define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0)
241
242#define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0)
243#define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)
244#define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
245
246#define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8)
247#define MT_ETBF_RX_FB_ALL GENMASK(31, 24)
248#define MT_ETBF_RX_FB_HE GENMASK(23, 16)
249#define MT_ETBF_RX_FB_VHT GENMASK(15, 8)
250#define MT_ETBF_RX_FB_HT GENMASK(7, 0)
251
252/* LPON: band 0(0x820eb000), band 1(0x820fb000) */
253#define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
254#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
255
256#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0))
257#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1))
258#define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR))
259
260#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \
261 (((n) * 4) << 1))
262#define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \
263 (((n) * 4) << 4))
264#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
265#define MT_LPON_TCR_SW_WRITE BIT(0)
266#define MT_LPON_TCR_SW_ADJUST BIT(1)
267#define MT_LPON_TCR_SW_READ GENMASK(1, 0)
268
269/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
270/* These counters are (mostly?) clear-on-read. So, some should not
271 * be read at all in case firmware is already reading them. These
272 * are commented with 'DNR' below. The DNR stats will be read by querying
273 * the firmware API for the appropriate message. For counters the driver
274 * does read, the driver should accumulate the counters.
275 */
276#define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
277#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
278
279#define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010)
280#define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0)
281
282#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3))
283#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
284#define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16)
285
286#define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4))
287#define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0)
288
289/* rx mpdu counter, full 32 bits */
290#define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5))
291
292#define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
293#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
294
295#define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7))
296#define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0)
297
298#define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8))
299#define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0)
300
301/* aka CCA_NAV_TX_TIME */
302#define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9))
303#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0)
304
305#define MT_MIB_SDR10(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10))
306#define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0)
307#define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0)
308
309#define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11))
310#define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0)
311
312/* tx ampdu cnt, full 32 bits */
313#define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12))
314
315#define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13))
316#define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0)
317
318/* counts all mpdus in ampdu, regardless of success */
319#define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14))
320#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0)
321#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0)
322
323/* counts all successfully tx'd mpdus in ampdu */
324#define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15))
325#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0)
326#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0)
327
328/* in units of 'us' */
329#define MT_MIB_SDR16(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16))
330#define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
331
332#define MT_MIB_SDR17(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17))
333#define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
334
335#define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18))
336#define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0)
337
338/* units are us */
339#define MT_MIB_SDR19(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19))
340#define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0)
341
342#define MT_MIB_SDR20(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20))
343#define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0)
344
345#define MT_MIB_SDR21(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21))
346#define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0)
347
348/* rx ampdu count, 32-bit */
349#define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22))
350
351/* rx ampdu bytes count, 32-bit */
352#define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23))
353
354/* rx ampdu valid subframe count */
355#define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24))
356#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0)
357#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0)
358
359/* rx ampdu valid subframe bytes count, 32bits */
360#define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25))
361
362/* remaining windows protected stats */
363#define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27))
364#define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0)
365
366#define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28))
367#define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0)
368
369#define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29))
370#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0)
371#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0)
372
373#define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC))
374#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0)
375#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16)
376
377/* rx blockack count, 32 bits */
378#define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31))
379
380#define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32))
381#define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0)
382#define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16)
383
384#define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088)
385#define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0)
386
387#define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF))
388#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
389
390/* 36, 37 both DNR */
391
392#define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8))
393#define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9))
394#define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11))
395
396#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n))
397#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
398#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
399
400#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n))
401#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
402#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
403
404#define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n))
405#define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n))
406
407#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \
408 ((n) << 2))
409#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \
410 ((n) << 2))
411#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \
412 ((n) << 2))
413#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
414
415#define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0)
416#define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0)
417#define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16)
418
419#define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4)
420#define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0)
421
422#define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8)
423#define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0)
424
425#define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc)
426#define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0)
427
428/* WTBLON TOP */
429#define MT_WTBLON_TOP_BASE 0x820d4000
430#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
431#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR))
432#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
433
434#define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE))
435#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
436#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
437#define MT_WTBL_UPDATE_BUSY BIT(31)
438
439/* WTBL */
440#define MT_WTBL_BASE 0x820d8000
441#define MT_WTBL_LMAC_ID GENMASK(14, 8)
442#define MT_WTBL_LMAC_DW GENMASK(7, 2)
443#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
444 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
445 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
446
447/* AGG: band 0(0x820e2000), band 1(0x820f2000) */
448#define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
449#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
450
451#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \
452 (_n) * 4))
453#define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \
454 (_n) * 4))
455#define MT_AGG_PCR0_MM_PROT BIT(0)
456#define MT_AGG_PCR0_GF_PROT BIT(1)
457#define MT_AGG_PCR0_BW20_PROT BIT(2)
458#define MT_AGG_PCR0_BW40_PROT BIT(4)
459#define MT_AGG_PCR0_BW80_PROT BIT(6)
460#define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8)
461#define MT_AGG_PCR0_VHT_PROT BIT(13)
462#define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
463
464#define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
465#define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
466
467#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0))
468#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
469#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
470
471#define MT_AGG_ACR4(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR4))
472#define MT_AGG_ACR_PPDU_TXS2H BIT(1)
473
474#define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR))
475#define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)
476#define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
477#define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)
478#define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)
479
480#define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1))
481#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3))
482
483/* ARB: band 0(0x820e3000), band 1(0x820f3000) */
484#define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
485#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
486
487#define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR))
488#define MT_ARB_SCR_TX_DISABLE BIT(8)
489#define MT_ARB_SCR_RX_DISABLE BIT(9)
490
491#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \
492 (_n) * 4))
493
494/* RMAC: band 0(0x820e5000), band 1(0x820f5000) */
495#define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
496#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
497
498#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
499#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
500#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
501#define MT_WF_RFCR_DROP_VERSION BIT(3)
502#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
503#define MT_WF_RFCR_DROP_MCAST BIT(5)
504#define MT_WF_RFCR_DROP_BCAST BIT(6)
505#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
506#define MT_WF_RFCR_DROP_A3_MAC BIT(8)
507#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
508#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
509#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
510#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
511#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
512#define MT_WF_RFCR_DROP_CTS BIT(14)
513#define MT_WF_RFCR_DROP_RTS BIT(15)
514#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
515#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
516#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
517#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
518#define MT_WF_RFCR_DROP_NDPA BIT(20)
519#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
520
521#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
522#define MT_WF_RFCR1_DROP_ACK BIT(4)
523#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
524#define MT_WF_RFCR1_DROP_BA BIT(6)
525#define MT_WF_RFCR1_DROP_CFEND BIT(7)
526#define MT_WF_RFCR1_DROP_CFACK BIT(8)
527
528#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
529#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
530
531/* WFDMA0 */
532#define MT_WFDMA0_BASE __REG(WFDMA0_ADDR)
533#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
534
535#define MT_WFDMA0_RST MT_WFDMA0(0x100)
536#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
537#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
538
539#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
540#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
541#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
542#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
543
544#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
545#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
546#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
547#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
548#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
549#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
550
551#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
552#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
553#define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
554#define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
555
556/* WFDMA1 */
557#define MT_WFDMA1_BASE 0xd5000
558#define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs))
559
560#define MT_WFDMA1_RST MT_WFDMA1(0x100)
561#define MT_WFDMA1_RST_LOGIC_RST BIT(4)
562#define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5)
563
564#define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c)
565#define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
566#define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
567#define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
568
569#define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
570#define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
571#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
572#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
573#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
574#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
575
576#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
577#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
578
579/* WFDMA CSR */
580#define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR)
581#define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000
582#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
583#define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs))
584
585#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30)
586#define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
587#define MT_WFDMA_HOST_CONFIG_WED BIT(1)
588
589#define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34)
590#define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0)
591#define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8)
592#define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16)
593
594#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44)
595#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
596
597#define MT_PCIE_RECOG_ID 0xd7090
598#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
599#define MT_PCIE_RECOG_ID_SEM BIT(31)
600
601#define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200)
602#define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204)
603
604#define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300)
605#define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400)
606
607/* WFDMA0 PCIE1 */
608#define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR)
609#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
610
611#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
612#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
613#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
614#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
615
616/* WFDMA1 PCIE1 */
617#define MT_WFDMA1_PCIE1_BASE 0xd9000
618#define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs))
619
620#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
621#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
622#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
623#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
624
625/* WFDMA COMMON */
626#define __RXQ(q) ((q) + __MT_MCUQ_MAX)
627#define __TXQ(q) (__RXQ(q) + MT_RXQ_BAND2)
628
629#define MT_Q_ID(q) (dev->q_id[(q)])
630#define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \
631 MT_WFDMA1_BASE : MT_WFDMA0_BASE)
632
633#define MT_MCUQ_ID(q) MT_Q_ID(q)
634#define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q))
635#define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q))
636
637#define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)
638#define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)
639#define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)
640
641#define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
642 MT_MCUQ_ID(q)* 0x4)
643#define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
644 MT_RXQ_ID(q)* 0x4)
645#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
646 MT_TXQ_ID(q)* 0x4)
647
648#define MT_TXQ_WED_RING_BASE __REG(TXQ_WED_RING_BASE)
649#define MT_RXQ_WED_RING_BASE __REG(RXQ_WED_RING_BASE)
650
651#define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
652#define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
653
654#define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR)
655#define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR)
656
657#define MT_INT_RX_DONE_BAND0 BIT(16)
658#define MT_INT_RX_DONE_BAND1 BIT(17)
659#define MT_INT_RX_DONE_WM BIT(0)
660#define MT_INT_RX_DONE_WA BIT(1)
661#define MT_INT_RX_DONE_WA_MAIN BIT(1)
662#define MT_INT_RX_DONE_WA_EXT BIT(2)
663#define MT_INT_MCU_CMD BIT(29)
664#define MT_INT_RX_DONE_BAND0_MT7916 BIT(22)
665#define MT_INT_RX_DONE_BAND1_MT7916 BIT(23)
666#define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2)
667#define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3)
668
669#define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18)
670#define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19)
671#define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1)
672#define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17)
673
674#define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)])
675#define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)])
676
677#define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \
678 MT_INT_RX(MT_RXQ_MCU_WA))
679
680#define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \
681 MT_INT_RX(MT_RXQ_MAIN_WA))
682
683#define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \
684 MT_INT_RX(MT_RXQ_BAND1_WA) | \
685 MT_INT_RX(MT_RXQ_MAIN_WA))
686
687#define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \
688 MT_INT_BAND0_RX_DONE | \
689 MT_INT_BAND1_RX_DONE)
690
691#define MT_INT_TX_DONE_FWDL BIT(26)
692#define MT_INT_TX_DONE_MCU_WM BIT(27)
693#define MT_INT_TX_DONE_MCU_WA BIT(15)
694#define MT_INT_TX_DONE_BAND0 BIT(30)
695#define MT_INT_TX_DONE_BAND1 BIT(31)
696#define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25)
697#define MT_INT_WED_TX_DONE_BAND0 BIT(4)
698#define MT_INT_WED_TX_DONE_BAND1 BIT(5)
699
700#define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \
701 MT_INT_TX_MCU(MT_MCUQ_WM) | \
702 MT_INT_TX_MCU(MT_MCUQ_FWDL))
703
704#define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE)
705#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
706#define MT_MCU_CMD_STOP_DMA BIT(2)
707#define MT_MCU_CMD_RESET_DONE BIT(3)
708#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
709#define MT_MCU_CMD_NORMAL_STATE BIT(5)
710#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
711
712/* TOP RGU */
713#define MT_TOP_RGU_BASE 0x18000000
714#define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0))
715#define MT_TOP_PWR_KEY (0x5746 << 16)
716#define MT_TOP_PWR_SW_RST BIT(0)
717#define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2)
718#define MT_TOP_PWR_HW_CTRL BIT(4)
719#define MT_TOP_PWR_PWR_ON BIT(7)
720
721#define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050)
722#define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054)
723#define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010)
724#define MT_TOP_PWR_EN_MASK BIT(7)
725#define MT_TOP_PWR_ACK_MASK BIT(6)
726#define MT_TOP_PWR_KEY_MASK GENMASK(31, 16)
727
728#define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120)
729#define MT7986_TOP_WM_RESET_MASK BIT(0)
730
731/* l1/l2 remap */
732#define MT_HIF_REMAP_L1 0xf11ac
733#define MT_HIF_REMAP_L1_MT7916 0xfe260
734#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
735#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
736#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
737#define MT_HIF_REMAP_BASE_L1 0xe0000
738
739#define MT_HIF_REMAP_L2 0xf11b0
740#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
741#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
742#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
743#define MT_HIF_REMAP_L2_MT7916 0x1b8
744#define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16)
745#define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0)
746#define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16)
747#define MT_HIF_REMAP_BASE_L2_MT7916 0x40000
748
749#define MT_INFRA_BASE 0x18000000
750#define MT_WFSYS0_PHY_START 0x18400000
751#define MT_WFSYS1_PHY_START 0x18800000
752#define MT_WFSYS1_PHY_END 0x18bfffff
753#define MT_CBTOP1_PHY_START 0x70000000
754#define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END)
755#define MT_CBTOP2_PHY_START 0xf0000000
756#define MT_CBTOP2_PHY_END 0xffffffff
757#define MT_INFRA_MCU_START 0x7c000000
758#define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END)
759#define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE)
760
761/* CONN INFRA CFG */
762#define MT_CONN_INFRA_BASE 0x18001000
763#define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs))
764
765#define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020)
766
767#define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030)
768#define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0)
769#define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2)
770
771#define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380)
772
773#define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300)
774#define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7)
775#define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0)
776
777#define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200)
778#define MT_CONN_INFRA_HW_CTRL_MASK BIT(0)
779
780#define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540)
781#define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0)
782
783#define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544)
784#define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31))
785#define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31))
786
787#define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414)
788#define MT_CONN_INFRA_EMI_REQ_MASK BIT(0)
789#define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5)
790
791/* AFE */
792#define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19))
793#define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs))
794
795#define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00)
796#define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04)
797#define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08)
798#define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c)
799
800#define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4)
801#define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))
802#define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
803 FIELD_PREP(GENMASK(14, 0), 0x7e4))
804#define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6)
805#define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0)
806#define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2)
807#define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16)
808#define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \
809 MT_AFE_WPLL_CFG_MASK | \
810 MT_AFE_MCU_WPLL_CFG_MASK | \
811 MT_AFE_MCU_BPLL_CFG_MASK)
812#define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \
813 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \
814 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \
815 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2))
816
817#define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15)
818#define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9)
819
820#define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0)
821#define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21)
822#define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20)
823#define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \
824 MT_AFE_RG_WBG_EN_WPLL_UP_MASK)
825#define MT_AFE_RG_WBG_EN_TXCAL_MASK GENMASK(21, 17)
826
827#define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19))
828#define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs))
829
830#define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120)
831
832/* ADIE */
833#define MT_ADIE_CHIP_ID 0x02c
834#define MT_ADIE_VERSION_MASK GENMASK(15, 0)
835#define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16)
836#define MT_ADIE_IDX0 GENMASK(15, 0)
837#define MT_ADIE_IDX1 GENMASK(31, 16)
838
839#define MT_ADIE_RG_TOP_THADC_BG 0x034
840#define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12)
841#define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3)
842
843#define MT_ADIE_RG_TOP_THADC 0x038
844#define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23)
845#define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0)
846#define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26)
847#define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5)
848
849#define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070
850#define MT_ADIE_EFUSE_RDATA0 0x130
851
852#define MT_ADIE_EFUSE2_CTRL 0x148
853#define MT_ADIE_EFUSE_CTRL_MASK BIT(1)
854
855#define MT_ADIE_EFUSE_CFG 0x144
856#define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6)
857#define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16)
858#define MT_ADIE_EFUSE_VALID_MASK BIT(29)
859#define MT_ADIE_EFUSE_KICK_MASK BIT(30)
860
861#define MT_ADIE_THADC_ANALOG 0x3a6
862
863#define MT_ADIE_THADC_SLOP 0x3a7
864#define MT_ADIE_ANA_EN_MASK BIT(7)
865
866#define MT_ADIE_7975_XTAL_CAL 0x3a1
867#define MT_ADIE_TRIM_MASK GENMASK(6, 0)
868#define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0)
869#define MT_ADIE_XO_TRIM_EN_MASK BIT(7)
870#define MT_ADIE_XTAL_DECREASE_MASK BIT(6)
871
872#define MT_ADIE_7975_XO_TRIM2 0x3a2
873#define MT_ADIE_7975_XO_TRIM3 0x3a3
874#define MT_ADIE_7975_XO_TRIM4 0x3a4
875#define MT_ADIE_7975_XTAL_EN 0x3a5
876
877#define MT_ADIE_XO_TRIM_FLOW 0x3ac
878#define MT_ADIE_XTAL_AXM_80M_OSC 0x390
879#define MT_ADIE_XTAL_AXM_40M_OSC 0x391
880#define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398
881#define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399
882#define MT_ADIE_WRI_CK_SEL 0x4ac
883#define MT_ADIE_RG_STRAP_PIN_IN 0x4fc
884#define MT_ADIE_XTAL_C1 0x654
885#define MT_ADIE_XTAL_C2 0x658
886#define MT_ADIE_RG_XO_01 0x65c
887#define MT_ADIE_RG_XO_03 0x664
888
889#define MT_ADIE_CLK_EN 0xa00
890
891#define MT_ADIE_7975_XTAL 0xa18
892#define MT_ADIE_7975_XTAL_EN_MASK BIT(29)
893
894#define MT_ADIE_7975_COCLK 0xa1c
895#define MT_ADIE_7975_XO_2 0xa84
896#define MT_ADIE_7975_XO_2_FIX_EN BIT(31)
897
898#define MT_ADIE_7975_XO_CTRL2 0xa94
899#define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20)
900#define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12)
901#define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \
902 MT_ADIE_7975_XO_CTRL2_C2_MASK)
903
904#define MT_ADIE_7975_XO_CTRL6 0xaa4
905#define MT_ADIE_7975_XO_CTRL6_MASK BIT(16)
906
907/* TOP SPI */
908#define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19))
909#define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs))
910
911#define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0)
912#define MT_TOP_SPI_POLLING_BIT BIT(5)
913
914#define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50)
915#define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15))
916#define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15))
917
918#define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54)
919#define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58)
920
921/* CONN INFRA CKGEN */
922#define MT_INFRA_CKGEN_BASE 0x18009000
923#define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs))
924
925#define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00)
926#define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23)
927#define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29)
928
929#define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008)
930#define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c)
931
932#define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040)
933#define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2)
934#define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0)
935
936/* CONN INFRA BUS */
937#define MT_INFRA_BUS_BASE 0x1800e000
938#define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs))
939
940#define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300)
941#define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7)
942#define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0)
943
944#define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c)
945#define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360)
946#define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364)
947
948/* CONN_INFRA_SKU */
949#define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000
950#define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)
951#define MT_ADIE_TYPE_MASK BIT(1)
952
953/* FW MODE SYNC */
954#define MT_FW_EXCEPTION __REG(FW_EXCEPTION_ADDR)
955
956#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR)
957
958#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
959#define MT_SWDEF_MODE MT_SWDEF(0x3c)
960#define MT_SWDEF_NORMAL_MODE 0
961#define MT_SWDEF_ICAP_MODE 1
962#define MT_SWDEF_SPECTRUM_MODE 2
963
964#define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
965#define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
966#define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
967#define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C)
968#define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
969#define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)
970#define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)
971#define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C)
972#define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060)
973#define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064)
974
975#define MT_DIC_CMD_REG_BASE 0x41f000
976#define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs))
977#define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10)
978
979#define MT_CPU_UTIL_BASE 0x41f030
980#define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs))
981#define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00)
982#define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04)
983#define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08)
984#define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c)
985#define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c)
986
987/* LED */
988#define MT_LED_TOP_BASE 0x18013000
989#define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n))
990
991#define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))
992#define MT_LED_CTRL_KICK BIT(7)
993#define MT_LED_CTRL_BLINK_MODE BIT(2)
994#define MT_LED_CTRL_POLARITY BIT(1)
995
996#define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))
997#define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)
998#define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8)
999
1000#define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
1001
1002#define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
1003#define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */
1004#define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)
1005
1006/* MT TOP */
1007#define MT_TOP_BASE 0x18060000
1008#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
1009
1010#define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
1011#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
1012#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
1013#define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2)
1014
1015#define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
1016#define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
1017
1018#define MT_TOP_MISC MT_TOP(0xf0)
1019#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
1020
1021#define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4)
1022#define MT_TOP_WFSYS_WAKEUP_MASK BIT(0)
1023
1024#define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4)
1025#define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0)
1026
1027#define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0)
1028#define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0)
1029
1030#define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc)
1031#define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30)
1032
1033/* SEMA */
1034#define MT_SEMA_BASE 0x18070000
1035#define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs))
1036
1037#define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4))
1038#define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4))
1039#define MT_SEMA_RFSPI_STATUS_MASK BIT(1)
1040
1041/* MCU BUS */
1042#define MT_MCU_BUS_BASE 0x18400000
1043#define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs))
1044
1045#define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440)
1046#define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0)
1047#define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28)
1048#define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31)
1049
1050#define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120)
1051
1052/* TOP CFG */
1053#define MT_TOP_CFG_BASE 0x184b0000
1054#define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs))
1055
1056#define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010)
1057
1058/* TOP CFG ON */
1059#define MT_TOP_CFG_ON_BASE 0x184c1000
1060#define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs))
1061
1062#define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604)
1063
1064/* SLP CTRL */
1065#define MT_SLP_BASE 0x184c3000
1066#define MT_SLP(ofs) (MT_SLP_BASE + (ofs))
1067
1068#define MT_SLP_STATUS MT_SLP(0x00c)
1069#define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23))
1070#define MT_SLP_CTRL_EN_MASK BIT(0)
1071#define MT_SLP_CTRL_BSY_MASK BIT(1)
1072
1073/* MCU BUS DBG */
1074#define MT_MCU_BUS_DBG_BASE 0x18500000
1075#define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs))
1076
1077#define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0)
1078#define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)
1079#define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
1080#define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2)
1081
1082#define MT_HW_BOUND 0x70010020
1083#define MT_HW_REV 0x70010204
1084#define MT_WF_SUBSYS_RST 0x70002600
1085
1086/* PCIE MAC */
1087#define MT_PCIE_MAC_BASE 0x74030000
1088#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
1089#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
1090
1091#define MT_PCIE1_MAC_INT_ENABLE 0x74020188
1092#define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188
1093
1094#define MT_WM_MCU_PC 0x7c060204
1095#define MT_WA_MCU_PC 0x7c06020c
1096
1097/* PP TOP */
1098#define MT_WF_PP_TOP_BASE 0x820cc000
1099#define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs))
1100
1101#define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8)
1102#define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6)
1103
1104#define MT_WF_IRPI_BASE 0x83000000
1105#define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + (ofs))
1106
1107#define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
1108#define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
1109
1110/* PHY */
1111#define MT_WF_PHY_BASE 0x83080000
1112#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
1113
1114#define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
1115#define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20))
1116#define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0)
1117#define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9)
1118
1119#define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16))
1120#define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20))
1121#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
1122#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
1123
1124#define MT_MCU_WM_CIRQ_BASE 0x89010000
1125#define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs))
1126#define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80)
1127#define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0)
1128
1129#endif