developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #include "mt76x2.h" |
| 8 | #include "eeprom.h" |
| 9 | #include "mcu.h" |
| 10 | #include "../mt76x02_phy.h" |
| 11 | |
| 12 | static void |
| 13 | mt76x2_adjust_high_lna_gain(struct mt76x02_dev *dev, int reg, s8 offset) |
| 14 | { |
| 15 | s8 gain; |
| 16 | |
| 17 | gain = FIELD_GET(MT_BBP_AGC_LNA_HIGH_GAIN, |
| 18 | mt76_rr(dev, MT_BBP(AGC, reg))); |
| 19 | gain -= offset / 2; |
| 20 | mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain); |
| 21 | } |
| 22 | |
| 23 | static void |
| 24 | mt76x2_adjust_agc_gain(struct mt76x02_dev *dev, int reg, s8 offset) |
| 25 | { |
| 26 | s8 gain; |
| 27 | |
| 28 | gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg))); |
| 29 | gain += offset; |
| 30 | mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain); |
| 31 | } |
| 32 | |
| 33 | void mt76x2_apply_gain_adj(struct mt76x02_dev *dev) |
| 34 | { |
| 35 | s8 *gain_adj = dev->cal.rx.high_gain; |
| 36 | |
| 37 | mt76x2_adjust_high_lna_gain(dev, 4, gain_adj[0]); |
| 38 | mt76x2_adjust_high_lna_gain(dev, 5, gain_adj[1]); |
| 39 | |
| 40 | mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]); |
| 41 | mt76x2_adjust_agc_gain(dev, 9, gain_adj[1]); |
| 42 | } |
| 43 | EXPORT_SYMBOL_GPL(mt76x2_apply_gain_adj); |
| 44 | |
| 45 | void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev, |
| 46 | enum nl80211_band band) |
| 47 | { |
| 48 | u32 pa_mode[2]; |
| 49 | u32 pa_mode_adj; |
| 50 | |
| 51 | if (band == NL80211_BAND_2GHZ) { |
| 52 | pa_mode[0] = 0x010055ff; |
| 53 | pa_mode[1] = 0x00550055; |
| 54 | |
| 55 | mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00); |
| 56 | mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06); |
| 57 | |
| 58 | if (mt76x02_ext_pa_enabled(dev, band)) { |
| 59 | mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00); |
| 60 | mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00); |
| 61 | } else { |
| 62 | mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200); |
| 63 | mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200); |
| 64 | } |
| 65 | } else { |
| 66 | pa_mode[0] = 0x0000ffff; |
| 67 | pa_mode[1] = 0x00ff00ff; |
| 68 | |
| 69 | if (mt76x02_ext_pa_enabled(dev, band)) { |
| 70 | mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400); |
| 71 | mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476); |
| 72 | } else { |
| 73 | mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400); |
| 74 | mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476); |
| 75 | } |
| 76 | |
| 77 | if (mt76x02_ext_pa_enabled(dev, band)) |
| 78 | pa_mode_adj = 0x04000000; |
| 79 | else |
| 80 | pa_mode_adj = 0; |
| 81 | |
| 82 | mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj); |
| 83 | mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj); |
| 84 | } |
| 85 | |
| 86 | mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]); |
| 87 | mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]); |
| 88 | mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]); |
| 89 | mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]); |
| 90 | |
| 91 | if (mt76x02_ext_pa_enabled(dev, band)) { |
| 92 | u32 val; |
| 93 | |
| 94 | if (band == NL80211_BAND_2GHZ) |
| 95 | val = 0x3c3c023c; |
| 96 | else |
| 97 | val = 0x363c023c; |
| 98 | |
| 99 | mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val); |
| 100 | mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val); |
| 101 | mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818); |
| 102 | } else { |
| 103 | if (band == NL80211_BAND_2GHZ) { |
| 104 | u32 val = 0x0f3c3c3c; |
| 105 | |
| 106 | mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val); |
| 107 | mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val); |
| 108 | mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606); |
| 109 | } else { |
| 110 | mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c); |
| 111 | mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28); |
| 112 | mt76_wr(dev, MT_TX_ALC_CFG_4, 0); |
| 113 | } |
| 114 | } |
| 115 | } |
| 116 | EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower_regs); |
| 117 | |
| 118 | static int |
| 119 | mt76x2_get_min_rate_power(struct mt76x02_rate_power *r) |
| 120 | { |
| 121 | int i; |
| 122 | s8 ret = 0; |
| 123 | |
| 124 | for (i = 0; i < sizeof(r->all); i++) { |
| 125 | if (!r->all[i]) |
| 126 | continue; |
| 127 | |
| 128 | if (ret) |
| 129 | ret = min(ret, r->all[i]); |
| 130 | else |
| 131 | ret = r->all[i]; |
| 132 | } |
| 133 | |
| 134 | return ret; |
| 135 | } |
| 136 | |
| 137 | void mt76x2_phy_set_txpower(struct mt76x02_dev *dev) |
| 138 | { |
| 139 | enum nl80211_chan_width width = dev->mphy.chandef.width; |
| 140 | struct ieee80211_channel *chan = dev->mphy.chandef.chan; |
| 141 | struct mt76x2_tx_power_info txp; |
| 142 | int txp_0, txp_1, delta = 0; |
| 143 | struct mt76x02_rate_power t = {}; |
| 144 | int base_power, gain; |
| 145 | |
| 146 | mt76x2_get_power_info(dev, &txp, chan); |
| 147 | |
| 148 | if (width == NL80211_CHAN_WIDTH_40) |
| 149 | delta = txp.delta_bw40; |
| 150 | else if (width == NL80211_CHAN_WIDTH_80) |
| 151 | delta = txp.delta_bw80; |
| 152 | |
| 153 | mt76x2_get_rate_power(dev, &t, chan); |
| 154 | mt76x02_add_rate_power_offset(&t, txp.target_power + delta); |
| 155 | mt76x02_limit_rate_power(&t, dev->txpower_conf); |
| 156 | dev->mphy.txpower_cur = mt76x02_get_max_rate_power(&t); |
| 157 | |
| 158 | base_power = mt76x2_get_min_rate_power(&t); |
| 159 | delta = base_power - txp.target_power; |
| 160 | txp_0 = txp.chain[0].target_power + txp.chain[0].delta + delta; |
| 161 | txp_1 = txp.chain[1].target_power + txp.chain[1].delta + delta; |
| 162 | |
| 163 | gain = min(txp_0, txp_1); |
| 164 | if (gain < 0) { |
| 165 | base_power -= gain; |
| 166 | txp_0 -= gain; |
| 167 | txp_1 -= gain; |
| 168 | } else if (gain > 0x2f) { |
| 169 | base_power -= gain - 0x2f; |
| 170 | txp_0 = 0x2f; |
| 171 | txp_1 = 0x2f; |
| 172 | } |
| 173 | |
| 174 | mt76x02_add_rate_power_offset(&t, -base_power); |
| 175 | dev->target_power = txp.target_power; |
| 176 | dev->target_power_delta[0] = txp_0 - txp.chain[0].target_power; |
| 177 | dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power; |
| 178 | dev->rate_power = t; |
| 179 | |
| 180 | mt76x02_phy_set_txpower(dev, txp_0, txp_1); |
| 181 | } |
| 182 | EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower); |
| 183 | |
| 184 | void mt76x2_configure_tx_delay(struct mt76x02_dev *dev, |
| 185 | enum nl80211_band band, u8 bw) |
| 186 | { |
| 187 | u32 cfg0, cfg1; |
| 188 | |
| 189 | if (mt76x02_ext_pa_enabled(dev, band)) { |
| 190 | cfg0 = bw ? 0x000b0c01 : 0x00101101; |
| 191 | cfg1 = 0x00011414; |
| 192 | } else { |
| 193 | cfg0 = bw ? 0x000b0b01 : 0x00101001; |
| 194 | cfg1 = 0x00021414; |
| 195 | } |
| 196 | mt76_wr(dev, MT_TX_SW_CFG0, cfg0); |
| 197 | mt76_wr(dev, MT_TX_SW_CFG1, cfg1); |
| 198 | |
| 199 | mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, 15); |
| 200 | } |
| 201 | EXPORT_SYMBOL_GPL(mt76x2_configure_tx_delay); |
| 202 | |
| 203 | void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev) |
| 204 | { |
| 205 | struct ieee80211_channel *chan = dev->mphy.chandef.chan; |
| 206 | struct mt76x2_tx_power_info txp; |
| 207 | struct mt76x2_tssi_comp t = {}; |
| 208 | |
| 209 | if (!dev->cal.tssi_cal_done) |
| 210 | return; |
| 211 | |
| 212 | if (!dev->cal.tssi_comp_pending) { |
| 213 | /* TSSI trigger */ |
| 214 | t.cal_mode = BIT(0); |
| 215 | mt76x2_mcu_tssi_comp(dev, &t); |
| 216 | dev->cal.tssi_comp_pending = true; |
| 217 | } else { |
| 218 | if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) |
| 219 | return; |
| 220 | |
| 221 | dev->cal.tssi_comp_pending = false; |
| 222 | mt76x2_get_power_info(dev, &txp, chan); |
| 223 | |
| 224 | if (mt76x02_ext_pa_enabled(dev, chan->band)) |
| 225 | t.pa_mode = 1; |
| 226 | |
| 227 | t.cal_mode = BIT(1); |
| 228 | t.slope0 = txp.chain[0].tssi_slope; |
| 229 | t.offset0 = txp.chain[0].tssi_offset; |
| 230 | t.slope1 = txp.chain[1].tssi_slope; |
| 231 | t.offset1 = txp.chain[1].tssi_offset; |
| 232 | mt76x2_mcu_tssi_comp(dev, &t); |
| 233 | |
| 234 | if (t.pa_mode || dev->cal.dpd_cal_done || dev->ed_tx_blocked) |
| 235 | return; |
| 236 | |
| 237 | usleep_range(10000, 20000); |
| 238 | mt76x02_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value); |
| 239 | dev->cal.dpd_cal_done = true; |
| 240 | } |
| 241 | } |
| 242 | EXPORT_SYMBOL_GPL(mt76x2_phy_tssi_compensate); |
| 243 | |
| 244 | static void |
| 245 | mt76x2_phy_set_gain_val(struct mt76x02_dev *dev) |
| 246 | { |
| 247 | u32 val; |
| 248 | u8 gain_val[2]; |
| 249 | |
| 250 | gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust; |
| 251 | gain_val[1] = dev->cal.agc_gain_cur[1] - dev->cal.agc_gain_adjust; |
| 252 | |
| 253 | val = 0x1836 << 16; |
| 254 | if (!mt76x2_has_ext_lna(dev) && |
| 255 | dev->mphy.chandef.width >= NL80211_CHAN_WIDTH_40) |
| 256 | val = 0x1e42 << 16; |
| 257 | |
| 258 | if (mt76x2_has_ext_lna(dev) && |
| 259 | dev->mphy.chandef.chan->band == NL80211_BAND_2GHZ && |
| 260 | dev->mphy.chandef.width < NL80211_CHAN_WIDTH_40) |
| 261 | val = 0x0f36 << 16; |
| 262 | |
| 263 | val |= 0xf8; |
| 264 | |
| 265 | mt76_wr(dev, MT_BBP(AGC, 8), |
| 266 | val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0])); |
| 267 | mt76_wr(dev, MT_BBP(AGC, 9), |
| 268 | val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[1])); |
| 269 | |
| 270 | if (dev->mphy.chandef.chan->flags & IEEE80211_CHAN_RADAR) |
| 271 | mt76x02_phy_dfs_adjust_agc(dev); |
| 272 | } |
| 273 | |
| 274 | void mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev) |
| 275 | { |
| 276 | u8 *gain = dev->cal.agc_gain_init; |
| 277 | u8 low_gain_delta, gain_delta; |
| 278 | u32 agc_35, agc_37; |
| 279 | bool gain_change; |
| 280 | int low_gain; |
| 281 | u32 val; |
| 282 | |
| 283 | dev->cal.avg_rssi_all = mt76_get_min_avg_rssi(&dev->mt76, false); |
| 284 | if (!dev->cal.avg_rssi_all) |
| 285 | dev->cal.avg_rssi_all = -75; |
| 286 | |
| 287 | low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) + |
| 288 | (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev)); |
| 289 | |
| 290 | gain_change = dev->cal.low_gain < 0 || |
| 291 | (dev->cal.low_gain & 2) ^ (low_gain & 2); |
| 292 | dev->cal.low_gain = low_gain; |
| 293 | |
| 294 | if (!gain_change) { |
| 295 | if (mt76x02_phy_adjust_vga_gain(dev)) |
| 296 | mt76x2_phy_set_gain_val(dev); |
| 297 | return; |
| 298 | } |
| 299 | |
| 300 | if (dev->mphy.chandef.width == NL80211_CHAN_WIDTH_80) { |
| 301 | mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211); |
| 302 | val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf; |
| 303 | if (low_gain == 2) |
| 304 | val |= 0x3; |
| 305 | else |
| 306 | val |= 0x5; |
| 307 | mt76_wr(dev, MT_BBP(AGC, 26), val); |
| 308 | } else { |
| 309 | mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423); |
| 310 | } |
| 311 | |
| 312 | if (mt76x2_has_ext_lna(dev)) |
| 313 | low_gain_delta = 10; |
| 314 | else |
| 315 | low_gain_delta = 14; |
| 316 | |
| 317 | agc_37 = 0x2121262c; |
| 318 | if (dev->mphy.chandef.chan->band == NL80211_BAND_2GHZ) |
| 319 | agc_35 = 0x11111516; |
| 320 | else if (low_gain == 2) |
| 321 | agc_35 = agc_37 = 0x08080808; |
| 322 | else if (dev->mphy.chandef.width == NL80211_CHAN_WIDTH_80) |
| 323 | agc_35 = 0x10101014; |
| 324 | else |
| 325 | agc_35 = 0x11111116; |
| 326 | |
| 327 | if (low_gain == 2) { |
| 328 | mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990); |
| 329 | mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808); |
| 330 | mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808); |
| 331 | gain_delta = low_gain_delta; |
| 332 | dev->cal.agc_gain_adjust = 0; |
| 333 | } else { |
| 334 | mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991); |
| 335 | gain_delta = 0; |
| 336 | dev->cal.agc_gain_adjust = low_gain_delta; |
| 337 | } |
| 338 | |
| 339 | mt76_wr(dev, MT_BBP(AGC, 35), agc_35); |
| 340 | mt76_wr(dev, MT_BBP(AGC, 37), agc_37); |
| 341 | |
| 342 | dev->cal.agc_gain_cur[0] = gain[0] - gain_delta; |
| 343 | dev->cal.agc_gain_cur[1] = gain[1] - gain_delta; |
| 344 | mt76x2_phy_set_gain_val(dev); |
| 345 | |
| 346 | /* clear false CCA counters */ |
| 347 | mt76_rr(dev, MT_RX_STAT_1); |
| 348 | } |
| 349 | EXPORT_SYMBOL_GPL(mt76x2_phy_update_channel_gain); |