blob: 72e766da6916e70ce3a7197eae1487da393ca426 [file] [log] [blame]
developer20d67712022-03-02 14:09:32 +08001From d7ead1b1556bb695c20d5616b73a4dd8d00766a9 Mon Sep 17 00:00:00 2001
2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Tue, 25 Jan 2022 14:48:58 +0800
4Subject: [PATCH 02/11] mt76: mt7915: fix txbf stats counters for newer chips
5
6Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
7---
8 .../net/wireless/mediatek/mt76/mt7915/mac.c | 73 ++++++++++++-------
9 .../net/wireless/mediatek/mt76/mt7915/mmio.c | 2 +
10 .../net/wireless/mediatek/mt76/mt7915/regs.h | 28 +++++--
11 3 files changed, 69 insertions(+), 34 deletions(-)
12
13diff --git a/mt7915/mac.c b/mt7915/mac.c
14index 268b7f9..081b533 100644
15--- a/mt7915/mac.c
16+++ b/mt7915/mac.c
17@@ -2191,15 +2191,6 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
18 cnt = mt76_rr(dev, MT_MIB_SDR31(phy->band_idx));
19 mib->rx_ba_cnt += cnt;
20
21- cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
22- mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK, cnt);
23-
24- if (is_mt7915(&dev->mt76))
25- cnt = mt76_rr(dev, MT_MIB_SDR33(phy->band_idx));
26- mib->tx_pkt_ibf_cnt += is_mt7915(&dev->mt76) ?
27- FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK, cnt) :
28- FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK_MT7916, cnt);
29-
30 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(phy->band_idx));
31 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);
32
33@@ -2212,24 +2203,10 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
34 cnt = mt76_rr(dev, MT_MIB_DR11(phy->band_idx));
35 mib->tx_su_acked_mpdu_cnt += cnt;
36
37- cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(phy->band_idx));
38- mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt);
39- mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt);
40-
41- cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(phy->band_idx));
42- mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt);
43- mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt);
44- mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt);
45- mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt);
46-
47- cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(phy->band_idx));
48- mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt);
49- mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt);
50- mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt);
51-
52- cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(phy->band_idx));
53- mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt);
54- mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt);
55+ cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(phy->band_idx));
56+ mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt);
57+ mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt);
58+ mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt);
59
60 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
61 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
62@@ -2258,6 +2235,26 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
63 dev->mt76.aggr_stats[aggr1++] += val & 0xffff;
64 dev->mt76.aggr_stats[aggr1++] += val >> 16;
65 }
66+
67+ cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
68+ mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
69+
70+ cnt = mt76_rr(dev, MT_MIB_SDR33(phy->band_idx));
71+ mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt);
72+
73+ cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(phy->band_idx));
74+ mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt);
75+ mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt);
76+
77+ cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(phy->band_idx));
78+ mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt);
79+ mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt);
80+
81+ cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(phy->band_idx));
82+ mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt);
83+ mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt);
84+ mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt);
85+ mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt);
86 } else {
87 for (i = 0; i < 2; i++) {
88 /* rts count */
89@@ -2286,6 +2283,28 @@ void mt7915_mac_update_stats(struct mt7915_phy *phy)
90 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val);
91 dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val);
92 }
93+
94+ cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx));
95+ mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
96+ mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt);
97+ mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
98+ mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt);
99+
100+ cnt = mt76_rr(dev, MT_MIB_BFCR7(phy->band_idx));
101+ mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt);
102+
103+ cnt = mt76_rr(dev, MT_MIB_BFCR2(phy->band_idx));
104+ mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt);
105+
106+ cnt = mt76_rr(dev, MT_MIB_BFCR0(phy->band_idx));
107+ mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
108+ mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt);
109+ mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
110+ mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt);
111+
112+ cnt = mt76_rr(dev, MT_MIB_BFCR1(phy->band_idx));
113+ mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
114+ mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt);
115 }
116 }
117
118diff --git a/mt7915/mmio.c b/mt7915/mmio.c
119index 1b14bba..5062e0d 100644
120--- a/mt7915/mmio.c
121+++ b/mt7915/mmio.c
122@@ -122,6 +122,7 @@ static const u32 mt7915_offs[] = {
123 [PLE_PG_HIF_GROUP] = 0x110,
124 [PLE_HIF_PG_INFO] = 0x114,
125 [AC_OFFSET] = 0x040,
126+ [ETBF_PAR_RPT0] = 0x068,
127 };
128
129 static const u32 mt7916_offs[] = {
130@@ -194,6 +195,7 @@ static const u32 mt7916_offs[] = {
131 [PLE_PG_HIF_GROUP] = 0x00c,
132 [PLE_HIF_PG_INFO] = 0x388,
133 [AC_OFFSET] = 0x080,
134+ [ETBF_PAR_RPT0] = 0x100,
135 };
136
137 static const struct __map mt7915_reg_map[] = {
138diff --git a/mt7915/regs.h b/mt7915/regs.h
139index 71f325a..d33d768 100644
140--- a/mt7915/regs.h
141+++ b/mt7915/regs.h
142@@ -103,6 +103,7 @@ enum offs_rev {
143 PLE_PG_HIF_GROUP,
144 PLE_HIF_PG_INFO,
145 AC_OFFSET,
146+ ETBF_PAR_RPT0,
147 __MT_OFFS_MAX,
148 };
149
150@@ -223,10 +224,10 @@ enum offs_rev {
151 #define MT_ETBF_TX_FB_CPL GENMASK(31, 16)
152 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
153
154-#define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x068)
155-#define MT_ETBF_RX_FB_BW GENMASK(7, 6)
156-#define MT_ETBF_RX_FB_NC GENMASK(5, 3)
157-#define MT_ETBF_RX_FB_NR GENMASK(2, 0)
158+#define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0))
159+#define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6)
160+#define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3)
161+#define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0)
162
163 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0)
164 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)
165@@ -367,11 +368,11 @@ enum offs_rev {
166 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31))
167
168 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32))
169-#define MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK GENMASK(15, 0)
170+#define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0)
171+#define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16)
172
173 #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088)
174-#define MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK GENMASK(15, 0)
175-#define MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK_MT7916 GENMASK(31, 16)
176+#define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0)
177
178 #define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF))
179 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
180@@ -401,6 +402,19 @@ enum offs_rev {
181 ((n) << 2))
182 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
183
184+#define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0)
185+#define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0)
186+#define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16)
187+
188+#define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4)
189+#define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0)
190+
191+#define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8)
192+#define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0)
193+
194+#define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc)
195+#define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0)
196+
197 /* WTBLON TOP */
198 #define MT_WTBLON_TOP_BASE 0x820d4000
199 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
200--
2012.25.1
202