developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988C DSA external-2.5G SPIM-NAND RFB"; |
| 12 | compatible = "mediatek,mt7988c-dsa-e2p5g-spim-snand", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0 0x40000000 0 0x10000000>; |
| 24 | }; |
| 25 | |
| 26 | nmbm_spim_nand { |
| 27 | compatible = "generic,nmbm"; |
| 28 | |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | |
| 32 | lower-mtd-device = <&spi_nand>; |
| 33 | forced-create; |
| 34 | |
| 35 | partitions { |
| 36 | compatible = "fixed-partitions"; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | |
| 40 | partition@0 { |
| 41 | label = "BL2"; |
| 42 | reg = <0x00000 0x0100000>; |
| 43 | read-only; |
| 44 | }; |
| 45 | |
| 46 | partition@100000 { |
| 47 | label = "u-boot-env"; |
| 48 | reg = <0x0100000 0x0080000>; |
| 49 | }; |
| 50 | |
| 51 | factory: partition@180000 { |
| 52 | label = "Factory"; |
| 53 | reg = <0x180000 0x0400000>; |
| 54 | }; |
| 55 | |
| 56 | partition@580000 { |
| 57 | label = "FIP"; |
| 58 | reg = <0x580000 0x0200000>; |
| 59 | }; |
| 60 | |
| 61 | partition@780000 { |
| 62 | label = "ubi"; |
| 63 | reg = <0x780000 0x7080000>; |
| 64 | }; |
| 65 | }; |
| 66 | }; |
| 67 | |
| 68 | wsys_adie: wsys_adie@0 { |
| 69 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 70 | compatible = "mediatek,rebb-mt7988-adie"; |
| 71 | adie_id = <7976>; |
| 72 | sku_type = <3000>; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | &fan { |
| 77 | pwms = <&pwm 0 50000 0>; |
| 78 | status = "okay"; |
| 79 | }; |
| 80 | |
| 81 | &i2c0 { |
| 82 | pinctrl-names = "default"; |
| 83 | pinctrl-0 = <&i2c0_pins>; |
| 84 | status = "okay"; |
| 85 | |
| 86 | rt5190a_64: rt5190a@64 { |
| 87 | compatible = "richtek,rt5190a"; |
| 88 | reg = <0x64>; |
| 89 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 90 | vin2-supply = <&rt5190_buck1>; |
| 91 | vin3-supply = <&rt5190_buck1>; |
| 92 | vin4-supply = <&rt5190_buck1>; |
| 93 | |
| 94 | regulators { |
| 95 | rt5190_buck1: buck1 { |
| 96 | regulator-name = "rt5190a-buck1"; |
| 97 | regulator-min-microvolt = <5090000>; |
| 98 | regulator-max-microvolt = <5090000>; |
| 99 | regulator-allowed-modes = |
| 100 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 101 | regulator-boot-on; |
| 102 | }; |
| 103 | buck2 { |
| 104 | regulator-name = "vcore"; |
| 105 | regulator-min-microvolt = <600000>; |
| 106 | regulator-max-microvolt = <1400000>; |
| 107 | regulator-boot-on; |
| 108 | }; |
| 109 | buck3 { |
| 110 | regulator-name = "proc"; |
| 111 | regulator-min-microvolt = <600000>; |
| 112 | regulator-max-microvolt = <1400000>; |
| 113 | regulator-boot-on; |
| 114 | }; |
| 115 | buck4 { |
| 116 | regulator-name = "rt5190a-buck4"; |
| 117 | regulator-min-microvolt = <850000>; |
| 118 | regulator-max-microvolt = <850000>; |
| 119 | regulator-allowed-modes = |
| 120 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 121 | regulator-boot-on; |
| 122 | }; |
| 123 | ldo { |
| 124 | regulator-name = "rt5190a-ldo"; |
| 125 | regulator-min-microvolt = <1200000>; |
| 126 | regulator-max-microvolt = <1200000>; |
| 127 | regulator-boot-on; |
| 128 | }; |
| 129 | }; |
| 130 | }; |
| 131 | }; |
| 132 | |
| 133 | &i2c1 { |
| 134 | pinctrl-names = "default"; |
| 135 | pinctrl-0 = <&i2c1_pins>; |
| 136 | status = "okay"; |
| 137 | }; |
| 138 | |
| 139 | &pwm { |
| 140 | status = "okay"; |
| 141 | }; |
| 142 | |
| 143 | &uart0 { |
| 144 | status = "okay"; |
| 145 | }; |
| 146 | |
| 147 | &spi0 { |
| 148 | pinctrl-names = "default"; |
| 149 | pinctrl-0 = <&spi0_flash_pins>; |
| 150 | status = "okay"; |
| 151 | |
| 152 | spi_nand: spi_nand@0 { |
| 153 | #address-cells = <1>; |
| 154 | #size-cells = <1>; |
| 155 | compatible = "spi-nand"; |
| 156 | spi-cal-enable; |
| 157 | spi-cal-mode = "read-data"; |
| 158 | spi-cal-datalen = <7>; |
| 159 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 160 | spi-cal-addrlen = <5>; |
| 161 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 162 | reg = <0>; |
| 163 | spi-max-frequency = <52000000>; |
developer | 5fb8060 | 2023-05-02 18:54:53 +0800 | [diff] [blame] | 164 | spi-tx-bus-width = <4>; |
| 165 | spi-rx-bus-width = <4>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 166 | }; |
| 167 | }; |
| 168 | |
| 169 | &spi1 { |
| 170 | pinctrl-names = "default"; |
| 171 | /* pin shared with snfi */ |
| 172 | pinctrl-0 = <&spic_pins>; |
| 173 | status = "disabled"; |
| 174 | }; |
| 175 | |
| 176 | &pcie0 { |
| 177 | pinctrl-names = "default"; |
| 178 | pinctrl-0 = <&pcie0_pins>; |
| 179 | status = "okay"; |
| 180 | }; |
| 181 | |
| 182 | &pcie1 { |
| 183 | pinctrl-names = "default"; |
| 184 | pinctrl-0 = <&pcie1_pins>; |
| 185 | status = "disabled"; |
| 186 | }; |
| 187 | |
| 188 | &pcie2 { |
| 189 | pinctrl-names = "default"; |
| 190 | pinctrl-0 = <&pcie2_pins>; |
| 191 | status = "disabled"; |
| 192 | }; |
| 193 | |
| 194 | &pcie3 { |
| 195 | pinctrl-names = "default"; |
| 196 | pinctrl-0 = <&pcie3_pins>; |
| 197 | status = "okay"; |
| 198 | }; |
| 199 | |
| 200 | &pio { |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 201 | gbe0_led0_pins: gbe0-pins { |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 202 | mux { |
| 203 | function = "led"; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 204 | groups = "gbe0_led0"; |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 205 | }; |
| 206 | }; |
| 207 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 208 | gbe1_led0_pins: gbe1-pins { |
| 209 | mux { |
| 210 | function = "led"; |
| 211 | groups = "gbe1_led0"; |
| 212 | }; |
| 213 | }; |
| 214 | |
| 215 | gbe2_led0_pins: gbe2-pins { |
| 216 | mux { |
| 217 | function = "led"; |
| 218 | groups = "gbe2_led0"; |
| 219 | }; |
| 220 | }; |
| 221 | |
| 222 | gbe3_led0_pins: gbe3-pins { |
| 223 | mux { |
| 224 | function = "led"; |
| 225 | groups = "gbe3_led0"; |
| 226 | }; |
| 227 | }; |
| 228 | |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 229 | i2p5gbe_led0_pins: 2p5gbe-pins { |
| 230 | mux { |
| 231 | function = "led"; |
| 232 | groups = "2p5gbe_led0"; |
| 233 | }; |
| 234 | }; |
| 235 | |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 236 | i2c0_pins: i2c0-pins-g0 { |
| 237 | mux { |
| 238 | function = "i2c"; |
| 239 | groups = "i2c0_1"; |
| 240 | }; |
| 241 | }; |
| 242 | |
| 243 | i2c1_pins: i2c1-pins-g0 { |
| 244 | mux { |
| 245 | function = "i2c"; |
| 246 | groups = "i2c1_0"; |
| 247 | }; |
| 248 | }; |
| 249 | |
| 250 | pcie0_pins: pcie0-pins { |
| 251 | mux { |
| 252 | function = "pcie"; |
| 253 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 254 | "pcie_wake_n0_0"; |
| 255 | }; |
| 256 | }; |
| 257 | |
| 258 | pcie1_pins: pcie1-pins { |
| 259 | mux { |
| 260 | function = "pcie"; |
| 261 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 262 | "pcie_wake_n1_0"; |
| 263 | }; |
| 264 | }; |
| 265 | |
| 266 | pcie2_pins: pcie2-pins { |
| 267 | mux { |
| 268 | function = "pcie"; |
| 269 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 270 | "pcie_wake_n2_0"; |
| 271 | }; |
| 272 | }; |
| 273 | |
| 274 | pcie3_pins: pcie3-pins { |
| 275 | mux { |
| 276 | function = "pcie"; |
| 277 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 278 | "pcie_wake_n3_0"; |
| 279 | }; |
| 280 | }; |
| 281 | |
| 282 | spi0_flash_pins: spi0-pins { |
| 283 | mux { |
| 284 | function = "spi"; |
| 285 | groups = "spi0", "spi0_wp_hold"; |
| 286 | }; |
| 287 | }; |
| 288 | |
| 289 | spic_pins: spi1-pins { |
| 290 | mux { |
| 291 | function = "spi"; |
developer | 1ceb26a | 2023-02-16 15:43:43 +0800 | [diff] [blame] | 292 | groups = "spi1"; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 293 | }; |
| 294 | }; |
| 295 | }; |
| 296 | |
| 297 | &watchdog { |
| 298 | status = "disabled"; |
| 299 | }; |
| 300 | |
| 301 | ð { |
| 302 | status = "okay"; |
| 303 | |
| 304 | gmac0: mac@0 { |
| 305 | compatible = "mediatek,eth-mac"; |
| 306 | reg = <0>; |
| 307 | mac-type = "xgdm"; |
| 308 | phy-mode = "10gbase-kr"; |
| 309 | |
| 310 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 311 | speed = <10000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 312 | full-duplex; |
| 313 | pause; |
| 314 | }; |
| 315 | }; |
| 316 | |
| 317 | gmac1: mac@1 { |
| 318 | compatible = "mediatek,eth-mac"; |
| 319 | reg = <1>; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 320 | mac-type = "xgdm"; |
| 321 | phy-mode = "xgmii"; |
| 322 | phy-handle = <&phy0>; |
| 323 | }; |
| 324 | |
| 325 | gmac2: mac@2 { |
| 326 | compatible = "mediatek,eth-mac"; |
| 327 | reg = <2>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 328 | mac-type = "gdm"; |
| 329 | phy-mode = "2500base-x"; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 330 | phy-handle = <&phy5>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | mdio: mdio-bus { |
| 334 | #address-cells = <1>; |
| 335 | #size-cells = <0>; |
| 336 | |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 337 | phy0: ethernet-phy@0 { |
| 338 | pinctrl-names = "default"; |
| 339 | pinctrl-0 = <&i2p5gbe_led0_pins>; |
| 340 | reg = <15>; |
| 341 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 342 | phy-mode = "xgmii"; |
| 343 | }; |
| 344 | |
| 345 | phy5: phy@5 { |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 346 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 347 | reg = <5>; |
| 348 | reset-gpios = <&pio 3 1>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 349 | reset-assert-us = <600>; |
| 350 | reset-deassert-us = <20000>; |
| 351 | }; |
| 352 | |
| 353 | switch@0 { |
| 354 | compatible = "mediatek,mt7988"; |
| 355 | reg = <31>; |
| 356 | ports { |
| 357 | #address-cells = <1>; |
| 358 | #size-cells = <0>; |
| 359 | |
| 360 | port@0 { |
| 361 | reg = <0>; |
| 362 | label = "lan0"; |
| 363 | phy-mode = "gmii"; |
| 364 | phy-handle = <&sphy0>; |
| 365 | }; |
| 366 | |
| 367 | port@1 { |
| 368 | reg = <1>; |
| 369 | label = "lan1"; |
| 370 | phy-mode = "gmii"; |
| 371 | phy-handle = <&sphy1>; |
| 372 | }; |
| 373 | |
| 374 | port@2 { |
| 375 | reg = <2>; |
| 376 | label = "lan2"; |
| 377 | phy-mode = "gmii"; |
| 378 | phy-handle = <&sphy2>; |
| 379 | }; |
| 380 | |
| 381 | port@3 { |
| 382 | reg = <3>; |
| 383 | label = "lan3"; |
| 384 | phy-mode = "gmii"; |
| 385 | phy-handle = <&sphy3>; |
| 386 | }; |
| 387 | |
| 388 | port@6 { |
| 389 | reg = <6>; |
| 390 | label = "cpu"; |
| 391 | ethernet = <&gmac0>; |
| 392 | phy-mode = "10gbase-kr"; |
| 393 | |
| 394 | fixed-link { |
| 395 | speed = <10000>; |
| 396 | full-duplex; |
| 397 | pause; |
| 398 | }; |
| 399 | }; |
| 400 | }; |
| 401 | |
| 402 | mdio { |
| 403 | compatible = "mediatek,dsa-slave-mdio"; |
| 404 | #address-cells = <1>; |
| 405 | #size-cells = <0>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 406 | |
| 407 | sphy0: switch_phy0@0 { |
| 408 | compatible = "ethernet-phy-id03a2.9481"; |
| 409 | reg = <0>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 410 | pinctrl-names = "gbe-led"; |
| 411 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 412 | nvmem-cells = <&phy_calibration_p0>; |
| 413 | nvmem-cell-names = "phy-cal-data"; |
| 414 | }; |
| 415 | |
| 416 | sphy1: switch_phy1@1 { |
| 417 | compatible = "ethernet-phy-id03a2.9481"; |
| 418 | reg = <1>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 419 | pinctrl-names = "gbe-led"; |
| 420 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 421 | nvmem-cells = <&phy_calibration_p1>; |
| 422 | nvmem-cell-names = "phy-cal-data"; |
| 423 | }; |
| 424 | |
| 425 | sphy2: switch_phy2@2 { |
| 426 | compatible = "ethernet-phy-id03a2.9481"; |
| 427 | reg = <2>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 428 | pinctrl-names = "gbe-led"; |
| 429 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 430 | nvmem-cells = <&phy_calibration_p2>; |
| 431 | nvmem-cell-names = "phy-cal-data"; |
| 432 | }; |
| 433 | |
| 434 | sphy3: switch_phy3@3 { |
| 435 | compatible = "ethernet-phy-id03a2.9481"; |
| 436 | reg = <3>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame^] | 437 | pinctrl-names = "gbe-led"; |
| 438 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 439 | nvmem-cells = <&phy_calibration_p3>; |
| 440 | nvmem-cell-names = "phy-cal-data"; |
| 441 | }; |
| 442 | }; |
| 443 | }; |
| 444 | }; |
| 445 | }; |
| 446 | |
| 447 | &hnat { |
| 448 | mtketh-wan = "eth1"; |
| 449 | mtketh-lan = "lan"; |
| 450 | mtketh-lan2 = "eth2"; |
| 451 | mtketh-max-gmac = <3>; |
| 452 | status = "okay"; |
| 453 | }; |