developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988C DSA internal-2.5G SPIM-NAND RFB"; |
| 12 | compatible = "mediatek,mt7988c-dsa-i2p5g-spim-snand", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0 0x40000000 0 0x10000000>; |
| 24 | }; |
| 25 | |
| 26 | nmbm_spim_nand { |
| 27 | compatible = "generic,nmbm"; |
| 28 | |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | |
| 32 | lower-mtd-device = <&spi_nand>; |
| 33 | forced-create; |
| 34 | |
| 35 | partitions { |
| 36 | compatible = "fixed-partitions"; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | |
| 40 | partition@0 { |
| 41 | label = "BL2"; |
| 42 | reg = <0x00000 0x0100000>; |
| 43 | read-only; |
| 44 | }; |
| 45 | |
| 46 | partition@100000 { |
| 47 | label = "u-boot-env"; |
| 48 | reg = <0x0100000 0x0080000>; |
| 49 | }; |
| 50 | |
| 51 | factory: partition@180000 { |
| 52 | label = "Factory"; |
| 53 | reg = <0x180000 0x0400000>; |
| 54 | }; |
| 55 | |
| 56 | partition@580000 { |
| 57 | label = "FIP"; |
| 58 | reg = <0x580000 0x0200000>; |
| 59 | }; |
| 60 | |
| 61 | partition@780000 { |
| 62 | label = "ubi"; |
| 63 | reg = <0x780000 0x7080000>; |
| 64 | }; |
| 65 | }; |
| 66 | }; |
| 67 | |
| 68 | wsys_adie: wsys_adie@0 { |
| 69 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 70 | compatible = "mediatek,rebb-mt7988-adie"; |
| 71 | adie_id = <7976>; |
| 72 | sku_type = <3000>; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | &uart0 { |
| 77 | status = "okay"; |
| 78 | }; |
| 79 | |
| 80 | &spi0 { |
| 81 | pinctrl-names = "default"; |
| 82 | pinctrl-0 = <&spi0_flash_pins>; |
| 83 | status = "okay"; |
| 84 | |
| 85 | spi_nand: spi_nand@0 { |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <1>; |
| 88 | compatible = "spi-nand"; |
| 89 | spi-cal-enable; |
| 90 | spi-cal-mode = "read-data"; |
| 91 | spi-cal-datalen = <7>; |
| 92 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 93 | spi-cal-addrlen = <5>; |
| 94 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 95 | reg = <0>; |
| 96 | spi-max-frequency = <52000000>; |
| 97 | spi-tx-buswidth = <4>; |
| 98 | spi-rx-buswidth = <4>; |
| 99 | }; |
| 100 | }; |
| 101 | |
| 102 | &spi1 { |
| 103 | pinctrl-names = "default"; |
| 104 | /* pin shared with snfi */ |
| 105 | pinctrl-0 = <&spic_pins>; |
| 106 | status = "disabled"; |
| 107 | }; |
| 108 | |
| 109 | &pcie0 { |
| 110 | pinctrl-names = "default"; |
| 111 | pinctrl-0 = <&pcie0_pins>; |
| 112 | status = "okay"; |
| 113 | }; |
| 114 | |
| 115 | &pcie1 { |
| 116 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pcie1_pins>; |
| 118 | status = "disabled"; |
| 119 | }; |
| 120 | |
| 121 | &pcie2 { |
| 122 | pinctrl-names = "default"; |
| 123 | pinctrl-0 = <&pcie2_pins>; |
| 124 | status = "disabled"; |
| 125 | }; |
| 126 | |
| 127 | &pcie3 { |
| 128 | pinctrl-names = "default"; |
| 129 | pinctrl-0 = <&pcie3_pins>; |
| 130 | status = "okay"; |
| 131 | }; |
| 132 | |
| 133 | &pio { |
| 134 | pcie0_pins: pcie0-pins { |
| 135 | mux { |
| 136 | function = "pcie"; |
| 137 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 138 | "pcie_wake_n0_0"; |
| 139 | }; |
| 140 | }; |
| 141 | |
| 142 | pcie1_pins: pcie1-pins { |
| 143 | mux { |
| 144 | function = "pcie"; |
| 145 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 146 | "pcie_wake_n1_0"; |
| 147 | }; |
| 148 | }; |
| 149 | |
| 150 | pcie2_pins: pcie2-pins { |
| 151 | mux { |
| 152 | function = "pcie"; |
| 153 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 154 | "pcie_wake_n2_0"; |
| 155 | }; |
| 156 | }; |
| 157 | |
| 158 | pcie3_pins: pcie3-pins { |
| 159 | mux { |
| 160 | function = "pcie"; |
| 161 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 162 | "pcie_wake_n3_0"; |
| 163 | }; |
| 164 | }; |
| 165 | |
| 166 | spi0_flash_pins: spi0-pins { |
| 167 | mux { |
| 168 | function = "spi"; |
| 169 | groups = "spi0", "spi0_wp_hold"; |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | spic_pins: spi1-pins { |
| 174 | mux { |
| 175 | function = "spi"; |
| 176 | groups = "spi1_1"; |
| 177 | }; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | &watchdog { |
| 182 | status = "disabled"; |
| 183 | }; |
| 184 | |
| 185 | ð { |
| 186 | status = "okay"; |
| 187 | |
| 188 | gmac0: mac@0 { |
| 189 | compatible = "mediatek,eth-mac"; |
| 190 | reg = <0>; |
| 191 | mac-type = "xgdm"; |
| 192 | phy-mode = "10gbase-kr"; |
| 193 | |
| 194 | fixed-link { |
| 195 | speed = <2500>; |
| 196 | full-duplex; |
| 197 | pause; |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | gmac1: mac@1 { |
| 202 | compatible = "mediatek,eth-mac"; |
| 203 | reg = <1>; |
| 204 | mac-type = "xgdm"; |
| 205 | phy-mode = "xgmii"; |
| 206 | phy-handle = <&phy0>; |
| 207 | }; |
| 208 | |
| 209 | mdio: mdio-bus { |
| 210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; |
| 212 | phy0: ethernet-phy@0 { |
| 213 | reg = <15>; |
| 214 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 215 | phy-mode = "xgmii"; |
| 216 | }; |
| 217 | |
| 218 | switch@0 { |
| 219 | compatible = "mediatek,mt7988"; |
| 220 | reg = <31>; |
| 221 | ports { |
| 222 | #address-cells = <1>; |
| 223 | #size-cells = <0>; |
| 224 | |
| 225 | port@0 { |
| 226 | reg = <0>; |
| 227 | label = "lan0"; |
| 228 | phy-mode = "gmii"; |
| 229 | phy-handle = <&sphy0>; |
| 230 | }; |
| 231 | |
| 232 | port@1 { |
| 233 | reg = <1>; |
| 234 | label = "lan1"; |
| 235 | phy-mode = "gmii"; |
| 236 | phy-handle = <&sphy1>; |
| 237 | }; |
| 238 | |
| 239 | port@2 { |
| 240 | reg = <2>; |
| 241 | label = "lan2"; |
| 242 | phy-mode = "gmii"; |
| 243 | phy-handle = <&sphy2>; |
| 244 | }; |
| 245 | |
| 246 | port@3 { |
| 247 | reg = <3>; |
| 248 | label = "lan3"; |
| 249 | phy-mode = "gmii"; |
| 250 | phy-handle = <&sphy3>; |
| 251 | }; |
| 252 | |
| 253 | port@6 { |
| 254 | reg = <6>; |
| 255 | label = "cpu"; |
| 256 | ethernet = <&gmac0>; |
| 257 | phy-mode = "10gbase-kr"; |
| 258 | |
| 259 | fixed-link { |
| 260 | speed = <10000>; |
| 261 | full-duplex; |
| 262 | pause; |
| 263 | }; |
| 264 | }; |
| 265 | }; |
| 266 | |
| 267 | mdio { |
| 268 | compatible = "mediatek,dsa-slave-mdio"; |
| 269 | #address-cells = <1>; |
| 270 | #size-cells = <0>; |
| 271 | |
| 272 | sphy0: switch_phy0@0 { |
| 273 | compatible = "ethernet-phy-id03a2.9481"; |
| 274 | reg = <0>; |
| 275 | phy-mode = "gmii"; |
| 276 | rext = "efuse"; |
| 277 | tx_r50 = "efuse"; |
| 278 | nvmem-cells = <&phy_calibration_p0>; |
| 279 | nvmem-cell-names = "phy-cal-data"; |
| 280 | }; |
| 281 | |
| 282 | sphy1: switch_phy1@1 { |
| 283 | compatible = "ethernet-phy-id03a2.9481"; |
| 284 | reg = <1>; |
| 285 | phy-mode = "gmii"; |
| 286 | rext = "efuse"; |
| 287 | tx_r50 = "efuse"; |
| 288 | nvmem-cells = <&phy_calibration_p1>; |
| 289 | nvmem-cell-names = "phy-cal-data"; |
| 290 | }; |
| 291 | |
| 292 | sphy2: switch_phy2@2 { |
| 293 | compatible = "ethernet-phy-id03a2.9481"; |
| 294 | reg = <2>; |
| 295 | phy-mode = "gmii"; |
| 296 | rext = "efuse"; |
| 297 | tx_r50 = "efuse"; |
| 298 | nvmem-cells = <&phy_calibration_p2>; |
| 299 | nvmem-cell-names = "phy-cal-data"; |
| 300 | }; |
| 301 | |
| 302 | sphy3: switch_phy3@3 { |
| 303 | compatible = "ethernet-phy-id03a2.9481"; |
| 304 | reg = <3>; |
| 305 | phy-mode = "gmii"; |
| 306 | rext = "efuse"; |
| 307 | tx_r50 = "efuse"; |
| 308 | nvmem-cells = <&phy_calibration_p3>; |
| 309 | nvmem-cell-names = "phy-cal-data"; |
| 310 | }; |
| 311 | }; |
| 312 | }; |
| 313 | }; |
| 314 | }; |
| 315 | |
| 316 | &hnat { |
| 317 | mtketh-wan = "eth1"; |
| 318 | mtketh-lan = "lan"; |
| 319 | mtketh-lan2 = "eth2"; |
| 320 | mtketh-max-gmac = <3>; |
| 321 | status = "okay"; |
| 322 | }; |