developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2022 MediaTek Inc. */ |
| 3 | |
| 4 | #include <linux/kernel.h> |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/platform_device.h> |
| 7 | #include <linux/of.h> |
| 8 | #include <linux/of_device.h> |
| 9 | #include <linux/of_reserved_mem.h> |
| 10 | #include <linux/of_gpio.h> |
| 11 | #include <linux/iopoll.h> |
| 12 | #include <linux/reset.h> |
| 13 | #include <linux/of_net.h> |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 14 | #include <linux/clk.h> |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 15 | |
| 16 | #include "mt7915.h" |
| 17 | |
| 18 | /* INFRACFG */ |
| 19 | #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0 |
| 20 | #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4 |
| 21 | |
| 22 | #define MT_INFRACFG_RX_EN_MASK BIT(16) |
| 23 | #define MT_INFRACFG_TX_RDY_MASK BIT(4) |
| 24 | #define MT_INFRACFG_TX_EN_MASK BIT(0) |
| 25 | |
| 26 | /* TOP POS */ |
| 27 | #define MT_TOP_POS_FAST_CTRL 0x114 |
| 28 | #define MT_TOP_POS_FAST_EN_MASK BIT(3) |
| 29 | |
| 30 | #define MT_TOP_POS_SKU 0x21c |
| 31 | #define MT_TOP_POS_SKU_MASK GENMASK(31, 28) |
| 32 | #define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2) |
| 33 | |
| 34 | enum { |
| 35 | ADIE_SB, |
| 36 | ADIE_DBDC |
| 37 | }; |
| 38 | |
| 39 | static int |
| 40 | mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val) |
| 41 | { |
| 42 | int ret; |
| 43 | u32 cur; |
| 44 | |
| 45 | ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), |
| 46 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 47 | dev, MT_TOP_SPI_BUSY_CR(adie)); |
| 48 | if (ret) |
| 49 | return ret; |
| 50 | |
| 51 | mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), |
| 52 | MT_TOP_SPI_READ_ADDR_FORMAT | addr); |
| 53 | mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0); |
| 54 | |
| 55 | ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), |
| 56 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 57 | dev, MT_TOP_SPI_BUSY_CR(adie)); |
| 58 | if (ret) |
| 59 | return ret; |
| 60 | |
| 61 | *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie)); |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static int |
| 67 | mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val) |
| 68 | { |
| 69 | int ret; |
| 70 | u32 cur; |
| 71 | |
| 72 | ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), |
| 73 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 74 | dev, MT_TOP_SPI_BUSY_CR(adie)); |
| 75 | if (ret) |
| 76 | return ret; |
| 77 | |
| 78 | mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie), |
| 79 | MT_TOP_SPI_WRITE_ADDR_FORMAT | addr); |
| 80 | mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val); |
| 81 | |
| 82 | return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), |
| 83 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 84 | dev, MT_TOP_SPI_BUSY_CR(adie)); |
| 85 | } |
| 86 | |
| 87 | static int |
| 88 | mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie, |
| 89 | u32 addr, u32 mask, u32 val) |
| 90 | { |
| 91 | u32 cur, ret; |
| 92 | |
| 93 | ret = mt76_wmac_spi_read(dev, adie, addr, &cur); |
| 94 | if (ret) |
| 95 | return ret; |
| 96 | |
| 97 | cur &= ~mask; |
| 98 | cur |= val; |
| 99 | |
| 100 | return mt76_wmac_spi_write(dev, adie, addr, cur); |
| 101 | } |
| 102 | |
| 103 | static int |
| 104 | mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie, |
| 105 | u32 addr, u32 *data) |
| 106 | { |
| 107 | int ret, temp; |
| 108 | u32 val, mask; |
| 109 | |
| 110 | ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG, |
| 111 | MT_ADIE_EFUSE_CTRL_MASK); |
| 112 | if (ret) |
| 113 | return ret; |
| 114 | |
| 115 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0); |
| 116 | if (ret) |
| 117 | return ret; |
| 118 | |
| 119 | mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK | |
| 120 | MT_ADIE_EFUSE_KICK_MASK); |
| 121 | val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) | |
| 122 | FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) | |
| 123 | FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1); |
| 124 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val); |
| 125 | if (ret) |
| 126 | return ret; |
| 127 | |
| 128 | ret = read_poll_timeout(mt76_wmac_spi_read, temp, |
| 129 | !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val), |
| 130 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 131 | dev, adie, MT_ADIE_EFUSE2_CTRL, &val); |
| 132 | if (ret) |
| 133 | return ret; |
| 134 | |
| 135 | ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val); |
| 136 | if (ret) |
| 137 | return ret; |
| 138 | |
| 139 | if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1) |
| 140 | ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0, |
| 141 | data); |
| 142 | |
| 143 | return ret; |
| 144 | } |
| 145 | |
| 146 | static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev) |
| 147 | { |
| 148 | u32 cur; |
| 149 | |
| 150 | read_poll_timeout(mt76_rr, cur, |
| 151 | FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur), |
| 152 | 1000, 1000 * MSEC_PER_SEC, false, dev, |
| 153 | MT_SEMA_RFSPI_STATUS); |
| 154 | } |
| 155 | |
| 156 | static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev) |
| 157 | { |
| 158 | mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1); |
| 159 | } |
| 160 | |
| 161 | static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) |
| 162 | { |
| 163 | val |= readl(base + offset) & ~mask; |
| 164 | writel(val, base + offset); |
| 165 | |
| 166 | return val; |
| 167 | } |
| 168 | |
| 169 | static u8 mt7986_wmac_check_adie_type(struct mt7915_dev *dev) |
| 170 | { |
| 171 | u32 val; |
| 172 | |
| 173 | val = readl(dev->sku + MT_TOP_POS_SKU); |
| 174 | |
| 175 | return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val); |
| 176 | } |
| 177 | |
| 178 | static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable) |
| 179 | { |
| 180 | if (!enable) |
| 181 | return reset_control_assert(dev->rstc); |
| 182 | |
| 183 | mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL, |
| 184 | MT_TOP_POS_FAST_EN_MASK, |
| 185 | FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1)); |
| 186 | |
| 187 | return reset_control_deassert(dev->rstc); |
| 188 | } |
| 189 | |
| 190 | static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev) |
| 191 | { |
| 192 | struct pinctrl_state *state; |
| 193 | struct pinctrl *pinctrl; |
| 194 | int ret; |
| 195 | u8 type; |
| 196 | |
| 197 | type = mt7986_wmac_check_adie_type(dev); |
| 198 | pinctrl = devm_pinctrl_get(dev->mt76.dev); |
| 199 | if (IS_ERR(pinctrl)) |
| 200 | return PTR_ERR(pinctrl); |
| 201 | |
| 202 | switch (type) { |
| 203 | case ADIE_SB: |
| 204 | state = pinctrl_lookup_state(pinctrl, "default"); |
| 205 | if (IS_ERR_OR_NULL(state)) |
| 206 | return -EINVAL; |
| 207 | break; |
| 208 | case ADIE_DBDC: |
| 209 | state = pinctrl_lookup_state(pinctrl, "dbdc"); |
| 210 | if (IS_ERR_OR_NULL(state)) |
| 211 | return -EINVAL; |
| 212 | break; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 213 | default: |
| 214 | return -EINVAL; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | ret = pinctrl_select_state(pinctrl, state); |
| 218 | if (ret) |
| 219 | return ret; |
| 220 | |
| 221 | usleep_range(500, 1000); |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable) |
| 227 | { |
| 228 | int ret; |
| 229 | u32 cur; |
| 230 | |
| 231 | mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, |
| 232 | MT_INFRACFG_RX_EN_MASK, |
| 233 | FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); |
| 234 | ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK), |
| 235 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 236 | dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); |
| 237 | if (ret) |
| 238 | return ret; |
| 239 | |
| 240 | mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT, |
| 241 | MT_INFRACFG_TX_EN_MASK, |
| 242 | FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); |
| 243 | ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK), |
| 244 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 245 | dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT); |
| 246 | if (ret) |
| 247 | return ret; |
| 248 | |
| 249 | mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, |
| 250 | MT_INFRACFG_RX_EN_MASK, |
| 251 | FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable)); |
| 252 | mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT, |
| 253 | MT_INFRACFG_TX_EN_MASK, |
| 254 | FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable)); |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
| 259 | static int mt7986_wmac_coninfra_check(struct mt7915_dev *dev) |
| 260 | { |
| 261 | u32 cur; |
| 262 | |
| 263 | return read_poll_timeout(mt76_rr, cur, (cur == 0x02070000), |
| 264 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, |
| 265 | false, dev, MT_CONN_INFRA_BASE); |
| 266 | } |
| 267 | |
| 268 | static int mt7986_wmac_coninfra_setup(struct mt7915_dev *dev) |
| 269 | { |
| 270 | struct device *pdev = dev->mt76.dev; |
| 271 | struct reserved_mem *rmem; |
| 272 | struct device_node *np; |
| 273 | u32 val; |
| 274 | |
| 275 | np = of_parse_phandle(pdev->of_node, "memory-region", 0); |
| 276 | if (!np) |
| 277 | return -EINVAL; |
| 278 | |
| 279 | rmem = of_reserved_mem_lookup(np); |
| 280 | if (!rmem) |
| 281 | return -EINVAL; |
| 282 | |
| 283 | val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK; |
| 284 | |
| 285 | /* Set conninfra subsys PLL check */ |
| 286 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, |
| 287 | MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); |
| 288 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, |
| 289 | MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1); |
| 290 | |
| 291 | mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE, |
| 292 | MT_TOP_MCU_EMI_BASE_MASK, val); |
| 293 | |
| 294 | mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base); |
| 295 | mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size); |
| 296 | |
| 297 | mt76_rr(dev, MT_CONN_INFRA_EFUSE); |
| 298 | |
| 299 | /* Set conninfra sysram */ |
| 300 | mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0); |
| 301 | mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1); |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | static int mt7986_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type) |
| 307 | { |
| 308 | int ret; |
| 309 | u32 adie_main, adie_ext; |
| 310 | |
| 311 | mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, |
| 312 | MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1); |
| 313 | mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET, |
| 314 | MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1); |
| 315 | |
| 316 | mt76_wmac_spi_lock(dev); |
| 317 | |
| 318 | ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main); |
| 319 | if (ret) |
| 320 | goto out; |
| 321 | |
| 322 | ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext); |
| 323 | if (ret) |
| 324 | goto out; |
| 325 | |
| 326 | *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) | |
| 327 | (MT_ADIE_CHIP_ID_MASK & adie_ext); |
| 328 | |
| 329 | out: |
| 330 | mt76_wmac_spi_unlock(dev); |
| 331 | |
| 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type) |
| 336 | { |
| 337 | if (adie == 0) |
| 338 | return u32_get_bits(adie_type, MT_ADIE_IDX0); |
| 339 | else |
| 340 | return u32_get_bits(adie_type, MT_ADIE_IDX1); |
| 341 | } |
| 342 | |
| 343 | static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type) |
| 344 | { |
| 345 | return mt7986_adie_idx(adie, adie_type) == 0x7975; |
| 346 | } |
| 347 | |
| 348 | static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type) |
| 349 | { |
| 350 | return mt7986_adie_idx(adie, adie_type) == 0x7976; |
| 351 | } |
| 352 | |
| 353 | static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie) |
| 354 | { |
| 355 | int ret; |
| 356 | u32 data, val; |
| 357 | |
| 358 | ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG, |
| 359 | &data); |
| 360 | if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { |
| 361 | val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data); |
| 362 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG, |
| 363 | MT_ADIE_VRPI_SEL_CR_MASK, |
| 364 | FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val)); |
| 365 | if (ret) |
| 366 | return ret; |
| 367 | |
| 368 | val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data); |
| 369 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, |
| 370 | MT_ADIE_PGA_GAIN_MASK, |
| 371 | FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val)); |
| 372 | if (ret) |
| 373 | return ret; |
| 374 | } |
| 375 | |
| 376 | ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP, |
| 377 | &data); |
| 378 | if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) { |
| 379 | val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data); |
| 380 | |
| 381 | return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC, |
| 382 | MT_ADIE_LDO_CTRL_MASK, |
| 383 | FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val)); |
| 384 | } |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static int |
| 390 | mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie, |
| 391 | bool is_40m, int *result) |
| 392 | { |
| 393 | int ret; |
| 394 | u32 data, addr; |
| 395 | |
| 396 | addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC; |
| 397 | ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); |
| 398 | if (ret) |
| 399 | return ret; |
| 400 | |
| 401 | if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) { |
| 402 | *result = 64; |
| 403 | } else { |
| 404 | *result = FIELD_GET(MT_ADIE_TRIM_MASK, data); |
| 405 | addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC : |
| 406 | MT_ADIE_XTAL_TRIM1_80M_OSC; |
| 407 | ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); |
| 408 | if (ret) |
| 409 | return ret; |
| 410 | |
| 411 | if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) && |
| 412 | FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data)) |
| 413 | *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); |
| 414 | else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) |
| 415 | *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data); |
| 416 | |
| 417 | *result = max(0, min(127, *result)); |
| 418 | } |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie) |
| 424 | { |
| 425 | int ret, trim_80m, trim_40m; |
| 426 | u32 data, val, mode; |
| 427 | |
| 428 | ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW, |
| 429 | &data); |
| 430 | if (ret || !FIELD_GET(BIT(1), data)) |
| 431 | return 0; |
| 432 | |
| 433 | ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m); |
| 434 | if (ret) |
| 435 | return ret; |
| 436 | |
| 437 | ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m); |
| 438 | if (ret) |
| 439 | return ret; |
| 440 | |
| 441 | ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val); |
| 442 | if (ret) |
| 443 | return ret; |
| 444 | |
| 445 | mode = FIELD_PREP(GENMASK(6, 4), val); |
| 446 | if (!mode || mode == 0x2) { |
| 447 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, |
| 448 | GENMASK(31, 24), |
| 449 | FIELD_PREP(GENMASK(31, 24), trim_80m)); |
| 450 | if (ret) |
| 451 | return ret; |
| 452 | |
| 453 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, |
| 454 | GENMASK(31, 24), |
| 455 | FIELD_PREP(GENMASK(31, 24), trim_80m)); |
| 456 | } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) { |
| 457 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1, |
| 458 | GENMASK(23, 16), |
| 459 | FIELD_PREP(GENMASK(23, 16), trim_40m)); |
| 460 | if (ret) |
| 461 | return ret; |
| 462 | |
| 463 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2, |
| 464 | GENMASK(23, 16), |
| 465 | FIELD_PREP(GENMASK(23, 16), trim_40m)); |
| 466 | } |
| 467 | |
| 468 | return ret; |
| 469 | } |
| 470 | |
| 471 | static int mt7986_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie) |
| 472 | { |
| 473 | int ret; |
| 474 | |
| 475 | ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00); |
| 476 | if (ret) |
| 477 | return ret; |
| 478 | |
| 479 | ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, 0x1d59080f); |
| 480 | if (ret) |
| 481 | return ret; |
| 482 | |
| 483 | return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, 0x34c00fe0); |
| 484 | } |
| 485 | |
| 486 | static int |
| 487 | mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie, |
| 488 | u32 addr, u32 *result) |
| 489 | { |
| 490 | int ret; |
| 491 | u32 data; |
| 492 | |
| 493 | ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data); |
| 494 | if (ret) |
| 495 | return ret; |
| 496 | |
| 497 | if ((data & MT_ADIE_XO_TRIM_EN_MASK)) { |
| 498 | if ((data & MT_ADIE_XTAL_DECREASE_MASK)) |
| 499 | *result -= (data & MT_ADIE_EFUSE_TRIM_MASK); |
| 500 | else |
| 501 | *result += (data & MT_ADIE_EFUSE_TRIM_MASK); |
| 502 | |
| 503 | *result = (*result & MT_ADIE_TRIM_MASK); |
| 504 | } |
| 505 | |
| 506 | return 0; |
| 507 | } |
| 508 | |
| 509 | static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie) |
| 510 | { |
| 511 | int ret; |
| 512 | u32 data, result = 0, value; |
| 513 | |
| 514 | ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN, |
| 515 | &data); |
| 516 | if (ret || !(data & BIT(1))) |
| 517 | return 0; |
| 518 | |
| 519 | ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL, |
| 520 | &data); |
| 521 | if (ret) |
| 522 | return ret; |
| 523 | |
| 524 | if (data & MT_ADIE_XO_TRIM_EN_MASK) |
| 525 | result = (data & MT_ADIE_TRIM_MASK); |
| 526 | |
| 527 | ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2, |
| 528 | &result); |
| 529 | if (ret) |
| 530 | return ret; |
| 531 | |
| 532 | ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3, |
| 533 | &result); |
| 534 | if (ret) |
| 535 | return ret; |
| 536 | |
| 537 | ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4, |
| 538 | &result); |
| 539 | if (ret) |
| 540 | return ret; |
| 541 | |
| 542 | /* Update trim value to C1 and C2*/ |
| 543 | value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) | |
| 544 | FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result); |
| 545 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2, |
| 546 | MT_ADIE_7975_XO_CTRL2_MASK, value); |
| 547 | if (ret) |
| 548 | return ret; |
| 549 | |
| 550 | ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value); |
| 551 | if (ret) |
| 552 | return ret; |
| 553 | |
| 554 | if (value & MT_ADIE_7975_XTAL_EN_MASK) { |
| 555 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2, |
| 556 | MT_ADIE_7975_XO_2_FIX_EN, 0x0); |
| 557 | if (ret) |
| 558 | return ret; |
| 559 | } |
| 560 | |
| 561 | return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6, |
| 562 | MT_ADIE_7975_XO_CTRL6_MASK, 0x1); |
| 563 | } |
| 564 | |
| 565 | static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie) |
| 566 | { |
| 567 | int ret; |
| 568 | |
| 569 | /* disable CAL LDO and fine tune RFDIG LDO */ |
| 570 | ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002); |
| 571 | if (ret) |
| 572 | return ret; |
| 573 | |
| 574 | ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002); |
| 575 | if (ret) |
| 576 | return ret; |
| 577 | |
| 578 | ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002); |
| 579 | if (ret) |
| 580 | return ret; |
| 581 | |
| 582 | ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002); |
| 583 | if (ret) |
| 584 | return ret; |
| 585 | |
| 586 | /* set CKA driving and filter */ |
| 587 | ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa); |
| 588 | if (ret) |
| 589 | return ret; |
| 590 | |
| 591 | /* set CKB LDO to 1.4V */ |
| 592 | ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a); |
| 593 | if (ret) |
| 594 | return ret; |
| 595 | |
| 596 | /* turn on SX0 LTBUF */ |
| 597 | ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002); |
| 598 | if (ret) |
| 599 | return ret; |
| 600 | |
| 601 | /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */ |
| 602 | ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0); |
| 603 | if (ret) |
| 604 | return ret; |
| 605 | |
| 606 | /* BT mode/WF normal mode 00000005 */ |
| 607 | ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005); |
| 608 | if (ret) |
| 609 | return ret; |
| 610 | |
| 611 | /* BG thermal sensor offset update */ |
| 612 | ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088); |
| 613 | if (ret) |
| 614 | return ret; |
| 615 | |
| 616 | ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088); |
| 617 | if (ret) |
| 618 | return ret; |
| 619 | |
| 620 | ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088); |
| 621 | if (ret) |
| 622 | return ret; |
| 623 | |
| 624 | ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088); |
| 625 | if (ret) |
| 626 | return ret; |
| 627 | |
| 628 | /* set WCON VDD IPTAT to "0000" */ |
| 629 | ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000); |
| 630 | if (ret) |
| 631 | return ret; |
| 632 | |
| 633 | /* change back LTBUF SX3 drving to default value */ |
| 634 | ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa); |
| 635 | if (ret) |
| 636 | return ret; |
| 637 | |
| 638 | /* SM input cap off */ |
| 639 | ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000); |
| 640 | if (ret) |
| 641 | return ret; |
| 642 | |
| 643 | /* set CKB driving and filter */ |
| 644 | return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072); |
| 645 | } |
| 646 | |
| 647 | static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type) |
| 648 | { |
| 649 | int ret; |
| 650 | |
| 651 | mt76_wmac_spi_lock(dev); |
| 652 | ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0); |
| 653 | if (ret) |
| 654 | goto out; |
| 655 | |
| 656 | if (is_7975(dev, adie, adie_type)) { |
| 657 | ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK, |
| 658 | BIT(1), 0x1); |
| 659 | if (ret) |
| 660 | goto out; |
| 661 | |
| 662 | ret = mt7986_wmac_adie_thermal_cal(dev, adie); |
| 663 | if (ret) |
| 664 | goto out; |
| 665 | |
| 666 | ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie); |
| 667 | if (ret) |
| 668 | goto out; |
| 669 | |
| 670 | ret = mt7986_wmac_adie_patch_7975(dev, adie); |
| 671 | } else if (is_7976(dev, adie, adie_type)) { |
| 672 | if (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC) { |
| 673 | ret = mt76_wmac_spi_write(dev, adie, |
| 674 | MT_ADIE_WRI_CK_SEL, 0x1c); |
| 675 | if (ret) |
| 676 | goto out; |
| 677 | } |
| 678 | |
| 679 | ret = mt7986_wmac_adie_thermal_cal(dev, adie); |
| 680 | if (ret) |
| 681 | goto out; |
| 682 | |
| 683 | ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie); |
| 684 | if (ret) |
| 685 | goto out; |
| 686 | |
| 687 | ret = mt7986_wmac_adie_patch_7976(dev, adie); |
| 688 | } |
| 689 | out: |
| 690 | mt76_wmac_spi_unlock(dev); |
| 691 | |
| 692 | return ret; |
| 693 | } |
| 694 | |
| 695 | static int |
| 696 | mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type) |
| 697 | { |
| 698 | int ret; |
| 699 | u8 idx; |
| 700 | |
| 701 | mt76_wmac_spi_lock(dev); |
| 702 | if (is_7975(dev, adie, adie_type)) |
| 703 | ret = mt76_wmac_spi_write(dev, adie, |
| 704 | MT_AFE_RG_ENCAL_WBTAC_IF_SW, |
| 705 | 0x80000000); |
| 706 | else |
| 707 | ret = mt76_wmac_spi_write(dev, adie, |
| 708 | MT_AFE_RG_ENCAL_WBTAC_IF_SW, |
| 709 | 0x88888005); |
| 710 | if (ret) |
| 711 | goto out; |
| 712 | |
| 713 | idx = dbdc ? ADIE_DBDC : adie; |
| 714 | |
| 715 | mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), |
| 716 | MT_AFE_RG_WBG_EN_RCK_MASK, 0x1); |
| 717 | usleep_range(60, 100); |
| 718 | |
| 719 | mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), |
| 720 | MT_AFE_RG_WBG_EN_RCK_MASK, 0x0); |
| 721 | |
| 722 | mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), |
| 723 | MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1); |
| 724 | usleep_range(30, 100); |
| 725 | |
| 726 | mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx), |
| 727 | MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1); |
| 728 | usleep_range(60, 100); |
| 729 | |
| 730 | mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx), |
| 731 | MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x1f); |
| 732 | usleep_range(800, 1000); |
| 733 | |
| 734 | mt76_rmw(dev, MT_AFE_DIG_EN_01(idx), |
| 735 | MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x0); |
| 736 | mt76_rmw(dev, MT_AFE_DIG_EN_03(idx), |
| 737 | MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0); |
| 738 | |
| 739 | ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW, |
| 740 | 0x5); |
| 741 | |
| 742 | out: |
| 743 | mt76_wmac_spi_unlock(dev); |
| 744 | |
| 745 | return ret; |
| 746 | } |
| 747 | |
| 748 | static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band) |
| 749 | { |
| 750 | mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band), |
| 751 | MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL); |
| 752 | |
| 753 | mt76_rmw(dev, MT_AFE_DIG_EN_02(band), |
| 754 | MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL); |
| 755 | |
| 756 | mt76_rmw(dev, MT_AFE_DIG_TOP_01(band), |
| 757 | MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL); |
| 758 | } |
| 759 | |
| 760 | static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev) |
| 761 | { |
| 762 | /* Subsys pll init */ |
| 763 | mt7986_wmac_subsys_pll_initial(dev, 0); |
| 764 | mt7986_wmac_subsys_pll_initial(dev, 1); |
| 765 | |
| 766 | /* Set legacy OSC control stable time*/ |
| 767 | mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN, |
| 768 | MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0); |
| 769 | mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL, |
| 770 | MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706); |
| 771 | |
| 772 | /* prevent subsys from power on/of in a short time interval */ |
| 773 | mt76_rmw(dev, MT_TOP_WFSYS_PWR, |
| 774 | MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK, |
| 775 | MT_TOP_PWR_KEY); |
| 776 | } |
| 777 | |
| 778 | static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev) |
| 779 | { |
| 780 | mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, |
| 781 | MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2); |
| 782 | |
| 783 | mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT, |
| 784 | MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); |
| 785 | |
| 786 | mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, |
| 787 | MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc); |
| 788 | |
| 789 | mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT, |
| 790 | MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf); |
| 791 | |
| 792 | return mt7986_wmac_coninfra_check(dev); |
| 793 | } |
| 794 | |
| 795 | static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type) |
| 796 | { |
| 797 | u32 cur; |
| 798 | |
| 799 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, |
| 800 | MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); |
| 801 | |
| 802 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, |
| 803 | MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1); |
| 804 | |
| 805 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1, |
| 806 | MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); |
| 807 | |
| 808 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2, |
| 809 | MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); |
| 810 | |
| 811 | mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, |
| 812 | MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8); |
| 813 | |
| 814 | mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV, |
| 815 | MT_INFRA_CKGEN_DIV_EN_MASK, 0x1); |
| 816 | |
| 817 | mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS, |
| 818 | MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0); |
| 819 | |
| 820 | mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL, |
| 821 | MT_CONN_INFRA_HW_CTRL_MASK, 0x1); |
| 822 | |
| 823 | mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, |
| 824 | MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1); |
| 825 | |
| 826 | usleep_range(900, 1000); |
| 827 | |
| 828 | mt76_wmac_spi_lock(dev); |
| 829 | if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) { |
| 830 | mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0), |
| 831 | MT_SLP_CTRL_EN_MASK, 0x1); |
| 832 | |
| 833 | read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), |
| 834 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 835 | dev, MT_ADIE_SLP_CTRL_CK0(0)); |
| 836 | } |
| 837 | if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) { |
| 838 | mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1), |
| 839 | MT_SLP_CTRL_EN_MASK, 0x1); |
| 840 | |
| 841 | read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), |
| 842 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 843 | dev, MT_ADIE_SLP_CTRL_CK0(0)); |
| 844 | } |
| 845 | mt76_wmac_spi_unlock(dev); |
| 846 | |
| 847 | mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP, |
| 848 | MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0); |
| 849 | usleep_range(900, 1000); |
| 850 | } |
| 851 | |
| 852 | static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable) |
| 853 | { |
| 854 | mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP, |
| 855 | MT_TOP_WFSYS_WAKEUP_MASK, enable); |
| 856 | |
| 857 | usleep_range(900, 1000); |
| 858 | |
| 859 | if (!enable) |
| 860 | return 0; |
| 861 | |
| 862 | return mt7986_wmac_coninfra_check(dev); |
| 863 | } |
| 864 | |
| 865 | static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable) |
| 866 | { |
| 867 | u32 cur; |
| 868 | |
| 869 | mt76_rmw_field(dev, MT7986_TOP_WM_RESET, |
| 870 | MT7986_TOP_WM_RESET_MASK, enable); |
| 871 | if (!enable) |
| 872 | return 0; |
| 873 | |
| 874 | return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e), |
| 875 | USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false, |
| 876 | dev, MT_TOP_CFG_ON_ROM_IDX); |
| 877 | } |
| 878 | |
| 879 | static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable) |
| 880 | { |
| 881 | u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK; |
| 882 | u32 cur; |
| 883 | |
| 884 | mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask, |
| 885 | MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable)); |
| 886 | |
| 887 | return read_poll_timeout(mt76_rr, cur, |
| 888 | (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable), |
| 889 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 890 | dev, MT_TOP_WFSYS_RESET_STATUS); |
| 891 | } |
| 892 | |
| 893 | static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev) |
| 894 | { |
| 895 | int ret; |
| 896 | u32 cur; |
| 897 | |
| 898 | /* Turn off wfsys2conn bus sleep protect */ |
| 899 | mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT, |
| 900 | MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0); |
| 901 | |
| 902 | ret = mt7986_wmac_wfsys_poweron(dev, true); |
| 903 | if (ret) |
| 904 | return ret; |
| 905 | |
| 906 | /* Check bus sleep protect */ |
| 907 | |
| 908 | ret = read_poll_timeout(mt76_rr, cur, |
| 909 | !(cur & MT_CONN_INFRA_CONN_WF_MASK), |
| 910 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 911 | dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); |
| 912 | if (ret) |
| 913 | return ret; |
| 914 | |
| 915 | ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK), |
| 916 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 917 | dev, MT_SLP_STATUS); |
| 918 | if (ret) |
| 919 | return ret; |
| 920 | |
| 921 | return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000), |
| 922 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 923 | dev, MT_TOP_CFG_IP_VERSION_ADDR); |
| 924 | } |
| 925 | |
| 926 | static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev) |
| 927 | { |
| 928 | u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK | |
| 929 | MT_MCU_BUS_TIMEOUT_CG_EN_MASK | |
| 930 | MT_MCU_BUS_TIMEOUT_EN_MASK; |
| 931 | u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) | |
| 932 | FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) | |
| 933 | FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1); |
| 934 | |
| 935 | mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val); |
| 936 | |
| 937 | mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000); |
| 938 | |
| 939 | mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK | |
| 940 | MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK | |
| 941 | MT_MCU_BUS_DBG_TIMEOUT_EN_MASK; |
| 942 | val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) | |
| 943 | FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) | |
| 944 | FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1); |
| 945 | |
| 946 | mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val); |
| 947 | } |
| 948 | |
| 949 | static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type) |
| 950 | { |
| 951 | u32 val; |
| 952 | |
| 953 | if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type)) |
| 954 | val = 0xf; |
| 955 | else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type)) |
| 956 | val = 0xd; |
| 957 | else if (is_7976(dev, 0, adie_type)) |
| 958 | val = 0x7; |
| 959 | else if (is_7975(dev, 1, adie_type)) |
| 960 | val = 0x8; |
| 961 | else if (is_7976(dev, 1, adie_type)) |
| 962 | val = 0xa; |
| 963 | else |
| 964 | return -EINVAL; |
| 965 | |
| 966 | mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK, |
| 967 | FIELD_PREP(MT_TOP_POS_SKU_MASK, val)); |
| 968 | |
| 969 | mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val); |
| 970 | |
| 971 | return 0; |
| 972 | } |
| 973 | |
| 974 | static int |
| 975 | mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type) |
| 976 | { |
| 977 | int ret; |
| 978 | |
| 979 | if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type))) |
| 980 | return 0; |
| 981 | |
| 982 | ret = mt7986_wmac_adie_cfg(dev, adie, adie_type); |
| 983 | if (ret) |
| 984 | return ret; |
| 985 | |
| 986 | ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type); |
| 987 | if (ret) |
| 988 | return ret; |
| 989 | |
| 990 | if (!adie && (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC)) |
| 991 | ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type); |
| 992 | |
| 993 | return ret; |
| 994 | } |
| 995 | |
| 996 | static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type) |
| 997 | { |
| 998 | int ret; |
| 999 | |
| 1000 | mt7986_wmac_subsys_setting(dev); |
| 1001 | |
| 1002 | ret = mt7986_wmac_bus_timeout(dev); |
| 1003 | if (ret) |
| 1004 | return ret; |
| 1005 | |
| 1006 | mt7986_wmac_clock_enable(dev, adie_type); |
| 1007 | |
| 1008 | return 0; |
| 1009 | } |
| 1010 | |
| 1011 | static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev) |
| 1012 | { |
| 1013 | int ret; |
| 1014 | |
| 1015 | ret = mt7986_wmac_wm_enable(dev, false); |
| 1016 | if (ret) |
| 1017 | return ret; |
| 1018 | |
| 1019 | ret = mt7986_wmac_wfsys_setting(dev); |
| 1020 | if (ret) |
| 1021 | return ret; |
| 1022 | |
| 1023 | mt7986_wmac_wfsys_set_timeout(dev); |
| 1024 | |
| 1025 | return mt7986_wmac_wm_enable(dev, true); |
| 1026 | } |
| 1027 | |
| 1028 | int mt7986_wmac_enable(struct mt7915_dev *dev) |
| 1029 | { |
| 1030 | int ret; |
| 1031 | u32 adie_type; |
| 1032 | |
| 1033 | ret = mt7986_wmac_consys_reset(dev, true); |
| 1034 | if (ret) |
| 1035 | return ret; |
| 1036 | |
| 1037 | ret = mt7986_wmac_gpio_setup(dev); |
| 1038 | if (ret) |
| 1039 | return ret; |
| 1040 | |
| 1041 | ret = mt7986_wmac_consys_lockup(dev, false); |
| 1042 | if (ret) |
| 1043 | return ret; |
| 1044 | |
| 1045 | ret = mt7986_wmac_coninfra_check(dev); |
| 1046 | if (ret) |
| 1047 | return ret; |
| 1048 | |
| 1049 | ret = mt7986_wmac_coninfra_setup(dev); |
| 1050 | if (ret) |
| 1051 | return ret; |
| 1052 | |
| 1053 | ret = mt7986_wmac_sku_setup(dev, &adie_type); |
| 1054 | if (ret) |
| 1055 | return ret; |
| 1056 | |
| 1057 | ret = mt7986_wmac_adie_setup(dev, 0, adie_type); |
| 1058 | if (ret) |
| 1059 | return ret; |
| 1060 | |
| 1061 | ret = mt7986_wmac_adie_setup(dev, 1, adie_type); |
| 1062 | if (ret) |
| 1063 | return ret; |
| 1064 | |
| 1065 | ret = mt7986_wmac_subsys_powerup(dev, adie_type); |
| 1066 | if (ret) |
| 1067 | return ret; |
| 1068 | |
| 1069 | ret = mt7986_wmac_top_wfsys_wakeup(dev, true); |
| 1070 | if (ret) |
| 1071 | return ret; |
| 1072 | |
| 1073 | ret = mt7986_wmac_wfsys_powerup(dev); |
| 1074 | if (ret) |
| 1075 | return ret; |
| 1076 | |
| 1077 | return mt7986_wmac_sku_update(dev, adie_type); |
| 1078 | } |
| 1079 | |
| 1080 | void mt7986_wmac_disable(struct mt7915_dev *dev) |
| 1081 | { |
| 1082 | u32 cur; |
| 1083 | |
| 1084 | mt7986_wmac_top_wfsys_wakeup(dev, true); |
| 1085 | |
| 1086 | /* Turn on wfsys2conn bus sleep protect */ |
| 1087 | mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT, |
| 1088 | MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1); |
| 1089 | |
| 1090 | /* Check wfsys2conn bus sleep protect */ |
| 1091 | read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN), |
| 1092 | USEC_PER_MSEC, 50 * USEC_PER_MSEC, false, |
| 1093 | dev, MT_CONN_INFRA_WF_SLP_PROT_RDY); |
| 1094 | |
| 1095 | mt7986_wmac_wfsys_poweron(dev, false); |
| 1096 | |
| 1097 | /* Turn back wpll setting */ |
| 1098 | mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2); |
| 1099 | mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2); |
| 1100 | |
| 1101 | /* Reset EMI */ |
| 1102 | mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, |
| 1103 | MT_CONN_INFRA_EMI_REQ_MASK, 0x1); |
| 1104 | mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, |
| 1105 | MT_CONN_INFRA_EMI_REQ_MASK, 0x0); |
| 1106 | mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, |
| 1107 | MT_CONN_INFRA_INFRA_REQ_MASK, 0x1); |
| 1108 | mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ, |
| 1109 | MT_CONN_INFRA_INFRA_REQ_MASK, 0x0); |
| 1110 | |
| 1111 | mt7986_wmac_top_wfsys_wakeup(dev, false); |
| 1112 | mt7986_wmac_consys_lockup(dev, true); |
| 1113 | mt7986_wmac_consys_reset(dev, false); |
| 1114 | } |
| 1115 | |
| 1116 | static int mt7986_wmac_init(struct mt7915_dev *dev) |
| 1117 | { |
| 1118 | struct device *pdev = dev->mt76.dev; |
| 1119 | struct platform_device *pfdev = to_platform_device(pdev); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1120 | struct clk *mcu_clk, *ap_conn_clk; |
| 1121 | |
| 1122 | mcu_clk = devm_clk_get(pdev, "mcu"); |
| 1123 | if (IS_ERR(mcu_clk)) |
| 1124 | dev_err(pdev, "mcu clock not found\n"); |
| 1125 | else if (clk_prepare_enable(mcu_clk)) |
| 1126 | dev_err(pdev, "mcu clock configuration failed\n"); |
| 1127 | |
| 1128 | ap_conn_clk = devm_clk_get(pdev, "ap2conn"); |
| 1129 | if (IS_ERR(ap_conn_clk)) |
| 1130 | dev_err(pdev, "ap2conn clock not found\n"); |
| 1131 | else if (clk_prepare_enable(ap_conn_clk)) |
| 1132 | dev_err(pdev, "ap2conn clock configuration failed\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1133 | |
| 1134 | dev->dcm = devm_platform_ioremap_resource(pfdev, 1); |
| 1135 | if (IS_ERR(dev->dcm)) |
| 1136 | return PTR_ERR(dev->dcm); |
| 1137 | |
| 1138 | dev->sku = devm_platform_ioremap_resource(pfdev, 2); |
| 1139 | if (IS_ERR(dev->sku)) |
| 1140 | return PTR_ERR(dev->sku); |
| 1141 | |
| 1142 | dev->rstc = devm_reset_control_get(pdev, "consys"); |
| 1143 | if (IS_ERR(dev->rstc)) |
| 1144 | return PTR_ERR(dev->rstc); |
| 1145 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1146 | return 0; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | static int mt7986_wmac_probe(struct platform_device *pdev) |
| 1150 | { |
| 1151 | void __iomem *mem_base; |
| 1152 | struct mt7915_dev *dev; |
| 1153 | struct mt76_dev *mdev; |
| 1154 | int irq, ret; |
| 1155 | u32 chip_id; |
| 1156 | |
| 1157 | chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev); |
| 1158 | |
| 1159 | irq = platform_get_irq(pdev, 0); |
| 1160 | if (irq < 0) |
| 1161 | return irq; |
| 1162 | |
| 1163 | mem_base = devm_platform_ioremap_resource(pdev, 0); |
| 1164 | if (IS_ERR(mem_base)) { |
| 1165 | dev_err(&pdev->dev, "Failed to get memory resource\n"); |
| 1166 | return PTR_ERR(mem_base); |
| 1167 | } |
| 1168 | |
| 1169 | dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id); |
| 1170 | if (IS_ERR(dev)) |
| 1171 | return PTR_ERR(dev); |
| 1172 | |
| 1173 | mdev = &dev->mt76; |
| 1174 | ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler, |
| 1175 | IRQF_SHARED, KBUILD_MODNAME, dev); |
| 1176 | if (ret) |
| 1177 | goto free_device; |
| 1178 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1179 | ret = mt7986_wmac_init(dev); |
| 1180 | if (ret) |
| 1181 | goto free_irq; |
| 1182 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1183 | mt7915_wfsys_reset(dev); |
| 1184 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 1185 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1186 | ret = mt7915_register_device(dev); |
| 1187 | if (ret) |
| 1188 | goto free_irq; |
| 1189 | |
| 1190 | return 0; |
| 1191 | |
| 1192 | free_irq: |
| 1193 | devm_free_irq(mdev->dev, irq, dev); |
| 1194 | |
| 1195 | free_device: |
| 1196 | mt76_free_device(&dev->mt76); |
| 1197 | |
| 1198 | return ret; |
| 1199 | } |
| 1200 | |
| 1201 | static int mt7986_wmac_remove(struct platform_device *pdev) |
| 1202 | { |
| 1203 | struct mt7915_dev *dev = platform_get_drvdata(pdev); |
| 1204 | |
| 1205 | mt7915_unregister_device(dev); |
| 1206 | |
| 1207 | return 0; |
| 1208 | } |
| 1209 | |
| 1210 | static const struct of_device_id mt7986_wmac_of_match[] = { |
| 1211 | { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 }, |
| 1212 | {}, |
| 1213 | }; |
| 1214 | |
| 1215 | struct platform_driver mt7986_wmac_driver = { |
| 1216 | .driver = { |
| 1217 | .name = "mt7986-wmac", |
| 1218 | .of_match_table = mt7986_wmac_of_match, |
| 1219 | }, |
| 1220 | .probe = mt7986_wmac_probe, |
| 1221 | .remove = mt7986_wmac_remove, |
| 1222 | }; |
| 1223 | |
| 1224 | MODULE_FIRMWARE(MT7986_FIRMWARE_WA); |
| 1225 | MODULE_FIRMWARE(MT7986_FIRMWARE_WM); |
| 1226 | MODULE_FIRMWARE(MT7986_FIRMWARE_WM_MT7975); |
| 1227 | MODULE_FIRMWARE(MT7986_ROM_PATCH); |
| 1228 | MODULE_FIRMWARE(MT7986_ROM_PATCH_MT7975); |