developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4 | #ifndef __BESRA_MAC_H |
| 5 | #define __BESRA_MAC_H |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6 | |
| 7 | #define MT_CT_PARSE_LEN 72 |
| 8 | #define MT_CT_DMA_BUF_NUM 2 |
| 9 | |
| 10 | #define MT_RXD0_LENGTH GENMASK(15, 0) |
| 11 | #define MT_RXD0_PKT_TYPE GENMASK(31, 27) |
| 12 | |
| 13 | #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16) |
| 14 | #define MT_RXD0_NORMAL_IP_SUM BIT(23) |
| 15 | #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) |
| 16 | |
| 17 | #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16) |
| 18 | #define MT_RXD0_SW_PKT_TYPE_MAP 0x380F |
| 19 | #define MT_RXD0_SW_PKT_TYPE_FRAME 0x3801 |
| 20 | |
| 21 | enum rx_pkt_type { |
| 22 | PKT_TYPE_TXS, |
| 23 | PKT_TYPE_TXRXV, |
| 24 | PKT_TYPE_NORMAL, |
| 25 | PKT_TYPE_RX_DUP_RFB, |
| 26 | PKT_TYPE_RX_TMR, |
| 27 | PKT_TYPE_RETRIEVE, |
| 28 | PKT_TYPE_TXRX_NOTIFY, |
| 29 | PKT_TYPE_RX_EVENT, |
| 30 | PKT_TYPE_RX_FW_MONITOR = 0x0c, |
| 31 | }; |
| 32 | |
| 33 | /* RXD DW1 */ |
| 34 | #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0) |
| 35 | #define MT_RXD1_NORMAL_GROUP_1 BIT(16) |
| 36 | #define MT_RXD1_NORMAL_GROUP_2 BIT(17) |
| 37 | #define MT_RXD1_NORMAL_GROUP_3 BIT(18) |
| 38 | #define MT_RXD1_NORMAL_GROUP_4 BIT(19) |
| 39 | #define MT_RXD1_NORMAL_GROUP_5 BIT(20) |
| 40 | #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21) |
| 41 | #define MT_RXD1_NORMAL_CM BIT(23) |
| 42 | #define MT_RXD1_NORMAL_CLM BIT(24) |
| 43 | #define MT_RXD1_NORMAL_ICV_ERR BIT(25) |
| 44 | #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26) |
| 45 | #define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27) |
| 46 | #define MT_RXD1_NORMAL_SPP_EN BIT(29) |
| 47 | #define MT_RXD1_NORMAL_ADD_OM BIT(30) |
| 48 | #define MT_RXD1_NORMAL_SEC_DONE BIT(31) |
| 49 | |
| 50 | /* RXD DW2 */ |
| 51 | #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0) |
| 52 | #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8) |
| 53 | #define MT_RXD2_NORMAL_HDR_TRANS BIT(7) |
| 54 | #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 13) |
| 55 | #define MT_RXD2_NORMAL_SEC_MODE GENMASK(20, 16) |
| 56 | #define MT_RXD2_NORMAL_MU_BAR BIT(21) |
| 57 | #define MT_RXD2_NORMAL_SW_BIT BIT(22) |
| 58 | #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23) |
| 59 | #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24) |
| 60 | #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25) |
| 61 | #define MT_RXD2_NORMAL_INT_FRAME BIT(26) |
| 62 | #define MT_RXD2_NORMAL_FRAG BIT(27) |
| 63 | #define MT_RXD2_NORMAL_NULL_FRAME BIT(28) |
| 64 | #define MT_RXD2_NORMAL_NDATA BIT(29) |
| 65 | #define MT_RXD2_NORMAL_NON_AMPDU BIT(30) |
| 66 | #define MT_RXD2_NORMAL_BF_REPORT BIT(31) |
| 67 | |
| 68 | /* RXD DW3 */ |
| 69 | #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0) |
| 70 | #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8) |
| 71 | #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16) |
| 72 | #define MT_RXD3_NORMAL_U2M BIT(0) |
| 73 | #define MT_RXD3_NORMAL_HTC_VLD BIT(18) |
| 74 | #define MT_RXD3_NORMAL_BEACON_MC BIT(20) |
| 75 | #define MT_RXD3_NORMAL_BEACON_UC BIT(21) |
| 76 | #define MT_RXD3_NORMAL_CO_ANT BIT(22) |
| 77 | #define MT_RXD3_NORMAL_FCS_ERR BIT(24) |
| 78 | #define MT_RXD3_NORMAL_VLAN2ETH BIT(31) |
| 79 | |
| 80 | /* RXD DW4 */ |
| 81 | #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0) |
| 82 | #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0) |
| 83 | #define MT_RXD4_MID_AMSDU_FRAME BIT(1) |
| 84 | #define MT_RXD4_LAST_AMSDU_FRAME BIT(0) |
| 85 | |
| 86 | #define MT_RXV_HDR_BAND_IDX BIT(24) |
| 87 | |
| 88 | /* RXD GROUP4 */ |
| 89 | #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0) |
| 90 | |
| 91 | #define MT_RXD8_SEQ_CTRL GENMASK(15, 0) |
| 92 | #define MT_RXD8_QOS_CTL GENMASK(31, 16) |
| 93 | |
| 94 | #define MT_RXD9_HT_CONTROL GENMASK(31, 0) |
| 95 | |
| 96 | /* P-RXV */ |
| 97 | #define MT_PRXV_TX_RATE GENMASK(6, 0) |
| 98 | #define MT_PRXV_TX_DCM BIT(4) |
| 99 | #define MT_PRXV_TX_ER_SU_106T BIT(5) |
| 100 | #define MT_PRXV_NSTS GENMASK(10, 7) |
| 101 | #define MT_PRXV_TXBF BIT(11) |
| 102 | #define MT_PRXV_HT_AD_CODE BIT(12) |
| 103 | #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28) |
| 104 | #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0) |
| 105 | #define MT_PRXV_RCPI3 GENMASK(31, 24) |
| 106 | #define MT_PRXV_RCPI2 GENMASK(23, 16) |
| 107 | #define MT_PRXV_RCPI1 GENMASK(15, 8) |
| 108 | #define MT_PRXV_RCPI0 GENMASK(7, 0) |
| 109 | #define MT_PRXV_HT_SHORT_GI GENMASK(4, 3) |
| 110 | #define MT_PRXV_HT_STBC GENMASK(10, 9) |
| 111 | #define MT_PRXV_TX_MODE GENMASK(14, 11) |
| 112 | #define MT_PRXV_FRAME_MODE GENMASK(2, 0) |
| 113 | #define MT_PRXV_DCM BIT(5) |
| 114 | #define MT_PRXV_NUM_RX BIT(8, 6) |
| 115 | |
| 116 | /* C-RXV */ |
| 117 | #define MT_CRXV_HT_STBC GENMASK(1, 0) |
| 118 | #define MT_CRXV_TX_MODE GENMASK(7, 4) |
| 119 | #define MT_CRXV_FRAME_MODE GENMASK(10, 8) |
| 120 | #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13) |
| 121 | #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17) |
| 122 | #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20) |
| 123 | #define MT_CRXV_HE_PE_DISAMBIG BIT(23) |
| 124 | #define MT_CRXV_HE_NUM_USER GENMASK(30, 24) |
| 125 | #define MT_CRXV_HE_UPLINK BIT(31) |
| 126 | #define MT_CRXV_HE_RU0 GENMASK(7, 0) |
| 127 | #define MT_CRXV_HE_RU1 GENMASK(15, 8) |
| 128 | #define MT_CRXV_HE_RU2 GENMASK(23, 16) |
| 129 | #define MT_CRXV_HE_RU3 GENMASK(31, 24) |
| 130 | |
| 131 | #define MT_CRXV_HE_MU_AID GENMASK(30, 20) |
| 132 | |
| 133 | #define MT_CRXV_HE_SR_MASK GENMASK(11, 8) |
| 134 | #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12) |
| 135 | #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17) |
| 136 | #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21) |
| 137 | |
| 138 | #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0) |
| 139 | #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6) |
| 140 | #define MT_CRXV_HE_BEAM_CHNG BIT(13) |
| 141 | #define MT_CRXV_HE_DOPPLER BIT(16) |
| 142 | |
| 143 | #define MT_CRXV_SNR GENMASK(18, 13) |
| 144 | #define MT_CRXV_FOE_LO GENMASK(31, 19) |
| 145 | #define MT_CRXV_FOE_HI GENMASK(6, 0) |
| 146 | #define MT_CRXV_FOE_SHIFT 13 |
| 147 | |
| 148 | enum tx_header_format { |
| 149 | MT_HDR_FORMAT_802_3, |
| 150 | MT_HDR_FORMAT_CMD, |
| 151 | MT_HDR_FORMAT_802_11, |
| 152 | MT_HDR_FORMAT_802_11_EXT, |
| 153 | }; |
| 154 | |
| 155 | enum tx_pkt_type { |
| 156 | MT_TX_TYPE_CT, |
| 157 | MT_TX_TYPE_SF, |
| 158 | MT_TX_TYPE_CMD, |
| 159 | MT_TX_TYPE_FW, |
| 160 | }; |
| 161 | |
| 162 | enum tx_port_idx { |
| 163 | MT_TX_PORT_IDX_LMAC, |
| 164 | MT_TX_PORT_IDX_MCU |
| 165 | }; |
| 166 | |
| 167 | enum tx_mcu_port_q_idx { |
| 168 | MT_TX_MCU_PORT_RX_Q0 = 0x20, |
| 169 | MT_TX_MCU_PORT_RX_Q1, |
| 170 | MT_TX_MCU_PORT_RX_Q2, |
| 171 | MT_TX_MCU_PORT_RX_Q3, |
| 172 | MT_TX_MCU_PORT_RX_FWDL = 0x3e |
| 173 | }; |
| 174 | |
| 175 | enum tx_mgnt_type { |
| 176 | MT_TX_NORMAL, |
| 177 | MT_TX_TIMING, |
| 178 | MT_TX_ADDBA, |
| 179 | }; |
| 180 | |
| 181 | #define MT_CT_INFO_APPLY_TXD BIT(0) |
| 182 | #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1) |
| 183 | #define MT_CT_INFO_MGMT_FRAME BIT(2) |
| 184 | #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3) |
| 185 | #define MT_CT_INFO_HSR2_TX BIT(4) |
| 186 | #define MT_CT_INFO_FROM_HOST BIT(7) |
| 187 | |
| 188 | #define MT_TXD_SIZE (8 * 4) |
| 189 | |
| 190 | #define MT_TXD0_Q_IDX GENMASK(31, 25) |
| 191 | #define MT_TXD0_PKT_FMT GENMASK(24, 23) |
| 192 | #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16) |
| 193 | #define MT_TXD0_TX_BYTES GENMASK(15, 0) |
| 194 | |
| 195 | #define MT_TXD1_FIXED_RATE BIT(31) |
| 196 | #define MT_TXD1_OWN_MAC GENMASK(30, 25) |
| 197 | #define MT_TXD1_TID GENMASK(24, 21) |
| 198 | #define MT_TXD1_BIP BIT(24) |
| 199 | #define MT_TXD1_ETH_802_3 BIT(20) |
| 200 | #define MT_TXD1_HDR_INFO GENMASK(20, 16) |
| 201 | #define MT_TXD1_HDR_FORMAT GENMASK(15, 14) |
| 202 | #define MT_TXD1_TGID GENMASK(13, 12) |
| 203 | #define MT_TXD1_WLAN_IDX GENMASK(11, 0) |
| 204 | |
| 205 | #define MT_TXD2_POWER_OFFSET GENMASK(31, 26) |
| 206 | #define MT_TXD2_MAX_TX_TIME GENMASK(25, 16) |
| 207 | #define MT_TXD2_FRAG GENMASK(15, 14) |
| 208 | #define MT_TXD2_HTC_VLD BIT(13) |
| 209 | #define MT_TXD2_DURATION BIT(12) |
| 210 | #define MT_TXD2_HDR_PAD GENMASK(11, 10) |
| 211 | #define MT_TXD2_RTS BIT(9) |
| 212 | #define MT_TXD2_OWN_MAC_MAP BIT(8) |
| 213 | #define MT_TXD2_BF_TYPE GENMASK(6, 7) |
| 214 | #define MT_TXD2_FRAME_TYPE GENMASK(5, 4) |
| 215 | #define MT_TXD2_SUB_TYPE GENMASK(3, 0) |
| 216 | |
| 217 | #define MT_TXD3_SN_VALID BIT(31) |
| 218 | #define MT_TXD3_PN_VALID BIT(30) |
| 219 | #define MT_TXD3_SW_POWER_MGMT BIT(29) |
| 220 | #define MT_TXD3_BA_DISABLE BIT(28) |
| 221 | #define MT_TXD3_SEQ GENMASK(27, 16) |
| 222 | #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11) |
| 223 | #define MT_TXD3_TX_COUNT GENMASK(10, 6) |
| 224 | #define MT_TXD3_HW_AMSDU BIT(5) |
| 225 | #define MT_TXD3_BCM BIT(4) |
| 226 | #define MT_TXD3_EEOSP BIT(3) |
| 227 | #define MT_TXD3_EMRD BIT(2) |
| 228 | #define MT_TXD3_PROTECT_FRAME BIT(1) |
| 229 | #define MT_TXD3_NO_ACK BIT(0) |
| 230 | |
| 231 | #define MT_TXD4_PN_LOW GENMASK(31, 0) |
| 232 | |
| 233 | #define MT_TXD5_PN_HIGH GENMASK(31, 16) |
| 234 | #define MT_TXD5_FL BIT(15) |
| 235 | #define MT_TXD5_BYPASS_TBB BIT(14) |
| 236 | #define MT_TXD5_BYPASS_RBB BIT(13) |
| 237 | #define MT_TXD5_BSS_COLOR_ZERO BIT(12) |
| 238 | #define MT_TXD5_TX_STATUS_HOST BIT(10) |
| 239 | #define MT_TXD5_TX_STATUS_MCU BIT(9) |
| 240 | #define MT_TXD5_TX_STATUS_FMT BIT(8) |
| 241 | #define MT_TXD5_PID GENMASK(7, 0) |
| 242 | |
| 243 | #define MT_TXD6_TX_SRC GENMASK(31, 30) |
| 244 | #define MT_TXD6_VTA BIT(28) |
| 245 | #define MT_TXD6_BW GENMASK(25, 22) |
| 246 | #define MT_TXD6_TX_RATE GENMASK(21, 16) |
| 247 | #define MT_TXD6_TIMESTAMP_OFS_EN BIT(15) |
| 248 | #define MT_TXD6_TIMESTAMP_OFS_IDX GENMASK(14, 10) |
| 249 | #define MT_TXD6_MSDU_CNT GENMASK(9, 4) |
| 250 | #define MT_TXD6_SPE_ID_IDX BIT(10) |
| 251 | #define MT_TXD6_ANT_ID GENMASK(7, 4) |
| 252 | #define MT_TXD6_DIS_MAT BIT(3) |
| 253 | #define MT_TXD6_DAS BIT(2) |
| 254 | #define MT_TXD6_AMSDU_CAP BIT(1) |
| 255 | |
| 256 | #define MT_TXD7_TXD_LEN GENMASK(31, 30) |
| 257 | #define MT_TXD7_IP_SUM BIT(29) |
| 258 | #define MT_TXD7_DROP_BY_SDO BIT(28) |
| 259 | #define MT_TXD7_MAC_TXD BIT(27) |
| 260 | #define MT_TXD7_CTXD BIT(26) |
| 261 | #define MT_TXD7_CTXD_CNT GENMASK(25, 22) |
| 262 | #define MT_TXD7_UDP_TCP_SUM BIT(15) |
| 263 | #define MT_TXD7_TX_TIME GENMASK(9, 0) |
| 264 | |
| 265 | #define MT_TX_RATE_STBC BIT(13) |
| 266 | #define MT_TX_RATE_NSS GENMASK(13, 10) |
| 267 | #define MT_TX_RATE_MODE GENMASK(9, 6) |
| 268 | #define MT_TX_RATE_SU_EXT_TONE BIT(5) |
| 269 | #define MT_TX_RATE_DCM BIT(4) |
| 270 | /* VHT/HE only use bits 0-3 */ |
| 271 | #define MT_TX_RATE_IDX GENMASK(5, 0) |
| 272 | |
| 273 | #define MT_TXP_MAX_BUF_NUM 6 |
| 274 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 275 | struct besra_txp { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 276 | __le16 flags; |
| 277 | __le16 token; |
| 278 | u8 bss_idx; |
| 279 | __le16 rept_wds_wcid; |
| 280 | u8 nbuf; |
| 281 | __le32 buf[MT_TXP_MAX_BUF_NUM]; |
| 282 | __le16 len[MT_TXP_MAX_BUF_NUM]; |
| 283 | } __packed __aligned(4); |
| 284 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 285 | struct besra_tx_free { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 286 | __le16 rx_byte_cnt; |
| 287 | __le16 ctrl; |
| 288 | __le32 txd; |
| 289 | __le32 info[]; |
| 290 | } __packed __aligned(4); |
| 291 | |
| 292 | #define MT_TX_FREE_VER GENMASK(18, 16) |
| 293 | #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0) |
| 294 | #define MT_TX_FREE_WLAN_ID GENMASK(23, 12) |
| 295 | #define MT_TX_FREE_LATENCY GENMASK(12, 0) |
| 296 | /* 0: success, others: dropped */ |
| 297 | #define MT_TX_FREE_MSDU_ID GENMASK(30, 16) |
| 298 | #define MT_TX_FREE_PAIR BIT(31) |
| 299 | #define MT_TX_FREE_MPDU_HEADER BIT(30) |
| 300 | #define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0) |
| 301 | |
| 302 | /* will support this field in further revision */ |
| 303 | #define MT_TX_FREE_RATE GENMASK(13, 0) |
| 304 | |
| 305 | #define MT_TXS0_BW GENMASK(31, 29) |
| 306 | #define MT_TXS0_TID GENMASK(28, 26) |
| 307 | #define MT_TXS0_AMPDU BIT(25) |
| 308 | #define MT_TXS0_TXS_FORMAT GENMASK(24, 23) |
| 309 | #define MT_TXS0_BA_ERROR BIT(22) |
| 310 | #define MT_TXS0_PS_FLAG BIT(21) |
| 311 | #define MT_TXS0_TXOP_TIMEOUT BIT(20) |
| 312 | #define MT_TXS0_BIP_ERROR BIT(19) |
| 313 | |
| 314 | #define MT_TXS0_QUEUE_TIMEOUT BIT(18) |
| 315 | #define MT_TXS0_RTS_TIMEOUT BIT(17) |
| 316 | #define MT_TXS0_ACK_TIMEOUT BIT(16) |
| 317 | #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16) |
| 318 | |
| 319 | #define MT_TXS0_TX_STATUS_HOST BIT(15) |
| 320 | #define MT_TXS0_TX_STATUS_MCU BIT(14) |
| 321 | #define MT_TXS0_TX_RATE GENMASK(13, 0) |
| 322 | |
| 323 | #define MT_TXS1_SEQNO GENMASK(31, 20) |
| 324 | #define MT_TXS1_RESP_RATE GENMASK(19, 16) |
| 325 | #define MT_TXS1_RXV_SEQNO GENMASK(15, 8) |
| 326 | #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0) |
| 327 | |
| 328 | #define MT_TXS2_BF_STATUS GENMASK(31, 30) |
| 329 | #define MT_TXS2_BAND GENMASK(29, 28) |
| 330 | #define MT_TXS2_WCID GENMASK(27, 16) |
| 331 | #define MT_TXS2_TX_DELAY GENMASK(15, 0) |
| 332 | |
| 333 | #define MT_TXS3_PID GENMASK(31, 24) |
| 334 | #define MT_TXS3_FIXED_RATE BIT(6) |
| 335 | #define MT_TXS3_SRC GENMASK(5, 4) |
| 336 | #define MT_TXS3_SHARED_ANTENNA BIT(3) |
| 337 | #define MT_TXS3_LAST_TX_RATE GENMASK(2, 0) |
| 338 | |
| 339 | #define MT_TXS4_TIMESTAMP GENMASK(31, 0) |
| 340 | |
| 341 | #define MT_TXS5_F0_FINAL_MPDU BIT(31) |
| 342 | #define MT_TXS5_F0_QOS BIT(30) |
| 343 | #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25) |
| 344 | #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0) |
| 345 | #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24) |
| 346 | #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0) |
| 347 | |
| 348 | #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24) |
| 349 | #define MT_TXS6_F0_NOISE_2 GENMASK(23, 16) |
| 350 | #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8) |
| 351 | #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0) |
| 352 | #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24) |
| 353 | #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0) |
| 354 | |
| 355 | #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24) |
| 356 | #define MT_TXS7_F0_RCPI_2 GENMASK(23, 16) |
| 357 | #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8) |
| 358 | #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0) |
| 359 | #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24) |
| 360 | #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0) |
| 361 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 362 | struct besra_dfs_pulse { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 363 | u32 max_width; /* us */ |
| 364 | int max_pwr; /* dbm */ |
| 365 | int min_pwr; /* dbm */ |
| 366 | u32 min_stgr_pri; /* us */ |
| 367 | u32 max_stgr_pri; /* us */ |
| 368 | u32 min_cr_pri; /* us */ |
| 369 | u32 max_cr_pri; /* us */ |
| 370 | }; |
| 371 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 372 | struct besra_dfs_pattern { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 373 | u8 enb; |
| 374 | u8 stgr; |
| 375 | u8 min_crpn; |
| 376 | u8 max_crpn; |
| 377 | u8 min_crpr; |
| 378 | u8 min_pw; |
| 379 | u32 min_pri; |
| 380 | u32 max_pri; |
| 381 | u8 max_pw; |
| 382 | u8 min_crbn; |
| 383 | u8 max_crbn; |
| 384 | u8 min_stgpn; |
| 385 | u8 max_stgpn; |
| 386 | u8 min_stgpr; |
| 387 | u8 rsv[2]; |
| 388 | u32 min_stgpr_diff; |
| 389 | } __packed; |
| 390 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 391 | struct besra_dfs_radar_spec { |
| 392 | struct besra_dfs_pulse pulse_th; |
| 393 | struct besra_dfs_pattern radar_pattern[16]; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 394 | }; |
| 395 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 396 | static inline struct besra_txp * |
| 397 | besra_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 398 | { |
| 399 | u8 *txwi; |
| 400 | |
| 401 | if (!t) |
| 402 | return NULL; |
| 403 | |
| 404 | txwi = mt76_get_txwi_ptr(dev, t); |
| 405 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 406 | return (struct besra_txp *)(txwi + MT_TXD_SIZE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | #endif |