developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 1 | From b4091a26e5e6ac5b80a587afdbfd8a54251d050f Mon Sep 17 00:00:00 2001 |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 2 | From: Sujuan Chen <sujuan.chen@mediatek.com> |
| 3 | Date: Fri, 2 Dec 2022 17:17:06 +0800 |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 4 | Subject: [PATCH 3007/3010] mt76: mt7915: wed: add mt7916 2 pcie support when |
developer | eb6a018 | 2022-12-12 18:53:32 +0800 | [diff] [blame] | 5 | wed on |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 6 | |
| 7 | It should use bit 23 in interrupt mask for wfdma band1 data |
| 8 | for 2 pcie mt7916, and use bit 19 for band1 data for 1 pcie. |
| 9 | |
| 10 | Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> |
| 11 | --- |
| 12 | mt7915/dma.c | 8 ++++++-- |
developer | afd7587 | 2022-12-14 21:15:46 +0800 | [diff] [blame] | 13 | mt7915/mcu.c | 3 ++- |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 14 | mt7915/mmio.c | 10 +++++----- |
developer | afd7587 | 2022-12-14 21:15:46 +0800 | [diff] [blame] | 15 | 3 files changed, 13 insertions(+), 8 deletions(-) |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 16 | |
| 17 | diff --git a/mt7915/dma.c b/mt7915/dma.c |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 18 | index abe17dac..52fabde0 100644 |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 19 | --- a/mt7915/dma.c |
| 20 | +++ b/mt7915/dma.c |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 21 | @@ -87,8 +87,12 @@ static void mt7915_dma_config(struct mt7915_dev *dev) |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 22 | MT7916_RXQ_BAND0); |
| 23 | RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916, |
| 24 | MT7916_RXQ_MCU_WA); |
| 25 | - RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916, |
| 26 | - MT7916_RXQ_BAND1); |
| 27 | + if (dev->hif2) |
| 28 | + RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, |
| 29 | + MT7916_RXQ_BAND1); |
| 30 | + else |
| 31 | + RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916, |
| 32 | + MT7916_RXQ_BAND1); |
| 33 | RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916, |
| 34 | MT7916_RXQ_MCU_WA_MAIN); |
| 35 | TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0, |
| 36 | diff --git a/mt7915/mcu.c b/mt7915/mcu.c |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 37 | index e3b7d824..b5a0967b 100644 |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 38 | --- a/mt7915/mcu.c |
| 39 | +++ b/mt7915/mcu.c |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 40 | @@ -2416,7 +2416,8 @@ int mt7915_mcu_init_firmware(struct mt7915_dev *dev) |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 41 | return ret; |
| 42 | |
developer | afd7587 | 2022-12-14 21:15:46 +0800 | [diff] [blame] | 43 | if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 44 | - if (is_mt7915(&dev->mt76)) |
developer | afd7587 | 2022-12-14 21:15:46 +0800 | [diff] [blame] | 45 | + if (is_mt7915(&dev->mt76) || |
| 46 | + !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) |
| 47 | ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), |
| 48 | 0, 0, 0); |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 49 | else |
| 50 | diff --git a/mt7915/mmio.c b/mt7915/mmio.c |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 51 | index 6ebb969f..890af388 100644 |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 52 | --- a/mt7915/mmio.c |
| 53 | +++ b/mt7915/mmio.c |
developer | c04f540 | 2023-02-03 09:22:26 +0800 | [diff] [blame^] | 54 | @@ -996,13 +996,13 @@ irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 55 | struct mt7915_dev *dev = dev_instance; |
| 56 | struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 57 | |
| 58 | - if (mtk_wed_device_active(wed)) { |
| 59 | + if (mtk_wed_device_active(wed)) |
| 60 | mtk_wed_device_irq_set_mask(wed, 0); |
| 61 | - } else { |
| 62 | + else |
| 63 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 64 | - if (dev->hif2) |
| 65 | - mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 66 | - } |
| 67 | + |
| 68 | + if (dev->hif2) |
| 69 | + mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 70 | |
| 71 | if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) |
| 72 | return IRQ_NONE; |
| 73 | -- |
developer | d75d363 | 2023-01-05 14:31:01 +0800 | [diff] [blame] | 74 | 2.18.0 |
developer | 1f23e2f | 2022-12-05 10:14:25 +0800 | [diff] [blame] | 75 | |