developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MT7996_H |
| 7 | #define __MT7996_H |
| 8 | |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/ktime.h> |
| 11 | #include "../mt76_connac.h" |
| 12 | #include "regs.h" |
| 13 | |
| 14 | #define MT7996_MAX_INTERFACES 19 |
| 15 | #define MT7996_MAX_WMM_SETS 4 |
| 16 | #define MT7996_WTBL_SIZE 544 |
| 17 | #define MT7996_WTBL_RESERVED (MT7996_WTBL_SIZE - 1) |
| 18 | #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ |
| 19 | MT7996_MAX_INTERFACES) |
| 20 | |
| 21 | #define MT7996_WATCHDOG_TIME (HZ / 10) |
| 22 | #define MT7996_RESET_TIMEOUT (30 * HZ) |
| 23 | |
| 24 | #define MT7996_TX_RING_SIZE 2048 |
| 25 | #define MT7996_TX_MCU_RING_SIZE 256 |
| 26 | #define MT7996_TX_FWDL_RING_SIZE 128 |
| 27 | |
| 28 | #define MT7996_RX_RING_SIZE 1536 |
| 29 | #define MT7996_RX_MCU_RING_SIZE 512 |
| 30 | |
| 31 | #define MT7996_FIRMWARE_WA "mediatek/mt7996_wa.bin" |
| 32 | #define MT7996_FIRMWARE_WM "mediatek/mt7996_wm.bin" |
| 33 | #define MT7996_ROM_PATCH "mediatek/mt7996_rom_patch.bin" |
| 34 | |
| 35 | #define MT7996_EEPROM_DEFAULT "mediatek/mt7996_eeprom.bin" |
| 36 | #define MT7996_EEPROM_SIZE 7680 |
| 37 | #define MT7996_EEPROM_BLOCK_SIZE 16 |
| 38 | #define MT7996_TOKEN_SIZE 8192 |
| 39 | |
| 40 | #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ |
| 41 | #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ |
| 42 | |
| 43 | #define MT7996_MAX_TWT_AGRT 16 |
| 44 | #define MT7996_MAX_STA_TWT_AGRT 8 |
| 45 | #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) |
| 46 | |
| 47 | struct mt7996_vif; |
| 48 | struct mt7996_sta; |
| 49 | struct mt7996_dfs_pulse; |
| 50 | struct mt7996_dfs_pattern; |
| 51 | |
| 52 | enum mt7996_txq_id { |
| 53 | MT7996_TXQ_FWDL = 16, |
| 54 | MT7996_TXQ_MCU_WM, |
| 55 | MT7996_TXQ_BAND0, |
| 56 | MT7996_TXQ_BAND1, |
| 57 | MT7996_TXQ_MCU_WA, |
| 58 | MT7996_TXQ_BAND2, |
| 59 | }; |
| 60 | |
| 61 | enum mt7996_rxq_id { |
| 62 | MT7996_RXQ_MCU_WM = 0, |
| 63 | MT7996_RXQ_MCU_WA, |
| 64 | MT7996_RXQ_MCU_WA_MAIN = 2, |
| 65 | MT7996_RXQ_MCU_WA_EXT = 2,/* unused */ |
| 66 | MT7996_RXQ_MCU_WA_TRI = 3, |
| 67 | MT7996_RXQ_BAND0 = 4, |
| 68 | MT7996_RXQ_BAND1 = 4,/* unused */ |
| 69 | MT7996_RXQ_BAND2 = 5, |
| 70 | MT7996_RXQ_TXFREE0 = 9, |
| 71 | MT7996_RXQ_TXFREE1 = 9, |
| 72 | MT7996_RXQ_TXFREE2 = 7, |
| 73 | }; |
| 74 | |
| 75 | struct mt7996_twt_flow { |
| 76 | struct list_head list; |
| 77 | u64 start_tsf; |
| 78 | u64 tsf; |
| 79 | u32 duration; |
| 80 | u16 wcid; |
| 81 | __le16 mantissa; |
| 82 | u8 exp; |
| 83 | u8 table_id; |
| 84 | u8 id; |
| 85 | u8 protection:1; |
| 86 | u8 flowtype:1; |
| 87 | u8 trigger:1; |
| 88 | u8 sched:1; |
| 89 | }; |
| 90 | |
| 91 | struct mt7996_sta { |
| 92 | struct mt76_wcid wcid; /* must be first */ |
| 93 | |
| 94 | struct mt7996_vif *vif; |
| 95 | |
| 96 | struct list_head poll_list; |
| 97 | struct list_head rc_list; |
| 98 | u32 airtime_ac[8]; |
| 99 | |
| 100 | unsigned long changed; |
| 101 | unsigned long jiffies; |
| 102 | unsigned long ampdu_state; |
| 103 | |
| 104 | struct mt76_sta_stats stats; |
| 105 | |
| 106 | struct mt76_connac_sta_key_conf bip; |
| 107 | |
| 108 | struct { |
| 109 | u8 flowid_mask; |
| 110 | struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; |
| 111 | } twt; |
| 112 | }; |
| 113 | |
| 114 | struct mt7996_vif_cap { |
| 115 | bool ht_ldpc:1; |
| 116 | bool vht_ldpc:1; |
| 117 | bool he_ldpc:1; |
| 118 | bool vht_su_ebfer:1; |
| 119 | bool vht_su_ebfee:1; |
| 120 | bool vht_mu_ebfer:1; |
| 121 | bool vht_mu_ebfee:1; |
| 122 | bool he_su_ebfer:1; |
| 123 | bool he_su_ebfee:1; |
| 124 | bool he_mu_ebfer:1; |
| 125 | }; |
| 126 | |
| 127 | struct mt7996_vif { |
| 128 | struct mt76_vif mt76; /* must be first */ |
| 129 | |
| 130 | struct mt7996_vif_cap cap; |
| 131 | struct mt7996_sta sta; |
| 132 | struct mt7996_phy *phy; |
| 133 | |
| 134 | struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; |
| 135 | struct cfg80211_bitrate_mask bitrate_mask; |
| 136 | }; |
| 137 | |
| 138 | /* per-phy stats. */ |
| 139 | struct mib_stats { |
| 140 | u32 ack_fail_cnt; |
| 141 | u32 fcs_err_cnt; |
| 142 | u32 rts_cnt; |
| 143 | u32 rts_retries_cnt; |
| 144 | u32 ba_miss_cnt; |
| 145 | u32 tx_mu_bf_cnt; |
| 146 | u32 tx_mu_mpdu_cnt; |
| 147 | u32 tx_mu_acked_mpdu_cnt; |
| 148 | u32 tx_su_acked_mpdu_cnt; |
| 149 | u32 tx_bf_ibf_ppdu_cnt; |
| 150 | u32 tx_bf_ebf_ppdu_cnt; |
| 151 | |
| 152 | u32 tx_bf_rx_fb_all_cnt; |
| 153 | u32 tx_bf_rx_fb_eht_cnt; |
| 154 | u32 tx_bf_rx_fb_he_cnt; |
| 155 | u32 tx_bf_rx_fb_vht_cnt; |
| 156 | u32 tx_bf_rx_fb_ht_cnt; |
| 157 | |
| 158 | u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ |
| 159 | u32 tx_bf_rx_fb_nc_cnt; |
| 160 | u32 tx_bf_rx_fb_nr_cnt; |
| 161 | u32 tx_bf_fb_cpl_cnt; |
| 162 | u32 tx_bf_fb_trig_cnt; |
| 163 | |
| 164 | u32 tx_ampdu_cnt; |
| 165 | u32 tx_stop_q_empty_cnt; |
| 166 | u32 tx_mpdu_attempts_cnt; |
| 167 | u32 tx_mpdu_success_cnt; |
| 168 | /* BF counter is PPDU-based, so remove MPDU-based BF counter */ |
| 169 | |
| 170 | u32 tx_rwp_fail_cnt; |
| 171 | u32 tx_rwp_need_cnt; |
| 172 | |
| 173 | /* rx stats */ |
| 174 | u32 rx_fifo_full_cnt; |
| 175 | u32 channel_idle_cnt; |
| 176 | u32 rx_vector_mismatch_cnt; |
| 177 | u32 rx_delimiter_fail_cnt; |
| 178 | u32 rx_len_mismatch_cnt; |
| 179 | u32 rx_mpdu_cnt; |
| 180 | u32 rx_ampdu_cnt; |
| 181 | u32 rx_ampdu_bytes_cnt; |
| 182 | u32 rx_ampdu_valid_subframe_cnt; |
| 183 | u32 rx_ampdu_valid_subframe_bytes_cnt; |
| 184 | u32 rx_pfdrop_cnt; |
| 185 | u32 rx_vec_queue_overflow_drop_cnt; |
| 186 | u32 rx_ba_cnt; |
| 187 | |
| 188 | u32 tx_amsdu[8]; |
| 189 | u32 tx_amsdu_cnt; |
| 190 | }; |
| 191 | |
| 192 | struct mt7996_hif { |
| 193 | struct list_head list; |
| 194 | |
| 195 | struct device *dev; |
| 196 | void __iomem *regs; |
| 197 | int irq; |
| 198 | }; |
| 199 | |
| 200 | struct mt7996_phy { |
| 201 | struct mt76_phy *mt76; |
| 202 | struct mt7996_dev *dev; |
| 203 | |
| 204 | struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; |
| 205 | |
| 206 | struct ieee80211_vif *monitor_vif; |
| 207 | |
| 208 | u32 rxfilter; |
| 209 | u64 omac_mask; |
| 210 | |
| 211 | u16 noise; |
| 212 | |
| 213 | s16 coverage_class; |
| 214 | u8 slottime; |
| 215 | |
| 216 | u8 rdd_state; |
| 217 | |
| 218 | u32 rx_ampdu_ts; |
| 219 | u32 ampdu_ref; |
| 220 | |
| 221 | struct mib_stats mib; |
| 222 | struct mt76_channel_state state_ts; |
| 223 | }; |
| 224 | |
| 225 | struct mt7996_dev { |
| 226 | union { /* must be first */ |
| 227 | struct mt76_dev mt76; |
| 228 | struct mt76_phy mphy; |
| 229 | }; |
| 230 | |
| 231 | struct mt7996_hif *hif2; |
| 232 | struct mt7996_reg_desc reg; |
| 233 | u8 q_id[MT7996_MAX_QUEUE]; |
| 234 | u32 q_int_mask[MT7996_MAX_QUEUE]; |
| 235 | u32 q_wfdma_mask; |
| 236 | |
| 237 | const struct mt76_bus_ops *bus_ops; |
| 238 | struct tasklet_struct irq_tasklet; |
| 239 | struct mt7996_phy phy; |
| 240 | |
| 241 | /* monitor rx chain configured channel */ |
| 242 | struct cfg80211_chan_def rdd2_chandef; |
| 243 | struct mt7996_phy *rdd2_phy; |
| 244 | |
| 245 | u16 chainmask; |
| 246 | u8 chainshift[__MT_MAX_BAND]; |
| 247 | u32 hif_idx; |
| 248 | |
| 249 | struct work_struct init_work; |
| 250 | struct work_struct rc_work; |
| 251 | struct work_struct reset_work; |
| 252 | wait_queue_head_t reset_wait; |
| 253 | u32 reset_state; |
| 254 | |
| 255 | struct list_head sta_rc_list; |
| 256 | struct list_head sta_poll_list; |
| 257 | struct list_head twt_list; |
| 258 | spinlock_t sta_poll_lock; |
| 259 | |
| 260 | u32 hw_pattern; |
| 261 | |
| 262 | bool dbdc_support:1; |
| 263 | bool tbtc_support:1; |
| 264 | bool flash_mode:1; |
| 265 | |
| 266 | bool ibf; |
| 267 | u8 fw_debug_wm; |
| 268 | u8 fw_debug_wa; |
| 269 | u8 fw_debug_bin; |
| 270 | u16 fw_debug_seq; |
| 271 | |
| 272 | struct dentry *debugfs_dir; |
| 273 | struct rchan *relay_fwlog; |
| 274 | |
| 275 | struct { |
| 276 | u8 table_mask; |
| 277 | u8 n_agrt; |
| 278 | } twt; |
| 279 | |
| 280 | u32 reg_l1_backup; |
| 281 | u32 reg_l2_backup; |
| 282 | }; |
| 283 | |
| 284 | enum { |
| 285 | WFDMA0 = 0x0, |
| 286 | WFDMA1, |
| 287 | WFDMA_EXT, |
| 288 | __MT_WFDMA_MAX, |
| 289 | }; |
| 290 | |
| 291 | enum { |
| 292 | MT_CTX0, |
| 293 | MT_HIF0 = 0x0, |
| 294 | |
| 295 | MT_LMAC_AC00 = 0x0, |
| 296 | MT_LMAC_AC01, |
| 297 | MT_LMAC_AC02, |
| 298 | MT_LMAC_AC03, |
| 299 | MT_LMAC_ALTX0 = 0x10, |
| 300 | MT_LMAC_BMC0, |
| 301 | MT_LMAC_BCN0, |
| 302 | MT_LMAC_PSMP0, |
| 303 | }; |
| 304 | |
| 305 | enum { |
| 306 | MT_RX_SEL0, |
| 307 | MT_RX_SEL1, |
| 308 | MT_RX_SEL2, /* monitor chain */ |
| 309 | }; |
| 310 | |
| 311 | enum mt7996_rdd_cmd { |
| 312 | RDD_STOP, |
| 313 | RDD_START, |
| 314 | RDD_DET_MODE, |
| 315 | RDD_RADAR_EMULATE, |
| 316 | RDD_START_TXQ = 20, |
| 317 | RDD_CAC_START = 50, |
| 318 | RDD_CAC_END, |
| 319 | RDD_NORMAL_START, |
| 320 | RDD_DISABLE_DFS_CAL, |
| 321 | RDD_PULSE_DBG, |
| 322 | RDD_READ_PULSE, |
| 323 | RDD_RESUME_BF, |
| 324 | RDD_IRQ_OFF, |
| 325 | }; |
| 326 | |
| 327 | static inline struct mt7996_phy * |
| 328 | mt7996_hw_phy(struct ieee80211_hw *hw) |
| 329 | { |
| 330 | struct mt76_phy *phy = hw->priv; |
| 331 | |
| 332 | return phy->priv; |
| 333 | } |
| 334 | |
| 335 | static inline struct mt7996_dev * |
| 336 | mt7996_hw_dev(struct ieee80211_hw *hw) |
| 337 | { |
| 338 | struct mt76_phy *phy = hw->priv; |
| 339 | |
| 340 | return container_of(phy->dev, struct mt7996_dev, mt76); |
| 341 | } |
| 342 | |
| 343 | static inline struct mt7996_phy * |
| 344 | __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) |
| 345 | { |
| 346 | struct mt76_phy *phy = dev->mt76.phys[band]; |
| 347 | |
| 348 | if (!phy) |
| 349 | return NULL; |
| 350 | |
| 351 | return phy->priv; |
| 352 | } |
| 353 | |
| 354 | static inline struct mt7996_phy * |
| 355 | mt7996_phy2(struct mt7996_dev *dev) |
| 356 | { |
| 357 | return __mt7996_phy(dev, MT_BAND1); |
| 358 | } |
| 359 | |
| 360 | static inline struct mt7996_phy * |
| 361 | mt7996_phy3(struct mt7996_dev *dev) |
| 362 | { |
| 363 | return __mt7996_phy(dev, MT_BAND2); |
| 364 | } |
| 365 | |
| 366 | extern const struct ieee80211_ops mt7996_ops; |
| 367 | extern struct pci_driver mt7996_pci_driver; |
| 368 | extern struct pci_driver mt7996_hif_driver; |
| 369 | |
| 370 | struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, |
| 371 | void __iomem *mem_base, u32 device_id); |
| 372 | void mt7996_wfsys_reset(struct mt7996_dev *dev); |
| 373 | irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); |
| 374 | u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); |
| 375 | int mt7996_register_device(struct mt7996_dev *dev); |
| 376 | void mt7996_unregister_device(struct mt7996_dev *dev); |
| 377 | int mt7996_eeprom_init(struct mt7996_dev *dev); |
| 378 | int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); |
| 379 | int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, |
| 380 | struct ieee80211_channel *chan); |
| 381 | s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); |
| 382 | int mt7996_dma_init(struct mt7996_dev *dev); |
| 383 | void mt7996_dma_prefetch(struct mt7996_dev *dev); |
| 384 | void mt7996_dma_cleanup(struct mt7996_dev *dev); |
| 385 | int mt7996_mcu_init(struct mt7996_dev *dev); |
| 386 | int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, |
| 387 | struct mt7996_vif *mvif, |
| 388 | struct mt7996_twt_flow *flow, |
| 389 | int cmd); |
| 390 | int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, |
| 391 | struct ieee80211_vif *vif, bool enable); |
| 392 | int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, |
| 393 | struct ieee80211_vif *vif, int enable); |
| 394 | int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
| 395 | struct ieee80211_sta *sta, bool enable); |
| 396 | int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, |
| 397 | struct ieee80211_ampdu_params *params, |
| 398 | bool add); |
| 399 | int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, |
| 400 | struct ieee80211_ampdu_params *params, |
| 401 | bool add); |
| 402 | int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
| 403 | struct cfg80211_he_bss_color *he_bss_color); |
| 404 | int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 405 | int enable); |
| 406 | int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, |
| 407 | struct ieee80211_vif *vif, u32 changed); |
| 408 | int mt7996_mcu_add_obss_spr(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
| 409 | bool enable); |
| 410 | int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, |
| 411 | struct ieee80211_sta *sta, bool changed); |
| 412 | int mt7996_set_channel(struct mt7996_phy *phy); |
| 413 | int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); |
| 414 | int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif); |
| 415 | int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, |
| 416 | void *data, u16 version); |
| 417 | int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); |
| 418 | int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset); |
| 419 | int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); |
| 420 | int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); |
| 421 | int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); |
| 422 | int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); |
| 423 | int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, |
| 424 | const struct mt7996_dfs_pulse *pulse); |
| 425 | int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, |
| 426 | const struct mt7996_dfs_pattern *pattern); |
| 427 | int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); |
| 428 | void mt7996_mcu_set_pm(void *priv, u8 *mac, struct ieee80211_vif *vif); |
| 429 | int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); |
| 430 | int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); |
| 431 | int mt7996_mcu_get_rx_rate(struct mt7996_phy *phy, struct ieee80211_vif *vif, |
| 432 | struct ieee80211_sta *sta, struct rate_info *rate); |
| 433 | int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, |
| 434 | u8 rx_sel, u8 val); |
| 435 | int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, |
| 436 | struct cfg80211_chan_def *chandef); |
| 437 | int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); |
| 438 | int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); |
| 439 | int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u8 val); |
| 440 | int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); |
| 441 | int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); |
| 442 | int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); |
| 443 | void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); |
| 444 | void mt7996_mcu_exit(struct mt7996_dev *dev); |
| 445 | |
| 446 | void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, |
| 447 | u32 clear, u32 set); |
| 448 | |
| 449 | static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) |
| 450 | { |
| 451 | if (dev->hif2) |
| 452 | mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); |
| 453 | else |
| 454 | mt76_set_irq_mask(&dev->mt76, 0, 0, mask); |
| 455 | |
| 456 | tasklet_schedule(&dev->irq_tasklet); |
| 457 | } |
| 458 | |
| 459 | static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) |
| 460 | { |
| 461 | if (dev->hif2) |
| 462 | mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); |
| 463 | else |
| 464 | mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); |
| 465 | } |
| 466 | |
| 467 | u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); |
| 468 | bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); |
| 469 | void mt7996_mac_reset_counters(struct mt7996_phy *phy); |
| 470 | void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); |
| 471 | void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); |
| 472 | void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, |
| 473 | struct sk_buff *skb, struct mt76_wcid *wcid, int pid, |
| 474 | struct ieee80211_key_conf *key, u32 changed); |
| 475 | void mt7996_mac_set_timing(struct mt7996_phy *phy); |
| 476 | int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, |
| 477 | struct ieee80211_sta *sta); |
| 478 | void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, |
| 479 | struct ieee80211_sta *sta); |
| 480 | void mt7996_mac_work(struct work_struct *work); |
| 481 | void mt7996_mac_reset_work(struct work_struct *work); |
| 482 | void mt7996_mac_sta_rc_work(struct work_struct *work); |
| 483 | void mt7996_mac_update_stats(struct mt7996_phy *phy); |
| 484 | void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, |
| 485 | struct mt7996_sta *msta, |
| 486 | u8 flowid); |
| 487 | void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, |
| 488 | struct ieee80211_sta *sta, |
| 489 | struct ieee80211_twt_setup *twt); |
| 490 | int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, |
| 491 | enum mt76_txq_id qid, struct mt76_wcid *wcid, |
| 492 | struct ieee80211_sta *sta, |
| 493 | struct mt76_tx_info *tx_info); |
| 494 | void mt7996_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e); |
| 495 | void mt7996_tx_token_put(struct mt7996_dev *dev); |
| 496 | void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, |
| 497 | struct sk_buff *skb); |
| 498 | bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); |
| 499 | void mt7996_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps); |
| 500 | void mt7996_stats_work(struct work_struct *work); |
| 501 | int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); |
| 502 | int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); |
| 503 | void mt7996_set_stream_he_caps(struct mt7996_phy *phy); |
| 504 | void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); |
| 505 | void mt7996_update_channel(struct mt76_phy *mphy); |
| 506 | int mt7996_init_debugfs(struct mt7996_phy *phy); |
| 507 | void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); |
| 508 | bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); |
| 509 | int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 510 | struct mt76_connac_sta_key_conf *sta_key_conf, |
| 511 | struct ieee80211_key_conf *key, int mcu_cmd, |
| 512 | struct mt76_wcid *wcid, enum set_key_cmd cmd); |
| 513 | int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, |
| 514 | struct ieee80211_vif *vif, struct ieee80211_sta *sta); |
| 515 | #ifdef CONFIG_MAC80211_DEBUGFS |
| 516 | void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 517 | struct ieee80211_sta *sta, struct dentry *dir); |
| 518 | #endif |
| 519 | |
| 520 | #endif |