developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #ifndef __MT7915_MCU_H |
| 5 | #define __MT7915_MCU_H |
| 6 | |
| 7 | #include "../mt76_connac_mcu.h" |
| 8 | |
| 9 | enum { |
| 10 | MCU_ATE_SET_TRX = 0x1, |
| 11 | MCU_ATE_SET_FREQ_OFFSET = 0xa, |
| 12 | MCU_ATE_SET_SLOT_TIME = 0x13, |
| 13 | MCU_ATE_CLEAN_TXQUEUE = 0x1c, |
| 14 | }; |
| 15 | |
| 16 | struct mt7915_mcu_thermal_ctrl { |
| 17 | u8 ctrl_id; |
| 18 | u8 band_idx; |
| 19 | union { |
| 20 | struct { |
| 21 | u8 protect_type; /* 1: duty admit, 2: radio off */ |
| 22 | u8 trigger_type; /* 0: low, 1: high */ |
| 23 | } __packed type; |
| 24 | struct { |
| 25 | u8 duty_level; /* level 0~3 */ |
| 26 | u8 duty_cycle; |
| 27 | } __packed duty; |
| 28 | }; |
| 29 | } __packed; |
| 30 | |
| 31 | struct mt7915_mcu_thermal_notify { |
| 32 | struct mt76_connac2_mcu_rxd rxd; |
| 33 | |
| 34 | struct mt7915_mcu_thermal_ctrl ctrl; |
| 35 | __le32 temperature; |
| 36 | u8 rsv[8]; |
| 37 | } __packed; |
| 38 | |
| 39 | struct mt7915_mcu_csa_notify { |
| 40 | struct mt76_connac2_mcu_rxd rxd; |
| 41 | |
| 42 | u8 omac_idx; |
| 43 | u8 csa_count; |
| 44 | u8 band_idx; |
| 45 | u8 rsv; |
| 46 | } __packed; |
| 47 | |
| 48 | struct mt7915_mcu_bcc_notify { |
| 49 | struct mt76_connac2_mcu_rxd rxd; |
| 50 | |
| 51 | u8 band_idx; |
| 52 | u8 omac_idx; |
| 53 | u8 cca_count; |
| 54 | u8 rsv; |
| 55 | } __packed; |
| 56 | |
| 57 | struct mt7915_mcu_rdd_report { |
| 58 | struct mt76_connac2_mcu_rxd rxd; |
| 59 | |
| 60 | u8 band_idx; |
| 61 | u8 long_detected; |
| 62 | u8 constant_prf_detected; |
| 63 | u8 staggered_prf_detected; |
| 64 | u8 radar_type_idx; |
| 65 | u8 periodic_pulse_num; |
| 66 | u8 long_pulse_num; |
| 67 | u8 hw_pulse_num; |
| 68 | |
| 69 | u8 out_lpn; |
| 70 | u8 out_spn; |
| 71 | u8 out_crpn; |
| 72 | u8 out_crpw; |
| 73 | u8 out_crbn; |
| 74 | u8 out_stgpn; |
| 75 | u8 out_stgpw; |
| 76 | |
| 77 | u8 rsv; |
| 78 | |
| 79 | __le32 out_pri_const; |
| 80 | __le32 out_pri_stg[3]; |
| 81 | |
| 82 | struct { |
| 83 | __le32 start; |
| 84 | __le16 pulse_width; |
| 85 | __le16 pulse_power; |
| 86 | u8 mdrdy_flag; |
| 87 | u8 rsv[3]; |
| 88 | } long_pulse[32]; |
| 89 | |
| 90 | struct { |
| 91 | __le32 start; |
| 92 | __le16 pulse_width; |
| 93 | __le16 pulse_power; |
| 94 | u8 mdrdy_flag; |
| 95 | u8 rsv[3]; |
| 96 | } periodic_pulse[32]; |
| 97 | |
| 98 | struct { |
| 99 | __le32 start; |
| 100 | __le16 pulse_width; |
| 101 | __le16 pulse_power; |
| 102 | u8 sc_pass; |
| 103 | u8 sw_reset; |
| 104 | u8 mdrdy_flag; |
| 105 | u8 tx_active; |
| 106 | } hw_pulse[32]; |
| 107 | } __packed; |
| 108 | |
| 109 | struct mt7915_mcu_background_chain_ctrl { |
| 110 | u8 chan; /* primary channel */ |
| 111 | u8 central_chan; /* central channel */ |
| 112 | u8 bw; |
| 113 | u8 tx_stream; |
| 114 | u8 rx_stream; |
| 115 | |
| 116 | u8 monitor_chan; /* monitor channel */ |
| 117 | u8 monitor_central_chan;/* monitor central channel */ |
| 118 | u8 monitor_bw; |
| 119 | u8 monitor_tx_stream; |
| 120 | u8 monitor_rx_stream; |
| 121 | |
| 122 | u8 scan_mode; /* 0: ScanStop |
| 123 | * 1: ScanStart |
| 124 | * 2: ScanRunning |
| 125 | */ |
| 126 | u8 band_idx; /* DBDC */ |
| 127 | u8 monitor_scan_type; |
| 128 | u8 band; /* 0: 2.4GHz, 1: 5GHz */ |
| 129 | u8 rsv[2]; |
| 130 | } __packed; |
| 131 | |
| 132 | struct mt7915_mcu_eeprom { |
| 133 | u8 buffer_mode; |
| 134 | u8 format; |
| 135 | __le16 len; |
| 136 | } __packed; |
| 137 | |
| 138 | struct mt7915_mcu_eeprom_info { |
| 139 | __le32 addr; |
| 140 | __le32 valid; |
| 141 | u8 data[16]; |
| 142 | } __packed; |
| 143 | |
| 144 | struct mt7915_mcu_phy_rx_info { |
| 145 | u8 category; |
| 146 | u8 rate; |
| 147 | u8 mode; |
| 148 | u8 nsts; |
| 149 | u8 gi; |
| 150 | u8 coding; |
| 151 | u8 stbc; |
| 152 | u8 bw; |
| 153 | }; |
| 154 | |
| 155 | struct mt7915_mcu_mib { |
| 156 | __le32 band; |
| 157 | __le32 offs; |
| 158 | __le64 data; |
| 159 | } __packed; |
| 160 | |
| 161 | enum mt7915_chan_mib_offs { |
| 162 | /* mt7915 */ |
| 163 | MIB_BUSY_TIME = 14, |
| 164 | MIB_TX_TIME = 81, |
| 165 | MIB_RX_TIME, |
| 166 | MIB_OBSS_AIRTIME = 86, |
| 167 | /* mt7916 */ |
| 168 | MIB_BUSY_TIME_V2 = 0, |
| 169 | MIB_TX_TIME_V2 = 6, |
| 170 | MIB_RX_TIME_V2 = 8, |
| 171 | MIB_OBSS_AIRTIME_V2 = 490 |
| 172 | }; |
| 173 | |
| 174 | struct edca { |
| 175 | u8 queue; |
| 176 | u8 set; |
| 177 | u8 aifs; |
| 178 | u8 cw_min; |
| 179 | __le16 cw_max; |
| 180 | __le16 txop; |
| 181 | }; |
| 182 | |
| 183 | struct mt7915_mcu_tx { |
| 184 | u8 total; |
| 185 | u8 action; |
| 186 | u8 valid; |
| 187 | u8 mode; |
| 188 | |
| 189 | struct edca edca[IEEE80211_NUM_ACS]; |
| 190 | } __packed; |
| 191 | |
| 192 | struct mt7915_mcu_muru_stats { |
| 193 | __le32 event_id; |
| 194 | struct { |
| 195 | __le32 cck_cnt; |
| 196 | __le32 ofdm_cnt; |
| 197 | __le32 htmix_cnt; |
| 198 | __le32 htgf_cnt; |
| 199 | __le32 vht_su_cnt; |
| 200 | __le32 vht_2mu_cnt; |
| 201 | __le32 vht_3mu_cnt; |
| 202 | __le32 vht_4mu_cnt; |
| 203 | __le32 he_su_cnt; |
| 204 | __le32 he_ext_su_cnt; |
| 205 | __le32 he_2ru_cnt; |
| 206 | __le32 he_2mu_cnt; |
| 207 | __le32 he_3ru_cnt; |
| 208 | __le32 he_3mu_cnt; |
| 209 | __le32 he_4ru_cnt; |
| 210 | __le32 he_4mu_cnt; |
| 211 | __le32 he_5to8ru_cnt; |
| 212 | __le32 he_9to16ru_cnt; |
| 213 | __le32 he_gtr16ru_cnt; |
| 214 | } dl; |
| 215 | |
| 216 | struct { |
| 217 | __le32 hetrig_su_cnt; |
| 218 | __le32 hetrig_2ru_cnt; |
| 219 | __le32 hetrig_3ru_cnt; |
| 220 | __le32 hetrig_4ru_cnt; |
| 221 | __le32 hetrig_5to8ru_cnt; |
| 222 | __le32 hetrig_9to16ru_cnt; |
| 223 | __le32 hetrig_gtr16ru_cnt; |
| 224 | __le32 hetrig_2mu_cnt; |
| 225 | __le32 hetrig_3mu_cnt; |
| 226 | __le32 hetrig_4mu_cnt; |
| 227 | } ul; |
| 228 | }; |
| 229 | |
| 230 | #define WMM_AIFS_SET BIT(0) |
| 231 | #define WMM_CW_MIN_SET BIT(1) |
| 232 | #define WMM_CW_MAX_SET BIT(2) |
| 233 | #define WMM_TXOP_SET BIT(3) |
| 234 | #define WMM_PARAM_SET GENMASK(3, 0) |
| 235 | |
| 236 | enum { |
| 237 | MCU_FW_LOG_WM, |
| 238 | MCU_FW_LOG_WA, |
| 239 | MCU_FW_LOG_TO_HOST, |
| 240 | }; |
| 241 | |
| 242 | enum { |
| 243 | MCU_TWT_AGRT_ADD, |
| 244 | MCU_TWT_AGRT_MODIFY, |
| 245 | MCU_TWT_AGRT_DELETE, |
| 246 | MCU_TWT_AGRT_TEARDOWN, |
| 247 | MCU_TWT_AGRT_GET_TSF, |
| 248 | }; |
| 249 | |
| 250 | enum { |
| 251 | MCU_WA_PARAM_CMD_QUERY, |
| 252 | MCU_WA_PARAM_CMD_SET, |
| 253 | MCU_WA_PARAM_CMD_CAPABILITY, |
| 254 | MCU_WA_PARAM_CMD_DEBUG, |
| 255 | }; |
| 256 | |
| 257 | enum { |
| 258 | MCU_WA_PARAM_PDMA_RX = 0x04, |
| 259 | MCU_WA_PARAM_CPU_UTIL = 0x0b, |
| 260 | MCU_WA_PARAM_RED = 0x0e, |
| 261 | }; |
| 262 | |
| 263 | enum mcu_mmps_mode { |
| 264 | MCU_MMPS_STATIC, |
| 265 | MCU_MMPS_DYNAMIC, |
| 266 | MCU_MMPS_RSV, |
| 267 | MCU_MMPS_DISABLE, |
| 268 | }; |
| 269 | |
| 270 | struct bss_info_bmc_rate { |
| 271 | __le16 tag; |
| 272 | __le16 len; |
| 273 | __le16 bc_trans; |
| 274 | __le16 mc_trans; |
| 275 | u8 short_preamble; |
| 276 | u8 rsv[7]; |
| 277 | } __packed; |
| 278 | |
| 279 | struct bss_info_ra { |
| 280 | __le16 tag; |
| 281 | __le16 len; |
| 282 | u8 op_mode; |
| 283 | u8 adhoc_en; |
| 284 | u8 short_preamble; |
| 285 | u8 tx_streams; |
| 286 | u8 rx_streams; |
| 287 | u8 algo; |
| 288 | u8 force_sgi; |
| 289 | u8 force_gf; |
| 290 | u8 ht_mode; |
| 291 | u8 has_20_sta; /* Check if any sta support GF. */ |
| 292 | u8 bss_width_trigger_events; |
| 293 | u8 vht_nss_cap; |
| 294 | u8 vht_bw_signal; /* not use */ |
| 295 | u8 vht_force_sgi; /* not use */ |
| 296 | u8 se_off; |
| 297 | u8 antenna_idx; |
| 298 | u8 train_up_rule; |
| 299 | u8 rsv[3]; |
| 300 | unsigned short train_up_high_thres; |
| 301 | short train_up_rule_rssi; |
| 302 | unsigned short low_traffic_thres; |
| 303 | __le16 max_phyrate; |
| 304 | __le32 phy_cap; |
| 305 | __le32 interval; |
| 306 | __le32 fast_interval; |
| 307 | } __packed; |
| 308 | |
| 309 | struct bss_info_hw_amsdu { |
| 310 | __le16 tag; |
| 311 | __le16 len; |
| 312 | __le32 cmp_bitmap_0; |
| 313 | __le32 cmp_bitmap_1; |
| 314 | __le16 trig_thres; |
| 315 | u8 enable; |
| 316 | u8 rsv; |
| 317 | } __packed; |
| 318 | |
| 319 | struct bss_info_color { |
| 320 | __le16 tag; |
| 321 | __le16 len; |
| 322 | u8 disable; |
| 323 | u8 color; |
| 324 | u8 rsv[2]; |
| 325 | } __packed; |
| 326 | |
| 327 | struct bss_info_he { |
| 328 | __le16 tag; |
| 329 | __le16 len; |
| 330 | u8 he_pe_duration; |
| 331 | u8 vht_op_info_present; |
| 332 | __le16 he_rts_thres; |
| 333 | __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; |
| 334 | u8 rsv[6]; |
| 335 | } __packed; |
| 336 | |
| 337 | struct bss_info_bcn { |
| 338 | __le16 tag; |
| 339 | __le16 len; |
| 340 | u8 ver; |
| 341 | u8 enable; |
| 342 | __le16 sub_ntlv; |
| 343 | } __packed __aligned(4); |
| 344 | |
| 345 | struct bss_info_bcn_cntdwn { |
| 346 | __le16 tag; |
| 347 | __le16 len; |
| 348 | u8 cnt; |
| 349 | u8 rsv[3]; |
| 350 | } __packed __aligned(4); |
| 351 | |
| 352 | struct bss_info_bcn_mbss { |
| 353 | #define MAX_BEACON_NUM 32 |
| 354 | __le16 tag; |
| 355 | __le16 len; |
| 356 | __le32 bitmap; |
| 357 | __le16 offset[MAX_BEACON_NUM]; |
| 358 | u8 rsv[8]; |
| 359 | } __packed __aligned(4); |
| 360 | |
| 361 | struct bss_info_bcn_cont { |
| 362 | __le16 tag; |
| 363 | __le16 len; |
| 364 | __le16 tim_ofs; |
| 365 | __le16 csa_ofs; |
| 366 | __le16 bcc_ofs; |
| 367 | __le16 pkt_len; |
| 368 | } __packed __aligned(4); |
| 369 | |
| 370 | struct bss_info_inband_discovery { |
| 371 | __le16 tag; |
| 372 | __le16 len; |
| 373 | u8 tx_type; |
| 374 | u8 tx_mode; |
| 375 | u8 tx_interval; |
| 376 | u8 enable; |
| 377 | __le16 rsv; |
| 378 | __le16 prob_rsp_len; |
| 379 | } __packed __aligned(4); |
| 380 | |
| 381 | enum { |
| 382 | BSS_INFO_BCN_CSA, |
| 383 | BSS_INFO_BCN_BCC, |
| 384 | BSS_INFO_BCN_MBSSID, |
| 385 | BSS_INFO_BCN_CONTENT, |
| 386 | BSS_INFO_BCN_DISCOV, |
| 387 | BSS_INFO_BCN_MAX |
| 388 | }; |
| 389 | |
| 390 | enum { |
| 391 | RATE_PARAM_FIXED = 3, |
| 392 | RATE_PARAM_MMPS_UPDATE = 5, |
| 393 | RATE_PARAM_FIXED_HE_LTF = 7, |
| 394 | RATE_PARAM_FIXED_MCS, |
| 395 | RATE_PARAM_FIXED_GI = 11, |
| 396 | RATE_PARAM_AUTO = 20, |
| 397 | RATE_PARAM_SPE_UPDATE = 22, |
| 398 | }; |
| 399 | |
| 400 | #define RATE_CFG_MCS GENMASK(3, 0) |
| 401 | #define RATE_CFG_NSS GENMASK(7, 4) |
| 402 | #define RATE_CFG_GI GENMASK(11, 8) |
| 403 | #define RATE_CFG_BW GENMASK(15, 12) |
| 404 | #define RATE_CFG_STBC GENMASK(19, 16) |
| 405 | #define RATE_CFG_LDPC GENMASK(23, 20) |
| 406 | #define RATE_CFG_PHY_TYPE GENMASK(27, 24) |
| 407 | #define RATE_CFG_HE_LTF GENMASK(31, 28) |
| 408 | |
| 409 | enum { |
| 410 | THERMAL_PROTECT_PARAMETER_CTRL, |
| 411 | THERMAL_PROTECT_BASIC_INFO, |
| 412 | THERMAL_PROTECT_ENABLE, |
| 413 | THERMAL_PROTECT_DISABLE, |
| 414 | THERMAL_PROTECT_DUTY_CONFIG, |
| 415 | THERMAL_PROTECT_MECH_INFO, |
| 416 | THERMAL_PROTECT_DUTY_INFO, |
| 417 | THERMAL_PROTECT_STATE_ACT, |
| 418 | }; |
| 419 | |
| 420 | enum { |
| 421 | MT_BF_SOUNDING_ON = 1, |
| 422 | MT_BF_TYPE_UPDATE = 20, |
| 423 | MT_BF_MODULE_UPDATE = 25 |
| 424 | }; |
| 425 | |
| 426 | enum { |
| 427 | MURU_SET_ARB_OP_MODE = 14, |
| 428 | MURU_SET_PLATFORM_TYPE = 25, |
| 429 | }; |
| 430 | |
| 431 | enum { |
| 432 | MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, |
| 433 | MURU_PLATFORM_TYPE_PERF_LEVEL_2, |
| 434 | }; |
| 435 | |
| 436 | /* tx cmd tx statistics */ |
| 437 | enum { |
| 438 | MURU_SET_TXC_TX_STATS_EN = 150, |
| 439 | MURU_GET_TXC_TX_STATS = 151, |
| 440 | }; |
| 441 | |
| 442 | enum { |
| 443 | SER_QUERY, |
| 444 | /* recovery */ |
| 445 | SER_SET_RECOVER_L1, |
| 446 | SER_SET_RECOVER_L2, |
| 447 | SER_SET_RECOVER_L3_RX_ABORT, |
| 448 | SER_SET_RECOVER_L3_TX_ABORT, |
| 449 | SER_SET_RECOVER_L3_TX_DISABLE, |
| 450 | SER_SET_RECOVER_L3_BF, |
| 451 | /* action */ |
| 452 | SER_ENABLE = 2, |
| 453 | SER_RECOVER |
| 454 | }; |
| 455 | |
| 456 | #define MT7915_MAX_BEACON_SIZE 512 |
| 457 | #define MT7915_MAX_INBAND_FRAME_SIZE 256 |
| 458 | #define MT7915_MAX_BSS_OFFLOAD_SIZE (MT7915_MAX_BEACON_SIZE + \ |
| 459 | MT7915_MAX_INBAND_FRAME_SIZE + \ |
| 460 | MT7915_BEACON_UPDATE_SIZE) |
| 461 | |
| 462 | #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ |
| 463 | sizeof(struct bss_info_omac) + \ |
| 464 | sizeof(struct bss_info_basic) +\ |
| 465 | sizeof(struct bss_info_rf_ch) +\ |
| 466 | sizeof(struct bss_info_ra) + \ |
| 467 | sizeof(struct bss_info_hw_amsdu) +\ |
| 468 | sizeof(struct bss_info_he) + \ |
| 469 | sizeof(struct bss_info_bmc_rate) +\ |
| 470 | sizeof(struct bss_info_ext_bss)) |
| 471 | |
| 472 | #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ |
| 473 | sizeof(struct bss_info_bcn_cntdwn) + \ |
| 474 | sizeof(struct bss_info_bcn_mbss) + \ |
| 475 | sizeof(struct bss_info_bcn_cont) + \ |
| 476 | sizeof(struct bss_info_inband_discovery)) |
| 477 | |
| 478 | #endif |