developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #ifndef __MT76_CONNAC_MCU_H |
| 5 | #define __MT76_CONNAC_MCU_H |
| 6 | |
| 7 | #include "mt76_connac.h" |
| 8 | |
| 9 | #define FW_FEATURE_SET_ENCRYPT BIT(0) |
| 10 | #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) |
| 11 | #define FW_FEATURE_ENCRY_MODE BIT(4) |
| 12 | #define FW_FEATURE_OVERRIDE_ADDR BIT(5) |
| 13 | #define FW_FEATURE_NON_DL BIT(6) |
| 14 | |
| 15 | #define DL_MODE_ENCRYPT BIT(0) |
| 16 | #define DL_MODE_KEY_IDX GENMASK(2, 1) |
| 17 | #define DL_MODE_RESET_SEC_IV BIT(3) |
| 18 | #define DL_MODE_WORKING_PDA_CR4 BIT(4) |
| 19 | #define DL_MODE_VALID_RAM_ENTRY BIT(5) |
| 20 | #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) |
| 21 | #define DL_MODE_NEED_RSP BIT(31) |
| 22 | |
| 23 | #define FW_START_OVERRIDE BIT(0) |
| 24 | #define FW_START_WORKING_PDA_CR4 BIT(2) |
| 25 | |
| 26 | #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) |
| 27 | #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) |
| 28 | #define PATCH_SEC_TYPE_INFO 0x2 |
| 29 | |
| 30 | #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) |
| 31 | #define PATCH_SEC_ENC_TYPE_PLAIN 0x00 |
| 32 | #define PATCH_SEC_ENC_TYPE_AES 0x01 |
| 33 | #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 |
| 34 | #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) |
| 35 | #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) |
| 36 | |
| 37 | enum { |
| 38 | FW_TYPE_DEFAULT = 0, |
| 39 | FW_TYPE_CLC = 2, |
| 40 | FW_TYPE_MAX_NUM = 255 |
| 41 | }; |
| 42 | |
| 43 | #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) |
| 44 | #define MCU_PKT_ID 0xa0 |
| 45 | |
| 46 | struct mt76_connac2_mcu_txd { |
| 47 | __le32 txd[8]; |
| 48 | |
| 49 | __le16 len; |
| 50 | __le16 pq_id; |
| 51 | |
| 52 | u8 cid; |
| 53 | u8 pkt_type; |
| 54 | u8 set_query; /* FW don't care */ |
| 55 | u8 seq; |
| 56 | |
| 57 | u8 uc_d2b0_rev; |
| 58 | u8 ext_cid; |
| 59 | u8 s2d_index; |
| 60 | u8 ext_cid_ack; |
| 61 | |
| 62 | u32 rsv[5]; |
| 63 | } __packed __aligned(4); |
| 64 | |
| 65 | /** |
| 66 | * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3 |
| 67 | * @txd: hardware descriptor |
| 68 | * @len: total length not including txd |
| 69 | * @cid: command identifier |
| 70 | * @pkt_type: must be 0xa0 (cmd packet by long format) |
| 71 | * @frag_n: fragment number |
| 72 | * @seq: sequence number |
| 73 | * @checksum: 0 mean there is no checksum |
| 74 | * @s2d_index: index for command source and destination |
| 75 | * Definition | value | note |
| 76 | * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM |
| 77 | * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM |
| 78 | * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA |
| 79 | * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM |
| 80 | * |
| 81 | * @option: command option |
| 82 | * BIT[0]: UNI_CMD_OPT_BIT_ACK |
| 83 | * set to 1 to request a fw reply |
| 84 | * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY |
| 85 | * is set, mcu firmware will send response event EID = 0x01 |
| 86 | * (UNI_EVENT_ID_CMD_RESULT) to the host. |
| 87 | * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD |
| 88 | * 0: original command |
| 89 | * 1: unified command |
| 90 | * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY |
| 91 | * 0: QUERY command |
| 92 | * 1: SET command |
| 93 | */ |
| 94 | struct mt76_connac2_mcu_uni_txd { |
| 95 | __le32 txd[8]; |
| 96 | |
| 97 | /* DW1 */ |
| 98 | __le16 len; |
| 99 | __le16 cid; |
| 100 | |
| 101 | /* DW2 */ |
| 102 | u8 rsv; |
| 103 | u8 pkt_type; |
| 104 | u8 frag_n; |
| 105 | u8 seq; |
| 106 | |
| 107 | /* DW3 */ |
| 108 | __le16 checksum; |
| 109 | u8 s2d_index; |
| 110 | u8 option; |
| 111 | |
| 112 | /* DW4 */ |
| 113 | u8 rsv1[4]; |
| 114 | } __packed __aligned(4); |
| 115 | |
| 116 | struct mt76_connac2_mcu_rxd { |
| 117 | __le32 rxd[6]; |
| 118 | |
| 119 | __le16 len; |
| 120 | __le16 pkt_type_id; |
| 121 | |
| 122 | u8 eid; |
| 123 | u8 seq; |
| 124 | u8 rsv[2]; |
| 125 | |
| 126 | u8 ext_eid; |
| 127 | u8 rsv1[2]; |
| 128 | u8 s2d_index; |
| 129 | }; |
| 130 | |
| 131 | struct mt76_connac2_patch_hdr { |
| 132 | char build_date[16]; |
| 133 | char platform[4]; |
| 134 | __be32 hw_sw_ver; |
| 135 | __be32 patch_ver; |
| 136 | __be16 checksum; |
| 137 | u16 rsv; |
| 138 | struct { |
| 139 | __be32 patch_ver; |
| 140 | __be32 subsys; |
| 141 | __be32 feature; |
| 142 | __be32 n_region; |
| 143 | __be32 crc; |
| 144 | u32 rsv[11]; |
| 145 | } desc; |
| 146 | } __packed; |
| 147 | |
| 148 | struct mt76_connac2_patch_sec { |
| 149 | __be32 type; |
| 150 | __be32 offs; |
| 151 | __be32 size; |
| 152 | union { |
| 153 | __be32 spec[13]; |
| 154 | struct { |
| 155 | __be32 addr; |
| 156 | __be32 len; |
| 157 | __be32 sec_key_idx; |
| 158 | __be32 align_len; |
| 159 | u32 rsv[9]; |
| 160 | } info; |
| 161 | }; |
| 162 | } __packed; |
| 163 | |
| 164 | struct mt76_connac2_fw_trailer { |
| 165 | u8 chip_id; |
| 166 | u8 eco_code; |
| 167 | u8 n_region; |
| 168 | u8 format_ver; |
| 169 | u8 format_flag; |
| 170 | u8 rsv[2]; |
| 171 | char fw_ver[10]; |
| 172 | char build_date[15]; |
| 173 | __le32 crc; |
| 174 | } __packed; |
| 175 | |
| 176 | struct mt76_connac2_fw_region { |
| 177 | __le32 decomp_crc; |
| 178 | __le32 decomp_len; |
| 179 | __le32 decomp_blk_sz; |
| 180 | u8 rsv[4]; |
| 181 | __le32 addr; |
| 182 | __le32 len; |
| 183 | u8 feature_set; |
| 184 | u8 type; |
| 185 | u8 rsv1[14]; |
| 186 | } __packed; |
| 187 | |
| 188 | struct tlv { |
| 189 | __le16 tag; |
| 190 | __le16 len; |
| 191 | } __packed; |
| 192 | |
| 193 | struct bss_info_omac { |
| 194 | __le16 tag; |
| 195 | __le16 len; |
| 196 | u8 hw_bss_idx; |
| 197 | u8 omac_idx; |
| 198 | u8 band_idx; |
| 199 | u8 rsv0; |
| 200 | __le32 conn_type; |
| 201 | u32 rsv1; |
| 202 | } __packed; |
| 203 | |
| 204 | struct bss_info_basic { |
| 205 | __le16 tag; |
| 206 | __le16 len; |
| 207 | __le32 network_type; |
| 208 | u8 active; |
| 209 | u8 rsv0; |
| 210 | __le16 bcn_interval; |
| 211 | u8 bssid[ETH_ALEN]; |
| 212 | u8 wmm_idx; |
| 213 | u8 dtim_period; |
| 214 | u8 bmc_wcid_lo; |
| 215 | u8 cipher; |
| 216 | u8 phy_mode; |
| 217 | u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ |
| 218 | u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ |
| 219 | u8 bmc_wcid_hi; /* high Byte and version */ |
| 220 | u8 rsv[2]; |
| 221 | } __packed; |
| 222 | |
| 223 | struct bss_info_rf_ch { |
| 224 | __le16 tag; |
| 225 | __le16 len; |
| 226 | u8 pri_ch; |
| 227 | u8 center_ch0; |
| 228 | u8 center_ch1; |
| 229 | u8 bw; |
| 230 | u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ |
| 231 | u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ |
| 232 | u8 rsv[2]; |
| 233 | } __packed; |
| 234 | |
| 235 | struct bss_info_ext_bss { |
| 236 | __le16 tag; |
| 237 | __le16 len; |
| 238 | __le32 mbss_tsf_offset; /* in unit of us */ |
| 239 | u8 rsv[8]; |
| 240 | } __packed; |
| 241 | |
| 242 | enum { |
| 243 | BSS_INFO_OMAC, |
| 244 | BSS_INFO_BASIC, |
| 245 | BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ |
| 246 | BSS_INFO_PM, /* sta only */ |
| 247 | BSS_INFO_UAPSD, /* sta only */ |
| 248 | BSS_INFO_ROAM_DETECT, /* obsoleted */ |
| 249 | BSS_INFO_LQ_RM, /* obsoleted */ |
| 250 | BSS_INFO_EXT_BSS, |
| 251 | BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ |
| 252 | BSS_INFO_SYNC_MODE, /* obsoleted */ |
| 253 | BSS_INFO_RA, |
| 254 | BSS_INFO_HW_AMSDU, |
| 255 | BSS_INFO_BSS_COLOR, |
| 256 | BSS_INFO_HE_BASIC, |
| 257 | BSS_INFO_PROTECT_INFO, |
| 258 | BSS_INFO_OFFLOAD, |
| 259 | BSS_INFO_11V_MBSSID, |
| 260 | BSS_INFO_MAX_NUM |
| 261 | }; |
| 262 | |
| 263 | /* sta_rec */ |
| 264 | |
| 265 | struct sta_ntlv_hdr { |
| 266 | u8 rsv[2]; |
| 267 | __le16 tlv_num; |
| 268 | } __packed; |
| 269 | |
| 270 | struct sta_req_hdr { |
| 271 | u8 bss_idx; |
| 272 | u8 wlan_idx_lo; |
| 273 | __le16 tlv_num; |
| 274 | u8 is_tlv_append; |
| 275 | u8 muar_idx; |
| 276 | u8 wlan_idx_hi; |
| 277 | u8 rsv; |
| 278 | } __packed; |
| 279 | |
| 280 | struct sta_rec_basic { |
| 281 | __le16 tag; |
| 282 | __le16 len; |
| 283 | __le32 conn_type; |
| 284 | u8 conn_state; |
| 285 | u8 qos; |
| 286 | __le16 aid; |
| 287 | u8 peer_addr[ETH_ALEN]; |
| 288 | #define EXTRA_INFO_VER BIT(0) |
| 289 | #define EXTRA_INFO_NEW BIT(1) |
| 290 | __le16 extra_info; |
| 291 | } __packed; |
| 292 | |
| 293 | struct sta_rec_ht { |
| 294 | __le16 tag; |
| 295 | __le16 len; |
| 296 | __le16 ht_cap; |
| 297 | u16 rsv; |
| 298 | } __packed; |
| 299 | |
| 300 | struct sta_rec_vht { |
| 301 | __le16 tag; |
| 302 | __le16 len; |
| 303 | __le32 vht_cap; |
| 304 | __le16 vht_rx_mcs_map; |
| 305 | __le16 vht_tx_mcs_map; |
| 306 | /* mt7915 - mt7921 */ |
| 307 | u8 rts_bw_sig; |
| 308 | u8 rsv[3]; |
| 309 | } __packed; |
| 310 | |
| 311 | struct sta_rec_uapsd { |
| 312 | __le16 tag; |
| 313 | __le16 len; |
| 314 | u8 dac_map; |
| 315 | u8 tac_map; |
| 316 | u8 max_sp; |
| 317 | u8 rsv0; |
| 318 | __le16 listen_interval; |
| 319 | u8 rsv1[2]; |
| 320 | } __packed; |
| 321 | |
| 322 | struct sta_rec_ba { |
| 323 | __le16 tag; |
| 324 | __le16 len; |
| 325 | u8 tid; |
| 326 | u8 ba_type; |
| 327 | u8 amsdu; |
| 328 | u8 ba_en; |
| 329 | __le16 ssn; |
| 330 | __le16 winsize; |
| 331 | } __packed; |
| 332 | |
| 333 | struct sta_rec_he { |
| 334 | __le16 tag; |
| 335 | __le16 len; |
| 336 | |
| 337 | __le32 he_cap; |
| 338 | |
| 339 | u8 t_frame_dur; |
| 340 | u8 max_ampdu_exp; |
| 341 | u8 bw_set; |
| 342 | u8 device_class; |
| 343 | u8 dcm_tx_mode; |
| 344 | u8 dcm_tx_max_nss; |
| 345 | u8 dcm_rx_mode; |
| 346 | u8 dcm_rx_max_nss; |
| 347 | u8 dcm_max_ru; |
| 348 | u8 punc_pream_rx; |
| 349 | u8 pkt_ext; |
| 350 | u8 rsv1; |
| 351 | |
| 352 | __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; |
| 353 | |
| 354 | u8 rsv2[2]; |
| 355 | } __packed; |
| 356 | |
| 357 | struct sta_rec_he_v2 { |
| 358 | __le16 tag; |
| 359 | __le16 len; |
| 360 | u8 he_mac_cap[6]; |
| 361 | u8 he_phy_cap[11]; |
| 362 | u8 pkt_ext; |
| 363 | /* 0: BW80, 1: BW160, 2: BW8080 */ |
| 364 | __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; |
| 365 | } __packed; |
| 366 | |
| 367 | struct sta_rec_amsdu { |
| 368 | __le16 tag; |
| 369 | __le16 len; |
| 370 | u8 max_amsdu_num; |
| 371 | u8 max_mpdu_size; |
| 372 | u8 amsdu_en; |
| 373 | u8 rsv; |
| 374 | } __packed; |
| 375 | |
| 376 | struct sta_rec_state { |
| 377 | __le16 tag; |
| 378 | __le16 len; |
| 379 | __le32 flags; |
| 380 | u8 state; |
| 381 | u8 vht_opmode; |
| 382 | u8 action; |
| 383 | u8 rsv[1]; |
| 384 | } __packed; |
| 385 | |
| 386 | #define RA_LEGACY_OFDM GENMASK(13, 6) |
| 387 | #define RA_LEGACY_CCK GENMASK(3, 0) |
| 388 | #define HT_MCS_MASK_NUM 10 |
| 389 | struct sta_rec_ra_info { |
| 390 | __le16 tag; |
| 391 | __le16 len; |
| 392 | __le16 legacy; |
| 393 | u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; |
| 394 | } __packed; |
| 395 | |
| 396 | struct sta_rec_phy { |
| 397 | __le16 tag; |
| 398 | __le16 len; |
| 399 | __le16 basic_rate; |
| 400 | u8 phy_type; |
| 401 | u8 ampdu; |
| 402 | u8 rts_policy; |
| 403 | u8 rcpi; |
| 404 | u8 max_ampdu_len; /* connac3 */ |
| 405 | u8 rsv[1]; |
| 406 | } __packed; |
| 407 | |
| 408 | struct sta_rec_he_6g_capa { |
| 409 | __le16 tag; |
| 410 | __le16 len; |
| 411 | __le16 capa; |
| 412 | u8 rsv[2]; |
| 413 | } __packed; |
| 414 | |
| 415 | struct sec_key { |
| 416 | u8 cipher_id; |
| 417 | u8 cipher_len; |
| 418 | u8 key_id; |
| 419 | u8 key_len; |
| 420 | u8 key[32]; |
| 421 | } __packed; |
| 422 | |
| 423 | struct sta_rec_sec { |
| 424 | __le16 tag; |
| 425 | __le16 len; |
| 426 | u8 add; |
| 427 | u8 n_cipher; |
| 428 | u8 rsv[2]; |
| 429 | |
| 430 | struct sec_key key[2]; |
| 431 | } __packed; |
| 432 | |
| 433 | struct sta_rec_bf { |
| 434 | __le16 tag; |
| 435 | __le16 len; |
| 436 | |
| 437 | __le16 pfmu; /* 0xffff: no access right for PFMU */ |
| 438 | bool su_mu; /* 0: SU, 1: MU */ |
| 439 | u8 bf_cap; /* 0: iBF, 1: eBF */ |
| 440 | u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ |
| 441 | u8 ndpa_rate; |
| 442 | u8 ndp_rate; |
| 443 | u8 rept_poll_rate; |
| 444 | u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ |
| 445 | u8 ncol; |
| 446 | u8 nrow; |
| 447 | u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ |
| 448 | |
| 449 | u8 mem_total; |
| 450 | u8 mem_20m; |
| 451 | struct { |
| 452 | u8 row; |
| 453 | u8 col: 6, row_msb: 2; |
| 454 | } mem[4]; |
| 455 | |
| 456 | __le16 smart_ant; |
| 457 | u8 se_idx; |
| 458 | u8 auto_sounding; /* b7: low traffic indicator |
| 459 | * b6: Stop sounding for this entry |
| 460 | * b5 ~ b0: postpone sounding |
| 461 | */ |
| 462 | u8 ibf_timeout; |
| 463 | u8 ibf_dbw; |
| 464 | u8 ibf_ncol; |
| 465 | u8 ibf_nrow; |
| 466 | u8 nrow_gt_bw80; |
| 467 | u8 ncol_gt_bw80; |
| 468 | u8 ru_start_idx; |
| 469 | u8 ru_end_idx; |
| 470 | |
| 471 | bool trigger_su; |
| 472 | bool trigger_mu; |
| 473 | bool ng16_su; |
| 474 | bool ng16_mu; |
| 475 | bool codebook42_su; |
| 476 | bool codebook75_mu; |
| 477 | |
| 478 | u8 he_ltf; |
| 479 | u8 rsv[3]; |
| 480 | } __packed; |
| 481 | |
| 482 | struct sta_rec_bfee { |
| 483 | __le16 tag; |
| 484 | __le16 len; |
| 485 | bool fb_identity_matrix; /* 1: feedback identity matrix */ |
| 486 | bool ignore_feedback; /* 1: ignore */ |
| 487 | u8 rsv[2]; |
| 488 | } __packed; |
| 489 | |
| 490 | struct sta_rec_muru { |
| 491 | __le16 tag; |
| 492 | __le16 len; |
| 493 | |
| 494 | struct { |
| 495 | bool ofdma_dl_en; |
| 496 | bool ofdma_ul_en; |
| 497 | bool mimo_dl_en; |
| 498 | bool mimo_ul_en; |
| 499 | u8 rsv[4]; |
| 500 | } cfg; |
| 501 | |
| 502 | struct { |
| 503 | u8 punc_pream_rx; |
| 504 | bool he_20m_in_40m_2g; |
| 505 | bool he_20m_in_160m; |
| 506 | bool he_80m_in_160m; |
| 507 | bool lt16_sigb; |
| 508 | bool rx_su_comp_sigb; |
| 509 | bool rx_su_non_comp_sigb; |
| 510 | u8 rsv; |
| 511 | } ofdma_dl; |
| 512 | |
| 513 | struct { |
| 514 | u8 t_frame_dur; |
| 515 | u8 mu_cascading; |
| 516 | u8 uo_ra; |
| 517 | u8 he_2x996_tone; |
| 518 | u8 rx_t_frame_11ac; |
| 519 | u8 rsv[3]; |
| 520 | } ofdma_ul; |
| 521 | |
| 522 | struct { |
| 523 | bool vht_mu_bfee; |
| 524 | bool partial_bw_dl_mimo; |
| 525 | u8 rsv[2]; |
| 526 | } mimo_dl; |
| 527 | |
| 528 | struct { |
| 529 | bool full_ul_mimo; |
| 530 | bool partial_ul_mimo; |
| 531 | u8 rsv[2]; |
| 532 | } mimo_ul; |
| 533 | } __packed; |
| 534 | |
| 535 | struct sta_phy { |
| 536 | u8 type; |
| 537 | u8 flag; |
| 538 | u8 stbc; |
| 539 | u8 sgi; |
| 540 | u8 bw; |
| 541 | u8 ldpc; |
| 542 | u8 mcs; |
| 543 | u8 nss; |
| 544 | u8 he_ltf; |
| 545 | }; |
| 546 | |
| 547 | struct sta_rec_ra { |
| 548 | __le16 tag; |
| 549 | __le16 len; |
| 550 | |
| 551 | u8 valid; |
| 552 | u8 auto_rate; |
| 553 | u8 phy_mode; |
| 554 | u8 channel; |
| 555 | u8 bw; |
| 556 | u8 disable_cck; |
| 557 | u8 ht_mcs32; |
| 558 | u8 ht_gf; |
| 559 | u8 ht_mcs[4]; |
| 560 | u8 mmps_mode; |
| 561 | u8 gband_256; |
| 562 | u8 af; |
| 563 | u8 auth_wapi_mode; |
| 564 | u8 rate_len; |
| 565 | |
| 566 | u8 supp_mode; |
| 567 | u8 supp_cck_rate; |
| 568 | u8 supp_ofdm_rate; |
| 569 | __le32 supp_ht_mcs; |
| 570 | __le16 supp_vht_mcs[4]; |
| 571 | |
| 572 | u8 op_mode; |
| 573 | u8 op_vht_chan_width; |
| 574 | u8 op_vht_rx_nss; |
| 575 | u8 op_vht_rx_nss_type; |
| 576 | |
| 577 | __le32 sta_cap; |
| 578 | |
| 579 | struct sta_phy phy; |
| 580 | } __packed; |
| 581 | |
| 582 | struct sta_rec_ra_fixed { |
| 583 | __le16 tag; |
| 584 | __le16 len; |
| 585 | |
| 586 | __le32 field; |
| 587 | u8 op_mode; |
| 588 | u8 op_vht_chan_width; |
| 589 | u8 op_vht_rx_nss; |
| 590 | u8 op_vht_rx_nss_type; |
| 591 | |
| 592 | struct sta_phy phy; |
| 593 | |
| 594 | u8 spe_idx; |
| 595 | u8 short_preamble; |
| 596 | u8 is_5g; |
| 597 | u8 mmps_mode; |
| 598 | } __packed; |
| 599 | |
| 600 | /* wtbl_rec */ |
| 601 | |
| 602 | struct wtbl_req_hdr { |
| 603 | u8 wlan_idx_lo; |
| 604 | u8 operation; |
| 605 | __le16 tlv_num; |
| 606 | u8 wlan_idx_hi; |
| 607 | u8 rsv[3]; |
| 608 | } __packed; |
| 609 | |
| 610 | struct wtbl_generic { |
| 611 | __le16 tag; |
| 612 | __le16 len; |
| 613 | u8 peer_addr[ETH_ALEN]; |
| 614 | u8 muar_idx; |
| 615 | u8 skip_tx; |
| 616 | u8 cf_ack; |
| 617 | u8 qos; |
| 618 | u8 mesh; |
| 619 | u8 adm; |
| 620 | __le16 partial_aid; |
| 621 | u8 baf_en; |
| 622 | u8 aad_om; |
| 623 | } __packed; |
| 624 | |
| 625 | struct wtbl_rx { |
| 626 | __le16 tag; |
| 627 | __le16 len; |
| 628 | u8 rcid; |
| 629 | u8 rca1; |
| 630 | u8 rca2; |
| 631 | u8 rv; |
| 632 | u8 rsv[4]; |
| 633 | } __packed; |
| 634 | |
| 635 | struct wtbl_ht { |
| 636 | __le16 tag; |
| 637 | __le16 len; |
| 638 | u8 ht; |
| 639 | u8 ldpc; |
| 640 | u8 af; |
| 641 | u8 mm; |
| 642 | u8 rsv[4]; |
| 643 | } __packed; |
| 644 | |
| 645 | struct wtbl_vht { |
| 646 | __le16 tag; |
| 647 | __le16 len; |
| 648 | u8 ldpc; |
| 649 | u8 dyn_bw; |
| 650 | u8 vht; |
| 651 | u8 txop_ps; |
| 652 | u8 rsv[4]; |
| 653 | } __packed; |
| 654 | |
| 655 | struct wtbl_tx_ps { |
| 656 | __le16 tag; |
| 657 | __le16 len; |
| 658 | u8 txps; |
| 659 | u8 rsv[3]; |
| 660 | } __packed; |
| 661 | |
| 662 | struct wtbl_hdr_trans { |
| 663 | __le16 tag; |
| 664 | __le16 len; |
| 665 | u8 to_ds; |
| 666 | u8 from_ds; |
| 667 | u8 no_rx_trans; |
| 668 | u8 rsv; |
| 669 | } __packed; |
| 670 | |
| 671 | struct wtbl_ba { |
| 672 | __le16 tag; |
| 673 | __le16 len; |
| 674 | /* common */ |
| 675 | u8 tid; |
| 676 | u8 ba_type; |
| 677 | u8 rsv0[2]; |
| 678 | /* originator only */ |
| 679 | __le16 sn; |
| 680 | u8 ba_en; |
| 681 | u8 ba_winsize_idx; |
| 682 | /* originator & recipient */ |
| 683 | __le16 ba_winsize; |
| 684 | /* recipient only */ |
| 685 | u8 peer_addr[ETH_ALEN]; |
| 686 | u8 rst_ba_tid; |
| 687 | u8 rst_ba_sel; |
| 688 | u8 rst_ba_sb; |
| 689 | u8 band_idx; |
| 690 | u8 rsv1[4]; |
| 691 | } __packed; |
| 692 | |
| 693 | struct wtbl_smps { |
| 694 | __le16 tag; |
| 695 | __le16 len; |
| 696 | u8 smps; |
| 697 | u8 rsv[3]; |
| 698 | } __packed; |
| 699 | |
| 700 | /* mt7615 only */ |
| 701 | |
| 702 | struct wtbl_bf { |
| 703 | __le16 tag; |
| 704 | __le16 len; |
| 705 | u8 ibf; |
| 706 | u8 ebf; |
| 707 | u8 ibf_vht; |
| 708 | u8 ebf_vht; |
| 709 | u8 gid; |
| 710 | u8 pfmu_idx; |
| 711 | u8 rsv[2]; |
| 712 | } __packed; |
| 713 | |
| 714 | struct wtbl_pn { |
| 715 | __le16 tag; |
| 716 | __le16 len; |
| 717 | u8 pn[6]; |
| 718 | u8 rsv[2]; |
| 719 | } __packed; |
| 720 | |
| 721 | struct wtbl_spe { |
| 722 | __le16 tag; |
| 723 | __le16 len; |
| 724 | u8 spe_idx; |
| 725 | u8 rsv[3]; |
| 726 | } __packed; |
| 727 | |
| 728 | struct wtbl_raw { |
| 729 | __le16 tag; |
| 730 | __le16 len; |
| 731 | u8 wtbl_idx; |
| 732 | u8 dw; |
| 733 | u8 rsv[2]; |
| 734 | __le32 msk; |
| 735 | __le32 val; |
| 736 | } __packed; |
| 737 | |
| 738 | #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ |
| 739 | sizeof(struct wtbl_generic) + \ |
| 740 | sizeof(struct wtbl_rx) + \ |
| 741 | sizeof(struct wtbl_ht) + \ |
| 742 | sizeof(struct wtbl_vht) + \ |
| 743 | sizeof(struct wtbl_tx_ps) + \ |
| 744 | sizeof(struct wtbl_hdr_trans) +\ |
| 745 | sizeof(struct wtbl_ba) + \ |
| 746 | sizeof(struct wtbl_bf) + \ |
| 747 | sizeof(struct wtbl_smps) + \ |
| 748 | sizeof(struct wtbl_pn) + \ |
| 749 | sizeof(struct wtbl_spe)) |
| 750 | |
| 751 | #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ |
| 752 | sizeof(struct sta_rec_basic) + \ |
| 753 | sizeof(struct sta_rec_bf) + \ |
| 754 | sizeof(struct sta_rec_ht) + \ |
| 755 | sizeof(struct sta_rec_he) + \ |
| 756 | sizeof(struct sta_rec_ba) + \ |
| 757 | sizeof(struct sta_rec_vht) + \ |
| 758 | sizeof(struct sta_rec_uapsd) + \ |
| 759 | sizeof(struct sta_rec_amsdu) + \ |
| 760 | sizeof(struct sta_rec_muru) + \ |
| 761 | sizeof(struct sta_rec_bfee) + \ |
| 762 | sizeof(struct sta_rec_ra) + \ |
| 763 | sizeof(struct sta_rec_sec) + \ |
| 764 | sizeof(struct sta_rec_ra_fixed) + \ |
| 765 | sizeof(struct sta_rec_he_6g_capa) + \ |
| 766 | sizeof(struct tlv) + \ |
| 767 | MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) |
| 768 | |
| 769 | enum { |
| 770 | STA_REC_BASIC, |
| 771 | STA_REC_RA, |
| 772 | STA_REC_RA_CMM_INFO, |
| 773 | STA_REC_RA_UPDATE, |
| 774 | STA_REC_BF, |
| 775 | STA_REC_AMSDU, |
| 776 | STA_REC_BA, |
| 777 | STA_REC_STATE, |
| 778 | STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ |
| 779 | STA_REC_HT, |
| 780 | STA_REC_VHT, |
| 781 | STA_REC_APPS, |
| 782 | STA_REC_KEY, |
| 783 | STA_REC_WTBL, |
| 784 | STA_REC_HE, |
| 785 | STA_REC_HW_AMSDU, |
| 786 | STA_REC_WTBL_AADOM, |
| 787 | STA_REC_KEY_V2, |
| 788 | STA_REC_MURU, |
| 789 | STA_REC_MUEDCA, |
| 790 | STA_REC_BFEE, |
| 791 | STA_REC_PHY = 0x15, |
| 792 | STA_REC_HE_6G = 0x17, |
| 793 | STA_REC_HE_V2 = 0x19, |
| 794 | STA_REC_HDRT = 0x28, |
| 795 | STA_REC_HDR_TRANS = 0x2B, |
| 796 | STA_REC_MAX_NUM |
| 797 | }; |
| 798 | |
| 799 | enum { |
| 800 | WTBL_GENERIC, |
| 801 | WTBL_RX, |
| 802 | WTBL_HT, |
| 803 | WTBL_VHT, |
| 804 | WTBL_PEER_PS, /* not used */ |
| 805 | WTBL_TX_PS, |
| 806 | WTBL_HDR_TRANS, |
| 807 | WTBL_SEC_KEY, |
| 808 | WTBL_BA, |
| 809 | WTBL_RDG, /* obsoleted */ |
| 810 | WTBL_PROTECT, /* not used */ |
| 811 | WTBL_CLEAR, /* not used */ |
| 812 | WTBL_BF, |
| 813 | WTBL_SMPS, |
| 814 | WTBL_RAW_DATA, /* debug only */ |
| 815 | WTBL_PN, |
| 816 | WTBL_SPE, |
| 817 | WTBL_MAX_NUM |
| 818 | }; |
| 819 | |
| 820 | #define STA_TYPE_STA BIT(0) |
| 821 | #define STA_TYPE_AP BIT(1) |
| 822 | #define STA_TYPE_ADHOC BIT(2) |
| 823 | #define STA_TYPE_WDS BIT(4) |
| 824 | #define STA_TYPE_BC BIT(5) |
| 825 | |
| 826 | #define NETWORK_INFRA BIT(16) |
| 827 | #define NETWORK_P2P BIT(17) |
| 828 | #define NETWORK_IBSS BIT(18) |
| 829 | #define NETWORK_WDS BIT(21) |
| 830 | |
| 831 | #define SCAN_FUNC_RANDOM_MAC BIT(0) |
| 832 | #define SCAN_FUNC_SPLIT_SCAN BIT(5) |
| 833 | |
| 834 | #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) |
| 835 | #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) |
| 836 | #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) |
| 837 | #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) |
| 838 | #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) |
| 839 | #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) |
| 840 | #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) |
| 841 | |
| 842 | #define CONN_STATE_DISCONNECT 0 |
| 843 | #define CONN_STATE_CONNECT 1 |
| 844 | #define CONN_STATE_PORT_SECURE 2 |
| 845 | |
| 846 | /* HE MAC */ |
| 847 | #define STA_REC_HE_CAP_HTC BIT(0) |
| 848 | #define STA_REC_HE_CAP_BQR BIT(1) |
| 849 | #define STA_REC_HE_CAP_BSR BIT(2) |
| 850 | #define STA_REC_HE_CAP_OM BIT(3) |
| 851 | #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) |
| 852 | /* HE PHY */ |
| 853 | #define STA_REC_HE_CAP_DUAL_BAND BIT(5) |
| 854 | #define STA_REC_HE_CAP_LDPC BIT(6) |
| 855 | #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) |
| 856 | #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) |
| 857 | /* STBC */ |
| 858 | #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) |
| 859 | #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) |
| 860 | #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) |
| 861 | #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) |
| 862 | /* GI */ |
| 863 | #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) |
| 864 | #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) |
| 865 | #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) |
| 866 | #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) |
| 867 | #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) |
| 868 | /* 242 TONE */ |
| 869 | #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) |
| 870 | #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) |
| 871 | #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) |
| 872 | |
| 873 | #define PHY_MODE_A BIT(0) |
| 874 | #define PHY_MODE_B BIT(1) |
| 875 | #define PHY_MODE_G BIT(2) |
| 876 | #define PHY_MODE_GN BIT(3) |
| 877 | #define PHY_MODE_AN BIT(4) |
| 878 | #define PHY_MODE_AC BIT(5) |
| 879 | #define PHY_MODE_AX_24G BIT(6) |
| 880 | #define PHY_MODE_AX_5G BIT(7) |
| 881 | |
| 882 | #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ |
| 883 | |
| 884 | #define MODE_CCK BIT(0) |
| 885 | #define MODE_OFDM BIT(1) |
| 886 | #define MODE_HT BIT(2) |
| 887 | #define MODE_VHT BIT(3) |
| 888 | #define MODE_HE BIT(4) |
| 889 | |
| 890 | #define STA_CAP_WMM BIT(0) |
| 891 | #define STA_CAP_SGI_20 BIT(4) |
| 892 | #define STA_CAP_SGI_40 BIT(5) |
| 893 | #define STA_CAP_TX_STBC BIT(6) |
| 894 | #define STA_CAP_RX_STBC BIT(7) |
| 895 | #define STA_CAP_VHT_SGI_80 BIT(16) |
| 896 | #define STA_CAP_VHT_SGI_160 BIT(17) |
| 897 | #define STA_CAP_VHT_TX_STBC BIT(18) |
| 898 | #define STA_CAP_VHT_RX_STBC BIT(19) |
| 899 | #define STA_CAP_VHT_LDPC BIT(23) |
| 900 | #define STA_CAP_LDPC BIT(24) |
| 901 | #define STA_CAP_HT BIT(26) |
| 902 | #define STA_CAP_VHT BIT(27) |
| 903 | #define STA_CAP_HE BIT(28) |
| 904 | |
| 905 | enum { |
| 906 | PHY_TYPE_HR_DSSS_INDEX = 0, |
| 907 | PHY_TYPE_ERP_INDEX, |
| 908 | PHY_TYPE_ERP_P2P_INDEX, |
| 909 | PHY_TYPE_OFDM_INDEX, |
| 910 | PHY_TYPE_HT_INDEX, |
| 911 | PHY_TYPE_VHT_INDEX, |
| 912 | PHY_TYPE_HE_INDEX, |
| 913 | PHY_TYPE_INDEX_NUM |
| 914 | }; |
| 915 | |
| 916 | #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) |
| 917 | #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) |
| 918 | #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) |
| 919 | #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) |
| 920 | #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) |
| 921 | #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) |
| 922 | |
| 923 | #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) |
| 924 | #define MT_WTBL_RATE_MCS GENMASK(5, 0) |
| 925 | #define MT_WTBL_RATE_NSS GENMASK(12, 10) |
| 926 | #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) |
| 927 | #define MT_WTBL_RATE_GI GENMASK(3, 0) |
| 928 | |
| 929 | #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) |
| 930 | #define MT_WTBL_W5_SHORT_GI_20 BIT(8) |
| 931 | #define MT_WTBL_W5_SHORT_GI_40 BIT(9) |
| 932 | #define MT_WTBL_W5_SHORT_GI_80 BIT(10) |
| 933 | #define MT_WTBL_W5_SHORT_GI_160 BIT(11) |
| 934 | #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) |
| 935 | #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) |
| 936 | #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) |
| 937 | #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) |
| 938 | |
| 939 | enum { |
| 940 | WTBL_RESET_AND_SET = 1, |
| 941 | WTBL_SET, |
| 942 | WTBL_QUERY, |
| 943 | WTBL_RESET_ALL |
| 944 | }; |
| 945 | |
| 946 | enum { |
| 947 | MT_BA_TYPE_INVALID, |
| 948 | MT_BA_TYPE_ORIGINATOR, |
| 949 | MT_BA_TYPE_RECIPIENT |
| 950 | }; |
| 951 | |
| 952 | enum { |
| 953 | RST_BA_MAC_TID_MATCH, |
| 954 | RST_BA_MAC_MATCH, |
| 955 | RST_BA_NO_MATCH |
| 956 | }; |
| 957 | |
| 958 | enum { |
| 959 | DEV_INFO_ACTIVE, |
| 960 | DEV_INFO_MAX_NUM |
| 961 | }; |
| 962 | |
| 963 | /* event table */ |
| 964 | enum { |
| 965 | MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, |
| 966 | MCU_EVENT_FW_START = 0x01, |
| 967 | MCU_EVENT_GENERIC = 0x01, |
| 968 | MCU_EVENT_ACCESS_REG = 0x02, |
| 969 | MCU_EVENT_MT_PATCH_SEM = 0x04, |
| 970 | MCU_EVENT_REG_ACCESS = 0x05, |
| 971 | MCU_EVENT_LP_INFO = 0x07, |
| 972 | MCU_EVENT_SCAN_DONE = 0x0d, |
| 973 | MCU_EVENT_TX_DONE = 0x0f, |
| 974 | MCU_EVENT_ROC = 0x10, |
| 975 | MCU_EVENT_BSS_ABSENCE = 0x11, |
| 976 | MCU_EVENT_BSS_BEACON_LOSS = 0x13, |
| 977 | MCU_EVENT_CH_PRIVILEGE = 0x18, |
| 978 | MCU_EVENT_SCHED_SCAN_DONE = 0x23, |
| 979 | MCU_EVENT_DBG_MSG = 0x27, |
| 980 | MCU_EVENT_TXPWR = 0xd0, |
| 981 | MCU_EVENT_EXT = 0xed, |
| 982 | MCU_EVENT_RESTART_DL = 0xef, |
| 983 | MCU_EVENT_COREDUMP = 0xf0, |
| 984 | }; |
| 985 | |
| 986 | /* ext event table */ |
| 987 | enum { |
| 988 | MCU_EXT_EVENT_PS_SYNC = 0x5, |
| 989 | MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, |
| 990 | MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, |
| 991 | MCU_EXT_EVENT_ASSERT_DUMP = 0x23, |
| 992 | MCU_EXT_EVENT_RDD_REPORT = 0x3a, |
| 993 | MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, |
| 994 | MCU_EXT_EVENT_BCC_NOTIFY = 0x75, |
| 995 | MCU_EXT_EVENT_MURU_CTRL = 0x9f, |
| 996 | }; |
| 997 | |
| 998 | /* unified event table */ |
| 999 | enum { |
| 1000 | MCU_UNI_EVENT_RESULT = 0x01, |
| 1001 | MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04, |
| 1002 | MCU_UNI_EVENT_IE_COUNTDOWN = 0x09, |
| 1003 | MCU_UNI_EVENT_RDD_REPORT = 0x11, |
| 1004 | }; |
| 1005 | |
| 1006 | #define MCU_UNI_CMD_EVENT BIT(1) |
| 1007 | #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2) |
| 1008 | |
| 1009 | enum { |
| 1010 | MCU_Q_QUERY, |
| 1011 | MCU_Q_SET, |
| 1012 | MCU_Q_RESERVED, |
| 1013 | MCU_Q_NA |
| 1014 | }; |
| 1015 | |
| 1016 | enum { |
| 1017 | MCU_S2D_H2N, |
| 1018 | MCU_S2D_C2N, |
| 1019 | MCU_S2D_H2C, |
| 1020 | MCU_S2D_H2CN |
| 1021 | }; |
| 1022 | |
| 1023 | enum { |
| 1024 | PATCH_NOT_DL_SEM_FAIL, |
| 1025 | PATCH_IS_DL, |
| 1026 | PATCH_NOT_DL_SEM_SUCCESS, |
| 1027 | PATCH_REL_SEM_SUCCESS |
| 1028 | }; |
| 1029 | |
| 1030 | enum { |
| 1031 | FW_STATE_INITIAL, |
| 1032 | FW_STATE_FW_DOWNLOAD, |
| 1033 | FW_STATE_NORMAL_OPERATION, |
| 1034 | FW_STATE_NORMAL_TRX, |
| 1035 | FW_STATE_RDY = 7 |
| 1036 | }; |
| 1037 | |
| 1038 | enum { |
| 1039 | CH_SWITCH_NORMAL = 0, |
| 1040 | CH_SWITCH_SCAN = 3, |
| 1041 | CH_SWITCH_MCC = 4, |
| 1042 | CH_SWITCH_DFS = 5, |
| 1043 | CH_SWITCH_BACKGROUND_SCAN_START = 6, |
| 1044 | CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, |
| 1045 | CH_SWITCH_BACKGROUND_SCAN_STOP = 8, |
| 1046 | CH_SWITCH_SCAN_BYPASS_DPD = 9 |
| 1047 | }; |
| 1048 | |
| 1049 | enum { |
| 1050 | THERMAL_SENSOR_TEMP_QUERY, |
| 1051 | THERMAL_SENSOR_MANUAL_CTRL, |
| 1052 | THERMAL_SENSOR_INFO_QUERY, |
| 1053 | THERMAL_SENSOR_TASK_CTRL, |
| 1054 | }; |
| 1055 | |
| 1056 | enum mcu_cipher_type { |
| 1057 | MCU_CIPHER_NONE = 0, |
| 1058 | MCU_CIPHER_WEP40, |
| 1059 | MCU_CIPHER_WEP104, |
| 1060 | MCU_CIPHER_WEP128, |
| 1061 | MCU_CIPHER_TKIP, |
| 1062 | MCU_CIPHER_AES_CCMP, |
| 1063 | MCU_CIPHER_CCMP_256, |
| 1064 | MCU_CIPHER_GCMP, |
| 1065 | MCU_CIPHER_GCMP_256, |
| 1066 | MCU_CIPHER_WAPI, |
| 1067 | MCU_CIPHER_BIP_CMAC_128, |
| 1068 | }; |
| 1069 | |
| 1070 | enum { |
| 1071 | EE_MODE_EFUSE, |
| 1072 | EE_MODE_BUFFER, |
| 1073 | }; |
| 1074 | |
| 1075 | enum { |
| 1076 | EE_FORMAT_BIN, |
| 1077 | EE_FORMAT_WHOLE, |
| 1078 | EE_FORMAT_MULTIPLE, |
| 1079 | }; |
| 1080 | |
| 1081 | enum { |
| 1082 | MCU_PHY_STATE_TX_RATE, |
| 1083 | MCU_PHY_STATE_RX_RATE, |
| 1084 | MCU_PHY_STATE_RSSI, |
| 1085 | MCU_PHY_STATE_CONTENTION_RX_RATE, |
| 1086 | MCU_PHY_STATE_OFDMLQ_CNINFO, |
| 1087 | }; |
| 1088 | |
| 1089 | #define MCU_CMD_ACK BIT(0) |
| 1090 | #define MCU_CMD_UNI BIT(1) |
| 1091 | #define MCU_CMD_SET BIT(2) |
| 1092 | |
| 1093 | #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ |
| 1094 | MCU_CMD_SET) |
| 1095 | #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI) |
| 1096 | |
| 1097 | #define __MCU_CMD_FIELD_ID GENMASK(7, 0) |
| 1098 | #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) |
| 1099 | #define __MCU_CMD_FIELD_QUERY BIT(16) |
| 1100 | #define __MCU_CMD_FIELD_UNI BIT(17) |
| 1101 | #define __MCU_CMD_FIELD_CE BIT(18) |
| 1102 | #define __MCU_CMD_FIELD_WA BIT(19) |
| 1103 | #define __MCU_CMD_FIELD_WM BIT(20) |
| 1104 | |
| 1105 | #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ |
| 1106 | MCU_CMD_##_t) |
| 1107 | #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ |
| 1108 | FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ |
| 1109 | MCU_EXT_CMD_##_t)) |
| 1110 | #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) |
| 1111 | #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ |
| 1112 | FIELD_PREP(__MCU_CMD_FIELD_ID, \ |
| 1113 | MCU_UNI_CMD_##_t)) |
| 1114 | #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ |
| 1115 | FIELD_PREP(__MCU_CMD_FIELD_ID, \ |
| 1116 | MCU_CE_CMD_##_t)) |
| 1117 | #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) |
| 1118 | |
| 1119 | #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) |
| 1120 | #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) |
| 1121 | #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ |
| 1122 | FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ |
| 1123 | MCU_WA_PARAM_CMD_##_t)) |
| 1124 | |
| 1125 | #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ |
| 1126 | __MCU_CMD_FIELD_WM) |
| 1127 | #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \ |
| 1128 | __MCU_CMD_FIELD_QUERY |\ |
| 1129 | __MCU_CMD_FIELD_WM) |
| 1130 | #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ |
| 1131 | __MCU_CMD_FIELD_WA) |
| 1132 | #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \ |
| 1133 | __MCU_CMD_FIELD_WA) |
| 1134 | |
| 1135 | enum { |
| 1136 | MCU_EXT_CMD_EFUSE_ACCESS = 0x01, |
| 1137 | MCU_EXT_CMD_RF_REG_ACCESS = 0x02, |
| 1138 | MCU_EXT_CMD_RF_TEST = 0x04, |
| 1139 | MCU_EXT_CMD_PM_STATE_CTRL = 0x07, |
| 1140 | MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, |
| 1141 | MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, |
| 1142 | MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, |
| 1143 | MCU_EXT_CMD_TXBF_ACTION = 0x1e, |
| 1144 | MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, |
| 1145 | MCU_EXT_CMD_THERMAL_PROT = 0x23, |
| 1146 | MCU_EXT_CMD_STA_REC_UPDATE = 0x25, |
| 1147 | MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, |
| 1148 | MCU_EXT_CMD_EDCA_UPDATE = 0x27, |
| 1149 | MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, |
| 1150 | MCU_EXT_CMD_THERMAL_CTRL = 0x2c, |
| 1151 | MCU_EXT_CMD_WTBL_UPDATE = 0x32, |
| 1152 | MCU_EXT_CMD_SET_DRR_CTRL = 0x36, |
| 1153 | MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, |
| 1154 | MCU_EXT_CMD_ATE_CTRL = 0x3d, |
| 1155 | MCU_EXT_CMD_PROTECT_CTRL = 0x3e, |
| 1156 | MCU_EXT_CMD_DBDC_CTRL = 0x45, |
| 1157 | MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, |
| 1158 | MCU_EXT_CMD_RX_HDR_TRANS = 0x47, |
| 1159 | MCU_EXT_CMD_MUAR_UPDATE = 0x48, |
| 1160 | MCU_EXT_CMD_BCN_OFFLOAD = 0x49, |
| 1161 | MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, |
| 1162 | MCU_EXT_CMD_SET_RX_PATH = 0x4e, |
| 1163 | MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, |
| 1164 | MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, |
| 1165 | MCU_EXT_CMD_RXDCOC_CAL = 0x59, |
| 1166 | MCU_EXT_CMD_GET_MIB_INFO = 0x5a, |
| 1167 | MCU_EXT_CMD_TXDPD_CAL = 0x60, |
| 1168 | MCU_EXT_CMD_CAL_CACHE = 0x67, |
| 1169 | MCU_EXT_CMD_SET_RADAR_TH = 0x7c, |
| 1170 | MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, |
| 1171 | MCU_EXT_CMD_MWDS_SUPPORT = 0x80, |
| 1172 | MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, |
| 1173 | MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, |
| 1174 | MCU_EXT_CMD_FW_DBG_CTRL = 0x95, |
| 1175 | MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, |
| 1176 | MCU_EXT_CMD_SET_RDD_TH = 0x9d, |
| 1177 | MCU_EXT_CMD_MURU_CTRL = 0x9f, |
| 1178 | MCU_EXT_CMD_SET_SPR = 0xa8, |
| 1179 | MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, |
| 1180 | MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, |
| 1181 | MCU_EXT_CMD_PHY_STAT_INFO = 0xad, |
| 1182 | }; |
| 1183 | |
| 1184 | enum { |
| 1185 | MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, |
| 1186 | MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, |
| 1187 | MCU_UNI_CMD_STA_REC_UPDATE = 0x03, |
| 1188 | MCU_UNI_CMD_EDCA_UPDATE = 0x04, |
| 1189 | MCU_UNI_CMD_SUSPEND = 0x05, |
| 1190 | MCU_UNI_CMD_OFFLOAD = 0x06, |
| 1191 | MCU_UNI_CMD_HIF_CTRL = 0x07, |
| 1192 | MCU_UNI_CMD_BAND_CONFIG = 0x08, |
| 1193 | MCU_UNI_CMD_WSYS_CONFIG = 0x0b, |
| 1194 | MCU_UNI_CMD_REG_ACCESS = 0x0d, |
| 1195 | MCU_UNI_CMD_POWER_CREL = 0x0f, |
| 1196 | MCU_UNI_CMD_RX_HDR_TRANS = 0x12, |
| 1197 | MCU_UNI_CMD_TWT = 0x14, |
| 1198 | MCU_UNI_CMD_RDD_CTRL = 0x19, |
| 1199 | MCU_UNI_CMD_GET_MIB_INFO = 0x22, |
| 1200 | MCU_UNI_CMD_SNIFFER = 0x24, |
| 1201 | MCU_UNI_CMD_SR = 0x25, |
| 1202 | MCU_UNI_CMD_TXPOWER = 0x2b, |
| 1203 | MCU_UNI_CMD_EFUSE_CTRL = 0x2d, |
| 1204 | MCU_UNI_CMD_RA = 0x2f, |
| 1205 | MCU_UNI_CMD_MURU = 0x31, |
| 1206 | MCU_UNI_CMD_BF = 0x33, |
| 1207 | MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, |
| 1208 | MCU_UNI_CMD_THERMAL = 0x35, |
| 1209 | MCU_UNI_CMD_VOW = 0x37, |
| 1210 | MCU_UNI_CMD_RRO = 0x57, |
| 1211 | }; |
| 1212 | |
| 1213 | enum { |
| 1214 | MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, |
| 1215 | MCU_CMD_FW_START_REQ = 0x02, |
| 1216 | MCU_CMD_INIT_ACCESS_REG = 0x3, |
| 1217 | MCU_CMD_NIC_POWER_CTRL = 0x4, |
| 1218 | MCU_CMD_PATCH_START_REQ = 0x05, |
| 1219 | MCU_CMD_PATCH_FINISH_REQ = 0x07, |
| 1220 | MCU_CMD_PATCH_SEM_CONTROL = 0x10, |
| 1221 | MCU_CMD_WA_PARAM = 0xc4, |
| 1222 | MCU_CMD_EXT_CID = 0xed, |
| 1223 | MCU_CMD_FW_SCATTER = 0xee, |
| 1224 | MCU_CMD_RESTART_DL_REQ = 0xef, |
| 1225 | }; |
| 1226 | |
| 1227 | /* offload mcu commands */ |
| 1228 | enum { |
| 1229 | MCU_CE_CMD_TEST_CTRL = 0x01, |
| 1230 | MCU_CE_CMD_START_HW_SCAN = 0x03, |
| 1231 | MCU_CE_CMD_SET_PS_PROFILE = 0x05, |
| 1232 | MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, |
| 1233 | MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, |
| 1234 | MCU_CE_CMD_SET_BSS_ABORT = 0x17, |
| 1235 | MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, |
| 1236 | MCU_CE_CMD_SET_ROC = 0x1c, |
| 1237 | MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, |
| 1238 | MCU_CE_CMD_SET_P2P_OPPPS = 0x33, |
| 1239 | MCU_CE_CMD_SET_CLC = 0x5c, |
| 1240 | MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, |
| 1241 | MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, |
| 1242 | MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, |
| 1243 | MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, |
| 1244 | MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, |
| 1245 | MCU_CE_CMD_REG_WRITE = 0xc0, |
| 1246 | MCU_CE_CMD_REG_READ = 0xc0, |
| 1247 | MCU_CE_CMD_CHIP_CONFIG = 0xca, |
| 1248 | MCU_CE_CMD_FWLOG_2_HOST = 0xc5, |
| 1249 | MCU_CE_CMD_GET_WTBL = 0xcd, |
| 1250 | MCU_CE_CMD_GET_TXPWR = 0xd0, |
| 1251 | }; |
| 1252 | |
| 1253 | enum { |
| 1254 | PATCH_SEM_RELEASE, |
| 1255 | PATCH_SEM_GET |
| 1256 | }; |
| 1257 | |
| 1258 | enum { |
| 1259 | UNI_BSS_INFO_BASIC = 0, |
| 1260 | UNI_BSS_INFO_RA = 1, |
| 1261 | UNI_BSS_INFO_RLM = 2, |
| 1262 | UNI_BSS_INFO_BSS_COLOR = 4, |
| 1263 | UNI_BSS_INFO_HE_BASIC = 5, |
| 1264 | UNI_BSS_INFO_BCN_CONTENT = 7, |
| 1265 | UNI_BSS_INFO_BCN_CSA = 8, |
| 1266 | UNI_BSS_INFO_BCN_BCC = 9, |
| 1267 | UNI_BSS_INFO_BCN_MBSSID = 10, |
| 1268 | UNI_BSS_INFO_RATE = 11, |
| 1269 | UNI_BSS_INFO_QBSS = 15, |
| 1270 | UNI_BSS_INFO_SEC = 16, |
| 1271 | UNI_BSS_INFO_TXCMD = 18, |
| 1272 | UNI_BSS_INFO_UAPSD = 19, |
| 1273 | UNI_BSS_INFO_PS = 21, |
| 1274 | UNI_BSS_INFO_BCNFT = 22, |
| 1275 | UNI_BSS_INFO_OFFLOAD = 25, |
| 1276 | UNI_BSS_INFO_MLD = 26, |
| 1277 | }; |
| 1278 | |
| 1279 | enum { |
| 1280 | UNI_OFFLOAD_OFFLOAD_ARP, |
| 1281 | UNI_OFFLOAD_OFFLOAD_ND, |
| 1282 | UNI_OFFLOAD_OFFLOAD_GTK_REKEY, |
| 1283 | UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, |
| 1284 | }; |
| 1285 | |
| 1286 | enum { |
| 1287 | MT_NIC_CAP_TX_RESOURCE, |
| 1288 | MT_NIC_CAP_TX_EFUSE_ADDR, |
| 1289 | MT_NIC_CAP_COEX, |
| 1290 | MT_NIC_CAP_SINGLE_SKU, |
| 1291 | MT_NIC_CAP_CSUM_OFFLOAD, |
| 1292 | MT_NIC_CAP_HW_VER, |
| 1293 | MT_NIC_CAP_SW_VER, |
| 1294 | MT_NIC_CAP_MAC_ADDR, |
| 1295 | MT_NIC_CAP_PHY, |
| 1296 | MT_NIC_CAP_MAC, |
| 1297 | MT_NIC_CAP_FRAME_BUF, |
| 1298 | MT_NIC_CAP_BEAM_FORM, |
| 1299 | MT_NIC_CAP_LOCATION, |
| 1300 | MT_NIC_CAP_MUMIMO, |
| 1301 | MT_NIC_CAP_BUFFER_MODE_INFO, |
| 1302 | MT_NIC_CAP_HW_ADIE_VERSION = 0x14, |
| 1303 | MT_NIC_CAP_ANTSWP = 0x16, |
| 1304 | MT_NIC_CAP_WFDMA_REALLOC, |
| 1305 | MT_NIC_CAP_6G, |
| 1306 | }; |
| 1307 | |
| 1308 | #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) |
| 1309 | #define UNI_WOW_DETECT_TYPE_ANY BIT(1) |
| 1310 | #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) |
| 1311 | #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) |
| 1312 | #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) |
| 1313 | #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) |
| 1314 | #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) |
| 1315 | |
| 1316 | enum { |
| 1317 | UNI_SUSPEND_MODE_SETTING, |
| 1318 | UNI_SUSPEND_WOW_CTRL, |
| 1319 | UNI_SUSPEND_WOW_GPIO_PARAM, |
| 1320 | UNI_SUSPEND_WOW_WAKEUP_PORT, |
| 1321 | UNI_SUSPEND_WOW_PATTERN, |
| 1322 | }; |
| 1323 | |
| 1324 | enum { |
| 1325 | WOW_USB = 1, |
| 1326 | WOW_PCIE = 2, |
| 1327 | WOW_GPIO = 3, |
| 1328 | }; |
| 1329 | |
| 1330 | struct mt76_connac_bss_basic_tlv { |
| 1331 | __le16 tag; |
| 1332 | __le16 len; |
| 1333 | u8 active; |
| 1334 | u8 omac_idx; |
| 1335 | u8 hw_bss_idx; |
| 1336 | u8 band_idx; |
| 1337 | __le32 conn_type; |
| 1338 | u8 conn_state; |
| 1339 | u8 wmm_idx; |
| 1340 | u8 bssid[ETH_ALEN]; |
| 1341 | __le16 bmc_tx_wlan_idx; |
| 1342 | __le16 bcn_interval; |
| 1343 | u8 dtim_period; |
| 1344 | u8 phymode; /* bit(0): A |
| 1345 | * bit(1): B |
| 1346 | * bit(2): G |
| 1347 | * bit(3): GN |
| 1348 | * bit(4): AN |
| 1349 | * bit(5): AC |
| 1350 | * bit(6): AX2 |
| 1351 | * bit(7): AX5 |
| 1352 | * bit(8): AX6 |
| 1353 | */ |
| 1354 | __le16 sta_idx; |
| 1355 | __le16 nonht_basic_phy; |
| 1356 | u8 phymode_ext; /* bit(0) AX_6G */ |
| 1357 | u8 pad[1]; |
| 1358 | } __packed; |
| 1359 | |
| 1360 | struct mt76_connac_bss_qos_tlv { |
| 1361 | __le16 tag; |
| 1362 | __le16 len; |
| 1363 | u8 qos; |
| 1364 | u8 pad[3]; |
| 1365 | } __packed; |
| 1366 | |
| 1367 | struct mt76_connac_beacon_loss_event { |
| 1368 | u8 bss_idx; |
| 1369 | u8 reason; |
| 1370 | u8 pad[2]; |
| 1371 | } __packed; |
| 1372 | |
| 1373 | struct mt76_connac_mcu_bss_event { |
| 1374 | u8 bss_idx; |
| 1375 | u8 is_absent; |
| 1376 | u8 free_quota; |
| 1377 | u8 pad; |
| 1378 | } __packed; |
| 1379 | |
| 1380 | struct mt76_connac_mcu_scan_ssid { |
| 1381 | __le32 ssid_len; |
| 1382 | u8 ssid[IEEE80211_MAX_SSID_LEN]; |
| 1383 | } __packed; |
| 1384 | |
| 1385 | struct mt76_connac_mcu_scan_channel { |
| 1386 | u8 band; /* 1: 2.4GHz |
| 1387 | * 2: 5.0GHz |
| 1388 | * Others: Reserved |
| 1389 | */ |
| 1390 | u8 channel_num; |
| 1391 | } __packed; |
| 1392 | |
| 1393 | struct mt76_connac_mcu_scan_match { |
| 1394 | __le32 rssi_th; |
| 1395 | u8 ssid[IEEE80211_MAX_SSID_LEN]; |
| 1396 | u8 ssid_len; |
| 1397 | u8 rsv[3]; |
| 1398 | } __packed; |
| 1399 | |
| 1400 | struct mt76_connac_hw_scan_req { |
| 1401 | u8 seq_num; |
| 1402 | u8 bss_idx; |
| 1403 | u8 scan_type; /* 0: PASSIVE SCAN |
| 1404 | * 1: ACTIVE SCAN |
| 1405 | */ |
| 1406 | u8 ssid_type; /* BIT(0) wildcard SSID |
| 1407 | * BIT(1) P2P wildcard SSID |
| 1408 | * BIT(2) specified SSID + wildcard SSID |
| 1409 | * BIT(2) + ssid_type_ext BIT(0) specified SSID only |
| 1410 | */ |
| 1411 | u8 ssids_num; |
| 1412 | u8 probe_req_num; /* Number of probe request for each SSID */ |
| 1413 | u8 scan_func; /* BIT(0) Enable random MAC scan |
| 1414 | * BIT(1) Disable DBDC scan type 1~3. |
| 1415 | * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). |
| 1416 | */ |
| 1417 | u8 version; /* 0: Not support fields after ies. |
| 1418 | * 1: Support fields after ies. |
| 1419 | */ |
| 1420 | struct mt76_connac_mcu_scan_ssid ssids[4]; |
| 1421 | __le16 probe_delay_time; |
| 1422 | __le16 channel_dwell_time; /* channel Dwell interval */ |
| 1423 | __le16 timeout_value; |
| 1424 | u8 channel_type; /* 0: Full channels |
| 1425 | * 1: Only 2.4GHz channels |
| 1426 | * 2: Only 5GHz channels |
| 1427 | * 3: P2P social channel only (channel #1, #6 and #11) |
| 1428 | * 4: Specified channels |
| 1429 | * Others: Reserved |
| 1430 | */ |
| 1431 | u8 channels_num; /* valid when channel_type is 4 */ |
| 1432 | /* valid when channels_num is set */ |
| 1433 | struct mt76_connac_mcu_scan_channel channels[32]; |
| 1434 | __le16 ies_len; |
| 1435 | u8 ies[MT76_CONNAC_SCAN_IE_LEN]; |
| 1436 | /* following fields are valid if version > 0 */ |
| 1437 | u8 ext_channels_num; |
| 1438 | u8 ext_ssids_num; |
| 1439 | __le16 channel_min_dwell_time; |
| 1440 | struct mt76_connac_mcu_scan_channel ext_channels[32]; |
| 1441 | struct mt76_connac_mcu_scan_ssid ext_ssids[6]; |
| 1442 | u8 bssid[ETH_ALEN]; |
| 1443 | u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ |
| 1444 | u8 pad[63]; |
| 1445 | u8 ssid_type_ext; |
| 1446 | } __packed; |
| 1447 | |
| 1448 | #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 |
| 1449 | |
| 1450 | struct mt76_connac_hw_scan_done { |
| 1451 | u8 seq_num; |
| 1452 | u8 sparse_channel_num; |
| 1453 | struct mt76_connac_mcu_scan_channel sparse_channel; |
| 1454 | u8 complete_channel_num; |
| 1455 | u8 current_state; |
| 1456 | u8 version; |
| 1457 | u8 pad; |
| 1458 | __le32 beacon_scan_num; |
| 1459 | u8 pno_enabled; |
| 1460 | u8 pad2[3]; |
| 1461 | u8 sparse_channel_valid_num; |
| 1462 | u8 pad3[3]; |
| 1463 | u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; |
| 1464 | /* idle format for channel_idle_time |
| 1465 | * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) |
| 1466 | * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) |
| 1467 | * 2: dwell time (16us) |
| 1468 | */ |
| 1469 | __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; |
| 1470 | /* beacon and probe response count */ |
| 1471 | u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; |
| 1472 | u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; |
| 1473 | __le32 beacon_2g_num; |
| 1474 | __le32 beacon_5g_num; |
| 1475 | } __packed; |
| 1476 | |
| 1477 | struct mt76_connac_sched_scan_req { |
| 1478 | u8 version; |
| 1479 | u8 seq_num; |
| 1480 | u8 stop_on_match; |
| 1481 | u8 ssids_num; |
| 1482 | u8 match_num; |
| 1483 | u8 pad; |
| 1484 | __le16 ie_len; |
| 1485 | struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; |
| 1486 | struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; |
| 1487 | u8 channel_type; |
| 1488 | u8 channels_num; |
| 1489 | u8 intervals_num; |
| 1490 | u8 scan_func; /* MT7663: BIT(0) eable random mac address */ |
| 1491 | struct mt76_connac_mcu_scan_channel channels[64]; |
| 1492 | __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; |
| 1493 | union { |
| 1494 | struct { |
| 1495 | u8 random_mac[ETH_ALEN]; |
| 1496 | u8 pad2[58]; |
| 1497 | } mt7663; |
| 1498 | struct { |
| 1499 | u8 bss_idx; |
| 1500 | u8 pad1[3]; |
| 1501 | __le32 delay; |
| 1502 | u8 pad2[12]; |
| 1503 | u8 random_mac[ETH_ALEN]; |
| 1504 | u8 pad3[38]; |
| 1505 | } mt7921; |
| 1506 | }; |
| 1507 | } __packed; |
| 1508 | |
| 1509 | struct mt76_connac_sched_scan_done { |
| 1510 | u8 seq_num; |
| 1511 | u8 status; /* 0: ssid found */ |
| 1512 | __le16 pad; |
| 1513 | } __packed; |
| 1514 | |
| 1515 | struct bss_info_uni_bss_color { |
| 1516 | __le16 tag; |
| 1517 | __le16 len; |
| 1518 | u8 enable; |
| 1519 | u8 bss_color; |
| 1520 | u8 rsv[2]; |
| 1521 | } __packed; |
| 1522 | |
| 1523 | struct bss_info_uni_he { |
| 1524 | __le16 tag; |
| 1525 | __le16 len; |
| 1526 | __le16 he_rts_thres; |
| 1527 | u8 he_pe_duration; |
| 1528 | u8 su_disable; |
| 1529 | __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; |
| 1530 | u8 rsv[2]; |
| 1531 | } __packed; |
| 1532 | |
| 1533 | struct mt76_connac_gtk_rekey_tlv { |
| 1534 | __le16 tag; |
| 1535 | __le16 len; |
| 1536 | u8 kek[NL80211_KEK_LEN]; |
| 1537 | u8 kck[NL80211_KCK_LEN]; |
| 1538 | u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; |
| 1539 | u8 rekey_mode; /* 0: rekey offload enable |
| 1540 | * 1: rekey offload disable |
| 1541 | * 2: rekey update |
| 1542 | */ |
| 1543 | u8 keyid; |
| 1544 | u8 option; /* 1: rekey data update without enabling offload */ |
| 1545 | u8 pad[1]; |
| 1546 | __le32 proto; /* WPA-RSN-WAPI-OPSN */ |
| 1547 | __le32 pairwise_cipher; |
| 1548 | __le32 group_cipher; |
| 1549 | __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ |
| 1550 | __le32 mgmt_group_cipher; |
| 1551 | u8 reserverd[4]; |
| 1552 | } __packed; |
| 1553 | |
| 1554 | #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 |
| 1555 | #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 |
| 1556 | |
| 1557 | struct mt76_connac_wow_pattern_tlv { |
| 1558 | __le16 tag; |
| 1559 | __le16 len; |
| 1560 | u8 index; /* pattern index */ |
| 1561 | u8 enable; /* 0: disable |
| 1562 | * 1: enable |
| 1563 | */ |
| 1564 | u8 data_len; /* pattern length */ |
| 1565 | u8 pad; |
| 1566 | u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; |
| 1567 | u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; |
| 1568 | u8 rsv[4]; |
| 1569 | } __packed; |
| 1570 | |
| 1571 | struct mt76_connac_wow_ctrl_tlv { |
| 1572 | __le16 tag; |
| 1573 | __le16 len; |
| 1574 | u8 cmd; /* 0x1: PM_WOWLAN_REQ_START |
| 1575 | * 0x2: PM_WOWLAN_REQ_STOP |
| 1576 | * 0x3: PM_WOWLAN_PARAM_CLEAR |
| 1577 | */ |
| 1578 | u8 trigger; /* 0: NONE |
| 1579 | * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT |
| 1580 | * BIT(1): NL80211_WOWLAN_TRIG_ANY |
| 1581 | * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT |
| 1582 | * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE |
| 1583 | * BIT(4): BEACON_LOST |
| 1584 | * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT |
| 1585 | */ |
| 1586 | u8 wakeup_hif; /* 0x0: HIF_SDIO |
| 1587 | * 0x1: HIF_USB |
| 1588 | * 0x2: HIF_PCIE |
| 1589 | * 0x3: HIF_GPIO |
| 1590 | */ |
| 1591 | u8 pad; |
| 1592 | u8 rsv[4]; |
| 1593 | } __packed; |
| 1594 | |
| 1595 | struct mt76_connac_wow_gpio_param_tlv { |
| 1596 | __le16 tag; |
| 1597 | __le16 len; |
| 1598 | u8 gpio_pin; |
| 1599 | u8 trigger_lvl; |
| 1600 | u8 pad[2]; |
| 1601 | __le32 gpio_interval; |
| 1602 | u8 rsv[4]; |
| 1603 | } __packed; |
| 1604 | |
| 1605 | struct mt76_connac_arpns_tlv { |
| 1606 | __le16 tag; |
| 1607 | __le16 len; |
| 1608 | u8 mode; |
| 1609 | u8 ips_num; |
| 1610 | u8 option; |
| 1611 | u8 pad[1]; |
| 1612 | } __packed; |
| 1613 | |
| 1614 | struct mt76_connac_suspend_tlv { |
| 1615 | __le16 tag; |
| 1616 | __le16 len; |
| 1617 | u8 enable; /* 0: suspend mode disabled |
| 1618 | * 1: suspend mode enabled |
| 1619 | */ |
| 1620 | u8 mdtim; /* LP parameter */ |
| 1621 | u8 wow_suspend; /* 0: update by origin policy |
| 1622 | * 1: update by wow dtim |
| 1623 | */ |
| 1624 | u8 pad[5]; |
| 1625 | } __packed; |
| 1626 | |
| 1627 | enum mt76_sta_info_state { |
| 1628 | MT76_STA_INFO_STATE_NONE, |
| 1629 | MT76_STA_INFO_STATE_AUTH, |
| 1630 | MT76_STA_INFO_STATE_ASSOC |
| 1631 | }; |
| 1632 | |
| 1633 | struct mt76_sta_cmd_info { |
| 1634 | struct ieee80211_sta *sta; |
| 1635 | struct mt76_wcid *wcid; |
| 1636 | |
| 1637 | struct ieee80211_vif *vif; |
| 1638 | |
| 1639 | bool offload_fw; |
| 1640 | bool enable; |
| 1641 | bool newly; |
| 1642 | int cmd; |
| 1643 | u8 rcpi; |
| 1644 | u8 state; |
| 1645 | }; |
| 1646 | |
| 1647 | #define MT_SKU_POWER_LIMIT 161 |
| 1648 | |
| 1649 | struct mt76_connac_sku_tlv { |
| 1650 | u8 channel; |
| 1651 | s8 pwr_limit[MT_SKU_POWER_LIMIT]; |
| 1652 | } __packed; |
| 1653 | |
| 1654 | struct mt76_connac_tx_power_limit_tlv { |
| 1655 | /* DW0 - common info*/ |
| 1656 | u8 ver; |
| 1657 | u8 pad0; |
| 1658 | __le16 len; |
| 1659 | /* DW1 - cmd hint */ |
| 1660 | u8 n_chan; /* # channel */ |
| 1661 | u8 band; /* 2.4GHz - 5GHz - 6GHz */ |
| 1662 | u8 last_msg; |
| 1663 | u8 pad1; |
| 1664 | /* DW3 */ |
| 1665 | u8 alpha2[4]; /* regulatory_request.alpha2 */ |
| 1666 | u8 pad2[32]; |
| 1667 | } __packed; |
| 1668 | |
| 1669 | struct mt76_connac_config { |
| 1670 | __le16 id; |
| 1671 | u8 type; |
| 1672 | u8 resp_type; |
| 1673 | __le16 data_size; |
| 1674 | __le16 resv; |
| 1675 | u8 data[320]; |
| 1676 | } __packed; |
| 1677 | |
| 1678 | static inline enum mcu_cipher_type |
| 1679 | mt76_connac_mcu_get_cipher(int cipher) |
| 1680 | { |
| 1681 | switch (cipher) { |
| 1682 | case WLAN_CIPHER_SUITE_WEP40: |
| 1683 | return MCU_CIPHER_WEP40; |
| 1684 | case WLAN_CIPHER_SUITE_WEP104: |
| 1685 | return MCU_CIPHER_WEP104; |
| 1686 | case WLAN_CIPHER_SUITE_TKIP: |
| 1687 | return MCU_CIPHER_TKIP; |
| 1688 | case WLAN_CIPHER_SUITE_AES_CMAC: |
| 1689 | return MCU_CIPHER_BIP_CMAC_128; |
| 1690 | case WLAN_CIPHER_SUITE_CCMP: |
| 1691 | return MCU_CIPHER_AES_CCMP; |
| 1692 | case WLAN_CIPHER_SUITE_CCMP_256: |
| 1693 | return MCU_CIPHER_CCMP_256; |
| 1694 | case WLAN_CIPHER_SUITE_GCMP: |
| 1695 | return MCU_CIPHER_GCMP; |
| 1696 | case WLAN_CIPHER_SUITE_GCMP_256: |
| 1697 | return MCU_CIPHER_GCMP_256; |
| 1698 | case WLAN_CIPHER_SUITE_SMS4: |
| 1699 | return MCU_CIPHER_WAPI; |
| 1700 | default: |
| 1701 | return MCU_CIPHER_NONE; |
| 1702 | } |
| 1703 | } |
| 1704 | |
| 1705 | static inline u32 |
| 1706 | mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) |
| 1707 | { |
| 1708 | u32 ret = 0; |
| 1709 | |
| 1710 | ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? |
| 1711 | DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; |
| 1712 | if (is_mt7921(dev)) |
| 1713 | ret |= feature_set & FW_FEATURE_ENCRY_MODE ? |
| 1714 | DL_CONFIG_ENCRY_MODE_SEL : 0; |
| 1715 | ret |= FIELD_PREP(DL_MODE_KEY_IDX, |
| 1716 | FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); |
| 1717 | ret |= DL_MODE_NEED_RSP; |
| 1718 | ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; |
| 1719 | |
| 1720 | return ret; |
| 1721 | } |
| 1722 | |
| 1723 | #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) |
| 1724 | #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) |
| 1725 | |
| 1726 | static inline void |
| 1727 | mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, |
| 1728 | u8 *wlan_idx_lo, u8 *wlan_idx_hi) |
| 1729 | { |
| 1730 | *wlan_idx_hi = 0; |
| 1731 | |
| 1732 | if (!is_connac_v1(dev)) { |
| 1733 | *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; |
| 1734 | *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; |
| 1735 | } else { |
| 1736 | *wlan_idx_lo = wcid ? wcid->idx : 0; |
| 1737 | } |
| 1738 | } |
| 1739 | |
| 1740 | struct sk_buff * |
| 1741 | __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, |
| 1742 | struct mt76_wcid *wcid, int len); |
| 1743 | static inline struct sk_buff * |
| 1744 | mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, |
| 1745 | struct mt76_wcid *wcid) |
| 1746 | { |
| 1747 | return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, |
| 1748 | MT76_CONNAC_STA_UPDATE_MAX_SIZE); |
| 1749 | } |
| 1750 | |
| 1751 | struct wtbl_req_hdr * |
| 1752 | mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, |
| 1753 | int cmd, void *sta_wtbl, struct sk_buff **skb); |
| 1754 | struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, |
| 1755 | int len, void *sta_ntlv, |
| 1756 | void *sta_wtbl); |
| 1757 | static inline struct tlv * |
| 1758 | mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) |
| 1759 | { |
| 1760 | return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); |
| 1761 | } |
| 1762 | |
| 1763 | int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); |
| 1764 | int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); |
| 1765 | void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, |
| 1766 | struct ieee80211_vif *vif, |
| 1767 | struct ieee80211_sta *sta, bool enable, |
| 1768 | bool newly); |
| 1769 | void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, |
| 1770 | struct ieee80211_vif *vif, |
| 1771 | struct ieee80211_sta *sta, void *sta_wtbl, |
| 1772 | void *wtbl_tlv); |
| 1773 | void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, |
| 1774 | struct ieee80211_vif *vif, |
| 1775 | struct mt76_wcid *wcid, |
| 1776 | void *sta_wtbl, void *wtbl_tlv); |
| 1777 | int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, |
| 1778 | struct ieee80211_vif *vif, |
| 1779 | struct mt76_wcid *wcid, int cmd); |
| 1780 | int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, |
| 1781 | struct ieee80211_vif *vif, |
| 1782 | struct ieee80211_sta *sta); |
| 1783 | void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, |
| 1784 | struct ieee80211_sta *sta, |
| 1785 | struct ieee80211_vif *vif, |
| 1786 | u8 rcpi, u8 state); |
| 1787 | void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, |
| 1788 | struct ieee80211_sta *sta, void *sta_wtbl, |
| 1789 | void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); |
| 1790 | void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, |
| 1791 | struct ieee80211_ampdu_params *params, |
| 1792 | bool enable, bool tx, void *sta_wtbl, |
| 1793 | void *wtbl_tlv); |
| 1794 | void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, |
| 1795 | struct ieee80211_ampdu_params *params, |
| 1796 | bool enable, bool tx); |
| 1797 | int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, |
| 1798 | struct ieee80211_vif *vif, |
| 1799 | struct mt76_wcid *wcid, |
| 1800 | bool enable); |
| 1801 | int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, |
| 1802 | struct ieee80211_ampdu_params *params, |
| 1803 | int cmd, bool enable, bool tx); |
| 1804 | int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, |
| 1805 | struct ieee80211_vif *vif, |
| 1806 | struct mt76_wcid *wcid, |
| 1807 | bool enable); |
| 1808 | int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, |
| 1809 | struct mt76_sta_cmd_info *info); |
| 1810 | void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, |
| 1811 | struct ieee80211_vif *vif); |
| 1812 | int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); |
| 1813 | int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, |
| 1814 | bool hdr_trans); |
| 1815 | int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, |
| 1816 | u32 mode); |
| 1817 | int mt76_connac_mcu_start_patch(struct mt76_dev *dev); |
| 1818 | int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); |
| 1819 | int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); |
| 1820 | int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); |
| 1821 | |
| 1822 | int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, |
| 1823 | struct ieee80211_scan_request *scan_req); |
| 1824 | int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, |
| 1825 | struct ieee80211_vif *vif); |
| 1826 | int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, |
| 1827 | struct ieee80211_vif *vif, |
| 1828 | struct cfg80211_sched_scan_request *sreq); |
| 1829 | int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, |
| 1830 | struct ieee80211_vif *vif, |
| 1831 | bool enable); |
| 1832 | int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, |
| 1833 | struct mt76_vif *vif, |
| 1834 | struct ieee80211_bss_conf *info); |
| 1835 | int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, |
| 1836 | struct ieee80211_vif *vif, |
| 1837 | struct cfg80211_gtk_rekey_data *key); |
| 1838 | int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); |
| 1839 | void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, |
| 1840 | struct ieee80211_vif *vif); |
| 1841 | int mt76_connac_sta_state_dp(struct mt76_dev *dev, |
| 1842 | enum ieee80211_sta_state old_state, |
| 1843 | enum ieee80211_sta_state new_state); |
| 1844 | int mt76_connac_mcu_chip_config(struct mt76_dev *dev); |
| 1845 | int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); |
| 1846 | void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, |
| 1847 | struct mt76_connac_coredump *coredump); |
| 1848 | int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); |
| 1849 | int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, |
| 1850 | struct ieee80211_vif *vif); |
| 1851 | u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); |
| 1852 | void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); |
| 1853 | |
| 1854 | const struct ieee80211_sta_he_cap * |
| 1855 | mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); |
| 1856 | u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, |
| 1857 | enum nl80211_band band, struct ieee80211_sta *sta); |
| 1858 | |
| 1859 | int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 1860 | struct mt76_connac_sta_key_conf *sta_key_conf, |
| 1861 | struct ieee80211_key_conf *key, int mcu_cmd, |
| 1862 | struct mt76_wcid *wcid, enum set_key_cmd cmd); |
| 1863 | |
| 1864 | void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); |
| 1865 | void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, |
| 1866 | struct ieee80211_vif *vif); |
| 1867 | int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, |
| 1868 | struct ieee80211_vif *vif, |
| 1869 | struct ieee80211_sta *sta, |
| 1870 | struct mt76_phy *phy, u16 wlan_idx, |
| 1871 | bool enable); |
| 1872 | void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, |
| 1873 | struct ieee80211_sta *sta); |
| 1874 | void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, |
| 1875 | struct ieee80211_sta *sta, |
| 1876 | void *sta_wtbl, void *wtbl_tlv); |
| 1877 | int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); |
| 1878 | int mt76_connac_mcu_restart(struct mt76_dev *dev); |
| 1879 | int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, |
| 1880 | u8 rx_sel, u8 val); |
| 1881 | int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, |
| 1882 | const char *fw_wa); |
| 1883 | int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); |
| 1884 | int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, |
| 1885 | int cmd, int *wait_seq); |
| 1886 | #endif /* __MT76_CONNAC_MCU_H */ |