developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #ifndef __MT7915_REGS_H |
| 5 | #define __MT7915_REGS_H |
| 6 | |
| 7 | struct __map { |
| 8 | u32 phys; |
| 9 | u32 maps; |
| 10 | u32 size; |
| 11 | }; |
| 12 | |
| 13 | /* used to differentiate between generations */ |
| 14 | struct mt7915_reg_desc { |
| 15 | const u32 *reg_rev; |
| 16 | const u32 *offs_rev; |
| 17 | const struct __map *map; |
| 18 | u32 map_size; |
| 19 | }; |
| 20 | |
| 21 | enum reg_rev { |
| 22 | INT_SOURCE_CSR, |
| 23 | INT_MASK_CSR, |
| 24 | INT1_SOURCE_CSR, |
| 25 | INT1_MASK_CSR, |
| 26 | INT_MCU_CMD_SOURCE, |
| 27 | INT_MCU_CMD_EVENT, |
| 28 | WFDMA0_ADDR, |
| 29 | WFDMA0_PCIE1_ADDR, |
| 30 | WFDMA_EXT_CSR_ADDR, |
| 31 | CBTOP1_PHY_END, |
| 32 | INFRA_MCU_ADDR_END, |
| 33 | __MT_REG_MAX, |
| 34 | }; |
| 35 | |
| 36 | enum offs_rev { |
| 37 | TMAC_CDTR, |
| 38 | TMAC_ODTR, |
| 39 | TMAC_ATCR, |
| 40 | TMAC_TRCR0, |
| 41 | TMAC_ICR0, |
| 42 | TMAC_ICR1, |
| 43 | TMAC_CTCR0, |
| 44 | TMAC_TFCR0, |
| 45 | MDP_BNRCFR0, |
| 46 | MDP_BNRCFR1, |
| 47 | ARB_DRNGR0, |
| 48 | ARB_SCR, |
| 49 | RMAC_MIB_AIRTIME14, |
| 50 | AGG_AWSCR0, |
| 51 | AGG_PCR0, |
| 52 | AGG_ACR0, |
| 53 | AGG_MRCR, |
| 54 | AGG_ATCR1, |
| 55 | AGG_ATCR3, |
| 56 | LPON_UTTR0, |
| 57 | LPON_UTTR1, |
| 58 | LPON_FRCR, |
| 59 | MIB_SDR3, |
| 60 | MIB_SDR4, |
| 61 | MIB_SDR5, |
| 62 | MIB_SDR7, |
| 63 | MIB_SDR8, |
| 64 | MIB_SDR9, |
| 65 | MIB_SDR10, |
| 66 | MIB_SDR11, |
| 67 | MIB_SDR12, |
| 68 | MIB_SDR13, |
| 69 | MIB_SDR14, |
| 70 | MIB_SDR15, |
| 71 | MIB_SDR16, |
| 72 | MIB_SDR17, |
| 73 | MIB_SDR18, |
| 74 | MIB_SDR19, |
| 75 | MIB_SDR20, |
| 76 | MIB_SDR21, |
| 77 | MIB_SDR22, |
| 78 | MIB_SDR23, |
| 79 | MIB_SDR24, |
| 80 | MIB_SDR25, |
| 81 | MIB_SDR27, |
| 82 | MIB_SDR28, |
| 83 | MIB_SDR29, |
| 84 | MIB_SDRVEC, |
| 85 | MIB_SDR31, |
| 86 | MIB_SDR32, |
| 87 | MIB_SDRMUBF, |
| 88 | MIB_DR8, |
| 89 | MIB_DR9, |
| 90 | MIB_DR11, |
| 91 | MIB_MB_SDR0, |
| 92 | MIB_MB_SDR1, |
| 93 | TX_AGG_CNT, |
| 94 | TX_AGG_CNT2, |
| 95 | MIB_ARNG, |
| 96 | WTBLON_TOP_WDUCR, |
| 97 | WTBL_UPDATE, |
| 98 | PLE_FL_Q_EMPTY, |
| 99 | PLE_FL_Q_CTRL, |
| 100 | PLE_AC_QEMPTY, |
| 101 | PLE_FREEPG_CNT, |
| 102 | PLE_FREEPG_HEAD_TAIL, |
| 103 | PLE_PG_HIF_GROUP, |
| 104 | PLE_HIF_PG_INFO, |
| 105 | AC_OFFSET, |
| 106 | ETBF_PAR_RPT0, |
| 107 | __MT_OFFS_MAX, |
| 108 | }; |
| 109 | |
| 110 | #define __REG(id) (dev->reg.reg_rev[(id)]) |
| 111 | #define __OFFS(id) (dev->reg.offs_rev[(id)]) |
| 112 | |
| 113 | /* MCU WFDMA0 */ |
| 114 | #define MT_MCU_WFDMA0_BASE 0x2000 |
| 115 | #define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs)) |
| 116 | |
| 117 | #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120) |
| 118 | |
| 119 | /* MCU WFDMA1 */ |
| 120 | #define MT_MCU_WFDMA1_BASE 0x3000 |
| 121 | #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) |
| 122 | |
| 123 | #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT) |
| 124 | #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) |
| 125 | #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) |
| 126 | #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) |
| 127 | #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) |
| 128 | |
| 129 | /* PLE */ |
| 130 | #define MT_PLE_BASE 0x820c0000 |
| 131 | #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) |
| 132 | |
| 133 | #define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY)) |
| 134 | #define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL)) |
| 135 | #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8) |
| 136 | #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc) |
| 137 | |
| 138 | #define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT)) |
| 139 | #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL)) |
| 140 | #define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP)) |
| 141 | #define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO)) |
| 142 | |
| 143 | #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \ |
| 144 | __OFFS(AC_OFFSET) * \ |
| 145 | (ac) + ((n) << 2)) |
| 146 | #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) |
| 147 | |
| 148 | #define MT_PSE_BASE 0x820c8000 |
| 149 | #define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) |
| 150 | |
| 151 | /* WF MDP TOP */ |
| 152 | #define MT_MDP_BASE 0x820cd000 |
| 153 | #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) |
| 154 | |
| 155 | #define MT_MDP_DCR0 MT_MDP(0x000) |
| 156 | #define MT_MDP_DCR0_DAMSDU_EN BIT(15) |
| 157 | |
| 158 | #define MT_MDP_DCR1 MT_MDP(0x004) |
| 159 | #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) |
| 160 | |
| 161 | #define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \ |
| 162 | ((_band) << 8)) |
| 163 | #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) |
| 164 | #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) |
| 165 | #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) |
| 166 | |
| 167 | #define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \ |
| 168 | ((_band) << 8)) |
| 169 | #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) |
| 170 | #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) |
| 171 | #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) |
| 172 | #define MT_MDP_TO_HIF 0 |
| 173 | #define MT_MDP_TO_WM 1 |
| 174 | |
| 175 | /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ |
| 176 | #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) |
| 177 | #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) |
| 178 | |
| 179 | #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) |
| 180 | #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) |
| 181 | #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) |
| 182 | |
| 183 | #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR)) |
| 184 | #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR)) |
| 185 | #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) |
| 186 | #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) |
| 187 | |
| 188 | #define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR)) |
| 189 | #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0) |
| 190 | |
| 191 | #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0)) |
| 192 | #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0) |
| 193 | #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16) |
| 194 | |
| 195 | #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0)) |
| 196 | #define MT_IFS_EIFS_OFDM GENMASK(8, 0) |
| 197 | #define MT_IFS_RIFS GENMASK(14, 10) |
| 198 | #define MT_IFS_SIFS GENMASK(22, 16) |
| 199 | #define MT_IFS_SLOT GENMASK(30, 24) |
| 200 | |
| 201 | #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1)) |
| 202 | #define MT_IFS_EIFS_CCK GENMASK(8, 0) |
| 203 | |
| 204 | #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0)) |
| 205 | #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) |
| 206 | #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) |
| 207 | #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) |
| 208 | |
| 209 | #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0)) |
| 210 | |
| 211 | /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */ |
| 212 | #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) |
| 213 | #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) |
| 214 | |
| 215 | #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) |
| 216 | #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) |
| 217 | #define MT_DMA_DCR0_RXD_G5_EN BIT(23) |
| 218 | |
| 219 | /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */ |
| 220 | #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) |
| 221 | #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) |
| 222 | |
| 223 | #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040) |
| 224 | #define MT_ETBF_TX_FB_CPL GENMASK(31, 16) |
| 225 | #define MT_ETBF_TX_FB_TRI GENMASK(15, 0) |
| 226 | |
| 227 | #define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0)) |
| 228 | #define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6) |
| 229 | #define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3) |
| 230 | #define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0) |
| 231 | |
| 232 | #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0) |
| 233 | #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) |
| 234 | #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) |
| 235 | |
| 236 | #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8) |
| 237 | #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) |
| 238 | #define MT_ETBF_RX_FB_HE GENMASK(23, 16) |
| 239 | #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) |
| 240 | #define MT_ETBF_RX_FB_HT GENMASK(7, 0) |
| 241 | |
| 242 | /* LPON: band 0(0x820eb000), band 1(0x820fb000) */ |
| 243 | #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) |
| 244 | #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) |
| 245 | |
| 246 | #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0)) |
| 247 | #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1)) |
| 248 | #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR)) |
| 249 | |
| 250 | #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \ |
| 251 | (((n) * 4) << 1)) |
| 252 | #define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \ |
| 253 | (((n) * 4) << 4)) |
| 254 | #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) |
| 255 | #define MT_LPON_TCR_SW_WRITE BIT(0) |
| 256 | #define MT_LPON_TCR_SW_ADJUST BIT(1) |
| 257 | #define MT_LPON_TCR_SW_READ GENMASK(1, 0) |
| 258 | |
| 259 | /* MIB: band 0(0x820ed000), band 1(0x820fd000) */ |
| 260 | /* These counters are (mostly?) clear-on-read. So, some should not |
| 261 | * be read at all in case firmware is already reading them. These |
| 262 | * are commented with 'DNR' below. The DNR stats will be read by querying |
| 263 | * the firmware API for the appropriate message. For counters the driver |
| 264 | * does read, the driver should accumulate the counters. |
| 265 | */ |
| 266 | #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) |
| 267 | #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) |
| 268 | |
| 269 | #define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010) |
| 270 | #define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0) |
| 271 | |
| 272 | #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3)) |
| 273 | #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) |
| 274 | #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16) |
| 275 | |
| 276 | #define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4)) |
| 277 | #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0) |
| 278 | |
| 279 | /* rx mpdu counter, full 32 bits */ |
| 280 | #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5)) |
| 281 | |
| 282 | #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) |
| 283 | #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) |
| 284 | |
| 285 | #define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7)) |
| 286 | #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0) |
| 287 | |
| 288 | #define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8)) |
| 289 | #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0) |
| 290 | |
| 291 | /* aka CCA_NAV_TX_TIME */ |
| 292 | #define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9)) |
| 293 | #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0) |
| 294 | |
| 295 | #define MT_MIB_SDR10_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10)) |
| 296 | #define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0) |
| 297 | #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0) |
| 298 | |
| 299 | #define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11)) |
| 300 | #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0) |
| 301 | |
| 302 | /* tx ampdu cnt, full 32 bits */ |
| 303 | #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12)) |
| 304 | |
| 305 | #define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13)) |
| 306 | #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0) |
| 307 | |
| 308 | /* counts all mpdus in ampdu, regardless of success */ |
| 309 | #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14)) |
| 310 | #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0) |
| 311 | #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0) |
| 312 | |
| 313 | /* counts all successfully tx'd mpdus in ampdu */ |
| 314 | #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15)) |
| 315 | #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0) |
| 316 | #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0) |
| 317 | |
| 318 | /* in units of 'us' */ |
| 319 | #define MT_MIB_SDR16_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16)) |
| 320 | #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) |
| 321 | |
| 322 | #define MT_MIB_SDR17_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17)) |
| 323 | #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) |
| 324 | |
| 325 | #define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18)) |
| 326 | #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0) |
| 327 | |
| 328 | /* units are us */ |
| 329 | #define MT_MIB_SDR19_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19)) |
| 330 | #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0) |
| 331 | |
| 332 | #define MT_MIB_SDR20_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20)) |
| 333 | #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0) |
| 334 | |
| 335 | #define MT_MIB_SDR21_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21)) |
| 336 | #define MT_MIB_SDR20_GREEN_MDRDY_TIME_MASK GENMASK(23, 0) |
| 337 | |
| 338 | /* rx ampdu count, 32-bit */ |
| 339 | #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22)) |
| 340 | |
| 341 | /* rx ampdu bytes count, 32-bit */ |
| 342 | #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23)) |
| 343 | |
| 344 | /* rx ampdu valid subframe count */ |
| 345 | #define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24)) |
| 346 | #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0) |
| 347 | #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0) |
| 348 | |
| 349 | /* rx ampdu valid subframe bytes count, 32bits */ |
| 350 | #define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25)) |
| 351 | |
| 352 | /* remaining windows protected stats */ |
| 353 | #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27)) |
| 354 | #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0) |
| 355 | |
| 356 | #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28)) |
| 357 | #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0) |
| 358 | |
| 359 | #define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29)) |
| 360 | #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0) |
| 361 | #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0) |
| 362 | |
| 363 | #define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC)) |
| 364 | #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0) |
| 365 | #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16) |
| 366 | |
| 367 | /* rx blockack count, 32 bits */ |
| 368 | #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31)) |
| 369 | |
| 370 | #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32)) |
| 371 | #define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0) |
| 372 | #define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16) |
| 373 | |
| 374 | #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088) |
| 375 | #define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0) |
| 376 | |
| 377 | #define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF)) |
| 378 | #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) |
| 379 | |
| 380 | /* 36, 37 both DNR */ |
| 381 | |
| 382 | #define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8)) |
| 383 | #define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9)) |
| 384 | #define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11)) |
| 385 | |
| 386 | #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n)) |
| 387 | #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) |
| 388 | #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) |
| 389 | |
| 390 | #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n)) |
| 391 | #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) |
| 392 | #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) |
| 393 | |
| 394 | #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n)) |
| 395 | #define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n)) |
| 396 | |
| 397 | #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \ |
| 398 | ((n) << 2)) |
| 399 | #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \ |
| 400 | ((n) << 2)) |
| 401 | #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \ |
| 402 | ((n) << 2)) |
| 403 | #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) |
| 404 | |
| 405 | #define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0) |
| 406 | #define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0) |
| 407 | #define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16) |
| 408 | |
| 409 | #define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4) |
| 410 | #define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0) |
| 411 | |
| 412 | #define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8) |
| 413 | #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0) |
| 414 | |
| 415 | #define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc) |
| 416 | #define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0) |
| 417 | |
| 418 | /* WTBLON TOP */ |
| 419 | #define MT_WTBLON_TOP_BASE 0x820d4000 |
| 420 | #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) |
| 421 | #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR)) |
| 422 | #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) |
| 423 | |
| 424 | #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) |
| 425 | #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) |
| 426 | #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) |
| 427 | #define MT_WTBL_UPDATE_BUSY BIT(31) |
| 428 | |
| 429 | /* WTBL */ |
| 430 | #define MT_WTBL_BASE 0x820d8000 |
| 431 | #define MT_WTBL_LMAC_ID GENMASK(14, 8) |
| 432 | #define MT_WTBL_LMAC_DW GENMASK(7, 2) |
| 433 | #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ |
| 434 | FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ |
| 435 | FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) |
| 436 | |
| 437 | /* AGG: band 0(0x820e2000), band 1(0x820f2000) */ |
| 438 | #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) |
| 439 | #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) |
| 440 | |
| 441 | #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \ |
| 442 | (_n) * 4)) |
| 443 | #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \ |
| 444 | (_n) * 4)) |
| 445 | #define MT_AGG_PCR0_MM_PROT BIT(0) |
| 446 | #define MT_AGG_PCR0_GF_PROT BIT(1) |
| 447 | #define MT_AGG_PCR0_BW20_PROT BIT(2) |
| 448 | #define MT_AGG_PCR0_BW40_PROT BIT(4) |
| 449 | #define MT_AGG_PCR0_BW80_PROT BIT(6) |
| 450 | #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) |
| 451 | #define MT_AGG_PCR0_VHT_PROT BIT(13) |
| 452 | #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) |
| 453 | |
| 454 | #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) |
| 455 | #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) |
| 456 | |
| 457 | #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0)) |
| 458 | #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) |
| 459 | #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) |
| 460 | |
| 461 | #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR)) |
| 462 | #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) |
| 463 | #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) |
| 464 | #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) |
| 465 | #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) |
| 466 | |
| 467 | #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1)) |
| 468 | #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3)) |
| 469 | |
| 470 | /* ARB: band 0(0x820e3000), band 1(0x820f3000) */ |
| 471 | #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) |
| 472 | #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) |
| 473 | |
| 474 | #define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR)) |
| 475 | #define MT_ARB_SCR_TX_DISABLE BIT(8) |
| 476 | #define MT_ARB_SCR_RX_DISABLE BIT(9) |
| 477 | |
| 478 | #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \ |
| 479 | (_n) * 4)) |
| 480 | |
| 481 | /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */ |
| 482 | #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) |
| 483 | #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) |
| 484 | |
| 485 | #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) |
| 486 | #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) |
| 487 | #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) |
| 488 | #define MT_WF_RFCR_DROP_VERSION BIT(3) |
| 489 | #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) |
| 490 | #define MT_WF_RFCR_DROP_MCAST BIT(5) |
| 491 | #define MT_WF_RFCR_DROP_BCAST BIT(6) |
| 492 | #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) |
| 493 | #define MT_WF_RFCR_DROP_A3_MAC BIT(8) |
| 494 | #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) |
| 495 | #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) |
| 496 | #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) |
| 497 | #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) |
| 498 | #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) |
| 499 | #define MT_WF_RFCR_DROP_CTS BIT(14) |
| 500 | #define MT_WF_RFCR_DROP_RTS BIT(15) |
| 501 | #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) |
| 502 | #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) |
| 503 | #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) |
| 504 | #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) |
| 505 | #define MT_WF_RFCR_DROP_NDPA BIT(20) |
| 506 | #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) |
| 507 | |
| 508 | #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) |
| 509 | #define MT_WF_RFCR1_DROP_ACK BIT(4) |
| 510 | #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) |
| 511 | #define MT_WF_RFCR1_DROP_BA BIT(6) |
| 512 | #define MT_WF_RFCR1_DROP_CFEND BIT(7) |
| 513 | #define MT_WF_RFCR1_DROP_CFACK BIT(8) |
| 514 | |
| 515 | #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) |
| 516 | #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) |
| 517 | |
| 518 | /* WFDMA0 */ |
| 519 | #define MT_WFDMA0_BASE __REG(WFDMA0_ADDR) |
| 520 | #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) |
| 521 | |
| 522 | #define MT_WFDMA0_RST MT_WFDMA0(0x100) |
| 523 | #define MT_WFDMA0_RST_LOGIC_RST BIT(4) |
| 524 | #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) |
| 525 | |
| 526 | #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) |
| 527 | #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) |
| 528 | #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) |
| 529 | #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) |
| 530 | |
| 531 | #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) |
| 532 | #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) |
| 533 | #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) |
| 534 | #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) |
| 535 | #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 536 | #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) |
| 537 | |
| 538 | #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) |
| 539 | #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) |
| 540 | #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) |
| 541 | #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) |
| 542 | |
| 543 | /* WFDMA1 */ |
| 544 | #define MT_WFDMA1_BASE 0xd5000 |
| 545 | #define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs)) |
| 546 | |
| 547 | #define MT_WFDMA1_RST MT_WFDMA1(0x100) |
| 548 | #define MT_WFDMA1_RST_LOGIC_RST BIT(4) |
| 549 | #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5) |
| 550 | |
| 551 | #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c) |
| 552 | #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0) |
| 553 | #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1) |
| 554 | #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2) |
| 555 | |
| 556 | #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208) |
| 557 | #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0) |
| 558 | #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2) |
| 559 | #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28) |
| 560 | #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 561 | #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) |
| 562 | |
| 563 | #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c) |
| 564 | #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0) |
| 565 | |
| 566 | /* WFDMA CSR */ |
| 567 | #define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR) |
| 568 | #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) |
| 569 | |
| 570 | #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) |
| 571 | #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) |
| 572 | |
| 573 | #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) |
| 574 | #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) |
| 575 | |
| 576 | #define MT_PCIE_RECOG_ID 0xd7090 |
| 577 | #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) |
| 578 | #define MT_PCIE_RECOG_ID_SEM BIT(31) |
| 579 | |
| 580 | /* WFDMA0 PCIE1 */ |
| 581 | #define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR) |
| 582 | #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) |
| 583 | |
| 584 | #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) |
| 585 | #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) |
| 586 | #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) |
| 587 | #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) |
| 588 | |
| 589 | /* WFDMA1 PCIE1 */ |
| 590 | #define MT_WFDMA1_PCIE1_BASE 0xd9000 |
| 591 | #define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs)) |
| 592 | |
| 593 | #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c) |
| 594 | #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) |
| 595 | #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) |
| 596 | #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2) |
| 597 | |
| 598 | /* WFDMA COMMON */ |
| 599 | #define __RXQ(q) ((q) + __MT_MCUQ_MAX) |
| 600 | #define __TXQ(q) (__RXQ(q) + __MT_RXQ_MAX) |
| 601 | |
| 602 | #define MT_Q_ID(q) (dev->q_id[(q)]) |
| 603 | #define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \ |
| 604 | MT_WFDMA1_BASE : MT_WFDMA0_BASE) |
| 605 | |
| 606 | #define MT_MCUQ_ID(q) MT_Q_ID(q) |
| 607 | #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) |
| 608 | #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) |
| 609 | |
| 610 | #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) |
| 611 | #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) |
| 612 | #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) |
| 613 | |
| 614 | #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ |
| 615 | MT_MCUQ_ID(q)* 0x4) |
| 616 | #define MT_RXQ_EXT_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ |
| 617 | MT_RXQ_ID(q)* 0x4) |
| 618 | #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ |
| 619 | MT_TXQ_ID(q)* 0x4) |
| 620 | |
| 621 | #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) |
| 622 | #define MT_INT_MASK_CSR __REG(INT_MASK_CSR) |
| 623 | |
| 624 | #define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR) |
| 625 | #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR) |
| 626 | |
| 627 | #define MT_INT_RX_DONE_BAND0 BIT(16) |
| 628 | #define MT_INT_RX_DONE_BAND1 BIT(17) |
| 629 | #define MT_INT_RX_DONE_WM BIT(0) |
| 630 | #define MT_INT_RX_DONE_WA BIT(1) |
| 631 | #define MT_INT_RX_DONE_WA_MAIN BIT(1) |
| 632 | #define MT_INT_RX_DONE_WA_EXT BIT(2) |
| 633 | #define MT_INT_MCU_CMD BIT(29) |
| 634 | #define MT_INT_RX_DONE_BAND0_MT7916 BIT(22) |
| 635 | #define MT_INT_RX_DONE_BAND1_MT7916 BIT(23) |
| 636 | #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2) |
| 637 | #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3) |
| 638 | |
| 639 | #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) |
| 640 | #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) |
| 641 | |
| 642 | #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ |
| 643 | MT_INT_RX(MT_RXQ_MCU_WA)) |
| 644 | |
| 645 | #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ |
| 646 | MT_INT_RX(MT_RXQ_MAIN_WA)) |
| 647 | |
| 648 | #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_EXT) | \ |
| 649 | MT_INT_RX(MT_RXQ_EXT_WA) | \ |
| 650 | MT_INT_RX(MT_RXQ_MAIN_WA)) |
| 651 | |
| 652 | #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ |
| 653 | MT_INT_BAND0_RX_DONE | \ |
| 654 | MT_INT_BAND1_RX_DONE) |
| 655 | |
| 656 | #define MT_INT_TX_DONE_FWDL BIT(26) |
| 657 | #define MT_INT_TX_DONE_MCU_WM BIT(27) |
| 658 | #define MT_INT_TX_DONE_MCU_WA BIT(15) |
| 659 | #define MT_INT_TX_DONE_BAND0 BIT(30) |
| 660 | #define MT_INT_TX_DONE_BAND1 BIT(31) |
| 661 | #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25) |
| 662 | |
| 663 | #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ |
| 664 | MT_INT_TX_MCU(MT_MCUQ_WM) | \ |
| 665 | MT_INT_TX_MCU(MT_MCUQ_FWDL)) |
| 666 | |
| 667 | #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE) |
| 668 | #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) |
| 669 | #define MT_MCU_CMD_STOP_DMA BIT(2) |
| 670 | #define MT_MCU_CMD_RESET_DONE BIT(3) |
| 671 | #define MT_MCU_CMD_RECOVERY_DONE BIT(4) |
| 672 | #define MT_MCU_CMD_NORMAL_STATE BIT(5) |
| 673 | #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) |
| 674 | |
| 675 | /* TOP RGU */ |
| 676 | #define MT_TOP_RGU_BASE 0x18000000 |
| 677 | #define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0)) |
| 678 | #define MT_TOP_PWR_KEY (0x5746 << 16) |
| 679 | #define MT_TOP_PWR_SW_RST BIT(0) |
| 680 | #define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2) |
| 681 | #define MT_TOP_PWR_HW_CTRL BIT(4) |
| 682 | #define MT_TOP_PWR_PWR_ON BIT(7) |
| 683 | |
| 684 | #define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050) |
| 685 | #define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054) |
| 686 | #define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010) |
| 687 | #define MT_TOP_PWR_EN_MASK BIT(7) |
| 688 | #define MT_TOP_PWR_ACK_MASK BIT(6) |
| 689 | #define MT_TOP_PWR_KEY_MASK GENMASK(31, 16) |
| 690 | |
| 691 | #define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120) |
| 692 | #define MT7986_TOP_WM_RESET_MASK BIT(0) |
| 693 | |
| 694 | /* l1/l2 remap */ |
| 695 | #define MT_HIF_REMAP_L1 0xf11ac |
| 696 | #define MT_HIF_REMAP_L1_MT7916 0xfe260 |
| 697 | #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) |
| 698 | #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) |
| 699 | #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) |
| 700 | #define MT_HIF_REMAP_BASE_L1 0xe0000 |
| 701 | |
| 702 | #define MT_HIF_REMAP_L2 0xf11b0 |
| 703 | #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) |
| 704 | #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) |
| 705 | #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) |
| 706 | #define MT_HIF_REMAP_L2_MT7916 0x1b8 |
| 707 | #define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16) |
| 708 | #define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0) |
| 709 | #define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16) |
| 710 | #define MT_HIF_REMAP_BASE_L2_MT7916 0x40000 |
| 711 | |
| 712 | #define MT_INFRA_BASE 0x18000000 |
| 713 | #define MT_WFSYS0_PHY_START 0x18400000 |
| 714 | #define MT_WFSYS1_PHY_START 0x18800000 |
| 715 | #define MT_WFSYS1_PHY_END 0x18bfffff |
| 716 | #define MT_CBTOP1_PHY_START 0x70000000 |
| 717 | #define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END) |
| 718 | #define MT_CBTOP2_PHY_START 0xf0000000 |
| 719 | #define MT_CBTOP2_PHY_END 0xffffffff |
| 720 | #define MT_INFRA_MCU_START 0x7c000000 |
| 721 | #define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END) |
| 722 | #define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE) |
| 723 | |
| 724 | /* CONN INFRA CFG */ |
| 725 | #define MT_CONN_INFRA_BASE 0x18001000 |
| 726 | #define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs)) |
| 727 | |
| 728 | #define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020) |
| 729 | |
| 730 | #define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030) |
| 731 | #define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0) |
| 732 | #define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2) |
| 733 | |
| 734 | #define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380) |
| 735 | |
| 736 | #define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300) |
| 737 | #define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7) |
| 738 | #define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0) |
| 739 | |
| 740 | #define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200) |
| 741 | #define MT_CONN_INFRA_HW_CTRL_MASK BIT(0) |
| 742 | |
| 743 | #define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540) |
| 744 | #define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0) |
| 745 | |
| 746 | #define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544) |
| 747 | #define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31)) |
| 748 | #define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31)) |
| 749 | |
| 750 | #define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414) |
| 751 | #define MT_CONN_INFRA_EMI_REQ_MASK BIT(0) |
| 752 | #define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5) |
| 753 | |
| 754 | /* AFE */ |
| 755 | #define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19)) |
| 756 | #define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs)) |
| 757 | |
| 758 | #define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00) |
| 759 | #define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04) |
| 760 | #define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08) |
| 761 | #define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c) |
| 762 | |
| 763 | #define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4) |
| 764 | #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0)) |
| 765 | #define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \ |
| 766 | FIELD_PREP(GENMASK(14, 0), 0x7e4)) |
| 767 | #define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6) |
| 768 | #define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0) |
| 769 | #define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2) |
| 770 | #define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16) |
| 771 | #define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \ |
| 772 | MT_AFE_WPLL_CFG_MASK | \ |
| 773 | MT_AFE_MCU_WPLL_CFG_MASK | \ |
| 774 | MT_AFE_MCU_BPLL_CFG_MASK) |
| 775 | #define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \ |
| 776 | FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \ |
| 777 | FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \ |
| 778 | FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2)) |
| 779 | |
| 780 | #define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15) |
| 781 | #define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9) |
| 782 | |
| 783 | #define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0) |
| 784 | #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21) |
| 785 | #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20) |
| 786 | #define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \ |
| 787 | MT_AFE_RG_WBG_EN_WPLL_UP_MASK) |
| 788 | #define MT_AFE_RG_WBG_EN_TXCAL_MASK GENMASK(21, 17) |
| 789 | |
| 790 | #define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19)) |
| 791 | #define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs)) |
| 792 | |
| 793 | #define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120) |
| 794 | |
| 795 | /* ADIE */ |
| 796 | #define MT_ADIE_CHIP_ID 0x02c |
| 797 | #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) |
| 798 | #define MT_ADIE_IDX0 GENMASK(15, 0) |
| 799 | #define MT_ADIE_IDX1 GENMASK(31, 16) |
| 800 | |
| 801 | #define MT_ADIE_RG_TOP_THADC_BG 0x034 |
| 802 | #define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12) |
| 803 | #define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3) |
| 804 | |
| 805 | #define MT_ADIE_RG_TOP_THADC 0x038 |
| 806 | #define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23) |
| 807 | #define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0) |
| 808 | #define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26) |
| 809 | #define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5) |
| 810 | |
| 811 | #define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070 |
| 812 | #define MT_ADIE_EFUSE_RDATA0 0x130 |
| 813 | |
| 814 | #define MT_ADIE_EFUSE2_CTRL 0x148 |
| 815 | #define MT_ADIE_EFUSE_CTRL_MASK BIT(1) |
| 816 | |
| 817 | #define MT_ADIE_EFUSE_CFG 0x144 |
| 818 | #define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6) |
| 819 | #define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16) |
| 820 | #define MT_ADIE_EFUSE_VALID_MASK BIT(29) |
| 821 | #define MT_ADIE_EFUSE_KICK_MASK BIT(30) |
| 822 | |
| 823 | #define MT_ADIE_THADC_ANALOG 0x3a6 |
| 824 | |
| 825 | #define MT_ADIE_THADC_SLOP 0x3a7 |
| 826 | #define MT_ADIE_ANA_EN_MASK BIT(7) |
| 827 | |
| 828 | #define MT_ADIE_7975_XTAL_CAL 0x3a1 |
| 829 | #define MT_ADIE_TRIM_MASK GENMASK(6, 0) |
| 830 | #define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0) |
| 831 | #define MT_ADIE_XO_TRIM_EN_MASK BIT(7) |
| 832 | #define MT_ADIE_XTAL_DECREASE_MASK BIT(6) |
| 833 | |
| 834 | #define MT_ADIE_7975_XO_TRIM2 0x3a2 |
| 835 | #define MT_ADIE_7975_XO_TRIM3 0x3a3 |
| 836 | #define MT_ADIE_7975_XO_TRIM4 0x3a4 |
| 837 | #define MT_ADIE_7975_XTAL_EN 0x3a5 |
| 838 | |
| 839 | #define MT_ADIE_XO_TRIM_FLOW 0x3ac |
| 840 | #define MT_ADIE_XTAL_AXM_80M_OSC 0x390 |
| 841 | #define MT_ADIE_XTAL_AXM_40M_OSC 0x391 |
| 842 | #define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398 |
| 843 | #define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399 |
| 844 | #define MT_ADIE_WRI_CK_SEL 0x4ac |
| 845 | #define MT_ADIE_RG_STRAP_PIN_IN 0x4fc |
| 846 | #define MT_ADIE_XTAL_C1 0x654 |
| 847 | #define MT_ADIE_XTAL_C2 0x658 |
| 848 | #define MT_ADIE_RG_XO_01 0x65c |
| 849 | #define MT_ADIE_RG_XO_03 0x664 |
| 850 | |
| 851 | #define MT_ADIE_CLK_EN 0xa00 |
| 852 | |
| 853 | #define MT_ADIE_7975_XTAL 0xa18 |
| 854 | #define MT_ADIE_7975_XTAL_EN_MASK BIT(29) |
| 855 | |
| 856 | #define MT_ADIE_7975_COCLK 0xa1c |
| 857 | #define MT_ADIE_7975_XO_2 0xa84 |
| 858 | #define MT_ADIE_7975_XO_2_FIX_EN BIT(31) |
| 859 | |
| 860 | #define MT_ADIE_7975_XO_CTRL2 0xa94 |
| 861 | #define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20) |
| 862 | #define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12) |
| 863 | #define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \ |
| 864 | MT_ADIE_7975_XO_CTRL2_C2_MASK) |
| 865 | |
| 866 | #define MT_ADIE_7975_XO_CTRL6 0xaa4 |
| 867 | #define MT_ADIE_7975_XO_CTRL6_MASK BIT(16) |
| 868 | |
| 869 | /* TOP SPI */ |
| 870 | #define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19)) |
| 871 | #define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs)) |
| 872 | |
| 873 | #define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0) |
| 874 | #define MT_TOP_SPI_POLLING_BIT BIT(5) |
| 875 | |
| 876 | #define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50) |
| 877 | #define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15)) |
| 878 | #define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15)) |
| 879 | |
| 880 | #define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54) |
| 881 | #define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58) |
| 882 | |
| 883 | /* CONN INFRA CKGEN */ |
| 884 | #define MT_INFRA_CKGEN_BASE 0x18009000 |
| 885 | #define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs)) |
| 886 | |
| 887 | #define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00) |
| 888 | #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23) |
| 889 | #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29) |
| 890 | |
| 891 | #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008) |
| 892 | #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c) |
| 893 | |
| 894 | #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040) |
| 895 | #define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2) |
| 896 | #define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0) |
| 897 | |
| 898 | /* CONN INFRA BUS */ |
| 899 | #define MT_INFRA_BUS_BASE 0x1800e000 |
| 900 | #define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs)) |
| 901 | |
| 902 | #define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300) |
| 903 | #define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7) |
| 904 | #define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0) |
| 905 | |
| 906 | #define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c) |
| 907 | #define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360) |
| 908 | #define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364) |
| 909 | |
| 910 | /* CONN_INFRA_SKU */ |
| 911 | #define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000 |
| 912 | #define MT_CONNINFRA_SKU_MASK GENMASK(15, 0) |
| 913 | #define MT_ADIE_TYPE_MASK BIT(1) |
| 914 | |
| 915 | /* FW MODE SYNC */ |
| 916 | #define MT_SWDEF_MODE 0x41f23c |
| 917 | #define MT_SWDEF_MODE_MT7916 0x41143c |
| 918 | #define MT_SWDEF_NORMAL_MODE 0 |
| 919 | #define MT_SWDEF_ICAP_MODE 1 |
| 920 | #define MT_SWDEF_SPECTRUM_MODE 2 |
| 921 | |
| 922 | #define MT_DIC_CMD_REG_BASE 0x41f000 |
| 923 | #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) |
| 924 | #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) |
| 925 | |
| 926 | #define MT_CPU_UTIL_BASE 0x41f030 |
| 927 | #define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs)) |
| 928 | #define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00) |
| 929 | #define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04) |
| 930 | #define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08) |
| 931 | #define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c) |
| 932 | #define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c) |
| 933 | |
| 934 | /* LED */ |
| 935 | #define MT_LED_TOP_BASE 0x18013000 |
| 936 | #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) |
| 937 | |
| 938 | #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) |
| 939 | #define MT_LED_CTRL_KICK BIT(7) |
| 940 | #define MT_LED_CTRL_BLINK_MODE BIT(2) |
| 941 | #define MT_LED_CTRL_POLARITY BIT(1) |
| 942 | |
| 943 | #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) |
| 944 | #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) |
| 945 | #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) |
| 946 | |
| 947 | #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) |
| 948 | |
| 949 | #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ |
| 950 | #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ |
| 951 | #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) |
| 952 | |
| 953 | /* MT TOP */ |
| 954 | #define MT_TOP_BASE 0x18060000 |
| 955 | #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) |
| 956 | |
| 957 | #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) |
| 958 | #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) |
| 959 | #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) |
| 960 | #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) |
| 961 | |
| 962 | #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) |
| 963 | #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) |
| 964 | |
| 965 | #define MT_TOP_MISC MT_TOP(0xf0) |
| 966 | #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) |
| 967 | |
| 968 | #define MT_HW_BOUND 0x70010020 |
| 969 | #define MT_HW_REV 0x70010204 |
| 970 | #define MT_WF_SUBSYS_RST 0x70002600 |
| 971 | |
| 972 | #define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4) |
| 973 | #define MT_TOP_WFSYS_WAKEUP_MASK BIT(0) |
| 974 | |
| 975 | #define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4) |
| 976 | #define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0) |
| 977 | |
| 978 | #define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0) |
| 979 | #define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0) |
| 980 | |
| 981 | #define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc) |
| 982 | #define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30) |
| 983 | |
| 984 | /* SEMA */ |
| 985 | #define MT_SEMA_BASE 0x18070000 |
| 986 | #define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs)) |
| 987 | |
| 988 | #define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4)) |
| 989 | #define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4)) |
| 990 | #define MT_SEMA_RFSPI_STATUS_MASK BIT(1) |
| 991 | |
| 992 | /* MCU BUS */ |
| 993 | #define MT_MCU_BUS_BASE 0x18400000 |
| 994 | #define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs)) |
| 995 | |
| 996 | #define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440) |
| 997 | #define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0) |
| 998 | #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28) |
| 999 | #define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31) |
| 1000 | |
| 1001 | #define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120) |
| 1002 | |
| 1003 | /* TOP CFG */ |
| 1004 | #define MT_TOP_CFG_BASE 0x184b0000 |
| 1005 | #define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs)) |
| 1006 | |
| 1007 | #define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010) |
| 1008 | |
| 1009 | /* TOP CFG ON */ |
| 1010 | #define MT_TOP_CFG_ON_BASE 0x184c1000 |
| 1011 | #define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs)) |
| 1012 | |
| 1013 | #define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604) |
| 1014 | |
| 1015 | /* SLP CTRL */ |
| 1016 | #define MT_SLP_BASE 0x184c3000 |
| 1017 | #define MT_SLP(ofs) (MT_SLP_BASE + (ofs)) |
| 1018 | |
| 1019 | #define MT_SLP_STATUS MT_SLP(0x00c) |
| 1020 | #define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23)) |
| 1021 | #define MT_SLP_CTRL_EN_MASK BIT(0) |
| 1022 | #define MT_SLP_CTRL_BSY_MASK BIT(1) |
| 1023 | |
| 1024 | /* MCU BUS DBG */ |
| 1025 | #define MT_MCU_BUS_DBG_BASE 0x18500000 |
| 1026 | #define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs)) |
| 1027 | |
| 1028 | #define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0) |
| 1029 | #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16) |
| 1030 | #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3) |
| 1031 | #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2) |
| 1032 | |
| 1033 | /* PCIE MAC */ |
| 1034 | #define MT_PCIE_MAC_BASE 0x74030000 |
| 1035 | #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) |
| 1036 | #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) |
| 1037 | |
| 1038 | #define MT_PCIE1_MAC_INT_ENABLE 0x74020188 |
| 1039 | #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188 |
| 1040 | |
| 1041 | /* PP TOP */ |
| 1042 | #define MT_WF_PP_TOP_BASE 0x820cc000 |
| 1043 | #define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs)) |
| 1044 | |
| 1045 | #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8) |
| 1046 | #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6) |
| 1047 | |
| 1048 | #define MT_WF_IRPI_BASE 0x83000000 |
| 1049 | #define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + (ofs)) |
| 1050 | |
| 1051 | #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16)) |
| 1052 | #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16)) |
| 1053 | |
| 1054 | /* PHY */ |
| 1055 | #define MT_WF_PHY_BASE 0x83080000 |
| 1056 | #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) |
| 1057 | |
| 1058 | #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16)) |
| 1059 | #define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20)) |
| 1060 | #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0) |
| 1061 | #define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9) |
| 1062 | |
| 1063 | #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16)) |
| 1064 | #define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20)) |
| 1065 | #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) |
| 1066 | #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) |
| 1067 | |
| 1068 | #define MT_MCU_WM_CIRQ_BASE 0x89010000 |
| 1069 | #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) |
| 1070 | #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) |
| 1071 | #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0) |
| 1072 | |
| 1073 | #endif |