developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018 MediaTek Inc. |
| 3 | * Author: Wenzhen.Yu <Wenzhen.Yu@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | &clkitg { |
| 16 | bring-up { |
| 17 | compatible = "mediatek,clk-bring-up"; |
| 18 | clocks = |
| 19 | <&apmixedsys CK_APMIXED_ARMPLL>, |
| 20 | <&apmixedsys CK_APMIXED_NET2PLL>, |
| 21 | <&apmixedsys CK_APMIXED_MMPLL>, |
| 22 | <&apmixedsys CK_APMIXED_SGMPLL>, |
| 23 | <&apmixedsys CK_APMIXED_WEDMCUPLL>, |
| 24 | <&apmixedsys CK_APMIXED_NET1PLL>, |
| 25 | <&apmixedsys CK_APMIXED_MPLL>, |
| 26 | <&apmixedsys CK_APMIXED_APLL2>, |
| 27 | <&infracfg CK_INFRA_CK_F26M>, |
| 28 | <&infracfg CK_INFRA_UART>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 29 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 30 | <&infracfg CK_INFRA_I2C>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 31 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 32 | <&infracfg CK_INFRA_PWM>, |
| 33 | <&infracfg CK_INFRA_66M_MCK>, |
| 34 | <&infracfg CK_INFRA_CK_F32K>, |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 35 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 36 | <&infracfg CK_INFRA_PWM_BCK>, |
| 37 | <&infracfg CK_INFRA_PWM_CK1>, |
| 38 | <&infracfg CK_INFRA_PWM_CK2>, |
| 39 | <&infracfg CK_INFRA_133M_HCK>, |
| 40 | <&infracfg CK_INFRA_EIP_CK>, |
| 41 | <&infracfg CK_INFRA_66M_PHCK>, |
| 42 | <&infracfg CK_INFRA_FAUD_L_CK >, |
| 43 | <&infracfg CK_INFRA_FAUD_AUD_CK>, |
| 44 | <&infracfg CK_INFRA_FAUD_EG2_CK>, |
| 45 | <&infracfg CK_INFRA_I2CS_CK>, |
| 46 | <&infracfg CK_INFRA_MUX_UART0>, |
| 47 | <&infracfg CK_INFRA_MUX_UART1>, |
| 48 | <&infracfg CK_INFRA_MUX_UART2>, |
| 49 | <&infracfg CK_INFRA_NFI_CK>, |
| 50 | <&infracfg CK_INFRA_SPINFI_CK>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 51 | <&clk40m>, |
| 52 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 53 | <&infracfg CK_INFRA_RTC_32K>, |
| 54 | <&infracfg CK_INFRA_FMSDC_CK>, |
| 55 | <&infracfg CK_INFRA_FMSDC_HCK_CK>, |
| 56 | <&infracfg CK_INFRA_PERI_133M>, |
| 57 | <&infracfg CK_INFRA_133M_PHCK>, |
| 58 | <&infracfg CK_INFRA_USB_SYS_CK>, |
| 59 | <&infracfg CK_INFRA_USB_CK>, |
| 60 | <&infracfg CK_INFRA_USB_XHCI_CK>, |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 61 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 62 | <&infracfg CK_INFRA_F26M_CK0>, |
| 63 | <&infracfg_ao CK_INFRA_UART0_SEL>, |
| 64 | <&infracfg_ao CK_INFRA_UART1_SEL>, |
| 65 | <&infracfg_ao CK_INFRA_UART2_SEL>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 66 | <&clk40m>, |
| 67 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 68 | <&infracfg_ao CK_INFRA_PWM1_SEL>, |
| 69 | <&infracfg_ao CK_INFRA_PWM2_SEL>, |
| 70 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 71 | <&clk40m>, |
developer | 7303ea2 | 2021-07-15 11:30:26 +0800 | [diff] [blame] | 72 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 73 | <&infracfg_ao CK_INFRA_PWM_HCK>, |
| 74 | <&infracfg_ao CK_INFRA_PWM_STA>, |
| 75 | <&infracfg_ao CK_INFRA_PWM1_CK>, |
| 76 | <&infracfg_ao CK_INFRA_PWM2_CK>, |
| 77 | <&infracfg_ao CK_INFRA_CQ_DMA_CK>, |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 78 | <&clk40m>, |
| 79 | <&clk40m>, |
| 80 | <&clk40m>, |
| 81 | <&clk40m>, |
| 82 | <&clk40m>, |
| 83 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 84 | <&infracfg_ao CK_INFRA_DRAMC_26M_CK>, |
developer | 86ee1e1 | 2021-06-30 11:18:53 +0800 | [diff] [blame] | 85 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 86 | <&infracfg_ao CK_INFRA_AP_DMA_CK>, |
| 87 | <&infracfg_ao CK_INFRA_SEJ_CK>, |
| 88 | <&infracfg_ao CK_INFRA_SEJ_13M_CK>, |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 89 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 90 | <&infracfg_ao CK_INFRA_I2CO_CK>, |
| 91 | <&infracfg_ao CK_INFRA_UART0_CK>, |
| 92 | <&infracfg_ao CK_INFRA_UART1_CK>, |
| 93 | <&infracfg_ao CK_INFRA_UART2_CK>, |
developer | 248c10b | 2021-07-14 16:11:19 +0800 | [diff] [blame] | 94 | <&clk40m>, |
| 95 | <&clk40m>, |
| 96 | <&clk40m>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 97 | <&clk40m>, |
| 98 | <&clk40m>, |
| 99 | <&clk40m>, |
| 100 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 101 | <&infracfg_ao CK_INFRA_FRTC_CK>, |
| 102 | <&infracfg_ao CK_INFRA_MSDC_CK>, |
| 103 | <&infracfg_ao CK_INFRA_MSDC_HCK_CK>, |
| 104 | <&infracfg_ao CK_INFRA_MSDC_133M_CK>, |
| 105 | <&infracfg_ao CK_INFRA_MSDC_66M_CK>, |
developer | 6ca84f9 | 2021-07-12 10:17:46 +0800 | [diff] [blame] | 106 | <&clk40m>, |
| 107 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 108 | <&infracfg_ao CK_INFRA_FBIST2FPC_CK>, |
| 109 | <&infracfg_ao CK_INFRA_IUSB_133_CK>, |
| 110 | <&infracfg_ao CK_INFRA_IUSB_66M_CK>, |
| 111 | <&infracfg_ao CK_INFRA_IUSB_SYS_CK>, |
| 112 | <&infracfg_ao CK_INFRA_IUSB_CK>, |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 113 | <&clk40m>, |
| 114 | <&clk40m>, |
| 115 | <&clk40m>, |
developer | 3c3ce6b | 2021-07-18 17:20:58 +0800 | [diff] [blame] | 116 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 117 | <&topckgen CK_TOP_CB_M_416M>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 118 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 119 | <&topckgen CK_TOP_CB_M_D4>, |
| 120 | <&topckgen CK_TOP_CB_M_D8>, |
| 121 | <&topckgen CK_TOP_M_D8_D2>, |
| 122 | <&topckgen CK_TOP_M_D3_D2>, |
| 123 | <&topckgen CK_TOP_CB_MM_D2>, |
| 124 | <&topckgen CK_TOP_CB_MM_D4>, |
| 125 | <&topckgen CK_TOP_CB_MM_D8>, |
| 126 | <&topckgen CK_TOP_MM_D8_D2>, |
| 127 | <&topckgen CK_TOP_MM_D3_D8>, |
| 128 | <&topckgen CK_TOP_CB_U2_PHYD_CK>, |
| 129 | <&topckgen CK_TOP_CB_APLL2_196M>, |
| 130 | <&topckgen CK_TOP_APLL2_D4>, |
| 131 | <&topckgen CK_TOP_CB_NET1_D4>, |
| 132 | <&topckgen CK_TOP_CB_NET1_D5>, |
| 133 | <&topckgen CK_TOP_NET1_D5_D2>, |
| 134 | <&topckgen CK_TOP_NET1_D5_D4>, |
| 135 | <&topckgen CK_TOP_NET1_D8_D2>, |
| 136 | <&topckgen CK_TOP_NET1_D8_D4>, |
| 137 | <&topckgen CK_TOP_CB_NET2_800M>, |
| 138 | <&topckgen CK_TOP_CB_NET2_D4>, |
| 139 | <&topckgen CK_TOP_NET2_D4_D2>, |
| 140 | <&topckgen CK_TOP_NET2_D3_D2>, |
| 141 | <&topckgen CK_TOP_CB_WEDMCU_760M>, |
| 142 | <&topckgen CK_TOP_WEDMCU_D5_D2 >, |
| 143 | <&topckgen CK_TOP_CB_SGM_325M>, |
| 144 | <&topckgen CK_TOP_CB_CKSQ_40M_D2>, |
| 145 | <&topckgen CK_TOP_CB_RTC_32K>, |
| 146 | <&topckgen CK_TOP_CB_RTC_32P7K>, |
| 147 | <&topckgen CK_TOP_NFI1X>, |
| 148 | <&topckgen CK_TOP_USB_EQ_RX250M>, |
| 149 | <&topckgen CK_TOP_USB_TX250M>, |
| 150 | <&topckgen CK_TOP_USB_LN0_CK>, |
| 151 | <&topckgen CK_TOP_USB_CDR_CK>, |
| 152 | <&topckgen CK_TOP_SPINFI_BCK>, |
| 153 | <&topckgen CK_TOP_I2C_BCK>, |
| 154 | <&topckgen CK_TOP_PEXTP_TL>, |
| 155 | <&topckgen CK_TOP_EMMC_250M>, |
| 156 | <&topckgen CK_TOP_EMMC_416M>, |
| 157 | <&topckgen CK_TOP_F_26M_ADC_CK>, |
| 158 | <&topckgen CK_TOP_SYSAXI>, |
| 159 | <&topckgen CK_TOP_NETSYS_WED_MCU>, |
| 160 | <&topckgen CK_TOP_NETSYS_2X>, |
| 161 | <&topckgen CK_TOP_SGM_325M>, |
| 162 | <&topckgen CK_TOP_A1SYS>, |
| 163 | <&topckgen CK_TOP_EIP_B>, |
| 164 | <&topckgen CK_TOP_F26M>, |
| 165 | <&topckgen CK_TOP_AUD_L>, |
| 166 | <&topckgen CK_TOP_A_TUNER>, |
| 167 | <&topckgen CK_TOP_U2U3_REF>, |
| 168 | <&topckgen CK_TOP_U2U3_SYS>, |
| 169 | <&topckgen CK_TOP_U2U3_XHCI>, |
| 170 | <&topckgen CK_TOP_AP2CNN_HOST>, |
| 171 | <&topckgen CK_TOP_NFI1X_SEL>, |
| 172 | <&topckgen CK_TOP_SPINFI_SEL>, |
developer | 1c90874 | 2021-07-13 19:03:48 +0800 | [diff] [blame] | 173 | <&clk40m>, |
| 174 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 175 | <&topckgen CK_TOP_UART_SEL>, |
| 176 | <&topckgen CK_TOP_PWM_SEL>, |
| 177 | <&topckgen CK_TOP_I2C_SEL>, |
| 178 | <&topckgen CK_TOP_PEXTP_TL_SEL>, |
| 179 | <&topckgen CK_TOP_EMMC_250M_SEL >, |
| 180 | <&topckgen CK_TOP_EMMC_416M_SEL >, |
| 181 | <&topckgen CK_TOP_F_26M_ADC_SEL>, |
| 182 | <&topckgen CK_TOP_DRAMC_SEL>, |
| 183 | <&topckgen CK_TOP_DRAMC_MD32_SEL>, |
| 184 | <&topckgen CK_TOP_SYSAXI_SEL>, |
| 185 | <&topckgen CK_TOP_SYSAPB_SEL>, |
| 186 | <&topckgen CK_TOP_ARM_DB_MAIN_SEL>, |
developer | 66b5c8d | 2021-07-16 14:02:47 +0800 | [diff] [blame] | 187 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 188 | <&topckgen CK_TOP_NETSYS_SEL>, |
| 189 | <&topckgen CK_TOP_NETSYS_500M_SEL>, |
| 190 | <&topckgen CK_TOP_NETSYS_MCU_SEL>, |
| 191 | <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 192 | <&topckgen CK_TOP_SGM_325M_SEL>, |
| 193 | <&topckgen CK_TOP_SGM_REG_SEL>, |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 194 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 195 | <&topckgen CK_TOP_CONN_MCUSYS_SEL>, |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 196 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 197 | <&topckgen CK_TOP_PCIE_PHY_SEL>, |
| 198 | <&topckgen CK_TOP_USB3_PHY_SEL>, |
| 199 | <&topckgen CK_TOP_F26M_SEL>, |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 200 | <&clk40m>, |
| 201 | <&clk40m>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 202 | <&topckgen CK_TOP_U2U3_SEL>, |
| 203 | <&topckgen CK_TOP_U2U3_SYS_SEL>, |
| 204 | <&topckgen CK_TOP_U2U3_XHCI_SEL>, |
| 205 | <&topckgen CK_TOP_DA_U2_REFSEL>, |
| 206 | <&topckgen CK_TOP_DA_U2_CK_1P_SEL>, |
| 207 | <&topckgen CK_TOP_AP2CNN_HOST_SEL>, |
| 208 | <&clk40m>, |
| 209 | <&clk40m>, |
| 210 | <&clk40m>, |
| 211 | <&clk40m>, |
| 212 | <&clk40m>, |
| 213 | <&clk40m>, |
| 214 | <&clk40m>, |
| 215 | <&clk40m>, |
| 216 | <&clk40m>, |
| 217 | <&clk40m>, |
| 218 | <&clk40m>, |
| 219 | <&clk40m>, |
| 220 | <&clk40m>; |
| 221 | |
| 222 | |
| 223 | clock-names = "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", |
| 224 | "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", |
| 225 | "24", "25", "26", "27", "28", "29", "30", "31", "32", "33", "34", "35", |
| 226 | "36", "37", "38", "39", "40", "41", "42", "43", "44", "45", "46", "47", |
| 227 | "48", "49", "50", "51", "52", "53", "54", "55", "56", "57", "58", "59", |
| 228 | "60", "61", "62", "63", "64", "65", "66", "67", "68", "69", "70", "71", |
| 229 | "72", "73", "74", "75", "76", "77", "78", "79", "80", "81", "82", "83", |
| 230 | "84", "85", "86", "87", "88", "89", "90", "91", "92", "93", "94", "95", |
| 231 | "96", "97", "98", "99", "100", "101", "102", "103", "104", "105", "106", "107", |
| 232 | "108", "109", "110", "111", "112", "113", "114", "115", "116", "117", |
| 233 | "118", "119", "120", "121", "122", "123", |
| 234 | "124", "125", "126", "127", "128", "129", "130", "131", "132", "133", "134", "135", |
| 235 | "136", "137", "138", "139", "140", "141", "142", "143", "144", "145", "146", "147", |
| 236 | "148", "149", "150", "151", "152", "153", "154", "155", "156", "157", "158", "159", |
| 237 | "160", "161", "162", "163", "164", "165", "166", "167", "168", "169", "170", "171", |
| 238 | "172", "173", "174", "175", "176", "177", "178", "179", "180", "181", "182", "183", |
| 239 | "184", "185", "186", "187", "188", "189", "190", "191", "192", "193", "194", "195", |
| 240 | "196", "197", "198", "199", "200", "201", "202", "203", "204", "205", "206", "207", |
| 241 | "208", "209", "210", "211", "212", "213", "214", "215", "216", "217", "218", "219", "220", "221"; |
| 242 | }; |
| 243 | }; |