developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From e17d8763f1279f43edf51a8ceb8b4f78d67eaefa Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:30 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [networking][999-2713-mt7531-gsw-internal_phy_calibration.patch] |
| 6 | |
| 7 | --- |
| 8 | drivers/net/phy/mtk/mt753x/Makefile | 2 +- |
| 9 | drivers/net/phy/mtk/mt753x/mt7531.c | 21 + |
| 10 | drivers/net/phy/mtk/mt753x/mt753x.h | 2 + |
| 11 | drivers/net/phy/mtk/mt753x/mt753x_phy.c | 1069 +++++++++++++++++++++++ |
| 12 | drivers/net/phy/mtk/mt753x/mt753x_phy.h | 145 +++ |
| 13 | 5 files changed, 1238 insertions(+), 1 deletion(-) |
| 14 | create mode 100644 drivers/net/phy/mtk/mt753x/mt753x_phy.c |
| 15 | create mode 100644 drivers/net/phy/mtk/mt753x/mt753x_phy.h |
| 16 | |
| 17 | diff --git a/drivers/net/phy/mtk/mt753x/Makefile b/drivers/net/phy/mtk/mt753x/Makefile |
| 18 | index e304fcb41..b5a63fe91 100644 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 19 | --- a/drivers/net/phy/mtk/mt753x/Makefile |
| 20 | +++ b/drivers/net/phy/mtk/mt753x/Makefile |
| 21 | @@ -7,5 +7,5 @@ obj-$(CONFIG_MT753X_GSW) += mt753x.o |
| 22 | mt753x-$(CONFIG_SWCONFIG) += mt753x_swconfig.o |
| 23 | |
| 24 | mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \ |
| 25 | - mt753x_common.o mt753x_vlan.o mt753x_nl.o |
| 26 | + mt753x_common.o mt753x_vlan.o mt753x_nl.o mt753x_phy.o |
| 27 | |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 28 | diff --git a/drivers/net/phy/mtk/mt753x/mt7531.c b/drivers/net/phy/mtk/mt753x/mt7531.c |
| 29 | index b27c679a5..512a89a94 100755 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 30 | --- a/drivers/net/phy/mtk/mt753x/mt7531.c |
| 31 | +++ b/drivers/net/phy/mtk/mt753x/mt7531.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 32 | @@ -662,6 +662,27 @@ static void mt7531_core_pll_setup(struct gsw_mt753x *gsw) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 33 | |
| 34 | static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw) |
| 35 | { |
| 36 | + u32 i, val; |
| 37 | + int ret; |
| 38 | + |
| 39 | + dev_info(gsw->dev,">>>>>>>>>>>>>>>>>>>>>>>>>>>>> START CALIBRATION:\n"); |
| 40 | + |
| 41 | + /* gphy value from sw path */ |
| 42 | + val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); |
| 43 | + val |= GBE_EFUSE_SETTING; |
| 44 | + gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 45 | + |
| 46 | + for (i = 0; i < 5; i++) { |
| 47 | + dev_info(gsw->dev, "-------- gephy-calbration (port:%d) --------\n", |
| 48 | + i); |
| 49 | + ret = mt753x_phy_calibration(gsw, i); |
| 50 | + |
| 51 | + /* set Auto-negotiation with giga extension. */ |
| 52 | + gsw->mii_write(gsw, i, 0, 0x1340); |
| 53 | + if (ret) |
| 54 | + return ret; |
| 55 | + } |
| 56 | + |
| 57 | return 0; |
| 58 | } |
| 59 | |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 60 | diff --git a/drivers/net/phy/mtk/mt753x/mt753x.h b/drivers/net/phy/mtk/mt753x/mt753x.h |
| 61 | index 344d2b0c6..252ce350f 100644 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 62 | --- a/drivers/net/phy/mtk/mt753x/mt753x.h |
| 63 | +++ b/drivers/net/phy/mtk/mt753x/mt753x.h |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 64 | @@ -146,6 +146,8 @@ void mt753x_irq_enable(struct gsw_mt753x *gsw); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 65 | int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr); |
| 66 | int extphy_init(struct gsw_mt753x *gsw, int addr); |
| 67 | |
| 68 | +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr); |
| 69 | + |
| 70 | /* MDIO Indirect Access Registers */ |
| 71 | #define MII_MMD_ACC_CTL_REG 0x0d |
| 72 | #define MMD_CMD_S 14 |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 73 | diff --git a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 74 | new file mode 100644 |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 75 | index 000000000..0c6f9c930 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 76 | --- /dev/null |
| 77 | +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c |
| 78 | @@ -0,0 +1,1069 @@ |
| 79 | +// SPDX-License-Identifier: GPL-2.0+ |
| 80 | +/* |
| 81 | + * Common part for MediaTek MT753x gigabit switch |
| 82 | + * |
| 83 | + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved. |
| 84 | + * |
| 85 | + * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 86 | + */ |
| 87 | + |
| 88 | +#include <linux/kernel.h> |
| 89 | +#include <linux/delay.h> |
| 90 | + |
| 91 | +#include "mt753x.h" |
| 92 | +#include "mt753x_regs.h" |
| 93 | +#include "mt753x_phy.h" |
| 94 | + |
| 95 | +u32 tc_phy_read_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr) |
| 96 | +{ |
| 97 | + u32 phy_val; |
| 98 | + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr); |
| 99 | + |
| 100 | + //printk("switch phy cl45 r %d 0x%x 0x%x = %x\n",port_num, dev_addr, reg_addr, phy_val); |
| 101 | + //switch_phy_read_cl45(port_num, dev_addr, reg_addr, &phy_val); |
| 102 | + return phy_val; |
| 103 | +} |
| 104 | + |
| 105 | +void tc_phy_write_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data) |
| 106 | +{ |
| 107 | + u32 phy_val; |
| 108 | + gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data); |
| 109 | + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr); |
| 110 | + //printk("switch phy cl45 w %d 0x%x 0x%x 0x%x --> read back 0x%x\n",port_num, dev_addr, reg_addr, write_data, phy_val); |
| 111 | + //switch_phy_write_cl45(port_num, dev_addr, reg_addr, write_data); |
| 112 | +} |
| 113 | + |
| 114 | +void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){ |
| 115 | + gsw->mii_write(gsw, port_num, reg_addr, write_data); |
| 116 | +} |
| 117 | + |
| 118 | +u32 switch_phy_read(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr){ |
| 119 | + return gsw->mii_read(gsw, port_num, reg_addr); |
| 120 | +} |
| 121 | + |
| 122 | +const u8 MT753x_ZCAL_TO_R50ohm_GE_TBL_100[64] = { |
| 123 | + 127, 127, 127, 127, 127, 127, 127, 127, |
| 124 | + 127, 127, 127, 127, 127, 123, 122, 117, |
| 125 | + 115, 112, 103, 100, 98, 87, 85, 83, |
| 126 | + 81, 72, 70, 68, 66, 64, 55, 53, |
| 127 | + 52, 50, 49, 48, 38, 36, 35, 34, |
| 128 | + 33, 32, 22, 21, 20, 19, 18, 17, |
| 129 | + 16, 7, 6, 5, 4, 3, 2, 1, |
| 130 | + 0, 0, 0, 0, 0, 0, 0, 0 |
| 131 | +}; |
| 132 | + |
| 133 | +const u8 MT753x_TX_OFFSET_TBL[64] = { |
| 134 | + 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, |
| 135 | + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, |
| 136 | + 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, |
| 137 | + 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0, |
| 138 | + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, |
| 139 | + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, |
| 140 | + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, |
| 141 | + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f |
| 142 | +}; |
| 143 | + |
| 144 | +u8 ge_cal_flag; |
| 145 | + |
| 146 | +u8 all_ge_ana_cal_wait(struct gsw_mt753x *gsw, u32 delay, u32 phyaddr) // for EN7512 |
| 147 | +{ |
| 148 | + u8 all_ana_cal_status; |
| 149 | + u32 cnt, tmp_1e_17c; |
| 150 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017c, 0x0001); // da_calin_flag pull high |
| 151 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); |
| 152 | + //printk("delay = %d\n", delay); |
| 153 | + |
| 154 | + cnt = 10000; |
| 155 | + do { |
| 156 | + udelay(delay); |
| 157 | + cnt--; |
| 158 | + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1; |
| 159 | + |
| 160 | + } while ((all_ana_cal_status == 0) && (cnt != 0)); |
| 161 | + |
| 162 | + |
| 163 | + if(all_ana_cal_status == 1) { |
| 164 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0); |
| 165 | + return all_ana_cal_status; |
| 166 | + } else { |
| 167 | + tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c); |
| 168 | + if ((tmp_1e_17c & 0x1) != 1) { |
| 169 | + pr_info("FIRST MDC/MDIO write error\n"); |
| 170 | + pr_info("FIRST 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c)); |
| 171 | + |
| 172 | + } |
| 173 | + printk("re-K again\n"); |
| 174 | + |
| 175 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0); |
| 176 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); |
| 177 | + cnt = 10000; |
| 178 | + do { |
| 179 | + udelay(delay); |
| 180 | + cnt--; |
| 181 | + tmp_1e_17c = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c); |
| 182 | + if ((tmp_1e_17c & 0x1) != 1) { |
| 183 | + pr_info("SECOND MDC/MDIO write error\n"); |
| 184 | + pr_info("SECOND 1e_17c = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17c)); |
| 185 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); |
| 186 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); |
| 187 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001); |
| 188 | + } |
| 189 | + } while ((cnt != 0) && (tmp_1e_17c == 0)); |
| 190 | + |
| 191 | + cnt = 10000; |
| 192 | + do { |
| 193 | + udelay(delay); |
| 194 | + cnt--; |
| 195 | + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1; |
| 196 | + |
| 197 | + } while ((all_ana_cal_status == 0) && (cnt != 0)); |
| 198 | + |
| 199 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0); |
| 200 | + } |
| 201 | + |
| 202 | + if(all_ana_cal_status == 0){ |
| 203 | + pr_info("!!!!!!!!!!!! dev1Eh_reg17b ERROR\n"); |
| 204 | + } |
| 205 | + |
| 206 | + return all_ana_cal_status; |
| 207 | +} |
| 208 | + |
| 209 | + |
| 210 | + |
| 211 | + |
| 212 | +int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| 213 | +{ |
| 214 | + u8 rg_zcal_ctrl, all_ana_cal_status; |
| 215 | + u16 ad_cal_comp_out_init; |
| 216 | + u16 dev1e_e0_ana_cal_r5; |
| 217 | + int calibration_polarity; |
| 218 | + u8 cnt = 0; |
| 219 | + u16 dev1e_17a_tmp, dev1e_e0_tmp; |
| 220 | + |
| 221 | + /* *** Iext/Rext Cal start ************ */ |
| 222 | + all_ana_cal_status = ANACAL_INIT; |
| 223 | + /* analog calibration enable, Rext calibration enable */ |
| 224 | + /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */ |
| 225 | + /* 1e_dc[0]:rg_txvos_calen */ |
| 226 | + /* 1e_e1[4]:rg_cal_refsel(0:1.2V) */ |
| 227 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110) |
| 228 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110); |
| 229 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000); |
| 230 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0); |
| 231 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000); |
| 232 | + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10); |
| 233 | + |
| 234 | + rg_zcal_ctrl = 0x20;/* start with 0 dB */ |
| 235 | + dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); // get default value |
| 236 | + /* 1e_e0[5:0]:rg_zcal_ctrl */ |
| 237 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl); |
| 238 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */ |
| 239 | + |
| 240 | + if (all_ana_cal_status == 0) { |
| 241 | + all_ana_cal_status = ANACAL_ERROR; |
| 242 | + printk(" GE Rext AnaCal ERROR init! \r\n"); |
| 243 | + return -1; |
| 244 | + } |
| 245 | + /* 1e_17a[8]:ad_cal_comp_out */ |
| 246 | + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1; |
| 247 | + if (ad_cal_comp_out_init == 1) |
| 248 | + calibration_polarity = -1; |
| 249 | + else /* ad_cal_comp_out_init == 0 */ |
| 250 | + calibration_polarity = 1; |
| 251 | + cnt = 0; |
| 252 | + while (all_ana_cal_status < ANACAL_ERROR) { |
| 253 | + cnt++; |
| 254 | + rg_zcal_ctrl += calibration_polarity; |
| 255 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, (rg_zcal_ctrl)); |
| 256 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); /* delay 20 usec */ |
| 257 | + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a); |
| 258 | + if (all_ana_cal_status == 0) { |
| 259 | + all_ana_cal_status = ANACAL_ERROR; |
| 260 | + printk(" GE Rext AnaCal ERROR 2! \r\n"); |
| 261 | + return -1; |
| 262 | + } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) { |
| 263 | + all_ana_cal_status = ANACAL_FINISH; |
| 264 | + //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl); |
| 265 | + } else { |
| 266 | + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a); |
| 267 | + dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); |
| 268 | + if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) { |
| 269 | + all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */ |
| 270 | + printk(" GE Rext AnaCal Saturation! \r\n"); |
| 271 | + rg_zcal_ctrl = 0x20; /* 0 dB */ |
| 272 | + } |
| 273 | + } |
| 274 | + } |
| 275 | + |
| 276 | + if (all_ana_cal_status == ANACAL_ERROR) { |
| 277 | + rg_zcal_ctrl = 0x20; /* 0 dB */ |
| 278 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); |
| 279 | + } else if(all_ana_cal_status == ANACAL_FINISH){ |
| 280 | + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); |
| 281 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl)); |
| 282 | + printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0)); |
| 283 | + /* **** 1f_115[2:0] = rg_zcal_ctrl[5:3] // Mog review */ |
| 284 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3)); |
| 285 | + printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115)); |
| 286 | + printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl); |
| 287 | + ge_cal_flag = 1; |
| 288 | + } else { |
| 289 | + printk("GE Rxet cal something wrong2\n"); |
| 290 | + } |
| 291 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); |
| 292 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); |
| 293 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); |
| 294 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); |
| 295 | + |
| 296 | + return 0; |
| 297 | +} |
| 298 | + |
| 299 | +//----------------------------------------------------------------- |
| 300 | +int ge_cal_r50(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| 301 | +{ |
| 302 | + u8 rg_zcal_ctrl, all_ana_cal_status, calibration_pair; |
| 303 | + u16 ad_cal_comp_out_init; |
| 304 | + u16 dev1e_e0_ana_cal_r5; |
| 305 | + int calibration_polarity; |
| 306 | + u8 cnt = 0; |
| 307 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 308 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // 1e_dc[0]:rg_txvos_calen |
| 309 | + |
| 310 | + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) { |
| 311 | + rg_zcal_ctrl = 0x20; // start with 0 dB |
| 312 | + dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0) & (~0x003f)); |
| 313 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); // 1e_e0[5:0]:rg_zcal_ctrl |
| 314 | + if(calibration_pair == ANACAL_PAIR_A) |
| 315 | + { |
| 316 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 317 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); |
| 318 | + //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); |
| 319 | + |
| 320 | + } |
| 321 | + else if(calibration_pair == ANACAL_PAIR_B) |
| 322 | + { |
| 323 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 324 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000); // 1e_dc[12]:rg_zcalen_b |
| 325 | + //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); |
| 326 | + |
| 327 | + } |
| 328 | + else if(calibration_pair == ANACAL_PAIR_C) |
| 329 | + { |
| 330 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 331 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100); // 1e_dc[8]:rg_zcalen_c |
| 332 | + //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); |
| 333 | + |
| 334 | + } |
| 335 | + else // if(calibration_pair == ANACAL_PAIR_D) |
| 336 | + { |
| 337 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 338 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010); // 1e_dc[4]:rg_zcalen_d |
| 339 | + //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc)); |
| 340 | + |
| 341 | + } |
| 342 | + |
| 343 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec |
| 344 | + if(all_ana_cal_status == 0) |
| 345 | + { |
| 346 | + all_ana_cal_status = ANACAL_ERROR; |
| 347 | + printk( "GE R50 AnaCal ERROR init! \r\n"); |
| 348 | + return -1; |
| 349 | + } |
| 350 | + |
| 351 | + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out |
| 352 | + if(ad_cal_comp_out_init == 1) |
| 353 | + calibration_polarity = -1; |
| 354 | + else |
| 355 | + calibration_polarity = 1; |
| 356 | + |
| 357 | + cnt = 0; |
| 358 | + while(all_ana_cal_status < ANACAL_ERROR) |
| 359 | + { |
| 360 | + cnt ++; |
| 361 | + rg_zcal_ctrl += calibration_polarity; |
| 362 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); |
| 363 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec |
| 364 | + |
| 365 | + if(all_ana_cal_status == 0) |
| 366 | + { |
| 367 | + all_ana_cal_status = ANACAL_ERROR; |
| 368 | + printk( " GE R50 AnaCal ERROR 2! \r\n"); |
| 369 | + return -1; |
| 370 | + } |
| 371 | + else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) |
| 372 | + { |
| 373 | + all_ana_cal_status = ANACAL_FINISH; |
| 374 | + } |
| 375 | + else { |
| 376 | + if((rg_zcal_ctrl == 0x3F)||(rg_zcal_ctrl == 0x00)) |
| 377 | + { |
| 378 | + all_ana_cal_status = ANACAL_SATURATION; // need to FT |
| 379 | + printk( " GE R50 AnaCal Saturation! \r\n"); |
| 380 | + } |
| 381 | + } |
| 382 | + } |
| 383 | + |
| 384 | + if(all_ana_cal_status == ANACAL_ERROR) { |
| 385 | + rg_zcal_ctrl = 0x20; // 0 dB |
| 386 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl)); |
| 387 | + } |
| 388 | + else { |
| 389 | + rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9]; // wait Mog zcal/r50 mapping table |
| 390 | + printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80)); |
| 391 | + } |
| 392 | + |
| 393 | + if(calibration_pair == ANACAL_PAIR_A) { |
| 394 | + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00); |
| 395 | + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174); |
| 396 | + //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 397 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_174[15:8] |
| 398 | + //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 399 | + } |
| 400 | + else if(calibration_pair == ANACAL_PAIR_B) { |
| 401 | + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x007f); |
| 402 | + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174); |
| 403 | + //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 404 | + |
| 405 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_174[7:0] |
| 406 | + //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 407 | + } |
| 408 | + else if(calibration_pair == ANACAL_PAIR_C) { |
| 409 | + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00); |
| 410 | + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175); |
| 411 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000))); // 1e_175[15:8] |
| 412 | + //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 413 | + } else {// if(calibration_pair == ANACAL_PAIR_D) |
| 414 | + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f); |
| 415 | + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175); |
| 416 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080))); // 1e_175[7:0] |
| 417 | + //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 418 | + } |
| 419 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl)); |
| 420 | + } |
| 421 | + |
| 422 | + printk( " GE 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175)); |
| 423 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); |
| 424 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); |
| 425 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); |
| 426 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); |
| 427 | + |
| 428 | + return 0; |
| 429 | +} |
| 430 | + |
| 431 | +int ge_cal_tx_offset(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| 432 | +{ |
| 433 | + u8 all_ana_cal_status, calibration_pair; |
| 434 | + u16 ad_cal_comp_out_init; |
| 435 | + int calibration_polarity, tx_offset_temp; |
| 436 | + u8 tx_offset_reg_shift, tabl_idx, i; |
| 437 | + u8 cnt = 0; |
| 438 | + u16 tx_offset_reg, reg_temp, cal_temp; |
| 439 | + //switch_phy_write(phyaddr, R0, 0x2100);//harry tmp |
| 440 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 441 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen |
| 442 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000); // 1e_96[15]:bypass_tx_offset_cal, Hw bypass, Fw cal |
| 443 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e |
| 444 | + for(i = 0; i <= 4; i++) |
| 445 | + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000); |
| 446 | + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) |
| 447 | + { |
| 448 | + tabl_idx = 31; |
| 449 | + tx_offset_temp = MT753x_TX_OFFSET_TBL[tabl_idx]; |
| 450 | + |
| 451 | + if(calibration_pair == ANACAL_PAIR_A) { |
| 452 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010); |
| 453 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:rg_txg_calen_a |
| 454 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V)); // 1e_17d:dac_in0_a |
| 455 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V)); // 1e_181:dac_in1_a |
| 456 | + //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181)); |
| 457 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00)); |
| 458 | + tx_offset_reg_shift = 8; // 1e_172[13:8] |
| 459 | + tx_offset_reg = 0x0172; |
| 460 | + |
| 461 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); |
| 462 | + } else if(calibration_pair == ANACAL_PAIR_B) { |
| 463 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5018); |
| 464 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:rg_txg_calen_b |
| 465 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V)); // 1e_17e:dac_in0_b |
| 466 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V)); // 1e_182:dac_in1_b |
| 467 | + //printk("tx offset pairB 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181)); |
| 468 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x003f)); |
| 469 | + tx_offset_reg_shift = 0; // 1e_172[5:0] |
| 470 | + tx_offset_reg = 0x0172; |
| 471 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); |
| 472 | + } else if(calibration_pair == ANACAL_PAIR_C) { |
| 473 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:rg_txg_calen_c |
| 474 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V)); // 1e_17f:dac_in0_c |
| 475 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V)); // 1e_183:dac_in1_c |
| 476 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x3f00)); |
| 477 | + //printk("tx offset pairC 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181)); |
| 478 | + tx_offset_reg_shift = 8; // 1e_173[13:8] |
| 479 | + tx_offset_reg = 0x0173; |
| 480 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); |
| 481 | + } else {// if(calibration_pair == ANACAL_PAIR_D) |
| 482 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:rg_txg_calen_d |
| 483 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V)); // 1e_180:dac_in0_d |
| 484 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V)); // 1e_184:dac_in1_d |
| 485 | + //printk("tx offset pairD 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181)); |
| 486 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x003f)); |
| 487 | + tx_offset_reg_shift = 0; // 1e_173[5:0] |
| 488 | + tx_offset_reg = 0x0173; |
| 489 | + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); |
| 490 | + } |
| 491 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); // 1e_172, 1e_173 |
| 492 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec |
| 493 | + if(all_ana_cal_status == 0) { |
| 494 | + all_ana_cal_status = ANACAL_ERROR; |
| 495 | + printk( " GE Tx offset AnaCal ERROR init! \r\n"); |
| 496 | + return -1; |
| 497 | + } |
| 498 | + |
| 499 | + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out |
| 500 | + if(ad_cal_comp_out_init == 1) |
| 501 | + calibration_polarity = 1; |
| 502 | + else |
| 503 | + calibration_polarity = -1; |
| 504 | + |
| 505 | + cnt = 0; |
| 506 | + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]); |
| 507 | + while(all_ana_cal_status < ANACAL_ERROR) { |
| 508 | + |
| 509 | + cnt ++; |
| 510 | + tabl_idx += calibration_polarity; |
| 511 | + //tx_offset_temp += calibration_polarity; |
| 512 | + //cal_temp = tx_offset_temp; |
| 513 | + cal_temp = MT753x_TX_OFFSET_TBL[tabl_idx]; |
| 514 | + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]); |
| 515 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(cal_temp<<tx_offset_reg_shift))); |
| 516 | + |
| 517 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec |
| 518 | + if(all_ana_cal_status == 0) { |
| 519 | + all_ana_cal_status = ANACAL_ERROR; |
| 520 | + printk( " GE Tx offset AnaCal ERROR init 2! \r\n"); |
| 521 | + return -1; |
| 522 | + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) { |
| 523 | + all_ana_cal_status = ANACAL_FINISH; |
| 524 | + } else { |
| 525 | + if((tabl_idx == 0)||(tabl_idx == 0x3f)) { |
| 526 | + all_ana_cal_status = ANACAL_SATURATION; // need to FT |
| 527 | + printk( " GE Tx offset AnaCal Saturation! \r\n"); |
| 528 | + } |
| 529 | + } |
| 530 | + } |
| 531 | + |
| 532 | + if(all_ana_cal_status == ANACAL_ERROR) { |
| 533 | + tx_offset_temp = TX_AMP_OFFSET_0MV; |
| 534 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift))); |
| 535 | + } else { |
| 536 | + printk( " GE Tx offset AnaCal Done! (pair-%d)(%d)(0x%x) 0x1e_%x=0x%x\n", calibration_pair, cnt, MT753x_TX_OFFSET_TBL[tabl_idx], tx_offset_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg)); |
| 537 | + } |
| 538 | + } |
| 539 | + |
| 540 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000); |
| 541 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000); |
| 542 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000); |
| 543 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000); |
| 544 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000); |
| 545 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000); |
| 546 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000); |
| 547 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000); |
| 548 | + |
| 549 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit |
| 550 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit |
| 551 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit |
| 552 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit |
| 553 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode |
| 554 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit |
| 555 | + |
| 556 | + return 0; |
| 557 | +} |
| 558 | + |
| 559 | +int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| 560 | +{ |
| 561 | + u8 all_ana_cal_status, calibration_pair, i; |
| 562 | + u16 ad_cal_comp_out_init; |
| 563 | + int calibration_polarity; |
| 564 | + u32 tx_amp_reg_shift; |
| 565 | + u16 reg_temp; |
| 566 | + u32 tx_amp_temp, tx_amp_reg, cnt=0, tx_amp_reg_100; |
| 567 | + u32 debug_tmp, reg_backup, reg_tmp; |
| 568 | + u32 orig_1e_11, orig_1f_300; |
| 569 | + |
| 570 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100); // 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a |
| 571 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001); // 1e_dc[0]:rg_txvos_calen |
| 572 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010); // 1e_e1[4]:select 1V |
| 573 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808); // 1e_3e:enable Tx VLD |
| 574 | + |
| 575 | + orig_1e_11 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11); |
| 576 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, 0xff00); |
| 577 | +// tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27a, 0x33); |
| 578 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0xffff); |
| 579 | + orig_1f_300 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x300); |
| 580 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x300, 0x4); |
| 581 | + for(i = 0; i <= 4; i++) |
| 582 | + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000); |
| 583 | + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) { |
| 584 | + tx_amp_temp = 0x20; // start with 0 dB |
| 585 | + |
| 586 | + if(calibration_pair == ANACAL_PAIR_A) { |
| 587 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]:tx_a amp calibration enable |
| 588 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d:dac_in0_a |
| 589 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181:dac_in1_a |
| 590 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x012) & (~0xfc00)); |
| 591 | + tx_amp_reg_shift = 10; // 1e_12[15:10] |
| 592 | + tx_amp_reg = 0x12; |
| 593 | + tx_amp_reg_100 = 0x16; |
| 594 | + } else if(calibration_pair == ANACAL_PAIR_B) { |
| 595 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]:tx_b amp calibration enable |
| 596 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e:dac_in0_b |
| 597 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182:dac_in1_b |
| 598 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x017) & (~0x3f00)); |
| 599 | + tx_amp_reg_shift = 8; // 1e_17[13:8] |
| 600 | + tx_amp_reg = 0x17; |
| 601 | + tx_amp_reg_100 = 0x18; |
| 602 | + } else if(calibration_pair == ANACAL_PAIR_C) { |
| 603 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]:tx_c amp calibration enable |
| 604 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f:dac_in0_c |
| 605 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183:dac_in1_c |
| 606 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x019) & (~0x3f00)); |
| 607 | + tx_amp_reg_shift = 8; // 1e_19[13:8] |
| 608 | + tx_amp_reg = 0x19; |
| 609 | + tx_amp_reg_100 = 0x20; |
| 610 | + } else { //if(calibration_pair == ANACAL_PAIR_D) |
| 611 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]:tx_d amp calibration enable |
| 612 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180:dac_in0_d |
| 613 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184:dac_in1_d |
| 614 | + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x021) & (~0x3f00)); |
| 615 | + tx_amp_reg_shift = 8; // 1e_21[13:8] |
| 616 | + tx_amp_reg = 0x21; |
| 617 | + tx_amp_reg_100 = 0x22; |
| 618 | + } |
| 619 | + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); // 1e_12, 1e_17, 1e_19, 1e_21 |
| 620 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); |
| 621 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec |
| 622 | + if(all_ana_cal_status == 0) { |
| 623 | + all_ana_cal_status = ANACAL_ERROR; |
| 624 | + printk( " GE Tx amp AnaCal ERROR init init! \r\n"); |
| 625 | + return -1; |
| 626 | + } |
| 627 | + |
| 628 | + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]:ad_cal_comp_out |
| 629 | + if(ad_cal_comp_out_init == 1) |
| 630 | + calibration_polarity = -1; |
| 631 | + else |
| 632 | + calibration_polarity = 1; |
| 633 | + |
| 634 | + cnt =0; |
| 635 | + while(all_ana_cal_status < ANACAL_ERROR) { |
| 636 | + cnt ++; |
| 637 | + tx_amp_temp += calibration_polarity; |
| 638 | + //printk("tx_amp : %x, 1e %x = %x\n", tx_amp_temp, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift))); |
| 639 | + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); |
| 640 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); |
| 641 | + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec |
| 642 | + if(all_ana_cal_status == 0) { |
| 643 | + all_ana_cal_status = ANACAL_ERROR; |
| 644 | + printk( " GE Tx amp AnaCal ERROR 2! \r\n"); |
| 645 | + return -1; |
| 646 | + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) { |
| 647 | + //printk("TX AMP ANACAL_FINISH\n"); |
| 648 | + all_ana_cal_status = ANACAL_FINISH; |
| 649 | + if (phyaddr == 0) { |
| 650 | + if (calibration_pair == ANACAL_PAIR_A) |
| 651 | + tx_amp_temp = tx_amp_temp - 2; |
| 652 | + else if(calibration_pair == ANACAL_PAIR_B) |
| 653 | + tx_amp_temp = tx_amp_temp - 1; |
| 654 | + else if(calibration_pair == ANACAL_PAIR_C) |
| 655 | + tx_amp_temp = tx_amp_temp - 2; |
| 656 | + else if(calibration_pair == ANACAL_PAIR_D) |
| 657 | + tx_amp_temp = tx_amp_temp - 1; |
| 658 | + } else if (phyaddr == 1) { |
| 659 | + if (calibration_pair == ANACAL_PAIR_A) |
| 660 | + tx_amp_temp = tx_amp_temp - 1; |
| 661 | + else if(calibration_pair == ANACAL_PAIR_B) |
| 662 | + tx_amp_temp = tx_amp_temp ; |
| 663 | + else if(calibration_pair == ANACAL_PAIR_C) |
| 664 | + tx_amp_temp = tx_amp_temp - 1; |
| 665 | + else if(calibration_pair == ANACAL_PAIR_D) |
| 666 | + tx_amp_temp = tx_amp_temp - 1; |
| 667 | + } else if (phyaddr == 2) { |
| 668 | + if (calibration_pair == ANACAL_PAIR_A) |
| 669 | + tx_amp_temp = tx_amp_temp; |
| 670 | + else if(calibration_pair == ANACAL_PAIR_B) |
| 671 | + tx_amp_temp = tx_amp_temp - 1; |
| 672 | + else if(calibration_pair == ANACAL_PAIR_C) |
| 673 | + tx_amp_temp = tx_amp_temp; |
| 674 | + else if(calibration_pair == ANACAL_PAIR_D) |
| 675 | + tx_amp_temp = tx_amp_temp - 1; |
| 676 | + } else if (phyaddr == 3) { |
| 677 | + tx_amp_temp = tx_amp_temp; |
| 678 | + } else if (phyaddr == 4) { |
| 679 | + if (calibration_pair == ANACAL_PAIR_A) |
| 680 | + tx_amp_temp = tx_amp_temp; |
| 681 | + else if(calibration_pair == ANACAL_PAIR_B) |
| 682 | + tx_amp_temp = tx_amp_temp - 1; |
| 683 | + else if(calibration_pair == ANACAL_PAIR_C) |
| 684 | + tx_amp_temp = tx_amp_temp; |
| 685 | + else if(calibration_pair == ANACAL_PAIR_D) |
| 686 | + tx_amp_temp = tx_amp_temp; |
| 687 | + } |
| 688 | + reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00); |
| 689 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift))); |
| 690 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift))); |
| 691 | + if (phyaddr == 0) { |
| 692 | + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) { |
| 693 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 694 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7)); |
| 695 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 696 | + } |
| 697 | + if (tx_amp_reg_100 == 0x16) { |
| 698 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 699 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+1+4)<<tx_amp_reg_shift))); |
| 700 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 701 | + } |
| 702 | + if (tx_amp_reg_100 == 0x18) { |
| 703 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 704 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift))); |
| 705 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 706 | + } |
| 707 | + } else if (phyaddr == 1) { |
| 708 | + if (tx_amp_reg == 0x12) { |
| 709 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 710 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 9)); |
| 711 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 712 | + } |
| 713 | + if (tx_amp_reg == 0x17){ |
| 714 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 715 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7)); |
| 716 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 717 | + } |
| 718 | + if (tx_amp_reg_100 == 0x16) { |
| 719 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 720 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift))); |
| 721 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 722 | + } |
| 723 | + if (tx_amp_reg_100 == 0x18) { |
| 724 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 725 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift))); |
| 726 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 727 | + } |
| 728 | + } else if (phyaddr == 2) { |
| 729 | + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) { |
| 730 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 731 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 6)); |
| 732 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 733 | + } |
| 734 | + if ((tx_amp_reg_100 == 0x16) || (tx_amp_reg_100 == 0x18)) { |
| 735 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 736 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift))); |
| 737 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 738 | + } |
| 739 | + } else if (phyaddr == 3) { |
| 740 | + if (tx_amp_reg == 0x12) { |
| 741 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 742 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 4)); |
| 743 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 744 | + } |
| 745 | + if (tx_amp_reg == 0x17) { |
| 746 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 747 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7)); |
| 748 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 749 | + } |
| 750 | + if (tx_amp_reg_100 == 0x16) { |
| 751 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 752 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift))); |
| 753 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 754 | + } |
| 755 | + if (tx_amp_reg_100 == 0x18) { |
| 756 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 757 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+3)<<tx_amp_reg_shift))); |
| 758 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 759 | + } |
| 760 | + } else if (phyaddr == 4) { |
| 761 | + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) { |
| 762 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 763 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 5)); |
| 764 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 765 | + } |
| 766 | + if (tx_amp_reg_100 == 0x16) { |
| 767 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 768 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift))); |
| 769 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 770 | + } |
| 771 | + if (tx_amp_reg_100 == 0x18) { |
| 772 | + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 773 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift))); |
| 774 | + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100)); |
| 775 | + } |
| 776 | + } |
| 777 | + |
| 778 | + if (calibration_pair == ANACAL_PAIR_A){ |
| 779 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); |
| 780 | + reg_tmp = ((reg_backup & 0xfc00) >> 10); |
| 781 | + reg_tmp -= 8; |
| 782 | + reg_backup = 0x0000; |
| 783 | + reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0)); |
| 784 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup); |
| 785 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); |
| 786 | + //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup); |
| 787 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); |
| 788 | + reg_tmp = ((reg_backup & 0x3f) >> 0); |
| 789 | + reg_tmp -= 8; |
| 790 | + reg_backup = (reg_backup & (~0x3f)); |
| 791 | + reg_backup |= (reg_tmp << 0); |
| 792 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup); |
| 793 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); |
| 794 | + //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup); |
| 795 | + } |
| 796 | + else if(calibration_pair == ANACAL_PAIR_B){ |
| 797 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); |
| 798 | + reg_tmp = ((reg_backup & 0x3f00) >> 8); |
| 799 | + reg_tmp -= 8; |
| 800 | + reg_backup = 0x0000; |
| 801 | + reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0)); |
| 802 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup); |
| 803 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); |
| 804 | + //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup); |
| 805 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); |
| 806 | + reg_tmp = ((reg_backup & 0x3f) >> 0); |
| 807 | + reg_tmp -= 8; |
| 808 | + reg_backup = (reg_backup & (~0x3f)); |
| 809 | + reg_backup |= (reg_tmp << 0); |
| 810 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup); |
| 811 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); |
| 812 | + //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup); |
| 813 | + } |
| 814 | + else if(calibration_pair == ANACAL_PAIR_C){ |
| 815 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); |
| 816 | + reg_tmp = ((reg_backup & 0x3f00) >> 8); |
| 817 | + reg_tmp -= 8; |
| 818 | + reg_backup = (reg_backup & (~0x3f00)); |
| 819 | + reg_backup |= (reg_tmp << 8); |
| 820 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup); |
| 821 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); |
| 822 | + //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup); |
| 823 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); |
| 824 | + reg_tmp = ((reg_backup & 0x3f) >> 0); |
| 825 | + reg_tmp -= 8; |
| 826 | + reg_backup = (reg_backup & (~0x3f)); |
| 827 | + reg_backup |= (reg_tmp << 0); |
| 828 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup); |
| 829 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); |
| 830 | + //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup); |
| 831 | + } |
| 832 | + else if(calibration_pair == ANACAL_PAIR_D){ |
| 833 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); |
| 834 | + reg_tmp = ((reg_backup & 0x3f00) >> 8); |
| 835 | + reg_tmp -= 8; |
| 836 | + reg_backup = (reg_backup & (~0x3f00)); |
| 837 | + reg_backup |= (reg_tmp << 8); |
| 838 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup); |
| 839 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); |
| 840 | + //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup); |
| 841 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); |
| 842 | + reg_tmp = ((reg_backup & 0x3f) >> 0); |
| 843 | + reg_tmp -= 8; |
| 844 | + reg_backup = (reg_backup & (~0x3f)); |
| 845 | + reg_backup |= (reg_tmp << 0); |
| 846 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup); |
| 847 | + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); |
| 848 | + //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup); |
| 849 | + } |
| 850 | + |
| 851 | + if (calibration_pair == ANACAL_PAIR_A){ |
| 852 | + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); |
| 853 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); |
| 854 | + //printk("1e.012 = 0x%x\n", debug_tmp); |
| 855 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); |
| 856 | + //printk("1e.016 = 0x%x\n", debug_tmp); |
| 857 | + } |
| 858 | + |
| 859 | + else if(calibration_pair == ANACAL_PAIR_B){ |
| 860 | + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); |
| 861 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); |
| 862 | + //printk("1e.017 = 0x%x\n", debug_tmp); |
| 863 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); |
| 864 | + //printk("1e.018 = 0x%x\n", debug_tmp); |
| 865 | + } |
| 866 | + else if(calibration_pair == ANACAL_PAIR_C){ |
| 867 | + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); |
| 868 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); |
| 869 | + //printk("1e.019 = 0x%x\n", debug_tmp); |
| 870 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); |
| 871 | + //printk("1e.020 = 0x%x\n", debug_tmp); |
| 872 | + } |
| 873 | + else if(calibration_pair == ANACAL_PAIR_D){ |
| 874 | + //printk("PORT (%d) TX_AMP PAIR (A) FINAL CALIBRATION RESULT\n", phyaddr); |
| 875 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); |
| 876 | + //printk("1e.021 = 0x%x\n", debug_tmp); |
| 877 | + debug_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); |
| 878 | + //printk("1e.022 = 0x%x\n", debug_tmp); |
| 879 | + } |
| 880 | + |
| 881 | + |
| 882 | + printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)); |
| 883 | + |
| 884 | + } else { |
| 885 | + if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) { |
| 886 | + all_ana_cal_status = ANACAL_SATURATION; // need to FT |
| 887 | + printk( " GE Tx amp AnaCal Saturation! \r\n"); |
| 888 | + } |
| 889 | + } |
| 890 | + } |
| 891 | + |
| 892 | + if(all_ana_cal_status == ANACAL_ERROR) { |
| 893 | + tx_amp_temp = 0x20; |
| 894 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift))); |
| 895 | + } |
| 896 | + } |
| 897 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000); |
| 898 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000); |
| 899 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000); |
| 900 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000); |
| 901 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000); |
| 902 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000); |
| 903 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000); |
| 904 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000); |
| 905 | + |
| 906 | + /* disable analog calibration circuit */ |
| 907 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000); |
| 908 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit |
| 909 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000); // disable analog calibration circuit |
| 910 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000); // disable Tx offset calibration circuit |
| 911 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000); // disable Tx VLD force mode |
| 912 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000); // disable Tx offset/amplitude calibration circuit |
| 913 | + |
| 914 | + |
| 915 | + |
| 916 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000); |
| 917 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0x0fff); |
| 918 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1000); |
| 919 | + |
| 920 | + /* Restore CR to default */ |
| 921 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, orig_1e_11); |
| 922 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x300, orig_1f_300); |
| 923 | + |
| 924 | + return 0; |
| 925 | +} |
| 926 | + |
| 927 | +//----------------------------------------------------------------- |
| 928 | + |
| 929 | +int phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr) |
| 930 | +{ |
| 931 | + //u32 reg_tmp,reg_tmp0, reg_tmp1, i; |
| 932 | + u32 reg_tmp; |
| 933 | + u32 CALDLY = 40; |
| 934 | + u32 orig_1e_11, orig_1e_185, orig_1e_e1, orig_1f_100; |
| 935 | + int ret; |
| 936 | + /* set [12]AN disable, [8]full duplex, [13/6]1000Mbps */ |
| 937 | + //tc_phy_write_dev_reg(phyaddr, 0x0, 0x0140); |
| 938 | + switch_phy_write(gsw, phyaddr, R0, 0x140); |
| 939 | + |
| 940 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);/* fix mdi */ |
| 941 | + orig_1e_185 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, RG_185); |
| 942 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);/* disable tx slew control */ |
| 943 | + orig_1f_100 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x100); |
| 944 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);/* BG voltage output */ |
| 945 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099); //bypass efuse |
| 946 | + |
| 947 | +#if (1) |
| 948 | + // 1f_27c[12:8] cr_da_tx_i2mpb_10m Trimming TX bias setup(@10M) |
| 949 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1f1f); |
| 950 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x3300); |
| 951 | + |
| 952 | + //reg_tmp1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x27c); |
| 953 | + //dev1Fh_reg273h TXVLD DA register - Adjust voltage mode TX amplitude. |
| 954 | + //tc_phy_write_dev_reg(phyaddr, 0x1f, 0x273, 0); |
| 955 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x1000); |
| 956 | + //reg_tmp1 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x273); |
| 957 | + //printk("reg_tmp1273 = %x\n", reg_tmp1); |
| 958 | + /*1e_11 TX overshoot Enable (PAIR A/B/C/D) in gbe mode*/ |
| 959 | + |
| 960 | + orig_1e_11 = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11); |
| 961 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11); |
| 962 | + reg_tmp = reg_tmp | (0xf << 12); |
| 963 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, reg_tmp); |
| 964 | + orig_1e_e1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e1); |
| 965 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10); |
| 966 | + /* calibration start ============ */ |
| 967 | + printk("CALDLY = %d\n", CALDLY); |
| 968 | + if(ge_cal_flag == 0){ |
| 969 | + ret = ge_cal_rext(gsw, 0, CALDLY); |
| 970 | + if (ret == -1){ |
| 971 | + printk("ge_cal_rext error K port =%d\n", phyaddr); |
| 972 | + return ret; |
| 973 | + } |
| 974 | + ge_cal_flag = 1; |
| 975 | + } |
| 976 | + |
| 977 | + /* *** R50 Cal start ***************************** */ |
| 978 | + /*phyaddress = 0*/ |
| 979 | + ret = ge_cal_r50(gsw, phyaddr, CALDLY); |
| 980 | + if (ret == -1){ |
| 981 | + printk("R50 error K port =%d\n", phyaddr); |
| 982 | + return ret; |
| 983 | + } |
| 984 | + /* *** R50 Cal end *** */ |
| 985 | + /* *** Tx offset Cal start *********************** */ |
| 986 | + ret = ge_cal_tx_offset(gsw, phyaddr, CALDLY); |
| 987 | + if (ret == -1){ |
| 988 | + printk("ge_cal_tx_offset error K port =%d\n", phyaddr); |
| 989 | + return ret; |
| 990 | + } |
| 991 | + /* *** Tx offset Cal end *** */ |
| 992 | + |
| 993 | + /* *** Tx Amp Cal start *** */ |
| 994 | + ret = ge_cal_tx_amp(gsw, phyaddr, CALDLY); |
| 995 | + if (ret == -1){ |
| 996 | + printk("ge_cal_tx_amp error K port =%d\n", phyaddr); |
| 997 | + return ret; |
| 998 | + } |
| 999 | + /* *** Tx Amp Cal end *** */ |
| 1000 | + /*tmp maybe changed*/ |
| 1001 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1111); |
| 1002 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27b, 0x47); |
| 1003 | + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000); |
| 1004 | + |
| 1005 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a8, 0x0810); |
| 1006 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, 0x0008); |
| 1007 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ab, 0x0810); |
| 1008 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ad, 0x0008); |
| 1009 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ae, 0x0106); |
| 1010 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b0, 0x0001); |
| 1011 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b1, 0x0106); |
| 1012 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b3, 0x0001); |
| 1013 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18c, 0x0001); |
| 1014 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18d, 0x0001); |
| 1015 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18e, 0x0001); |
| 1016 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18f, 0x0001); |
| 1017 | + |
| 1018 | + /*da_tx_bias1_b_tx_standby = 5'b10 (dev1eh_reg3aah[12:8])*/ |
| 1019 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3aa); |
| 1020 | + reg_tmp = reg_tmp & ~(0x1f00); |
| 1021 | + reg_tmp = reg_tmp | 0x2 << 8; |
| 1022 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, reg_tmp); |
| 1023 | + |
| 1024 | + /*da_tx_bias1_a_tx_standby = 5'b10 (dev1eh_reg3a9h[4:0])*/ |
| 1025 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3a9); |
| 1026 | + reg_tmp = reg_tmp & ~(0x1f); |
| 1027 | + reg_tmp = reg_tmp | 0x2; |
| 1028 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a9, reg_tmp); |
| 1029 | + |
| 1030 | + /* Restore CR to default */ |
| 1031 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, orig_1e_185); |
| 1032 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, orig_1f_100); |
| 1033 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, orig_1e_11); |
| 1034 | + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, orig_1e_e1); |
| 1035 | +#endif |
| 1036 | + return 0; |
| 1037 | +} |
| 1038 | + |
| 1039 | +void rx_dc_offset(struct gsw_mt753x *gsw, u8 phyaddr) |
| 1040 | +{ |
| 1041 | + pr_info("PORT %d RX_DC_OFFSET\n", phyaddr); |
| 1042 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x96, 0x8000); |
| 1043 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x37, 0x3); |
| 1044 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x107, 0x4000); |
| 1045 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x1e5); |
| 1046 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x200f); |
| 1047 | + udelay(40); |
| 1048 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x000f); |
| 1049 | + udelay(40); |
| 1050 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x65); |
| 1051 | +} |
| 1052 | + |
| 1053 | +void check_rx_dc_offset_pair_a(struct gsw_mt753x *gsw, u8 phyaddr) |
| 1054 | +{ |
| 1055 | + u32 reg_tmp; |
| 1056 | + |
| 1057 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x114f); |
| 1058 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1059 | + reg_tmp = reg_tmp & 0xff; |
| 1060 | + pr_info("before pairA output = %x\n", reg_tmp); |
| 1061 | + udelay(40); |
| 1062 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1142); |
| 1063 | + udelay(40); |
| 1064 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1065 | + reg_tmp = reg_tmp & 0xff; |
| 1066 | + pr_info("after pairA output = %x\n", reg_tmp); |
| 1067 | + if ((reg_tmp & 0x80) != 0) |
| 1068 | + reg_tmp = (~reg_tmp) + 1; |
| 1069 | + if ((reg_tmp & 0xff) >4) |
| 1070 | + pr_info("pairA RX_DC_OFFSET error"); |
| 1071 | +} |
| 1072 | + |
| 1073 | +void check_rx_dc_offset_pair_b(struct gsw_mt753x *gsw, u8 phyaddr) |
| 1074 | +{ |
| 1075 | + u32 reg_tmp; |
| 1076 | + |
| 1077 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151); |
| 1078 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1079 | + reg_tmp = reg_tmp & 0xff; |
| 1080 | + pr_info("before pairB output = %x\n", reg_tmp); |
| 1081 | + udelay(40); |
| 1082 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143); |
| 1083 | + udelay(40); |
| 1084 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1085 | + reg_tmp = reg_tmp & 0xff; |
| 1086 | + pr_info("after pairB output = %x\n", reg_tmp); |
| 1087 | + if ((reg_tmp & 0x80) != 0) |
| 1088 | + reg_tmp = (~reg_tmp) + 1; |
| 1089 | + if ((reg_tmp & 0xff) >4) |
| 1090 | + pr_info("pairB RX_DC_OFFSET error"); |
| 1091 | +} |
| 1092 | + |
| 1093 | +void check_rx_dc_offset_pair_c(struct gsw_mt753x *gsw, u8 phyaddr) |
| 1094 | +{ |
| 1095 | + u32 reg_tmp; |
| 1096 | + |
| 1097 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153); |
| 1098 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1099 | + reg_tmp = reg_tmp & 0xff; |
| 1100 | + pr_info("before pairC output = %x\n", reg_tmp); |
| 1101 | + udelay(40); |
| 1102 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144); |
| 1103 | + udelay(40); |
| 1104 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1105 | + reg_tmp = reg_tmp & 0xff; |
| 1106 | + pr_info("after pairC output = %x\n", reg_tmp); |
| 1107 | + if ((reg_tmp & 0x80) != 0) |
| 1108 | + reg_tmp = (~reg_tmp) + 1; |
| 1109 | + if ((reg_tmp & 0xff) >4) |
| 1110 | + pr_info("pairC RX_DC_OFFSET error"); |
| 1111 | +} |
| 1112 | + |
| 1113 | +void check_rx_dc_offset_pair_d(struct gsw_mt753x *gsw, u8 phyaddr) |
| 1114 | +{ |
| 1115 | + u32 reg_tmp; |
| 1116 | + |
| 1117 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155); |
| 1118 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1119 | + reg_tmp = reg_tmp & 0xff; |
| 1120 | + pr_info("before pairD output = %x\n", reg_tmp); |
| 1121 | + udelay(40); |
| 1122 | + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145); |
| 1123 | + udelay(40); |
| 1124 | + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a); |
| 1125 | + reg_tmp = reg_tmp & 0xff; |
| 1126 | + pr_info("after pairD output = %x\n", reg_tmp); |
| 1127 | + if ((reg_tmp & 0x80) != 0) |
| 1128 | + reg_tmp = (~reg_tmp) + 1; |
| 1129 | + if ((reg_tmp & 0xff) >4) |
| 1130 | + pr_info("pairD RX_DC_OFFSET error"); |
| 1131 | +} |
| 1132 | + |
| 1133 | + |
| 1134 | +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr){ |
| 1135 | + |
| 1136 | + int ret; |
| 1137 | + |
| 1138 | + ret = phy_calibration(gsw, phyaddr); |
| 1139 | + |
| 1140 | + rx_dc_offset(gsw, phyaddr); |
| 1141 | + check_rx_dc_offset_pair_a(gsw, phyaddr); |
| 1142 | + check_rx_dc_offset_pair_b(gsw, phyaddr); |
| 1143 | + check_rx_dc_offset_pair_c(gsw, phyaddr); |
| 1144 | + check_rx_dc_offset_pair_d(gsw, phyaddr); |
| 1145 | + |
| 1146 | + return ret; |
| 1147 | +} |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1148 | diff --git a/drivers/net/phy/mtk/mt753x/mt753x_phy.h b/drivers/net/phy/mtk/mt753x/mt753x_phy.h |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1149 | new file mode 100644 |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1150 | index 000000000..1b9e2ea80 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1151 | --- /dev/null |
| 1152 | +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.h |
| 1153 | @@ -0,0 +1,145 @@ |
| 1154 | +/* SPDX-License-Identifier: GPL-2.0+ */ |
| 1155 | +/* |
| 1156 | + * Register definitions for MediaTek MT753x Gigabit switches |
| 1157 | + * |
| 1158 | + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved. |
| 1159 | + * |
| 1160 | + * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 1161 | + */ |
| 1162 | + |
| 1163 | +#ifndef _MT753X_PHY_H_ |
| 1164 | +#define _MT753X_PHY_H_ |
| 1165 | + |
| 1166 | +#include <linux/bitops.h> |
| 1167 | + |
| 1168 | +/*phy calibration use*/ |
| 1169 | +#define DEV_1E 0x1E |
| 1170 | +/*global device 0x1f, always set P0*/ |
| 1171 | +#define DEV_1F 0x1F |
| 1172 | + |
| 1173 | + |
| 1174 | +/************IEXT/REXT CAL***************/ |
| 1175 | +/* bits range: for example BITS(16,23) = 0xFF0000*/ |
| 1176 | +#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n))) |
| 1177 | +#define ANACAL_INIT 0x01 |
| 1178 | +#define ANACAL_ERROR 0xFD |
| 1179 | +#define ANACAL_SATURATION 0xFE |
| 1180 | +#define ANACAL_FINISH 0xFF |
| 1181 | +#define ANACAL_PAIR_A 0 |
| 1182 | +#define ANACAL_PAIR_B 1 |
| 1183 | +#define ANACAL_PAIR_C 2 |
| 1184 | +#define ANACAL_PAIR_D 3 |
| 1185 | +#define DAC_IN_0V 0x00 |
| 1186 | +#define DAC_IN_2V 0xf0 |
| 1187 | +#define TX_AMP_OFFSET_0MV 0x20 |
| 1188 | +#define TX_AMP_OFFSET_VALID_BITS 6 |
| 1189 | + |
| 1190 | +#define R0 0 |
| 1191 | +#define PHY0 0 |
| 1192 | +#define PHY1 1 |
| 1193 | +#define PHY2 2 |
| 1194 | +#define PHY3 3 |
| 1195 | +#define PHY4 4 |
| 1196 | +#define ANA_TEST_MODE BITS(8, 15) |
| 1197 | +#define TST_TCLK_SEL BITs(6, 7) |
| 1198 | +#define ANA_TEST_VGA_RG 0x100 |
| 1199 | + |
| 1200 | +#define FORCE_MDI_CROSS_OVER BITS(3, 4) |
| 1201 | +#define T10_TEST_CTL_RG 0x145 |
| 1202 | +#define RG_185 0x185 |
| 1203 | +#define RG_TX_SLEW BIT(0) |
| 1204 | +#define ANA_CAL_0 0xdb |
| 1205 | +#define RG_CAL_CKINV BIT(12) |
| 1206 | +#define RG_ANA_CALEN BIT(8) |
| 1207 | +#define RG_REXT_CALEN BIT(4) |
| 1208 | +#define RG_ZCALEN_A BIT(0) |
| 1209 | +#define ANA_CAL_1 0xdc |
| 1210 | +#define RG_ZCALEN_B BIT(12) |
| 1211 | +#define RG_ZCALEN_C BIT(8) |
| 1212 | +#define RG_ZCALEN_D BIT(4) |
| 1213 | +#define RG_TXVOS_CALEN BIT(0) |
| 1214 | +#define ANA_CAL_6 0xe1 |
| 1215 | +#define RG_CAL_REFSEL BIT(4) |
| 1216 | +#define RG_CAL_COMP_PWD BIT(0) |
| 1217 | +#define ANA_CAL_5 0xe0 |
| 1218 | +#define RG_REXT_TRIM BITs(8, 13) |
| 1219 | +#define RG_ZCAL_CTRL BITs(0, 5) |
| 1220 | +#define RG_17A 0x17a |
| 1221 | +#define AD_CAL_COMP_OUT BIT(8) |
| 1222 | +#define RG_17B 0x17b |
| 1223 | +#define AD_CAL_CLK bit(0) |
| 1224 | +#define RG_17C 0x17c |
| 1225 | +#define DA_CALIN_FLAG bit(0) |
| 1226 | +/************R50 CAL****************************/ |
| 1227 | +#define RG_174 0x174 |
| 1228 | +#define RG_R50OHM_RSEL_TX_A_EN BIT[15] |
| 1229 | +#define CR_R50OHM_RSEL_TX_A BITS[8:14] |
| 1230 | +#define RG_R50OHM_RSEL_TX_B_EN BIT[7] |
| 1231 | +#define CR_R50OHM_RSEL_TX_B BITS[6:0] |
| 1232 | +#define RG_175 0x175 |
| 1233 | +#define RG_R50OHM_RSEL_TX_C_EN BITS[15] |
| 1234 | +#define CR_R50OHM_RSEL_TX_C BITS[8:14] |
| 1235 | +#define RG_R50OHM_RSEL_TX_D_EN BIT[7] |
| 1236 | +#define CR_R50OHM_RSEL_TX_D BITS[0:6] |
| 1237 | +/**********TX offset Calibration***************************/ |
| 1238 | +#define RG_95 0x96 |
| 1239 | +#define BYPASS_TX_OFFSET_CAL BIT(15) |
| 1240 | +#define RG_3E 0x3e |
| 1241 | +#define BYPASS_PD_TXVLD_A BIT(15) |
| 1242 | +#define BYPASS_PD_TXVLD_B BIT(14) |
| 1243 | +#define BYPASS_PD_TXVLD_C BIT(13) |
| 1244 | +#define BYPASS_PD_TXVLD_D BIT(12) |
| 1245 | +#define BYPASS_PD_TX_10M BIT(11) |
| 1246 | +#define POWER_DOWN_TXVLD_A BIT(7) |
| 1247 | +#define POWER_DOWN_TXVLD_B BIT(6) |
| 1248 | +#define POWER_DOWN_TXVLD_C BIT(5) |
| 1249 | +#define POWER_DOWN_TXVLD_D BIT(4) |
| 1250 | +#define POWER_DOWN_TX_10M BIT(3) |
| 1251 | +#define RG_DD 0xdd |
| 1252 | +#define RG_TXG_CALEN_A BIT(12) |
| 1253 | +#define RG_TXG_CALEN_B BIT(8) |
| 1254 | +#define RG_TXG_CALEN_C BIT(4) |
| 1255 | +#define RG_TXG_CALEN_D BIT(0) |
| 1256 | +#define RG_17D 0x17D |
| 1257 | +#define FORCE_DASN_DAC_IN0_A BIT(15) |
| 1258 | +#define DASN_DAC_IN0_A BITS(0, 9) |
| 1259 | +#define RG_17E 0x17E |
| 1260 | +#define FORCE_DASN_DAC_IN0_B BIT(15) |
| 1261 | +#define DASN_DAC_IN0_B BITS(0, 9) |
| 1262 | +#define RG_17F 0x17F |
| 1263 | + |
| 1264 | +#define FORCE_DASN_DAC_IN0_C BIT(15) |
| 1265 | +#define DASN_DAC_IN0_C BITS(0, 9) |
| 1266 | +#define RG_180 0x180 |
| 1267 | +#define FORCE_DASN_DAC_IN0_D BIT(15) |
| 1268 | +#define DASN_DAC_IN0_D BITS(0, 9) |
| 1269 | + |
| 1270 | +#define RG_181 0x181 |
| 1271 | +#define FORCE_DASN_DAC_IN1_A BIT(15) |
| 1272 | +#define DASN_DAC_IN1_A BITS(0, 9) |
| 1273 | +#define RG_182 0x182 |
| 1274 | +#define FORCE_DASN_DAC_IN1_B BIT(15) |
| 1275 | +#define DASN_DAC_IN1_B BITS(0, 9) |
| 1276 | +#define RG_183 0x183 |
| 1277 | +#define FORCE_DASN_DAC_IN1_C BIT15] |
| 1278 | +#define DASN_DAC_IN1_C BITS(0, 9) |
| 1279 | +#define RG_184 0x184 |
| 1280 | +#define FORCE_DASN_DAC_IN1_D BIT(15) |
| 1281 | +#define DASN_DAC_IN1_D BITS(0, 9) |
| 1282 | +#define RG_172 0x172 |
| 1283 | +#define CR_TX_AMP_OFFSET_A BITS(8, 13) |
| 1284 | +#define CR_TX_AMP_OFFSET_B BITS(0, 5) |
| 1285 | +#define RG_173 0x173 |
| 1286 | +#define CR_TX_AMP_OFFSET_C BITS(8, 13) |
| 1287 | +#define CR_TX_AMP_OFFSET_D BITS(0, 5) |
| 1288 | +/**********TX Amp Calibration ***************************/ |
| 1289 | +#define RG_12 0x12 |
| 1290 | +#define DA_TX_I2MPB_A_GBE BITS(10, 15) |
| 1291 | +#define RG_17 0x17 |
| 1292 | +#define DA_TX_I2MPB_B_GBE BITS(8, 13) |
| 1293 | +#define RG_19 0x19 |
| 1294 | +#define DA_TX_I2MPB_C_GBE BITS(8, 13) |
| 1295 | +#define RG_21 0x21 |
| 1296 | +#define DA_TX_I2MPB_D_GBE BITS(8, 13) |
| 1297 | + |
| 1298 | +#endif /* _MT753X_REGS_H_ */ |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1299 | -- |
| 1300 | 2.34.1 |
| 1301 | |