developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988C DSA 10G SNFI-NAND RFB"; |
| 12 | compatible = "mediatek,mt7988c-dsa-10g-snfi-snand", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0 0x40000000 0 0x10000000>; |
| 24 | }; |
| 25 | |
| 26 | nmbm_snfi { |
| 27 | compatible = "generic,nmbm"; |
| 28 | |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | |
| 32 | lower-mtd-device = <&snand>; |
| 33 | forced-create; |
| 34 | empty-page-ecc-protected; |
| 35 | |
| 36 | partitions { |
| 37 | compatible = "fixed-partitions"; |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <1>; |
| 40 | |
| 41 | partition@0 { |
| 42 | label = "BL2"; |
| 43 | reg = <0x00000 0x0100000>; |
| 44 | read-only; |
| 45 | }; |
| 46 | |
| 47 | partition@100000 { |
| 48 | label = "u-boot-env"; |
| 49 | reg = <0x0100000 0x0080000>; |
| 50 | }; |
| 51 | |
| 52 | factory: partition@180000 { |
| 53 | label = "Factory"; |
| 54 | reg = <0x180000 0x0400000>; |
| 55 | }; |
| 56 | |
| 57 | partition@580000 { |
| 58 | label = "FIP"; |
| 59 | reg = <0x580000 0x0200000>; |
| 60 | }; |
| 61 | |
| 62 | partition@780000 { |
| 63 | label = "ubi"; |
developer | ba03dd7 | 2023-04-28 10:12:23 +0800 | [diff] [blame^] | 64 | reg = <0x780000 0x7080000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 65 | }; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | wsys_adie: wsys_adie@0 { |
| 70 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 71 | compatible = "mediatek,rebb-mt7988-adie"; |
| 72 | adie_id = <7976>; |
| 73 | sku_type = <3000>; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | &fan { |
| 78 | pwms = <&pwm 0 50000 0>; |
| 79 | status = "okay"; |
| 80 | }; |
| 81 | |
| 82 | &pwm { |
| 83 | status = "okay"; |
| 84 | }; |
| 85 | |
| 86 | &uart0 { |
| 87 | status = "okay"; |
| 88 | }; |
| 89 | |
| 90 | &spi1 { |
| 91 | pinctrl-names = "default"; |
| 92 | /* pin shared with snfi */ |
| 93 | pinctrl-0 = <&spic_pins>; |
| 94 | status = "disabled"; |
| 95 | }; |
| 96 | |
| 97 | &pcie0 { |
| 98 | pinctrl-names = "default"; |
| 99 | pinctrl-0 = <&pcie0_pins>; |
| 100 | status = "okay"; |
| 101 | }; |
| 102 | |
| 103 | &pcie1 { |
| 104 | pinctrl-names = "default"; |
| 105 | pinctrl-0 = <&pcie1_pins>; |
| 106 | status = "disabled"; |
| 107 | }; |
| 108 | |
| 109 | &pcie2 { |
| 110 | pinctrl-names = "default"; |
| 111 | pinctrl-0 = <&pcie2_pins>; |
| 112 | status = "disabled"; |
| 113 | }; |
| 114 | |
| 115 | &pcie3 { |
| 116 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pcie3_pins>; |
| 118 | status = "okay"; |
| 119 | }; |
| 120 | |
| 121 | &pio { |
| 122 | mdio0_pins: mdio0-pins { |
| 123 | mux { |
| 124 | function = "mdio"; |
| 125 | groups = "mdc_mdio0"; |
| 126 | }; |
| 127 | |
| 128 | conf { |
| 129 | groups = "mdc_mdio0"; |
| 130 | drive-strength = <MTK_DRIVE_8mA>; |
| 131 | }; |
| 132 | }; |
| 133 | |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 134 | gbe_led0_pins: gbe-pins { |
| 135 | mux { |
| 136 | function = "led"; |
| 137 | groups = "gbe_led0"; |
| 138 | }; |
| 139 | }; |
| 140 | |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 141 | i2p5gbe_led0_pins: 2p5gbe-pins { |
| 142 | mux { |
| 143 | function = "led"; |
| 144 | groups = "2p5gbe_led0"; |
| 145 | }; |
| 146 | }; |
| 147 | |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 148 | pcie0_pins: pcie0-pins { |
| 149 | mux { |
| 150 | function = "pcie"; |
| 151 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 152 | "pcie_wake_n0_0"; |
| 153 | }; |
| 154 | }; |
| 155 | |
| 156 | pcie1_pins: pcie1-pins { |
| 157 | mux { |
| 158 | function = "pcie"; |
| 159 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 160 | "pcie_wake_n1_0"; |
| 161 | }; |
| 162 | }; |
| 163 | |
| 164 | pcie2_pins: pcie2-pins { |
| 165 | mux { |
| 166 | function = "pcie"; |
| 167 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 168 | "pcie_wake_n2_0"; |
| 169 | }; |
| 170 | }; |
| 171 | |
| 172 | pcie3_pins: pcie3-pins { |
| 173 | mux { |
| 174 | function = "pcie"; |
| 175 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 176 | "pcie_wake_n3_0"; |
| 177 | }; |
| 178 | }; |
| 179 | |
| 180 | snfi_pins: snfi-pins { |
| 181 | mux { |
| 182 | function = "flash"; |
| 183 | groups = "snfi"; |
| 184 | }; |
| 185 | }; |
| 186 | |
| 187 | spic_pins: spi1-pins { |
| 188 | mux { |
| 189 | function = "spi"; |
developer | 1ceb26a | 2023-02-16 15:43:43 +0800 | [diff] [blame] | 190 | groups = "spi1"; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 191 | }; |
| 192 | }; |
| 193 | }; |
| 194 | |
| 195 | &watchdog { |
| 196 | status = "disabled"; |
| 197 | }; |
| 198 | |
| 199 | &snand { |
| 200 | pinctrl-names = "default"; |
| 201 | /* pin shared with spic */ |
| 202 | pinctrl-0 = <&snfi_pins>; |
| 203 | status = "okay"; |
| 204 | mediatek,quad-spi; |
| 205 | }; |
| 206 | |
| 207 | ð { |
| 208 | pinctrl-names = "default"; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 209 | pinctrl-0 = <&mdio0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 210 | status = "okay"; |
| 211 | |
| 212 | gmac0: mac@0 { |
| 213 | compatible = "mediatek,eth-mac"; |
| 214 | reg = <0>; |
| 215 | mac-type = "xgdm"; |
| 216 | phy-mode = "10gbase-kr"; |
| 217 | |
| 218 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 219 | speed = <10000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 220 | full-duplex; |
| 221 | pause; |
| 222 | }; |
| 223 | }; |
| 224 | |
| 225 | gmac1: mac@1 { |
| 226 | compatible = "mediatek,eth-mac"; |
| 227 | reg = <1>; |
| 228 | mac-type = "xgdm"; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 229 | phy-mode = "xgmii"; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 230 | phy-handle = <&phy0>; |
| 231 | }; |
| 232 | |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 233 | gmac2: mac@2 { |
| 234 | compatible = "mediatek,eth-mac"; |
| 235 | reg = <2>; |
| 236 | mac-type = "xgdm"; |
| 237 | phy-mode = "usxgmii"; |
| 238 | phy-handle = <&phy1>; |
| 239 | }; |
| 240 | |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 241 | mdio: mdio-bus { |
| 242 | #address-cells = <1>; |
| 243 | #size-cells = <0>; |
developer | c4d8da7 | 2023-03-16 14:37:28 +0800 | [diff] [blame] | 244 | clock-frequency = <10500000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 245 | |
| 246 | phy0: ethernet-phy@0 { |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 247 | pinctrl-names = "default"; |
| 248 | pinctrl-0 = <&i2p5gbe_led0_pins>; |
| 249 | reg = <15>; |
| 250 | compatible = "ethernet-phy-ieee802.3-c45"; |
| 251 | phy-mode = "xgmii"; |
| 252 | }; |
| 253 | |
| 254 | phy1: ethernet-phy@8 { |
| 255 | reg = <8>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 256 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | b4a8e1f | 2023-04-28 10:18:42 +0800 | [diff] [blame] | 257 | reset-gpios = <&pio 3 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 258 | reset-assert-us = <100000>; |
| 259 | reset-deassert-us = <221000>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 260 | }; |
| 261 | |
| 262 | switch@0 { |
| 263 | compatible = "mediatek,mt7988"; |
| 264 | reg = <31>; |
| 265 | ports { |
| 266 | #address-cells = <1>; |
| 267 | #size-cells = <0>; |
| 268 | |
| 269 | port@0 { |
| 270 | reg = <0>; |
| 271 | label = "lan0"; |
| 272 | phy-mode = "gmii"; |
| 273 | phy-handle = <&sphy0>; |
| 274 | }; |
| 275 | |
| 276 | port@1 { |
| 277 | reg = <1>; |
| 278 | label = "lan1"; |
| 279 | phy-mode = "gmii"; |
| 280 | phy-handle = <&sphy1>; |
| 281 | }; |
| 282 | |
| 283 | port@2 { |
| 284 | reg = <2>; |
| 285 | label = "lan2"; |
| 286 | phy-mode = "gmii"; |
| 287 | phy-handle = <&sphy2>; |
| 288 | }; |
| 289 | |
| 290 | port@3 { |
| 291 | reg = <3>; |
| 292 | label = "lan3"; |
| 293 | phy-mode = "gmii"; |
| 294 | phy-handle = <&sphy3>; |
| 295 | }; |
| 296 | |
| 297 | port@6 { |
| 298 | reg = <6>; |
| 299 | label = "cpu"; |
| 300 | ethernet = <&gmac0>; |
| 301 | phy-mode = "10gbase-kr"; |
| 302 | |
| 303 | fixed-link { |
| 304 | speed = <10000>; |
| 305 | full-duplex; |
| 306 | pause; |
| 307 | }; |
| 308 | }; |
| 309 | }; |
| 310 | |
| 311 | mdio { |
| 312 | compatible = "mediatek,dsa-slave-mdio"; |
| 313 | #address-cells = <1>; |
| 314 | #size-cells = <0>; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 315 | pinctrl-names = "default"; |
| 316 | pinctrl-0 = <&gbe_led0_pins>; |
developer | c54ce9d | 2023-01-03 13:30:49 +0800 | [diff] [blame] | 317 | |
| 318 | sphy0: switch_phy0@0 { |
| 319 | compatible = "ethernet-phy-id03a2.9481"; |
| 320 | reg = <0>; |
| 321 | phy-mode = "gmii"; |
| 322 | rext = "efuse"; |
| 323 | tx_r50 = "efuse"; |
| 324 | nvmem-cells = <&phy_calibration_p0>; |
| 325 | nvmem-cell-names = "phy-cal-data"; |
| 326 | }; |
| 327 | |
| 328 | sphy1: switch_phy1@1 { |
| 329 | compatible = "ethernet-phy-id03a2.9481"; |
| 330 | reg = <1>; |
| 331 | phy-mode = "gmii"; |
| 332 | rext = "efuse"; |
| 333 | tx_r50 = "efuse"; |
| 334 | nvmem-cells = <&phy_calibration_p1>; |
| 335 | nvmem-cell-names = "phy-cal-data"; |
| 336 | }; |
| 337 | |
| 338 | sphy2: switch_phy2@2 { |
| 339 | compatible = "ethernet-phy-id03a2.9481"; |
| 340 | reg = <2>; |
| 341 | phy-mode = "gmii"; |
| 342 | rext = "efuse"; |
| 343 | tx_r50 = "efuse"; |
| 344 | nvmem-cells = <&phy_calibration_p2>; |
| 345 | nvmem-cell-names = "phy-cal-data"; |
| 346 | }; |
| 347 | |
| 348 | sphy3: switch_phy3@3 { |
| 349 | compatible = "ethernet-phy-id03a2.9481"; |
| 350 | reg = <3>; |
| 351 | phy-mode = "gmii"; |
| 352 | rext = "efuse"; |
| 353 | tx_r50 = "efuse"; |
| 354 | nvmem-cells = <&phy_calibration_p3>; |
| 355 | nvmem-cell-names = "phy-cal-data"; |
| 356 | }; |
| 357 | }; |
| 358 | }; |
| 359 | }; |
| 360 | }; |
| 361 | |
| 362 | &hnat { |
| 363 | mtketh-wan = "eth1"; |
| 364 | mtketh-lan = "lan"; |
| 365 | mtketh-lan2 = "eth2"; |
| 366 | mtketh-max-gmac = <3>; |
| 367 | status = "okay"; |
| 368 | }; |