developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 1 | /dts-v1/; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 2 | #include "mt7986a.dtsi" |
| 3 | #include "mt7986a-pinctrl.dtsi" |
developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 4 | / { |
| 5 | model = "MediaTek MT7986a RFB"; |
| 6 | compatible = "mediatek,mt7986a-emmc-rfb"; |
developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 7 | chosen { |
| 8 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 9 | earlycon=uart8250,mmio32,0x11002000 \ |
developer | 8262b0d | 2021-11-12 09:02:17 +0800 | [diff] [blame] | 10 | root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; |
developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 11 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | reg_1p8v: regulator-1p8v { |
| 18 | compatible = "regulator-fixed"; |
| 19 | regulator-name = "fixed-1.8V"; |
| 20 | regulator-min-microvolt = <1800000>; |
| 21 | regulator-max-microvolt = <1800000>; |
| 22 | regulator-boot-on; |
| 23 | regulator-always-on; |
| 24 | }; |
| 25 | |
| 26 | reg_3p3v: regulator-3p3v { |
| 27 | compatible = "regulator-fixed"; |
| 28 | regulator-name = "fixed-3.3V"; |
| 29 | regulator-min-microvolt = <3300000>; |
| 30 | regulator-max-microvolt = <3300000>; |
| 31 | regulator-boot-on; |
| 32 | regulator-always-on; |
| 33 | }; |
| 34 | |
developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 35 | sound_wm8960 { |
| 36 | compatible = "mediatek,mt79xx-wm8960-machine"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 37 | mediatek,platform = <&afe>; |
| 38 | audio-routing = "Headphone", "HP_L", |
| 39 | "Headphone", "HP_R", |
| 40 | "LINPUT1", "AMIC", |
| 41 | "RINPUT1", "AMIC"; |
| 42 | mediatek,audio-codec = <&wm8960>; |
| 43 | status = "okay"; |
| 44 | }; |
developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 45 | |
| 46 | sound_si3218x { |
| 47 | compatible = "mediatek,mt79xx-si3218x-machine"; |
| 48 | mediatek,platform = <&afe>; |
| 49 | mediatek,ext-codec = <&proslic_spi>; |
| 50 | status = "okay"; |
| 51 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 52 | }; |
| 53 | |
developer | 209e52d | 2022-06-30 11:32:57 +0800 | [diff] [blame] | 54 | &fan { |
| 55 | pwms = <&pwm 1 50000 0>; |
| 56 | status = "disabled"; |
| 57 | }; |
| 58 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 59 | &pwm { |
| 60 | pinctrl-names = "default"; |
| 61 | pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>; |
| 62 | status = "okay"; |
| 63 | }; |
| 64 | |
| 65 | &uart0 { |
| 66 | status = "okay"; |
| 67 | }; |
| 68 | |
| 69 | &uart1 { |
| 70 | pinctrl-names = "default"; |
| 71 | pinctrl-0 = <&uart1_pins>; |
| 72 | status = "okay"; |
| 73 | }; |
| 74 | |
| 75 | &uart2 { |
| 76 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = <&uart2_pins>; |
| 78 | status = "okay"; |
| 79 | }; |
| 80 | |
| 81 | &i2c0 { |
| 82 | pinctrl-names = "default"; |
| 83 | pinctrl-0 = <&i2c_pins>; |
| 84 | status = "okay"; |
| 85 | |
| 86 | wm8960: wm8960@1a { |
| 87 | compatible = "wlf,wm8960"; |
| 88 | reg = <0x1a>; |
| 89 | }; |
| 90 | }; |
| 91 | |
| 92 | &auxadc { |
| 93 | status = "okay"; |
| 94 | }; |
| 95 | |
| 96 | &watchdog { |
| 97 | status = "okay"; |
| 98 | }; |
| 99 | |
| 100 | ð { |
| 101 | status = "okay"; |
| 102 | |
| 103 | gmac0: mac@0 { |
| 104 | compatible = "mediatek,eth-mac"; |
| 105 | reg = <0>; |
| 106 | phy-mode = "2500base-x"; |
| 107 | |
| 108 | fixed-link { |
| 109 | speed = <2500>; |
| 110 | full-duplex; |
| 111 | pause; |
| 112 | }; |
| 113 | }; |
| 114 | |
| 115 | gmac1: mac@1 { |
| 116 | compatible = "mediatek,eth-mac"; |
| 117 | reg = <1>; |
| 118 | phy-mode = "2500base-x"; |
| 119 | |
| 120 | fixed-link { |
| 121 | speed = <2500>; |
| 122 | full-duplex; |
| 123 | pause; |
| 124 | }; |
| 125 | }; |
| 126 | |
| 127 | mdio: mdio-bus { |
| 128 | #address-cells = <1>; |
| 129 | #size-cells = <0>; |
| 130 | |
| 131 | phy5: phy@5 { |
| 132 | compatible = "ethernet-phy-id67c9.de0a"; |
| 133 | reg = <5>; |
| 134 | reset-gpios = <&pio 6 1>; |
developer | 8c5a08b | 2022-05-06 09:10:38 +0800 | [diff] [blame] | 135 | reset-assert-us = <600>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 136 | reset-deassert-us = <20000>; |
| 137 | phy-mode = "2500base-x"; |
| 138 | }; |
| 139 | |
| 140 | phy6: phy@6 { |
| 141 | compatible = "ethernet-phy-id67c9.de0a"; |
| 142 | reg = <6>; |
| 143 | phy-mode = "2500base-x"; |
| 144 | }; |
| 145 | |
| 146 | switch@0 { |
| 147 | compatible = "mediatek,mt7531"; |
| 148 | reg = <31>; |
| 149 | reset-gpios = <&pio 5 0>; |
| 150 | |
| 151 | ports { |
| 152 | #address-cells = <1>; |
| 153 | #size-cells = <0>; |
| 154 | |
| 155 | port@0 { |
| 156 | reg = <0>; |
| 157 | label = "lan0"; |
| 158 | }; |
| 159 | |
| 160 | port@1 { |
| 161 | reg = <1>; |
| 162 | label = "lan1"; |
| 163 | }; |
| 164 | |
| 165 | port@2 { |
| 166 | reg = <2>; |
| 167 | label = "lan2"; |
| 168 | }; |
| 169 | |
| 170 | port@3 { |
| 171 | reg = <3>; |
| 172 | label = "lan3"; |
| 173 | }; |
| 174 | |
| 175 | port@6 { |
| 176 | reg = <6>; |
| 177 | label = "cpu"; |
| 178 | ethernet = <&gmac0>; |
| 179 | phy-mode = "2500base-x"; |
| 180 | |
| 181 | fixed-link { |
| 182 | speed = <2500>; |
| 183 | full-duplex; |
| 184 | pause; |
| 185 | }; |
| 186 | }; |
| 187 | }; |
| 188 | }; |
| 189 | }; |
developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 190 | }; |
| 191 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 192 | &hnat { |
| 193 | mtketh-wan = "eth1"; |
| 194 | mtketh-lan = "lan"; |
| 195 | mtketh-max-gmac = <2>; |
| 196 | status = "okay"; |
| 197 | }; |
| 198 | |
| 199 | &spi1 { |
| 200 | pinctrl-names = "default"; |
| 201 | pinctrl-0 = <&spic_pins_g2>; |
| 202 | status = "okay"; |
developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 203 | |
| 204 | proslic_spi: proslic_spi@0 { |
| 205 | compatible = "silabs,proslic_spi"; |
| 206 | reg = <0>; |
| 207 | spi-max-frequency = <10000000>; |
| 208 | spi-cpha = <1>; |
| 209 | spi-cpol = <1>; |
| 210 | channel_count = <1>; |
| 211 | debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ |
| 212 | reset_gpio = <&pio 7 0>; |
| 213 | ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ |
| 214 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 215 | }; |
| 216 | |
| 217 | &mmc0 { |
| 218 | pinctrl-names = "default", "state_uhs"; |
| 219 | pinctrl-0 = <&mmc0_pins_default>; |
| 220 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 221 | bus-width = <8>; |
| 222 | max-frequency = <200000000>; |
| 223 | cap-mmc-highspeed; |
| 224 | mmc-hs200-1_8v; |
| 225 | mmc-hs400-1_8v; |
| 226 | hs400-ds-delay = <0x14014>; |
| 227 | vmmc-supply = <®_3p3v>; |
| 228 | vqmmc-supply = <®_1p8v>; |
| 229 | non-removable; |
| 230 | no-sd; |
| 231 | no-sdio; |
| 232 | status = "okay"; |
developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 233 | }; |
| 234 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 235 | &pcie0 { |
| 236 | pinctrl-names = "default"; |
| 237 | pinctrl-0 = <&pcie0_pins>; |
| 238 | status = "okay"; |
| 239 | }; |
| 240 | |
| 241 | &wbsys { |
| 242 | status = "okay"; |
| 243 | }; |
| 244 | |
| 245 | &pio { |
| 246 | mmc0_pins_default: mmc0-pins-50-to-61-default { |
| 247 | mux { |
| 248 | function = "flash"; |
| 249 | groups = "emmc_51"; |
| 250 | }; |
| 251 | conf-cmd-dat { |
| 252 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 253 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 254 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 255 | input-enable; |
| 256 | drive-strength = <MTK_DRIVE_4mA>; |
| 257 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 258 | }; |
| 259 | conf-clk { |
| 260 | pins = "EMMC_CK"; |
| 261 | drive-strength = <MTK_DRIVE_6mA>; |
| 262 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 263 | }; |
| 264 | conf-ds { |
| 265 | pins = "EMMC_DSL"; |
| 266 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 267 | }; |
| 268 | conf-rst { |
| 269 | pins = "EMMC_RSTB"; |
| 270 | drive-strength = <MTK_DRIVE_4mA>; |
| 271 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 272 | }; |
| 273 | }; |
| 274 | |
| 275 | mmc0_pins_uhs: mmc0-pins-50-to-61-uhs { |
| 276 | mux { |
| 277 | function = "flash"; |
| 278 | groups = "emmc_51"; |
| 279 | }; |
| 280 | conf-cmd-dat { |
| 281 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 282 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 283 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 284 | input-enable; |
| 285 | drive-strength = <MTK_DRIVE_4mA>; |
| 286 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 287 | }; |
| 288 | conf-clk { |
| 289 | pins = "EMMC_CK"; |
| 290 | drive-strength = <MTK_DRIVE_6mA>; |
| 291 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 292 | }; |
| 293 | conf-ds { |
| 294 | pins = "EMMC_DSL"; |
| 295 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 296 | }; |
| 297 | conf-rst { |
| 298 | pins = "EMMC_RSTB"; |
| 299 | drive-strength = <MTK_DRIVE_4mA>; |
| 300 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 301 | }; |
| 302 | }; |
developer | 19e8ed4 | 2021-06-10 19:15:03 +0800 | [diff] [blame] | 303 | }; |