developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | #include <linux/bitfield.h> |
| 3 | #include <linux/module.h> |
| 4 | #include <linux/nvmem-consumer.h> |
| 5 | #include <linux/of_address.h> |
| 6 | #include <linux/of_platform.h> |
| 7 | #include <linux/pinctrl/consumer.h> |
| 8 | #include <linux/phy.h> |
| 9 | |
| 10 | #define MTK_GPHY_ID_MT7981 0x03a29461 |
| 11 | #define MTK_GPHY_ID_MT7988 0x03a29481 |
| 12 | |
| 13 | #define MTK_EXT_PAGE_ACCESS 0x1f |
| 14 | #define MTK_PHY_PAGE_STANDARD 0x0000 |
| 15 | #define MTK_PHY_PAGE_EXTENDED_3 0x0003 |
| 16 | |
| 17 | #define MTK_PHY_LPI_REG_14 0x14 |
| 18 | #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) |
| 19 | |
| 20 | #define MTK_PHY_LPI_REG_1c 0x1c |
| 21 | #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) |
| 22 | |
| 23 | #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 |
| 24 | #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 |
| 25 | |
| 26 | #define ANALOG_INTERNAL_OPERATION_MAX_US 20 |
| 27 | #define TXRESERVE_MIN 0 |
| 28 | #define TXRESERVE_MAX 7 |
| 29 | |
| 30 | #define MTK_PHY_ANARG_RG 0x10 |
| 31 | #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) |
| 32 | |
| 33 | /* Registers on MDIO_MMD_VEND1 */ |
| 34 | #define MTK_PHY_TXVLD_DA_RG 0x12 |
| 35 | #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) |
| 36 | #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) |
| 37 | |
| 38 | #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 |
| 39 | #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) |
| 40 | #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) |
| 41 | |
| 42 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 |
| 43 | #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) |
| 44 | #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) |
| 45 | |
| 46 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 |
| 47 | #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) |
| 48 | #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) |
| 49 | |
| 50 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 |
| 51 | #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) |
| 52 | #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) |
| 53 | |
| 54 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 |
| 55 | #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) |
| 56 | #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) |
| 57 | |
| 58 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 |
| 59 | #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) |
| 60 | #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) |
| 61 | |
| 62 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 |
| 63 | #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) |
| 64 | #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) |
| 65 | |
| 66 | #define MTK_PHY_RXADC_CTRL_RG7 0xc6 |
| 67 | #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) |
| 68 | |
| 69 | #define MTK_PHY_RXADC_CTRL_RG9 0xc8 |
| 70 | #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) |
| 71 | #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) |
| 72 | #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) |
| 73 | #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) |
| 74 | |
| 75 | #define MTK_PHY_LDO_OUTPUT_V 0xd7 |
| 76 | |
| 77 | #define MTK_PHY_RG_ANA_CAL_RG0 0xdb |
| 78 | #define MTK_PHY_RG_CAL_CKINV BIT(12) |
| 79 | #define MTK_PHY_RG_ANA_CALEN BIT(8) |
| 80 | #define MTK_PHY_RG_ZCALEN_A BIT(0) |
| 81 | |
| 82 | #define MTK_PHY_RG_ANA_CAL_RG1 0xdc |
| 83 | #define MTK_PHY_RG_ZCALEN_B BIT(12) |
| 84 | #define MTK_PHY_RG_ZCALEN_C BIT(8) |
| 85 | #define MTK_PHY_RG_ZCALEN_D BIT(4) |
| 86 | #define MTK_PHY_RG_TXVOS_CALEN BIT(0) |
| 87 | |
| 88 | #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 |
| 89 | #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) |
| 90 | |
| 91 | #define MTK_PHY_RG_TX_FILTER 0xfe |
| 92 | |
| 93 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 |
| 94 | #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) |
| 95 | #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) |
| 96 | |
| 97 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 |
| 98 | #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) |
| 99 | |
| 100 | #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 |
| 101 | #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) |
| 102 | |
| 103 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 |
| 104 | #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) |
| 105 | #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) |
| 106 | |
| 107 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 |
| 108 | #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) |
| 109 | #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) |
| 110 | |
| 111 | #define MTK_PHY_RG_AD_CAL_COMP 0x17a |
| 112 | #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) |
| 113 | |
| 114 | #define MTK_PHY_RG_AD_CAL_CLK 0x17b |
| 115 | #define MTK_PHY_DA_CAL_CLK BIT(0) |
| 116 | |
| 117 | #define MTK_PHY_RG_AD_CALIN 0x17c |
| 118 | #define MTK_PHY_DA_CALIN_FLAG BIT(0) |
| 119 | |
| 120 | #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d |
| 121 | #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) |
| 122 | |
| 123 | #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e |
| 124 | #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) |
| 125 | |
| 126 | #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f |
| 127 | #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) |
| 128 | |
| 129 | #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 |
| 130 | #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) |
| 131 | |
| 132 | #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 |
| 133 | #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) |
| 134 | |
| 135 | #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 |
| 136 | #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) |
| 137 | |
| 138 | #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 |
| 139 | #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) |
| 140 | |
| 141 | #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 |
| 142 | #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) |
| 143 | |
| 144 | #define MTK_PHY_RG_DEV1E_REG19b 0x19b |
| 145 | #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) |
| 146 | |
| 147 | #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a |
| 148 | #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b |
| 149 | #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c |
| 150 | #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d |
| 151 | #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e |
| 152 | #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f |
| 153 | #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 |
| 154 | #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 |
| 155 | #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 |
| 156 | #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 |
| 157 | |
| 158 | #define MTK_PHY_RG_DEV1E_REG234 0x234 |
| 159 | #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) |
| 160 | #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) |
| 161 | #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) |
| 162 | |
| 163 | #define MTK_PHY_RG_LPF_CNT_VAL 0x235 |
| 164 | |
| 165 | #define MTK_PHY_RG_DEV1E_REG238 0x238 |
| 166 | #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) |
| 167 | #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) |
| 168 | |
| 169 | #define MTK_PHY_RG_DEV1E_REG239 0x239 |
| 170 | #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) |
| 171 | #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) |
| 172 | |
| 173 | #define MTK_PHY_RG_DEV1E_REG27C 0x27c |
| 174 | #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) |
| 175 | #define MTK_PHY_RG_DEV1E_REG27D 0x27d |
| 176 | #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) |
| 177 | |
| 178 | #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 |
| 179 | #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) |
| 180 | #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) |
| 181 | |
| 182 | #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 |
| 183 | #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) |
| 184 | #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) |
| 185 | #define MTK_PHY_LPI_TR_READY BIT(9) |
| 186 | #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) |
| 187 | |
| 188 | #define MTK_PHY_RG_DEV1E_REG323 0x323 |
| 189 | #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) |
| 190 | #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) |
| 191 | |
| 192 | #define MTK_PHY_RG_DEV1E_REG324 0x324 |
| 193 | #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) |
| 194 | #define MTK_PHY_SMI_DET_MAX_EN BIT(8) |
| 195 | |
| 196 | #define MTK_PHY_RG_DEV1E_REG326 0x326 |
| 197 | #define MTK_PHY_LPI_MODE_SD_ON BIT(0) |
| 198 | #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) |
| 199 | #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) |
| 200 | #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) |
| 201 | #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) |
| 202 | |
| 203 | #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 |
| 204 | #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 |
| 205 | |
| 206 | #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d |
| 207 | #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e |
| 208 | #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f |
| 209 | #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 |
| 210 | |
| 211 | /* Registers on MDIO_MMD_VEND2 */ |
| 212 | #define MTK_PHY_LED0_ON_CTRL 0x24 |
| 213 | #define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) |
| 214 | #define MTK_PHY_LED0_ON_LINK1000 BIT(0) |
| 215 | #define MTK_PHY_LED0_ON_LINK100 BIT(1) |
| 216 | #define MTK_PHY_LED0_ON_LINK10 BIT(2) |
| 217 | #define MTK_PHY_LED0_ON_LINKDOWN BIT(3) |
| 218 | #define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ |
| 219 | #define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ |
| 220 | #define MTK_PHY_LED0_FORCE_ON BIT(6) |
| 221 | #define MTK_PHY_LED0_POLARITY BIT(14) |
| 222 | #define MTK_PHY_LED0_ENABLE BIT(15) |
| 223 | |
| 224 | #define MTK_PHY_LED0_BLINK_CTRL 0x25 |
| 225 | #define MTK_PHY_LED0_1000TX BIT(0) |
| 226 | #define MTK_PHY_LED0_1000RX BIT(1) |
| 227 | #define MTK_PHY_LED0_100TX BIT(2) |
| 228 | #define MTK_PHY_LED0_100RX BIT(3) |
| 229 | #define MTK_PHY_LED0_10TX BIT(4) |
| 230 | #define MTK_PHY_LED0_10RX BIT(5) |
| 231 | #define MTK_PHY_LED0_COLLISION BIT(6) |
| 232 | #define MTK_PHY_LED0_RX_CRC_ERR BIT(7) |
| 233 | #define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) |
| 234 | #define MTK_PHY_LED0_FORCE_BLINK BIT(9) |
| 235 | |
| 236 | #define MTK_PHY_LED1_ON_CTRL 0x26 |
| 237 | #define MTK_PHY_LED1_ON_MASK GENMASK(6, 0) |
| 238 | #define MTK_PHY_LED1_ON_LINK1000 BIT(0) |
| 239 | #define MTK_PHY_LED1_ON_LINK100 BIT(1) |
| 240 | #define MTK_PHY_LED1_ON_LINK10 BIT(2) |
| 241 | #define MTK_PHY_LED1_ON_LINKDOWN BIT(3) |
| 242 | #define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */ |
| 243 | #define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */ |
| 244 | #define MTK_PHY_LED1_FORCE_ON BIT(6) |
| 245 | #define MTK_PHY_LED1_POLARITY BIT(14) |
| 246 | #define MTK_PHY_LED1_ENABLE BIT(15) |
| 247 | |
| 248 | #define MTK_PHY_LED1_BLINK_CTRL 0x27 |
| 249 | #define MTK_PHY_LED1_1000TX BIT(0) |
| 250 | #define MTK_PHY_LED1_1000RX BIT(1) |
| 251 | #define MTK_PHY_LED1_100TX BIT(2) |
| 252 | #define MTK_PHY_LED1_100RX BIT(3) |
| 253 | #define MTK_PHY_LED1_10TX BIT(4) |
| 254 | #define MTK_PHY_LED1_10RX BIT(5) |
| 255 | #define MTK_PHY_LED1_COLLISION BIT(6) |
| 256 | #define MTK_PHY_LED1_RX_CRC_ERR BIT(7) |
| 257 | #define MTK_PHY_LED1_RX_IDLE_ERR BIT(8) |
| 258 | #define MTK_PHY_LED1_FORCE_BLINK BIT(9) |
| 259 | |
| 260 | #define MTK_PHY_RG_BG_RASEL 0x115 |
| 261 | #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) |
| 262 | |
| 263 | /* These macro privides efuse parsing for internal phy. */ |
| 264 | #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) |
| 265 | #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) |
| 266 | #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) |
| 267 | #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) |
| 268 | #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) |
| 269 | |
| 270 | #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) |
| 271 | #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) |
| 272 | #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) |
| 273 | #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) |
| 274 | #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) |
| 275 | |
| 276 | #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) |
| 277 | #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) |
| 278 | |
| 279 | #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) |
| 280 | #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) |
| 281 | |
| 282 | enum { |
| 283 | NO_PAIR, |
| 284 | PAIR_A, |
| 285 | PAIR_B, |
| 286 | PAIR_C, |
| 287 | PAIR_D, |
| 288 | }; |
| 289 | |
| 290 | enum { |
| 291 | GPHY_PORT0, |
| 292 | GPHY_PORT1, |
| 293 | GPHY_PORT2, |
| 294 | GPHY_PORT3, |
| 295 | }; |
| 296 | |
| 297 | enum calibration_mode { |
| 298 | EFUSE_K, |
| 299 | SW_K |
| 300 | }; |
| 301 | |
| 302 | enum CAL_ITEM { |
| 303 | REXT, |
| 304 | TX_OFFSET, |
| 305 | TX_AMP, |
| 306 | TX_R50, |
| 307 | TX_VCM |
| 308 | }; |
| 309 | |
| 310 | enum CAL_MODE { |
| 311 | EFUSE_M, |
| 312 | SW_M |
| 313 | }; |
| 314 | |
| 315 | struct mtk_socphy_shared_priv { |
| 316 | u32 boottrap; |
| 317 | }; |
| 318 | |
| 319 | static int mtk_socphy_read_page(struct phy_device *phydev) |
| 320 | { |
| 321 | return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); |
| 322 | } |
| 323 | |
| 324 | static int mtk_socphy_write_page(struct phy_device *phydev, int page) |
| 325 | { |
| 326 | return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); |
| 327 | } |
| 328 | |
| 329 | /* One calibration cycle consists of: |
| 330 | * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high |
| 331 | * until AD_CAL_COMP is ready to output calibration result. |
| 332 | * 2.Wait until DA_CAL_CLK is available. |
| 333 | * 3.Fetch AD_CAL_COMP_OUT. |
| 334 | */ |
| 335 | static int cal_cycle(struct phy_device *phydev, int devad, |
| 336 | u32 regnum, u16 mask, u16 cal_val) |
| 337 | { |
| 338 | int reg_val; |
| 339 | int ret; |
| 340 | |
| 341 | phy_modify_mmd(phydev, devad, regnum, |
| 342 | mask, cal_val); |
| 343 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 344 | MTK_PHY_DA_CALIN_FLAG); |
| 345 | |
| 346 | ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, |
| 347 | MTK_PHY_RG_AD_CAL_CLK, reg_val, |
| 348 | reg_val & MTK_PHY_DA_CAL_CLK, 500, |
| 349 | ANALOG_INTERNAL_OPERATION_MAX_US, false); |
| 350 | if (ret) { |
| 351 | phydev_err(phydev, "Calibration cycle timeout\n"); |
| 352 | return ret; |
| 353 | } |
| 354 | |
| 355 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 356 | MTK_PHY_DA_CALIN_FLAG); |
| 357 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> |
| 358 | MTK_PHY_AD_CAL_COMP_OUT_SHIFT; |
| 359 | phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); |
| 360 | |
| 361 | return ret; |
| 362 | } |
| 363 | |
| 364 | static int rext_fill_result(struct phy_device *phydev, u16 *buf) |
| 365 | { |
| 366 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 367 | MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); |
| 368 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, |
| 369 | MTK_PHY_RG_BG_RASEL_MASK, buf[1]); |
| 370 | |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 375 | { |
| 376 | u16 rext_cal_val[2]; |
| 377 | |
| 378 | rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); |
| 379 | rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); |
| 380 | rext_fill_result(phydev, rext_cal_val); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) |
| 386 | { |
| 387 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
| 388 | MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); |
| 389 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
| 390 | MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); |
| 391 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
| 392 | MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); |
| 393 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
| 394 | MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 400 | { |
| 401 | u16 tx_offset_cal_val[4]; |
| 402 | |
| 403 | tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); |
| 404 | tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); |
| 405 | tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); |
| 406 | tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); |
| 407 | |
| 408 | tx_offset_fill_result(phydev, tx_offset_cal_val); |
| 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) |
| 414 | { |
| 415 | int i; |
| 416 | int bias[16] = {}; |
| 417 | const int vals_9461[16] = { 7, 1, 4, 7, |
| 418 | 7, 1, 4, 7, |
| 419 | 7, 1, 4, 7, |
| 420 | 7, 1, 4, 7 }; |
| 421 | const int vals_9481[16] = { 10, 6, 6, 10, |
| 422 | 10, 6, 6, 10, |
| 423 | 10, 6, 6, 10, |
| 424 | 10, 6, 6, 10 }; |
| 425 | switch (phydev->drv->phy_id) { |
| 426 | case MTK_GPHY_ID_MT7981: |
| 427 | /* We add some calibration to efuse values |
| 428 | * due to board level influence. |
| 429 | * GBE: +7, TBT: +1, HBT: +4, TST: +7 |
| 430 | */ |
| 431 | memcpy(bias, (const void *)vals_9461, sizeof(bias)); |
| 432 | break; |
| 433 | case MTK_GPHY_ID_MT7988: |
| 434 | memcpy(bias, (const void *)vals_9481, sizeof(bias)); |
| 435 | break; |
| 436 | } |
| 437 | |
| 438 | /* Prevent overflow */ |
| 439 | for (i = 0; i < 12; i++) { |
| 440 | if (buf[i >> 2] + bias[i] > 63) { |
| 441 | buf[i >> 2] = 63; |
| 442 | bias[i] = 0; |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
| 447 | MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); |
| 448 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
| 449 | MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); |
| 450 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
| 451 | MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); |
| 452 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
| 453 | MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); |
| 454 | |
| 455 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
| 456 | MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); |
| 457 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
| 458 | MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); |
| 459 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
| 460 | MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); |
| 461 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
| 462 | MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); |
| 463 | |
| 464 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
| 465 | MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); |
| 466 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
| 467 | MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); |
| 468 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
| 469 | MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); |
| 470 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
| 471 | MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); |
| 472 | |
| 473 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
| 474 | MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); |
| 475 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
| 476 | MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); |
| 477 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
| 478 | MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); |
| 479 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
| 480 | MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); |
| 481 | |
| 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 486 | { |
| 487 | u16 tx_amp_cal_val[4]; |
| 488 | |
| 489 | tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); |
| 490 | tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); |
| 491 | tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); |
| 492 | tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); |
| 493 | tx_amp_fill_result(phydev, tx_amp_cal_val); |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, |
| 499 | u8 txg_calen_x) |
| 500 | { |
| 501 | int bias = 0; |
| 502 | u16 reg, val; |
| 503 | |
| 504 | if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 505 | bias = -1; |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 506 | |
| 507 | val = clamp_val(bias + tx_r50_cal_val, 0, 63); |
| 508 | |
| 509 | switch (txg_calen_x) { |
| 510 | case PAIR_A: |
| 511 | reg = MTK_PHY_DA_TX_R50_PAIR_A; |
| 512 | break; |
| 513 | case PAIR_B: |
| 514 | reg = MTK_PHY_DA_TX_R50_PAIR_B; |
| 515 | break; |
| 516 | case PAIR_C: |
| 517 | reg = MTK_PHY_DA_TX_R50_PAIR_C; |
| 518 | break; |
| 519 | case PAIR_D: |
| 520 | reg = MTK_PHY_DA_TX_R50_PAIR_D; |
| 521 | break; |
| 522 | default: |
| 523 | return -EINVAL; |
| 524 | } |
| 525 | |
| 526 | phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, |
| 532 | u8 txg_calen_x) |
| 533 | { |
| 534 | u16 tx_r50_cal_val; |
| 535 | |
| 536 | switch (txg_calen_x) { |
| 537 | case PAIR_A: |
| 538 | tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); |
| 539 | break; |
| 540 | case PAIR_B: |
| 541 | tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); |
| 542 | break; |
| 543 | case PAIR_C: |
| 544 | tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); |
| 545 | break; |
| 546 | case PAIR_D: |
| 547 | tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); |
| 548 | break; |
| 549 | default: |
| 550 | return -EINVAL; |
| 551 | } |
| 552 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) |
| 558 | { |
| 559 | u8 lower_idx, upper_idx, txreserve_val; |
| 560 | u8 lower_ret, upper_ret; |
| 561 | int ret; |
| 562 | |
| 563 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 564 | MTK_PHY_RG_ANA_CALEN); |
| 565 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 566 | MTK_PHY_RG_CAL_CKINV); |
| 567 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 568 | MTK_PHY_RG_TXVOS_CALEN); |
| 569 | |
| 570 | switch (rg_txreserve_x) { |
| 571 | case PAIR_A: |
| 572 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 573 | MTK_PHY_RG_DASN_DAC_IN0_A, |
| 574 | MTK_PHY_DASN_DAC_IN0_A_MASK); |
| 575 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 576 | MTK_PHY_RG_DASN_DAC_IN1_A, |
| 577 | MTK_PHY_DASN_DAC_IN1_A_MASK); |
| 578 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 579 | MTK_PHY_RG_ANA_CAL_RG0, |
| 580 | MTK_PHY_RG_ZCALEN_A); |
| 581 | break; |
| 582 | case PAIR_B: |
| 583 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 584 | MTK_PHY_RG_DASN_DAC_IN0_B, |
| 585 | MTK_PHY_DASN_DAC_IN0_B_MASK); |
| 586 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 587 | MTK_PHY_RG_DASN_DAC_IN1_B, |
| 588 | MTK_PHY_DASN_DAC_IN1_B_MASK); |
| 589 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 590 | MTK_PHY_RG_ANA_CAL_RG1, |
| 591 | MTK_PHY_RG_ZCALEN_B); |
| 592 | break; |
| 593 | case PAIR_C: |
| 594 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 595 | MTK_PHY_RG_DASN_DAC_IN0_C, |
| 596 | MTK_PHY_DASN_DAC_IN0_C_MASK); |
| 597 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 598 | MTK_PHY_RG_DASN_DAC_IN1_C, |
| 599 | MTK_PHY_DASN_DAC_IN1_C_MASK); |
| 600 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 601 | MTK_PHY_RG_ANA_CAL_RG1, |
| 602 | MTK_PHY_RG_ZCALEN_C); |
| 603 | break; |
| 604 | case PAIR_D: |
| 605 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 606 | MTK_PHY_RG_DASN_DAC_IN0_D, |
| 607 | MTK_PHY_DASN_DAC_IN0_D_MASK); |
| 608 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 609 | MTK_PHY_RG_DASN_DAC_IN1_D, |
| 610 | MTK_PHY_DASN_DAC_IN1_D_MASK); |
| 611 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 612 | MTK_PHY_RG_ANA_CAL_RG1, |
| 613 | MTK_PHY_RG_ZCALEN_D); |
| 614 | break; |
| 615 | default: |
| 616 | ret = -EINVAL; |
| 617 | goto restore; |
| 618 | } |
| 619 | |
| 620 | lower_idx = TXRESERVE_MIN; |
| 621 | upper_idx = TXRESERVE_MAX; |
| 622 | |
| 623 | phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); |
| 624 | while ((upper_idx - lower_idx) > 1) { |
| 625 | txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); |
| 626 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
| 627 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 628 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 629 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 630 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 631 | txreserve_val << 12 | txreserve_val << 8 | |
| 632 | txreserve_val << 4 | txreserve_val); |
| 633 | if (ret == 1) { |
| 634 | upper_idx = txreserve_val; |
| 635 | upper_ret = ret; |
| 636 | } else if (ret == 0) { |
| 637 | lower_idx = txreserve_val; |
| 638 | lower_ret = ret; |
| 639 | } else { |
| 640 | goto restore; |
| 641 | } |
| 642 | } |
| 643 | |
| 644 | if (lower_idx == TXRESERVE_MIN) { |
| 645 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 646 | MTK_PHY_RXADC_CTRL_RG9, |
| 647 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 648 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 649 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 650 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 651 | lower_idx << 12 | lower_idx << 8 | |
| 652 | lower_idx << 4 | lower_idx); |
| 653 | ret = lower_ret; |
| 654 | } else if (upper_idx == TXRESERVE_MAX) { |
| 655 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 656 | MTK_PHY_RXADC_CTRL_RG9, |
| 657 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 658 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 659 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 660 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 661 | upper_idx << 12 | upper_idx << 8 | |
| 662 | upper_idx << 4 | upper_idx); |
| 663 | ret = upper_ret; |
| 664 | } |
| 665 | if (ret < 0) |
| 666 | goto restore; |
| 667 | |
| 668 | /* We calibrate TX-VCM in different logic. Check upper index and then |
| 669 | * lower index. If this calibration is valid, apply lower index's result. |
| 670 | */ |
| 671 | ret = upper_ret - lower_ret; |
| 672 | if (ret == 1) { |
| 673 | ret = 0; |
| 674 | /* Make sure we use upper_idx in our calibration system */ |
| 675 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
| 676 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 677 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 678 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 679 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 680 | upper_idx << 12 | upper_idx << 8 | |
| 681 | upper_idx << 4 | upper_idx); |
developer | 41dfe8b | 2023-06-29 16:58:19 +0800 | [diff] [blame] | 682 | phydev_info(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 683 | } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && |
| 684 | lower_ret == 1) { |
| 685 | ret = 0; |
| 686 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
| 687 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 688 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 689 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 690 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 691 | lower_idx << 12 | lower_idx << 8 | |
| 692 | lower_idx << 4 | lower_idx); |
| 693 | phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", |
| 694 | lower_idx); |
| 695 | } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && |
| 696 | lower_ret == 0) { |
| 697 | ret = 0; |
| 698 | phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", |
| 699 | upper_idx); |
| 700 | } else { |
| 701 | ret = -EINVAL; |
| 702 | } |
| 703 | |
| 704 | restore: |
| 705 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 706 | MTK_PHY_RG_ANA_CALEN); |
| 707 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 708 | MTK_PHY_RG_TXVOS_CALEN); |
| 709 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
| 710 | MTK_PHY_RG_ZCALEN_A); |
| 711 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
| 712 | MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | |
| 713 | MTK_PHY_RG_ZCALEN_D); |
| 714 | |
| 715 | return ret; |
| 716 | } |
| 717 | |
| 718 | static void mt798x_phy_common_finetune(struct phy_device *phydev) |
| 719 | { |
| 720 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 721 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ |
| 722 | __phy_write(phydev, 0x11, 0xc71); |
| 723 | __phy_write(phydev, 0x12, 0xc); |
| 724 | __phy_write(phydev, 0x10, 0x8fae); |
| 725 | |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 726 | /* EnabRandUpdTrig = 1 */ |
| 727 | __phy_write(phydev, 0x11, 0x2f00); |
| 728 | __phy_write(phydev, 0x12, 0xe); |
| 729 | __phy_write(phydev, 0x10, 0x8fb0); |
| 730 | |
| 731 | /* NormMseLoThresh = 85 */ |
| 732 | __phy_write(phydev, 0x11, 0x55a0); |
| 733 | __phy_write(phydev, 0x12, 0x0); |
| 734 | __phy_write(phydev, 0x10, 0x83aa); |
| 735 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 736 | /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */ |
| 737 | __phy_write(phydev, 0x11, 0x240); |
| 738 | __phy_write(phydev, 0x12, 0x0); |
| 739 | __phy_write(phydev, 0x10, 0x9680); |
| 740 | |
| 741 | /* TrFreeze = 0 (mt7988 default) */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 742 | __phy_write(phydev, 0x11, 0x0); |
| 743 | __phy_write(phydev, 0x12, 0x0); |
| 744 | __phy_write(phydev, 0x10, 0x9686); |
| 745 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 746 | /* SSTrKp100 = 5 */ |
| 747 | /* SSTrKf100 = 6 */ |
| 748 | /* SSTrKp1000Mas = 5 */ |
| 749 | /* SSTrKf1000Mas = 6 */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 750 | /* SSTrKp1000Slv = 5 */ |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 751 | /* SSTrKf1000Slv = 6 */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 752 | __phy_write(phydev, 0x11, 0xbaef); |
| 753 | __phy_write(phydev, 0x12, 0x2e); |
| 754 | __phy_write(phydev, 0x10, 0x968c); |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 755 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 756 | } |
| 757 | |
| 758 | static void mt7981_phy_finetune(struct phy_device *phydev) |
| 759 | { |
| 760 | u16 val[8] = { 0x01ce, 0x01c1, |
| 761 | 0x020f, 0x0202, |
| 762 | 0x03d0, 0x03c0, |
| 763 | 0x0013, 0x0005 }; |
| 764 | int i, k; |
| 765 | |
| 766 | /* 100M eye finetune: |
| 767 | * Keep middle level of TX MLT3 shapper as default. |
| 768 | * Only change TX MLT3 overshoot level here. |
| 769 | */ |
| 770 | for (k = 0, i = 1; i < 12; i++) { |
| 771 | if (i % 3 == 0) |
| 772 | continue; |
| 773 | phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); |
| 774 | } |
| 775 | |
| 776 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 777 | /* ResetSyncOffset = 6 */ |
| 778 | __phy_write(phydev, 0x11, 0x600); |
| 779 | __phy_write(phydev, 0x12, 0x0); |
| 780 | __phy_write(phydev, 0x10, 0x8fc0); |
| 781 | |
| 782 | /* VgaDecRate = 1 */ |
| 783 | __phy_write(phydev, 0x11, 0x4c2a); |
| 784 | __phy_write(phydev, 0x12, 0x3e); |
| 785 | __phy_write(phydev, 0x10, 0x8fa4); |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 786 | |
| 787 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
| 788 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
| 789 | */ |
| 790 | __phy_write(phydev, 0x11, 0xd10a); |
| 791 | __phy_write(phydev, 0x12, 0x34); |
| 792 | __phy_write(phydev, 0x10, 0x8f82); |
| 793 | |
| 794 | /* VcoSlicerThreshBitsHigh */ |
| 795 | __phy_write(phydev, 0x11, 0x5555); |
| 796 | __phy_write(phydev, 0x12, 0x55); |
| 797 | __phy_write(phydev, 0x10, 0x8ec0); |
| 798 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 799 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 800 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 801 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
| 802 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 803 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
| 804 | |
| 805 | /* rg_tr_lpf_cnt_val = 512 */ |
| 806 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 807 | |
| 808 | /* IIR2 related */ |
| 809 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 810 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 811 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 812 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 813 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 814 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 815 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 816 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 817 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 818 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 819 | |
| 820 | /* FFE peaking */ |
| 821 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
| 822 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
| 823 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
| 824 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
| 825 | |
| 826 | /* Disable LDO pump */ |
| 827 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); |
| 828 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); |
| 829 | /* Adjust LDO output voltage */ |
| 830 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 831 | |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 832 | } |
| 833 | |
| 834 | static void mt7988_phy_finetune(struct phy_device *phydev) |
| 835 | { |
| 836 | u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, |
| 837 | 0x020d, 0x0206, 0x0384, 0x03d0, |
| 838 | 0x03c6, 0x030a, 0x0011, 0x0005 }; |
| 839 | int i; |
| 840 | |
| 841 | /* Set default MLT3 shaper first */ |
| 842 | for (i = 0; i < 12; i++) |
| 843 | phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); |
| 844 | |
| 845 | /* TCT finetune */ |
| 846 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); |
| 847 | |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 848 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 849 | /* ResetSyncOffset = 5 */ |
| 850 | __phy_write(phydev, 0x11, 0x500); |
| 851 | __phy_write(phydev, 0x12, 0x0); |
| 852 | __phy_write(phydev, 0x10, 0x8fc0); |
| 853 | |
| 854 | /* VgaDecRate is 1 at default on mt7988 */ |
| 855 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 856 | /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7, |
| 857 | * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7 |
| 858 | */ |
| 859 | __phy_write(phydev, 0x11, 0xb90a); |
| 860 | __phy_write(phydev, 0x12, 0x6f); |
| 861 | __phy_write(phydev, 0x10, 0x8f82); |
| 862 | |
| 863 | /* RemAckCntLimitCtrl = 1 */ |
| 864 | __phy_write(phydev, 0x11, 0xfbba); |
| 865 | __phy_write(phydev, 0x12, 0xc3); |
| 866 | __phy_write(phydev, 0x10, 0x87f8); |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 867 | |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 868 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 869 | |
| 870 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ |
| 871 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
| 872 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 873 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); |
| 874 | |
| 875 | /* rg_tr_lpf_cnt_val = 1023 */ |
| 876 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); |
| 877 | |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | static void mt798x_phy_eee(struct phy_device *phydev) |
| 881 | { |
| 882 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 883 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, |
| 884 | MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | |
| 885 | MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, |
| 886 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | |
| 887 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); |
| 888 | |
| 889 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 890 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 891 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 892 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 893 | 0xff)); |
| 894 | |
| 895 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 896 | MTK_PHY_RG_TESTMUX_ADC_CTRL, |
| 897 | MTK_PHY_RG_TXEN_DIG_MASK); |
| 898 | |
| 899 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 900 | MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); |
| 901 | |
| 902 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 903 | MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); |
| 904 | |
| 905 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, |
| 906 | MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | |
| 907 | MTK_PHY_LPI_SLV_SEND_TX_EN, |
| 908 | FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); |
| 909 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 910 | /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ |
| 911 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, |
| 912 | MTK_PHY_LPI_TXPCS_LOC_RCV); |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 913 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 914 | /* This also fixes some IoT issues, such as CH340 */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 915 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, |
| 916 | MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, |
| 917 | FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | |
| 918 | FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); |
| 919 | |
| 920 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, |
| 921 | MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
| 922 | FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
| 923 | 0x33) | |
| 924 | MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | |
| 925 | MTK_PHY_LPI_VCO_EEE_STG0_EN); |
| 926 | |
| 927 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, |
| 928 | MTK_PHY_EEE_WAKE_MAS_INT_DC | |
| 929 | MTK_PHY_EEE_WAKE_SLV_INT_DC); |
| 930 | |
| 931 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, |
| 932 | MTK_PHY_SMI_DETCNT_MAX_MASK, |
| 933 | FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | |
| 934 | MTK_PHY_SMI_DET_MAX_EN); |
| 935 | |
| 936 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, |
| 937 | MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | |
| 938 | MTK_PHY_TREC_UPDATE_ENAB_CLR | |
| 939 | MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | |
| 940 | MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); |
| 941 | |
| 942 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 943 | /* Regsigdet_sel_1000 = 0 */ |
| 944 | __phy_write(phydev, 0x11, 0xb); |
| 945 | __phy_write(phydev, 0x12, 0x0); |
| 946 | __phy_write(phydev, 0x10, 0x9690); |
| 947 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 948 | /* REG_EEE_st2TrKf1000 = 2 */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 949 | __phy_write(phydev, 0x11, 0x114f); |
| 950 | __phy_write(phydev, 0x12, 0x2); |
| 951 | __phy_write(phydev, 0x10, 0x969a); |
| 952 | |
| 953 | /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ |
| 954 | __phy_write(phydev, 0x11, 0x3028); |
| 955 | __phy_write(phydev, 0x12, 0x0); |
| 956 | __phy_write(phydev, 0x10, 0x969e); |
| 957 | |
| 958 | /* RegEEE_slv_wake_int_timer_tar = 8 */ |
| 959 | __phy_write(phydev, 0x11, 0x5010); |
| 960 | __phy_write(phydev, 0x12, 0x0); |
| 961 | __phy_write(phydev, 0x10, 0x96a0); |
| 962 | |
| 963 | /* RegEEE_trfreeze_timer2 = 586 */ |
| 964 | __phy_write(phydev, 0x11, 0x24a); |
| 965 | __phy_write(phydev, 0x12, 0x0); |
| 966 | __phy_write(phydev, 0x10, 0x96a8); |
| 967 | |
| 968 | /* RegEEE100Stg1_tar = 16 */ |
| 969 | __phy_write(phydev, 0x11, 0x3210); |
| 970 | __phy_write(phydev, 0x12, 0x0); |
| 971 | __phy_write(phydev, 0x10, 0x96b8); |
| 972 | |
developer | d529b84 | 2023-05-24 12:39:34 +0800 | [diff] [blame] | 973 | /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */ |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 974 | __phy_write(phydev, 0x11, 0x1463); |
| 975 | __phy_write(phydev, 0x12, 0x0); |
| 976 | __phy_write(phydev, 0x10, 0x96ca); |
| 977 | |
| 978 | /* DfeTailEnableVgaThresh1000 = 27 */ |
| 979 | __phy_write(phydev, 0x11, 0x36); |
| 980 | __phy_write(phydev, 0x12, 0x0); |
| 981 | __phy_write(phydev, 0x10, 0x8f80); |
| 982 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 983 | |
| 984 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); |
| 985 | __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, |
| 986 | FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); |
| 987 | |
| 988 | __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, |
| 989 | FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); |
| 990 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 991 | |
| 992 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 993 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 994 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 995 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
| 996 | } |
| 997 | |
| 998 | static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 999 | u8 start_pair, u8 end_pair) |
| 1000 | { |
| 1001 | u8 pair_n; |
| 1002 | int ret; |
| 1003 | |
| 1004 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1005 | /* TX_OFFSET & TX_AMP have no SW calibration. */ |
| 1006 | switch (cal_item) { |
| 1007 | case TX_VCM: |
| 1008 | ret = tx_vcm_cal_sw(phydev, pair_n); |
| 1009 | break; |
| 1010 | default: |
| 1011 | return -EINVAL; |
| 1012 | } |
| 1013 | if (ret) |
| 1014 | return ret; |
| 1015 | } |
| 1016 | return 0; |
| 1017 | } |
| 1018 | |
| 1019 | static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1020 | u8 start_pair, u8 end_pair, u32 *buf) |
| 1021 | { |
| 1022 | u8 pair_n; |
| 1023 | int ret; |
| 1024 | |
| 1025 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1026 | /* TX_VCM has no efuse calibration. */ |
| 1027 | switch (cal_item) { |
| 1028 | case REXT: |
| 1029 | ret = rext_cal_efuse(phydev, buf); |
| 1030 | break; |
| 1031 | case TX_OFFSET: |
| 1032 | ret = tx_offset_cal_efuse(phydev, buf); |
| 1033 | break; |
| 1034 | case TX_AMP: |
| 1035 | ret = tx_amp_cal_efuse(phydev, buf); |
| 1036 | break; |
| 1037 | case TX_R50: |
| 1038 | ret = tx_r50_cal_efuse(phydev, buf, pair_n); |
| 1039 | break; |
| 1040 | default: |
| 1041 | return -EINVAL; |
| 1042 | } |
| 1043 | if (ret) |
| 1044 | return ret; |
| 1045 | } |
| 1046 | |
| 1047 | return 0; |
| 1048 | } |
| 1049 | |
| 1050 | static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1051 | enum CAL_MODE cal_mode, u8 start_pair, |
| 1052 | u8 end_pair, u32 *buf) |
| 1053 | { |
| 1054 | int ret; |
| 1055 | |
| 1056 | switch (cal_mode) { |
| 1057 | case EFUSE_M: |
| 1058 | ret = cal_efuse(phydev, cal_item, start_pair, |
| 1059 | end_pair, buf); |
| 1060 | break; |
| 1061 | case SW_M: |
| 1062 | ret = cal_sw(phydev, cal_item, start_pair, end_pair); |
| 1063 | break; |
| 1064 | default: |
| 1065 | return -EINVAL; |
| 1066 | } |
| 1067 | |
| 1068 | if (ret) { |
| 1069 | phydev_err(phydev, "cal %d failed\n", cal_item); |
| 1070 | return -EIO; |
| 1071 | } |
| 1072 | |
| 1073 | return 0; |
| 1074 | } |
| 1075 | |
| 1076 | static int mt798x_phy_calibration(struct phy_device *phydev) |
| 1077 | { |
| 1078 | int ret = 0; |
| 1079 | u32 *buf; |
| 1080 | size_t len; |
| 1081 | struct nvmem_cell *cell; |
| 1082 | |
| 1083 | cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); |
| 1084 | if (IS_ERR(cell)) { |
| 1085 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 1086 | return PTR_ERR(cell); |
| 1087 | return 0; |
| 1088 | } |
| 1089 | |
| 1090 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 1091 | if (IS_ERR(buf)) |
| 1092 | return PTR_ERR(buf); |
| 1093 | nvmem_cell_put(cell); |
| 1094 | |
| 1095 | if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { |
| 1096 | phydev_err(phydev, "invalid efuse data\n"); |
| 1097 | ret = -EINVAL; |
| 1098 | goto out; |
| 1099 | } |
| 1100 | |
| 1101 | ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
| 1102 | if (ret) |
| 1103 | goto out; |
| 1104 | ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
| 1105 | if (ret) |
| 1106 | goto out; |
| 1107 | ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
| 1108 | if (ret) |
| 1109 | goto out; |
| 1110 | ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); |
| 1111 | if (ret) |
| 1112 | goto out; |
| 1113 | ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); |
| 1114 | if (ret) |
| 1115 | goto out; |
| 1116 | |
| 1117 | out: |
| 1118 | kfree(buf); |
| 1119 | return ret; |
| 1120 | } |
| 1121 | |
| 1122 | static int mt798x_phy_config_init(struct phy_device *phydev) |
| 1123 | { |
| 1124 | switch (phydev->drv->phy_id) { |
| 1125 | case MTK_GPHY_ID_MT7981: |
| 1126 | mt7981_phy_finetune(phydev); |
| 1127 | break; |
| 1128 | case MTK_GPHY_ID_MT7988: |
| 1129 | mt7988_phy_finetune(phydev); |
| 1130 | break; |
| 1131 | } |
| 1132 | |
| 1133 | mt798x_phy_common_finetune(phydev); |
| 1134 | mt798x_phy_eee(phydev); |
| 1135 | |
developer | 41dfe8b | 2023-06-29 16:58:19 +0800 | [diff] [blame] | 1136 | return 0; |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 1137 | } |
| 1138 | |
| 1139 | static int mt7988_phy_setup_led(struct phy_device *phydev) |
| 1140 | { |
| 1141 | struct mtk_socphy_shared_priv *priv = phydev->shared->priv; |
| 1142 | int port = phydev->mdio.addr; |
| 1143 | u32 reg = priv->boottrap; |
| 1144 | struct pinctrl *pinctrl; |
| 1145 | |
| 1146 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 1147 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | |
| 1148 | MTK_PHY_LED0_ON_LINK10 | |
| 1149 | MTK_PHY_LED0_ON_LINK100 | |
| 1150 | MTK_PHY_LED0_ON_LINK1000); |
| 1151 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, |
| 1152 | MTK_PHY_LED1_ENABLE | MTK_PHY_LED1_POLARITY | |
| 1153 | MTK_PHY_LED1_ON_LINK10 | |
| 1154 | MTK_PHY_LED1_ON_LINK100 | |
| 1155 | MTK_PHY_LED1_ON_LINK1000); |
| 1156 | |
| 1157 | if ((port == GPHY_PORT0 && reg & BIT(8)) || |
| 1158 | (port == GPHY_PORT1 && reg & BIT(9)) || |
| 1159 | (port == GPHY_PORT2 && reg & BIT(10)) || |
| 1160 | (port == GPHY_PORT3 && reg & BIT(11))) { |
| 1161 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 1162 | MTK_PHY_LED0_POLARITY); |
| 1163 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, |
| 1164 | MTK_PHY_LED1_POLARITY); |
| 1165 | } |
| 1166 | |
| 1167 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, |
| 1168 | MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | |
| 1169 | MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | |
| 1170 | MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); |
| 1171 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, |
| 1172 | MTK_PHY_LED1_1000TX | MTK_PHY_LED1_1000RX | |
| 1173 | MTK_PHY_LED1_100TX | MTK_PHY_LED1_100RX | |
| 1174 | MTK_PHY_LED1_10TX | MTK_PHY_LED1_10RX); |
| 1175 | |
| 1176 | pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); |
| 1177 | if (IS_ERR(pinctrl)) { |
| 1178 | dev_err(&phydev->mdio.bus->dev, "Failed to setup LED pins\n"); |
| 1179 | return PTR_ERR(pinctrl); |
| 1180 | } |
| 1181 | |
| 1182 | return 0; |
| 1183 | } |
| 1184 | |
| 1185 | static int mt7988_phy_probe_shared(struct phy_device *phydev) |
| 1186 | { |
| 1187 | struct mtk_socphy_shared_priv *priv = phydev->shared->priv; |
| 1188 | void __iomem *boottrap; |
| 1189 | struct device_node *np; |
| 1190 | u32 reg; |
| 1191 | |
| 1192 | np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); |
| 1193 | if (!np) |
| 1194 | return -ENOENT; |
| 1195 | |
| 1196 | boottrap = of_iomap(np, 0); |
| 1197 | if (!boottrap) |
| 1198 | return -ENOMEM; |
| 1199 | |
| 1200 | reg = readl(boottrap); |
| 1201 | iounmap(boottrap); |
| 1202 | |
| 1203 | priv->boottrap = reg; |
| 1204 | |
| 1205 | return 0; |
| 1206 | } |
| 1207 | |
| 1208 | static int mt7981_phy_probe(struct phy_device *phydev) |
| 1209 | { |
| 1210 | return mt798x_phy_calibration(phydev); |
| 1211 | } |
| 1212 | |
| 1213 | static int mt7988_phy_probe(struct phy_device *phydev) |
| 1214 | { |
| 1215 | int err; |
| 1216 | |
| 1217 | err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, |
| 1218 | sizeof(struct mtk_socphy_shared_priv)); |
| 1219 | if (err) |
| 1220 | return err; |
| 1221 | |
| 1222 | if (phy_package_probe_once(phydev)) { |
| 1223 | err = mt7988_phy_probe_shared(phydev); |
| 1224 | if (err) |
| 1225 | return err; |
| 1226 | } |
| 1227 | |
developer | 41dfe8b | 2023-06-29 16:58:19 +0800 | [diff] [blame] | 1228 | /* Disable TX power saving at probing to: |
| 1229 | * 1. Meet common mode compliance test criteria |
| 1230 | * 2. Make sure that TX-VCM calibration works fine |
| 1231 | */ |
| 1232 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, |
| 1233 | MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); |
| 1234 | |
developer | 394d5eb | 2023-04-14 16:46:45 +0800 | [diff] [blame] | 1235 | mt7988_phy_setup_led(phydev); |
| 1236 | |
| 1237 | return mt798x_phy_calibration(phydev); |
| 1238 | } |
| 1239 | |
| 1240 | static struct phy_driver mtk_socphy_driver[] = { |
| 1241 | { |
| 1242 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), |
| 1243 | .name = "MediaTek MT7981 PHY", |
| 1244 | .config_init = mt798x_phy_config_init, |
| 1245 | .config_intr = genphy_no_config_intr, |
| 1246 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1247 | .probe = mt7981_phy_probe, |
| 1248 | .suspend = genphy_suspend, |
| 1249 | .resume = genphy_resume, |
| 1250 | .read_page = mtk_socphy_read_page, |
| 1251 | .write_page = mtk_socphy_write_page, |
| 1252 | }, |
| 1253 | { |
| 1254 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), |
| 1255 | .name = "MediaTek MT7988 PHY", |
| 1256 | .config_init = mt798x_phy_config_init, |
| 1257 | .config_intr = genphy_no_config_intr, |
| 1258 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1259 | .probe = mt7988_phy_probe, |
| 1260 | .suspend = genphy_suspend, |
| 1261 | .resume = genphy_resume, |
| 1262 | .read_page = mtk_socphy_read_page, |
| 1263 | .write_page = mtk_socphy_write_page, |
| 1264 | }, |
| 1265 | }; |
| 1266 | |
| 1267 | module_phy_driver(mtk_socphy_driver); |
| 1268 | |
| 1269 | static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { |
| 1270 | { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, |
| 1271 | { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, |
| 1272 | { } |
| 1273 | }; |
| 1274 | |
| 1275 | MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); |
| 1276 | MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); |
| 1277 | MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); |
| 1278 | MODULE_LICENSE("GPL"); |
| 1279 | |
| 1280 | MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); |