developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/kernel.h> |
| 8 | #include <linux/module.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/device.h> |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/reset.h> |
| 13 | #include <linux/hrtimer.h> |
| 14 | #include <linux/mii.h> |
| 15 | #include <linux/of_mdio.h> |
| 16 | #include <linux/of_platform.h> |
| 17 | #include <linux/of_gpio.h> |
| 18 | #include <linux/of_net.h> |
| 19 | #include <linux/of_irq.h> |
| 20 | #include <linux/phy.h> |
| 21 | |
| 22 | #include "mt753x.h" |
| 23 | #include "mt753x_swconfig.h" |
| 24 | #include "mt753x_regs.h" |
| 25 | #include "mt753x_nl.h" |
| 26 | #include "mt7530.h" |
| 27 | #include "mt7531.h" |
| 28 | |
| 29 | static u32 mt753x_id; |
| 30 | struct list_head mt753x_devs; |
| 31 | static DEFINE_MUTEX(mt753x_devs_lock); |
| 32 | |
| 33 | static struct mt753x_sw_id *mt753x_sw_ids[] = { |
| 34 | &mt7530_id, |
| 35 | &mt7531_id, |
| 36 | }; |
| 37 | |
| 38 | u32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg) |
| 39 | { |
| 40 | u32 high, low; |
| 41 | |
| 42 | mutex_lock(&gsw->host_bus->mdio_lock); |
| 43 | |
| 44 | gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f, |
| 45 | (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S); |
| 46 | |
| 47 | low = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, |
| 48 | (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S); |
| 49 | |
| 50 | high = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10); |
| 51 | |
| 52 | mutex_unlock(&gsw->host_bus->mdio_lock); |
| 53 | |
| 54 | return (high << 16) | (low & 0xffff); |
| 55 | } |
| 56 | |
| 57 | void mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val) |
| 58 | { |
| 59 | mutex_lock(&gsw->host_bus->mdio_lock); |
| 60 | |
| 61 | gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f, |
| 62 | (reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S); |
| 63 | |
| 64 | gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, |
| 65 | (reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff); |
| 66 | |
| 67 | gsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16); |
| 68 | |
| 69 | mutex_unlock(&gsw->host_bus->mdio_lock); |
| 70 | } |
| 71 | |
| 72 | /* Indirect MDIO clause 22/45 access */ |
| 73 | static int mt753x_mii_rw(struct gsw_mt753x *gsw, int phy, int reg, u16 data, |
| 74 | u32 cmd, u32 st) |
| 75 | { |
| 76 | ktime_t timeout; |
| 77 | u32 val, timeout_us; |
| 78 | int ret = 0; |
| 79 | |
| 80 | timeout_us = 100000; |
| 81 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 82 | while (1) { |
| 83 | val = mt753x_reg_read(gsw, PHY_IAC); |
| 84 | |
| 85 | if ((val & PHY_ACS_ST) == 0) |
| 86 | break; |
| 87 | |
| 88 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 89 | return -ETIMEDOUT; |
| 90 | } |
| 91 | |
| 92 | val = (st << MDIO_ST_S) | |
| 93 | ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | |
| 94 | ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | |
| 95 | ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); |
| 96 | |
| 97 | if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR) |
| 98 | val |= data & MDIO_RW_DATA_M; |
| 99 | |
| 100 | mt753x_reg_write(gsw, PHY_IAC, val | PHY_ACS_ST); |
| 101 | |
| 102 | timeout_us = 100000; |
| 103 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 104 | while (1) { |
| 105 | val = mt753x_reg_read(gsw, PHY_IAC); |
| 106 | |
| 107 | if ((val & PHY_ACS_ST) == 0) |
| 108 | break; |
| 109 | |
| 110 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 111 | return -ETIMEDOUT; |
| 112 | } |
| 113 | |
| 114 | if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) { |
| 115 | val = mt753x_reg_read(gsw, PHY_IAC); |
| 116 | ret = val & MDIO_RW_DATA_M; |
| 117 | } |
| 118 | |
| 119 | return ret; |
| 120 | } |
| 121 | |
| 122 | int mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg) |
| 123 | { |
| 124 | int val; |
| 125 | |
| 126 | if (phy < MT753X_NUM_PHYS) |
| 127 | phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK; |
| 128 | |
| 129 | mutex_lock(&gsw->mii_lock); |
| 130 | val = mt753x_mii_rw(gsw, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); |
| 131 | mutex_unlock(&gsw->mii_lock); |
| 132 | |
| 133 | return val; |
| 134 | } |
| 135 | |
| 136 | void mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val) |
| 137 | { |
| 138 | if (phy < MT753X_NUM_PHYS) |
| 139 | phy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK; |
| 140 | |
| 141 | mutex_lock(&gsw->mii_lock); |
| 142 | mt753x_mii_rw(gsw, phy, reg, val, MDIO_CMD_WRITE, MDIO_ST_C22); |
| 143 | mutex_unlock(&gsw->mii_lock); |
| 144 | } |
| 145 | |
| 146 | int mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg) |
| 147 | { |
| 148 | int val; |
| 149 | |
| 150 | if (addr < MT753X_NUM_PHYS) |
| 151 | addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; |
| 152 | |
| 153 | mutex_lock(&gsw->mii_lock); |
| 154 | mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); |
| 155 | val = mt753x_mii_rw(gsw, addr, devad, 0, MDIO_CMD_READ_C45, |
| 156 | MDIO_ST_C45); |
| 157 | mutex_unlock(&gsw->mii_lock); |
| 158 | |
| 159 | return val; |
| 160 | } |
| 161 | |
| 162 | void mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, |
| 163 | u16 val) |
| 164 | { |
| 165 | if (addr < MT753X_NUM_PHYS) |
| 166 | addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; |
| 167 | |
| 168 | mutex_lock(&gsw->mii_lock); |
| 169 | mt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); |
| 170 | mt753x_mii_rw(gsw, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45); |
| 171 | mutex_unlock(&gsw->mii_lock); |
| 172 | } |
| 173 | |
| 174 | int mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg) |
| 175 | { |
| 176 | u16 val; |
| 177 | |
| 178 | if (addr < MT753X_NUM_PHYS) |
| 179 | addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; |
| 180 | |
| 181 | mutex_lock(&gsw->mii_lock); |
| 182 | |
| 183 | mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, |
| 184 | (MMD_ADDR << MMD_CMD_S) | |
| 185 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), |
| 186 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 187 | |
| 188 | mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg, |
| 189 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 190 | |
| 191 | mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, |
| 192 | (MMD_DATA << MMD_CMD_S) | |
| 193 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), |
| 194 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 195 | |
| 196 | val = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0, |
| 197 | MDIO_CMD_READ, MDIO_ST_C22); |
| 198 | |
| 199 | mutex_unlock(&gsw->mii_lock); |
| 200 | |
| 201 | return val; |
| 202 | } |
| 203 | |
| 204 | void mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg, |
| 205 | u16 val) |
| 206 | { |
| 207 | if (addr < MT753X_NUM_PHYS) |
| 208 | addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; |
| 209 | |
| 210 | mutex_lock(&gsw->mii_lock); |
| 211 | |
| 212 | mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, |
| 213 | (MMD_ADDR << MMD_CMD_S) | |
| 214 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), |
| 215 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 216 | |
| 217 | mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg, |
| 218 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 219 | |
| 220 | mt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG, |
| 221 | (MMD_DATA << MMD_CMD_S) | |
| 222 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M), |
| 223 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 224 | |
| 225 | mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val, |
| 226 | MDIO_CMD_WRITE, MDIO_ST_C22); |
| 227 | |
| 228 | mutex_unlock(&gsw->mii_lock); |
| 229 | } |
| 230 | |
| 231 | static inline int mt753x_get_duplex(const struct device_node *np) |
| 232 | { |
| 233 | return of_property_read_bool(np, "full-duplex"); |
| 234 | } |
| 235 | |
| 236 | static void mt753x_load_port_cfg(struct gsw_mt753x *gsw) |
| 237 | { |
| 238 | struct device_node *port_np; |
| 239 | struct device_node *fixed_link_node; |
| 240 | struct mt753x_port_cfg *port_cfg; |
| 241 | u32 port; |
| 242 | |
| 243 | for_each_child_of_node(gsw->dev->of_node, port_np) { |
| 244 | if (!of_device_is_compatible(port_np, "mediatek,mt753x-port")) |
| 245 | continue; |
| 246 | |
| 247 | if (!of_device_is_available(port_np)) |
| 248 | continue; |
| 249 | |
| 250 | if (of_property_read_u32(port_np, "reg", &port)) |
| 251 | continue; |
| 252 | |
| 253 | switch (port) { |
| 254 | case 5: |
| 255 | port_cfg = &gsw->port5_cfg; |
| 256 | break; |
| 257 | case 6: |
| 258 | port_cfg = &gsw->port6_cfg; |
| 259 | break; |
| 260 | default: |
| 261 | continue; |
| 262 | } |
| 263 | |
| 264 | if (port_cfg->enabled) { |
| 265 | dev_info(gsw->dev, "duplicated node for port%d\n", |
| 266 | port_cfg->phy_mode); |
| 267 | continue; |
| 268 | } |
| 269 | |
| 270 | port_cfg->np = port_np; |
| 271 | |
| 272 | port_cfg->phy_mode = of_get_phy_mode(port_np); |
| 273 | if (port_cfg->phy_mode < 0) { |
| 274 | dev_info(gsw->dev, "incorrect phy-mode %d\n", port); |
| 275 | continue; |
| 276 | } |
| 277 | |
| 278 | fixed_link_node = of_get_child_by_name(port_np, "fixed-link"); |
| 279 | if (fixed_link_node) { |
| 280 | u32 speed; |
| 281 | |
| 282 | port_cfg->force_link = 1; |
| 283 | port_cfg->duplex = mt753x_get_duplex(fixed_link_node); |
| 284 | |
| 285 | if (of_property_read_u32(fixed_link_node, "speed", |
| 286 | &speed)) { |
| 287 | speed = 0; |
| 288 | continue; |
| 289 | } |
| 290 | |
| 291 | of_node_put(fixed_link_node); |
| 292 | |
| 293 | switch (speed) { |
| 294 | case 10: |
| 295 | port_cfg->speed = MAC_SPD_10; |
| 296 | break; |
| 297 | case 100: |
| 298 | port_cfg->speed = MAC_SPD_100; |
| 299 | break; |
| 300 | case 1000: |
| 301 | port_cfg->speed = MAC_SPD_1000; |
| 302 | break; |
| 303 | case 2500: |
| 304 | port_cfg->speed = MAC_SPD_2500; |
| 305 | break; |
| 306 | default: |
| 307 | dev_info(gsw->dev, "incorrect speed %d\n", |
| 308 | speed); |
| 309 | continue; |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | port_cfg->ssc_on = of_property_read_bool(port_cfg->np, |
| 314 | "mediatek,ssc-on"); |
| 315 | port_cfg->stag_on = of_property_read_bool(port_cfg->np, |
| 316 | "mediatek,stag-on"); |
| 317 | port_cfg->enabled = 1; |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | void mt753x_tr_write(struct gsw_mt753x *gsw, int addr, u8 ch, u8 node, u8 daddr, |
| 322 | u32 data) |
| 323 | { |
| 324 | ktime_t timeout; |
| 325 | u32 timeout_us; |
| 326 | u32 val; |
| 327 | |
| 328 | if (addr < MT753X_NUM_PHYS) |
| 329 | addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; |
| 330 | |
| 331 | gsw->mii_write(gsw, addr, PHY_CL22_PAGE_CTRL, PHY_TR_PAGE); |
| 332 | |
| 333 | val = gsw->mii_read(gsw, addr, PHY_TR_CTRL); |
| 334 | |
| 335 | timeout_us = 100000; |
| 336 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 337 | while (1) { |
| 338 | val = gsw->mii_read(gsw, addr, PHY_TR_CTRL); |
| 339 | |
| 340 | if (!!(val & PHY_TR_PKT_XMT_STA)) |
| 341 | break; |
| 342 | |
| 343 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 344 | goto out; |
| 345 | } |
| 346 | |
| 347 | gsw->mii_write(gsw, addr, PHY_TR_LOW_DATA, PHY_TR_LOW_VAL(data)); |
| 348 | gsw->mii_write(gsw, addr, PHY_TR_HIGH_DATA, PHY_TR_HIGH_VAL(data)); |
| 349 | val = PHY_TR_PKT_XMT_STA | (PHY_TR_WRITE << PHY_TR_WR_S) | |
| 350 | (ch << PHY_TR_CH_ADDR_S) | (node << PHY_TR_NODE_ADDR_S) | |
| 351 | (daddr << PHY_TR_DATA_ADDR_S); |
| 352 | gsw->mii_write(gsw, addr, PHY_TR_CTRL, val); |
| 353 | |
| 354 | timeout_us = 100000; |
| 355 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 356 | while (1) { |
| 357 | val = gsw->mii_read(gsw, addr, PHY_TR_CTRL); |
| 358 | |
| 359 | if (!!(val & PHY_TR_PKT_XMT_STA)) |
| 360 | break; |
| 361 | |
| 362 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 363 | goto out; |
| 364 | } |
| 365 | out: |
| 366 | gsw->mii_write(gsw, addr, PHY_CL22_PAGE_CTRL, 0); |
| 367 | } |
| 368 | |
| 369 | int mt753x_tr_read(struct gsw_mt753x *gsw, int addr, u8 ch, u8 node, u8 daddr) |
| 370 | { |
| 371 | ktime_t timeout; |
| 372 | u32 timeout_us; |
| 373 | u32 val; |
| 374 | u8 val_h; |
| 375 | |
| 376 | if (addr < MT753X_NUM_PHYS) |
| 377 | addr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK; |
| 378 | |
| 379 | gsw->mii_write(gsw, addr, PHY_CL22_PAGE_CTRL, PHY_TR_PAGE); |
| 380 | |
| 381 | val = gsw->mii_read(gsw, addr, PHY_TR_CTRL); |
| 382 | |
| 383 | timeout_us = 100000; |
| 384 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 385 | while (1) { |
| 386 | val = gsw->mii_read(gsw, addr, PHY_TR_CTRL); |
| 387 | |
| 388 | if (!!(val & PHY_TR_PKT_XMT_STA)) |
| 389 | break; |
| 390 | |
| 391 | if (ktime_compare(ktime_get(), timeout) > 0) { |
| 392 | gsw->mii_write(gsw, addr, PHY_CL22_PAGE_CTRL, 0); |
| 393 | return -ETIMEDOUT; |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | val = PHY_TR_PKT_XMT_STA | (PHY_TR_READ << PHY_TR_WR_S) | |
| 398 | (ch << PHY_TR_CH_ADDR_S) | (node << PHY_TR_NODE_ADDR_S) | |
| 399 | (daddr << PHY_TR_DATA_ADDR_S); |
| 400 | gsw->mii_write(gsw, addr, PHY_TR_CTRL, val); |
| 401 | |
| 402 | timeout_us = 100000; |
| 403 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 404 | while (1) { |
| 405 | val = gsw->mii_read(gsw, addr, PHY_TR_CTRL); |
| 406 | |
| 407 | if (!!(val & PHY_TR_PKT_XMT_STA)) |
| 408 | break; |
| 409 | |
| 410 | if (ktime_compare(ktime_get(), timeout) > 0) { |
| 411 | gsw->mii_write(gsw, addr, PHY_CL22_PAGE_CTRL, 0); |
| 412 | return -ETIMEDOUT; |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | val = gsw->mii_read(gsw, addr, PHY_TR_LOW_DATA); |
| 417 | val_h = gsw->mii_read(gsw, addr, PHY_TR_HIGH_DATA); |
| 418 | val |= (val_h << 16); |
| 419 | |
| 420 | gsw->mii_write(gsw, addr, PHY_CL22_PAGE_CTRL, 0); |
| 421 | |
| 422 | return val; |
| 423 | } |
| 424 | |
| 425 | static void mt753x_add_gsw(struct gsw_mt753x *gsw) |
| 426 | { |
| 427 | mutex_lock(&mt753x_devs_lock); |
| 428 | gsw->id = mt753x_id++; |
| 429 | INIT_LIST_HEAD(&gsw->list); |
| 430 | list_add_tail(&gsw->list, &mt753x_devs); |
| 431 | mutex_unlock(&mt753x_devs_lock); |
| 432 | } |
| 433 | |
| 434 | static void mt753x_remove_gsw(struct gsw_mt753x *gsw) |
| 435 | { |
| 436 | mutex_lock(&mt753x_devs_lock); |
| 437 | list_del(&gsw->list); |
| 438 | mutex_unlock(&mt753x_devs_lock); |
| 439 | } |
| 440 | |
| 441 | |
| 442 | struct gsw_mt753x *mt753x_get_gsw(u32 id) |
| 443 | { |
| 444 | struct gsw_mt753x *dev; |
| 445 | |
| 446 | mutex_lock(&mt753x_devs_lock); |
| 447 | |
| 448 | list_for_each_entry(dev, &mt753x_devs, list) { |
| 449 | if (dev->id == id) |
| 450 | return dev; |
| 451 | } |
| 452 | |
| 453 | mutex_unlock(&mt753x_devs_lock); |
| 454 | |
| 455 | return NULL; |
| 456 | } |
| 457 | |
| 458 | struct gsw_mt753x *mt753x_get_first_gsw(void) |
| 459 | { |
| 460 | struct gsw_mt753x *dev; |
| 461 | |
| 462 | mutex_lock(&mt753x_devs_lock); |
| 463 | |
| 464 | list_for_each_entry(dev, &mt753x_devs, list) |
| 465 | return dev; |
| 466 | |
| 467 | mutex_unlock(&mt753x_devs_lock); |
| 468 | |
| 469 | return NULL; |
| 470 | } |
| 471 | |
| 472 | void mt753x_put_gsw(void) |
| 473 | { |
| 474 | mutex_unlock(&mt753x_devs_lock); |
| 475 | } |
| 476 | |
| 477 | void mt753x_lock_gsw(void) |
| 478 | { |
| 479 | mutex_lock(&mt753x_devs_lock); |
| 480 | } |
| 481 | |
| 482 | static int mt753x_hw_reset(struct gsw_mt753x *gsw) |
| 483 | { |
| 484 | struct device_node *np = gsw->dev->of_node; |
| 485 | struct reset_control *rstc; |
| 486 | int mcm; |
| 487 | int ret = -EINVAL; |
| 488 | |
| 489 | mcm = of_property_read_bool(np, "mediatek,mcm"); |
| 490 | if (mcm) { |
| 491 | rstc = devm_reset_control_get(gsw->dev, "mcm"); |
| 492 | ret = IS_ERR(rstc); |
| 493 | if (IS_ERR(rstc)) { |
| 494 | dev_err(gsw->dev, "Missing reset ctrl of switch\n"); |
| 495 | return ret; |
| 496 | } |
| 497 | |
| 498 | reset_control_assert(rstc); |
| 499 | msleep(30); |
| 500 | reset_control_deassert(rstc); |
| 501 | |
| 502 | gsw->reset_pin = -1; |
| 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | gsw->reset_pin = of_get_named_gpio(np, "reset-gpios", 0); |
| 507 | if (gsw->reset_pin < 0) { |
| 508 | dev_err(gsw->dev, "Missing reset pin of switch\n"); |
| 509 | return ret; |
| 510 | } |
| 511 | |
| 512 | ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mt753x-reset"); |
| 513 | if (ret) { |
| 514 | dev_info(gsw->dev, "Failed to request gpio %d\n", |
| 515 | gsw->reset_pin); |
| 516 | return ret; |
| 517 | } |
| 518 | |
| 519 | gpio_direction_output(gsw->reset_pin, 0); |
| 520 | msleep(30); |
| 521 | gpio_set_value(gsw->reset_pin, 1); |
| 522 | msleep(500); |
| 523 | |
| 524 | return 0; |
| 525 | } |
| 526 | #if 1 //XDXDXDXD |
| 527 | static int mt753x_mdio_read(struct mii_bus *bus, int addr, int reg) |
| 528 | { |
| 529 | struct gsw_mt753x *gsw = bus->priv; |
| 530 | |
| 531 | return gsw->mii_read(gsw, addr, reg); |
| 532 | } |
| 533 | |
| 534 | static int mt753x_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) |
| 535 | { |
| 536 | struct gsw_mt753x *gsw = bus->priv; |
| 537 | |
| 538 | gsw->mii_write(gsw, addr, reg, val); |
| 539 | |
| 540 | return 0; |
| 541 | } |
| 542 | |
| 543 | static const struct net_device_ops mt753x_dummy_netdev_ops = { |
| 544 | }; |
| 545 | |
| 546 | static void mt753x_phy_link_handler(struct net_device *dev) |
| 547 | { |
| 548 | struct mt753x_phy *phy = container_of(dev, struct mt753x_phy, netdev); |
| 549 | struct phy_device *phydev = phy->phydev; |
| 550 | struct gsw_mt753x *gsw = phy->gsw; |
| 551 | u32 port = phy - gsw->phys; |
| 552 | |
| 553 | if (phydev->link) { |
| 554 | dev_info(gsw->dev, |
| 555 | "Port %d Link is Up - %s/%s - flow control %s\n", |
| 556 | port, phy_speed_to_str(phydev->speed), |
| 557 | (phydev->duplex == DUPLEX_FULL) ? "Full" : "Half", |
| 558 | phydev->pause ? "rx/tx" : "off"); |
| 559 | } else { |
| 560 | dev_info(gsw->dev, "Port %d Link is Down\n", port); |
| 561 | } |
| 562 | } |
| 563 | |
| 564 | static void mt753x_connect_internal_phys(struct gsw_mt753x *gsw, |
| 565 | struct device_node *mii_np) |
| 566 | { |
| 567 | struct device_node *phy_np; |
| 568 | struct mt753x_phy *phy; |
| 569 | int phy_mode; |
| 570 | u32 phyad; |
| 571 | |
| 572 | if (!mii_np) |
| 573 | return; |
| 574 | |
| 575 | for_each_child_of_node(mii_np, phy_np) { |
| 576 | if (of_property_read_u32(phy_np, "reg", &phyad)) |
| 577 | continue; |
| 578 | |
| 579 | if (phyad >= MT753X_NUM_PHYS) |
| 580 | continue; |
| 581 | |
| 582 | phy_mode = of_get_phy_mode(phy_np); |
| 583 | if (phy_mode < 0) { |
| 584 | dev_info(gsw->dev, "incorrect phy-mode %d for PHY %d\n", |
| 585 | phy_mode, phyad); |
| 586 | continue; |
| 587 | } |
| 588 | |
| 589 | phy = &gsw->phys[phyad]; |
| 590 | phy->gsw = gsw; |
| 591 | |
| 592 | init_dummy_netdev(&phy->netdev); |
| 593 | phy->netdev.netdev_ops = &mt753x_dummy_netdev_ops; |
| 594 | |
| 595 | phy->phydev = of_phy_connect(&phy->netdev, phy_np, |
| 596 | mt753x_phy_link_handler, 0, phy_mode); |
| 597 | if (!phy->phydev) { |
| 598 | dev_info(gsw->dev, "could not connect to PHY %d\n", |
| 599 | phyad); |
| 600 | continue; |
| 601 | } |
| 602 | |
| 603 | phy_start(phy->phydev); |
| 604 | } |
| 605 | } |
| 606 | |
| 607 | static void mt753x_disconnect_internal_phys(struct gsw_mt753x *gsw) |
| 608 | { |
| 609 | int i; |
| 610 | |
| 611 | for (i = 0; i < ARRAY_SIZE(gsw->phys); i++) { |
| 612 | if (gsw->phys[i].phydev) { |
| 613 | phy_stop(gsw->phys[i].phydev); |
| 614 | phy_disconnect(gsw->phys[i].phydev); |
| 615 | gsw->phys[i].phydev = NULL; |
| 616 | } |
| 617 | } |
| 618 | } |
| 619 | |
| 620 | static int mt753x_mdio_register(struct gsw_mt753x *gsw) |
| 621 | { |
| 622 | struct device_node *mii_np; |
| 623 | int i, ret; |
| 624 | |
| 625 | mii_np = of_get_child_by_name(gsw->dev->of_node, "mdio-bus"); |
| 626 | if (mii_np && !of_device_is_available(mii_np)) { |
| 627 | ret = -ENODEV; |
| 628 | goto err_put_node; |
| 629 | } |
| 630 | |
| 631 | gsw->gphy_bus = devm_mdiobus_alloc(gsw->dev); |
| 632 | if (!gsw->gphy_bus) { |
| 633 | ret = -ENOMEM; |
| 634 | goto err_put_node; |
| 635 | } |
| 636 | |
| 637 | gsw->gphy_bus->name = "mt753x_mdio"; |
| 638 | gsw->gphy_bus->read = mt753x_mdio_read; |
| 639 | gsw->gphy_bus->write = mt753x_mdio_write; |
| 640 | gsw->gphy_bus->priv = gsw; |
| 641 | gsw->gphy_bus->parent = gsw->dev; |
| 642 | gsw->gphy_bus->phy_mask = BIT(MT753X_NUM_PHYS) - 1; |
| 643 | // gsw->gphy_bus->irq = gsw->phy_irqs; |
| 644 | |
| 645 | for (i = 0; i < PHY_MAX_ADDR; i++) |
| 646 | gsw->gphy_bus->irq[i] = PHY_POLL; |
| 647 | |
| 648 | if (mii_np) |
| 649 | snprintf(gsw->gphy_bus->id, MII_BUS_ID_SIZE, "%s@%s", |
| 650 | mii_np->name, gsw->dev->of_node->name); |
| 651 | else |
| 652 | snprintf(gsw->gphy_bus->id, MII_BUS_ID_SIZE, "mdio@%s", |
| 653 | gsw->dev->of_node->name); |
| 654 | |
| 655 | ret = of_mdiobus_register(gsw->gphy_bus, mii_np); |
| 656 | |
| 657 | if (ret) { |
| 658 | devm_mdiobus_free(gsw->dev, gsw->gphy_bus); |
| 659 | gsw->gphy_bus = NULL; |
| 660 | } else { |
| 661 | if (gsw->phy_status_poll) |
| 662 | mt753x_connect_internal_phys(gsw, mii_np); |
| 663 | } |
| 664 | |
| 665 | err_put_node: |
| 666 | if (mii_np) |
| 667 | of_node_put(mii_np); |
| 668 | |
| 669 | return ret; |
| 670 | } |
| 671 | #endif |
| 672 | |
| 673 | static irqreturn_t mt753x_irq_handler(int irq, void *dev) |
| 674 | { |
| 675 | struct gsw_mt753x *gsw = dev; |
| 676 | |
| 677 | disable_irq_nosync(gsw->irq); |
| 678 | |
| 679 | schedule_work(&gsw->irq_worker); |
| 680 | |
| 681 | return IRQ_HANDLED; |
| 682 | } |
| 683 | |
| 684 | static int mt753x_probe(struct platform_device *pdev) |
| 685 | { |
| 686 | struct gsw_mt753x *gsw; |
| 687 | struct mt753x_sw_id *sw; |
| 688 | struct device_node *np = pdev->dev.of_node; |
| 689 | struct device_node *mdio; |
| 690 | struct mii_bus *mdio_bus; |
| 691 | int ret = -EINVAL; |
| 692 | struct chip_rev rev; |
| 693 | struct mt753x_mapping *map; |
| 694 | int i; |
| 695 | |
| 696 | mdio = of_parse_phandle(np, "mediatek,mdio", 0); |
| 697 | if (!mdio) |
| 698 | return -EINVAL; |
| 699 | |
| 700 | mdio_bus = of_mdio_find_bus(mdio); |
| 701 | if (!mdio_bus) |
| 702 | return -EPROBE_DEFER; |
| 703 | |
| 704 | gsw = devm_kzalloc(&pdev->dev, sizeof(struct gsw_mt753x), GFP_KERNEL); |
| 705 | if (!gsw) |
| 706 | return -ENOMEM; |
| 707 | |
| 708 | gsw->host_bus = mdio_bus; |
| 709 | gsw->dev = &pdev->dev; |
| 710 | mutex_init(&gsw->mii_lock); |
| 711 | |
| 712 | /* Switch hard reset */ |
| 713 | if (mt753x_hw_reset(gsw)) |
| 714 | goto fail; |
| 715 | |
| 716 | /* Fetch the SMI address dirst */ |
| 717 | if (of_property_read_u32(np, "mediatek,smi-addr", &gsw->smi_addr)) |
| 718 | gsw->smi_addr = MT753X_DFL_SMI_ADDR; |
| 719 | |
| 720 | /* Get LAN/WAN port mapping */ |
| 721 | map = mt753x_find_mapping(np); |
| 722 | if (map) { |
| 723 | mt753x_apply_mapping(gsw, map); |
| 724 | gsw->global_vlan_enable = 1; |
| 725 | dev_info(gsw->dev, "LAN/WAN VLAN setting=%s\n", map->name); |
| 726 | } |
| 727 | |
| 728 | /* Load MAC port configurations */ |
| 729 | mt753x_load_port_cfg(gsw); |
| 730 | |
| 731 | /* Check for valid switch and then initialize */ |
| 732 | for (i = 0; i < ARRAY_SIZE(mt753x_sw_ids); i++) { |
| 733 | if (!mt753x_sw_ids[i]->detect(gsw, &rev)) { |
| 734 | sw = mt753x_sw_ids[i]; |
| 735 | |
| 736 | gsw->name = rev.name; |
| 737 | gsw->model = sw->model; |
| 738 | |
| 739 | dev_info(gsw->dev, "Switch is MediaTek %s rev %d", |
| 740 | gsw->name, rev.rev); |
| 741 | |
| 742 | /* Initialize the switch */ |
| 743 | ret = sw->init(gsw); |
| 744 | if (ret) |
| 745 | goto fail; |
| 746 | |
| 747 | break; |
| 748 | } |
| 749 | } |
| 750 | |
| 751 | if (i >= ARRAY_SIZE(mt753x_sw_ids)) { |
| 752 | dev_err(gsw->dev, "No mt753x switch found\n"); |
| 753 | goto fail; |
| 754 | } |
| 755 | |
| 756 | gsw->irq = platform_get_irq(pdev, 0); |
| 757 | if (gsw->irq >= 0) { |
| 758 | ret = devm_request_irq(gsw->dev, gsw->irq, mt753x_irq_handler, |
| 759 | 0, dev_name(gsw->dev), gsw); |
| 760 | if (ret) { |
| 761 | dev_err(gsw->dev, "Failed to request irq %d\n", |
| 762 | gsw->irq); |
| 763 | goto fail; |
| 764 | } |
| 765 | |
| 766 | INIT_WORK(&gsw->irq_worker, mt753x_irq_worker); |
| 767 | } |
| 768 | |
| 769 | platform_set_drvdata(pdev, gsw); |
| 770 | |
| 771 | gsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node, |
| 772 | "mediatek,phy-poll"); |
| 773 | |
| 774 | mt753x_add_gsw(gsw); |
| 775 | #if 1 //XDXD |
| 776 | mt753x_mdio_register(gsw); |
| 777 | #endif |
| 778 | |
developer | 5145ebb | 2022-07-14 15:16:24 +0800 | [diff] [blame] | 779 | mt753x_nl_init(); |
| 780 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 781 | mt753x_swconfig_init(gsw); |
| 782 | |
| 783 | if (sw->post_init) |
| 784 | sw->post_init(gsw); |
| 785 | |
| 786 | if (gsw->irq >= 0) |
| 787 | mt753x_irq_enable(gsw); |
| 788 | |
| 789 | return 0; |
| 790 | |
| 791 | fail: |
| 792 | devm_kfree(&pdev->dev, gsw); |
| 793 | |
| 794 | return ret; |
| 795 | } |
| 796 | |
| 797 | static int mt753x_remove(struct platform_device *pdev) |
| 798 | { |
| 799 | struct gsw_mt753x *gsw = platform_get_drvdata(pdev); |
| 800 | |
| 801 | if (gsw->irq >= 0) |
| 802 | cancel_work_sync(&gsw->irq_worker); |
| 803 | |
| 804 | if (gsw->reset_pin >= 0) |
| 805 | devm_gpio_free(&pdev->dev, gsw->reset_pin); |
| 806 | |
| 807 | #ifdef CONFIG_SWCONFIG |
| 808 | mt753x_swconfig_destroy(gsw); |
| 809 | #endif |
| 810 | |
| 811 | #if 1 //XDXD |
| 812 | mt753x_disconnect_internal_phys(gsw); |
| 813 | |
| 814 | mdiobus_unregister(gsw->gphy_bus); |
| 815 | #endif |
| 816 | |
developer | 5145ebb | 2022-07-14 15:16:24 +0800 | [diff] [blame] | 817 | mt753x_nl_exit(); |
| 818 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 819 | mt753x_remove_gsw(gsw); |
| 820 | |
| 821 | platform_set_drvdata(pdev, NULL); |
| 822 | |
| 823 | return 0; |
| 824 | } |
| 825 | |
| 826 | static const struct of_device_id mt753x_ids[] = { |
| 827 | { .compatible = "mediatek,mt753x" }, |
| 828 | { }, |
| 829 | }; |
| 830 | |
| 831 | MODULE_DEVICE_TABLE(of, mt753x_ids); |
| 832 | |
| 833 | static struct platform_driver mt753x_driver = { |
| 834 | .probe = mt753x_probe, |
| 835 | .remove = mt753x_remove, |
| 836 | .driver = { |
| 837 | .name = "mt753x", |
| 838 | .of_match_table = mt753x_ids, |
| 839 | }, |
| 840 | }; |
| 841 | |
| 842 | static int __init mt753x_init(void) |
| 843 | { |
| 844 | int ret; |
| 845 | |
| 846 | INIT_LIST_HEAD(&mt753x_devs); |
| 847 | ret = platform_driver_register(&mt753x_driver); |
| 848 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 849 | return ret; |
| 850 | } |
| 851 | module_init(mt753x_init); |
| 852 | |
| 853 | static void __exit mt753x_exit(void) |
| 854 | { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 855 | platform_driver_unregister(&mt753x_driver); |
| 856 | } |
| 857 | module_exit(mt753x_exit); |
| 858 | |
| 859 | MODULE_LICENSE("GPL"); |
| 860 | MODULE_AUTHOR("Weijie Gao <weijie.gao@mediatek.com>"); |
| 861 | MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch"); |