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developer978a0512022-03-08 15:20:03 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
5 compatible = "mediatek,mt7981-spim-snand-gsw-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
16 nmbm_spim_nand {
17 compatible = "generic,nmbm";
18
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 lower-mtd-device = <&spi_nand>;
23 forced-create;
24
25 partitions {
26 compatible = "fixed-partitions";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 partition@0 {
31 label = "BL2";
32 reg = <0x00000 0x0100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "u-boot-env";
38 reg = <0x0100000 0x0080000>;
39 };
40
41 partition@180000 {
42 label = "Factory";
43 reg = <0x180000 0x0200000>;
44 };
45
46 partition@380000 {
47 label = "FIP";
48 reg = <0x380000 0x0200000>;
49 };
50
51 partition@580000 {
52 label = "ubi";
53 reg = <0x580000 0x4000000>;
54 };
55 };
56 };
57
58 sound_wm8960 {
59 compatible = "mediatek,mt79xx-wm8960-machine";
60 mediatek,platform = <&afe>;
61 audio-routing = "Headphone", "HP_L",
62 "Headphone", "HP_R",
63 "LINPUT1", "AMIC",
64 "RINPUT1", "AMIC";
65 mediatek,audio-codec = <&wm8960>;
66 status = "disabled";
67 };
68
69 sound_si3218x {
70 compatible = "mediatek,mt79xx-si3218x-machine";
71 mediatek,platform = <&afe>;
72 mediatek,ext-codec = <&proslic_spi>;
73 status = "disabled";
74 };
75
76 gsw: gsw@0 {
77 compatible = "mediatek,mt753x";
78 mediatek,ethsys = <&ethsys>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81 };
82};
83
84&afe {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pcm_pins>;
87 status = "okay";
88};
89
90&i2c0 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&i2c_pins>;
93 status = "disabled";
94
95 wm8960: wm8960@1a {
96 compatible = "wlf,wm8960";
97 reg = <0x1a>;
98 };
99};
100
101&uart0 {
102 status = "okay";
103};
104
105&watchdog {
106 status = "okay";
107};
108
109&eth {
110 status = "okay";
111
112 gmac0: mac@0 {
113 compatible = "mediatek,eth-mac";
114 reg = <0>;
115 phy-mode = "2500base-x";
116
117 fixed-link {
118 speed = <2500>;
119 full-duplex;
120 pause;
121 };
122 };
123
124 gmac1: mac@1 {
125 compatible = "mediatek,eth-mac";
126 reg = <1>;
127 phy-mode = "gmii";
128 phy-handle = <&phy0>;
129 };
130
131 mdio: mdio-bus {
132 #address-cells = <1>;
133 #size-cells = <0>;
134
135 phy0: ethernet-phy@0 {
136 compatible = "ethernet-phy-id03a2.9461";
137 reg = <0>;
138 phy-mode = "gmii";
139 nvmem-cells = <&phy_calibration>;
140 nvmem-cell-names = "phy-cal-data";
141 };
142
143 };
144};
145
146&gsw {
147 mediatek,mdio = <&mdio>;
148 mediatek,portmap = "llllw";
149 mediatek,mdio_master_pinmux = <1>;
150 reset-gpios = <&pio 39 0>;
151 interrupt-parent = <&pio>;
152 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
153 status = "okay";
154
155 port6: port@6 {
156 compatible = "mediatek,mt753x-port";
157 reg = <6>;
158 phy-mode = "sgmii";
159 fixed-link {
160 speed = <2500>;
161 full-duplex;
162 };
163 };
164};
165
166&hnat {
167 mtketh-wan = "eth1";
168 mtketh-lan = "eth0";
169 mtketh-max-gmac = <2>;
170 status = "okay";
171};
172
173&spi0 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&spi0_flash_pins>;
176 status = "okay";
177 spi_nand: spi_nand@0 {
178 #address-cells = <1>;
179 #size-cells = <1>;
180 compatible = "spi-nand";
181 reg = <0>;
182 spi-max-frequency = <52000000>;
183 spi-tx-buswidth = <4>;
184 spi-rx-buswidth = <4>;
185 };
186};
187
188&spi1 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&spic_pins>;
191 status = "okay";
192
193 proslic_spi: proslic_spi@0 {
194 compatible = "silabs,proslic_spi";
195 reg = <0>;
196 spi-max-frequency = <10000000>;
197 spi-cpha = <1>;
198 spi-cpol = <1>;
199 channel_count = <1>;
200 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
201 reset_gpio = <&pio 15 0>;
202 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
203 };
204};
205
206&pio {
207
208 i2c_pins: i2c-pins-g0 {
209 mux {
210 function = "i2c";
211 groups = "i2c0_0";
212 };
213 };
214
215 pcm_pins: pcm-pins-g0 {
216 mux {
217 function = "pcm";
218 groups = "pcm";
219 };
220 };
221
222 pwm0_pin: pwm0-pin-g0 {
223 mux {
224 function = "pwm";
225 groups = "pwm0_0";
226 };
227 };
228
229 pwm1_pin: pwm1-pin-g0 {
230 mux {
231 function = "pwm";
232 groups = "pwm1_0";
233 };
234 };
235
236 pwm2_pin: pwm2-pin {
237 mux {
238 function = "pwm";
239 groups = "pwm2";
240 };
241 };
242
243 spi0_flash_pins: spi0-pins {
244 mux {
245 function = "spi";
246 groups = "spi0", "spi0_wp_hold";
247 };
248
249 conf-pu {
250 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
251 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800252 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer978a0512022-03-08 15:20:03 +0800253 };
254
255 conf-pd {
256 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
257 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800258 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer978a0512022-03-08 15:20:03 +0800259 };
260 };
261
262 spic_pins: spi1-pins {
263 mux {
264 function = "spi";
265 groups = "spi1_1";
266 };
267 };
268
269 uart1_pins: uart1-pins-g1 {
270 mux {
271 function = "uart";
272 groups = "uart1_1";
273 };
274 };
275
276 uart2_pins: uart2-pins-g1 {
277 mux {
278 function = "uart";
279 groups = "uart2_1";
280 };
281 };
282};
283
284&xhci {
285 mediatek,u3p-dis-msk = <0x0>;
286 phys = <&u2port0 PHY_TYPE_USB2>,
287 <&u3port0 PHY_TYPE_USB3>;
288 status = "okay";
289};