blob: c12d50f80b8d7c1221b314c6f2b2602637e2e612 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4/ {
5 model = "MediaTek MT7986a RFB";
developer8262b0d2021-11-12 09:02:17 +08006 compatible = "mediatek,mt7986a-emmc-rfb";
developer565bacb2021-09-28 21:26:32 +08007 chosen {
8 bootargs = "console=ttyS0,115200n1 loglevel=8 \
9 earlycon=uart8250,mmio32,0x11002000 \
developer8262b0d2021-11-12 09:02:17 +080010 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
developer565bacb2021-09-28 21:26:32 +080011 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_1p8v: regulator-1p8v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-1.8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on;
32 regulator-always-on;
33 };
34
35 sound {
36 compatible = "mediatek,mt7986-wm8960-machine";
37 mediatek,platform = <&afe>;
38 audio-routing = "Headphone", "HP_L",
39 "Headphone", "HP_R",
40 "LINPUT1", "AMIC",
41 "RINPUT1", "AMIC";
42 mediatek,audio-codec = <&wm8960>;
43 status = "okay";
44 };
45};
46
47&pwm {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
50 status = "okay";
51};
52
53&uart0 {
54 status = "okay";
55};
56
57&uart1 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart1_pins>;
60 status = "okay";
61};
62
63&uart2 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&uart2_pins>;
66 status = "okay";
67};
68
69&i2c0 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&i2c_pins>;
72 status = "okay";
73
74 wm8960: wm8960@1a {
75 compatible = "wlf,wm8960";
76 reg = <0x1a>;
77 };
78};
79
80&auxadc {
81 status = "okay";
82};
83
84&watchdog {
85 status = "okay";
86};
87
88&eth {
89 status = "okay";
90
91 gmac0: mac@0 {
92 compatible = "mediatek,eth-mac";
93 reg = <0>;
94 phy-mode = "2500base-x";
95
96 fixed-link {
97 speed = <2500>;
98 full-duplex;
99 pause;
100 };
101 };
102
103 gmac1: mac@1 {
104 compatible = "mediatek,eth-mac";
105 reg = <1>;
106 phy-mode = "2500base-x";
107
108 fixed-link {
109 speed = <2500>;
110 full-duplex;
111 pause;
112 };
113 };
114
115 mdio: mdio-bus {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 phy5: phy@5 {
120 compatible = "ethernet-phy-id67c9.de0a";
121 reg = <5>;
122 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800123 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800124 reset-deassert-us = <20000>;
125 phy-mode = "2500base-x";
126 };
127
128 phy6: phy@6 {
129 compatible = "ethernet-phy-id67c9.de0a";
130 reg = <6>;
131 phy-mode = "2500base-x";
132 };
133
134 switch@0 {
135 compatible = "mediatek,mt7531";
136 reg = <31>;
137 reset-gpios = <&pio 5 0>;
138
139 ports {
140 #address-cells = <1>;
141 #size-cells = <0>;
142
143 port@0 {
144 reg = <0>;
145 label = "lan0";
146 };
147
148 port@1 {
149 reg = <1>;
150 label = "lan1";
151 };
152
153 port@2 {
154 reg = <2>;
155 label = "lan2";
156 };
157
158 port@3 {
159 reg = <3>;
160 label = "lan3";
161 };
162
163 port@4 {
164 reg = <4>;
165 label = "lan4";
166 };
167
168 port@5 {
169 reg = <5>;
170 label = "lan5";
171 phy-mode = "2500base-x";
172
173 fixed-link {
174 speed = <2500>;
175 full-duplex;
176 pause;
177 };
178 };
179
180 port@6 {
181 reg = <6>;
182 label = "cpu";
183 ethernet = <&gmac0>;
184 phy-mode = "2500base-x";
185
186 fixed-link {
187 speed = <2500>;
188 full-duplex;
189 pause;
190 };
191 };
192 };
193 };
194 };
195};
196
197&hnat {
198 mtketh-wan = "eth1";
199 mtketh-lan = "lan";
200 mtketh-max-gmac = <2>;
201 status = "okay";
202};
203
204&spi1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&spic_pins_g2>;
207 status = "okay";
208};
209
210&mmc0 {
211 pinctrl-names = "default", "state_uhs";
212 pinctrl-0 = <&mmc0_pins_default>;
213 pinctrl-1 = <&mmc0_pins_uhs>;
214 bus-width = <8>;
215 max-frequency = <200000000>;
216 cap-mmc-highspeed;
217 mmc-hs200-1_8v;
218 mmc-hs400-1_8v;
219 hs400-ds-delay = <0x14014>;
220 vmmc-supply = <&reg_3p3v>;
221 vqmmc-supply = <&reg_1p8v>;
222 non-removable;
223 no-sd;
224 no-sdio;
225 status = "okay";
226};
227
228&pcie0 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pcie0_pins>;
231 status = "okay";
232};
233
234&wbsys {
235 mediatek,mtd-eeprom = <&factory 0x0000>;
236 status = "okay";
237};
238
239&pio {
240 mmc0_pins_default: mmc0-pins-50-to-61-default {
241 mux {
242 function = "flash";
243 groups = "emmc_51";
244 };
245 conf-cmd-dat {
246 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
247 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
248 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
249 input-enable;
250 drive-strength = <MTK_DRIVE_4mA>;
251 mediatek,pull-up-adv = <1>; /* pull-up 10K */
252 };
253 conf-clk {
254 pins = "EMMC_CK";
255 drive-strength = <MTK_DRIVE_6mA>;
256 mediatek,pull-down-adv = <2>; /* pull-down 50K */
257 };
258 conf-ds {
259 pins = "EMMC_DSL";
260 mediatek,pull-down-adv = <2>; /* pull-down 50K */
261 };
262 conf-rst {
263 pins = "EMMC_RSTB";
264 drive-strength = <MTK_DRIVE_4mA>;
265 mediatek,pull-up-adv = <1>; /* pull-up 10K */
266 };
267 };
268
269 mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
270 mux {
271 function = "flash";
272 groups = "emmc_51";
273 };
274 conf-cmd-dat {
275 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
276 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
277 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
278 input-enable;
279 drive-strength = <MTK_DRIVE_4mA>;
280 mediatek,pull-up-adv = <1>; /* pull-up 10K */
281 };
282 conf-clk {
283 pins = "EMMC_CK";
284 drive-strength = <MTK_DRIVE_6mA>;
285 mediatek,pull-down-adv = <2>; /* pull-down 50K */
286 };
287 conf-ds {
288 pins = "EMMC_DSL";
289 mediatek,pull-down-adv = <2>; /* pull-down 50K */
290 };
291 conf-rst {
292 pins = "EMMC_RSTB";
293 drive-strength = <MTK_DRIVE_4mA>;
294 mediatek,pull-up-adv = <1>; /* pull-up 10K */
295 };
296 };
297};