developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __MT76x02_H |
| 8 | #define __MT76x02_H |
| 9 | |
| 10 | #include <linux/kfifo.h> |
| 11 | |
| 12 | #include "mt76.h" |
| 13 | #include "mt76x02_regs.h" |
| 14 | #include "mt76x02_mac.h" |
| 15 | #include "mt76x02_dfs.h" |
| 16 | #include "mt76x02_dma.h" |
| 17 | |
| 18 | #define MT76x02_TX_RING_SIZE 512 |
| 19 | #define MT76x02_PSD_RING_SIZE 128 |
| 20 | #define MT76x02_N_WCIDS 128 |
| 21 | #define MT_CALIBRATE_INTERVAL HZ |
| 22 | #define MT_MAC_WORK_INTERVAL (HZ / 10) |
| 23 | |
| 24 | #define MT_WATCHDOG_TIME (HZ / 10) |
| 25 | #define MT_TX_HANG_TH 10 |
| 26 | |
| 27 | #define MT_MAX_CHAINS 2 |
| 28 | struct mt76x02_rx_freq_cal { |
| 29 | s8 high_gain[MT_MAX_CHAINS]; |
| 30 | s8 rssi_offset[MT_MAX_CHAINS]; |
| 31 | s8 lna_gain; |
| 32 | u32 mcu_gain; |
| 33 | s16 temp_offset; |
| 34 | u8 freq_offset; |
| 35 | }; |
| 36 | |
| 37 | struct mt76x02_calibration { |
| 38 | struct mt76x02_rx_freq_cal rx; |
| 39 | |
| 40 | u8 agc_gain_init[MT_MAX_CHAINS]; |
| 41 | u8 agc_gain_cur[MT_MAX_CHAINS]; |
| 42 | |
| 43 | u16 false_cca; |
| 44 | s8 avg_rssi_all; |
| 45 | s8 agc_gain_adjust; |
| 46 | s8 agc_lowest_gain; |
| 47 | s8 low_gain; |
| 48 | |
| 49 | s8 temp_vco; |
| 50 | s8 temp; |
| 51 | |
| 52 | bool init_cal_done; |
| 53 | bool tssi_cal_done; |
| 54 | bool tssi_comp_pending; |
| 55 | bool dpd_cal_done; |
| 56 | bool channel_cal_done; |
| 57 | bool gain_init_done; |
| 58 | |
| 59 | int tssi_target; |
| 60 | s8 tssi_dc; |
| 61 | }; |
| 62 | |
| 63 | struct mt76x02_beacon_ops { |
| 64 | unsigned int nslots; |
| 65 | unsigned int slot_size; |
| 66 | void (*pre_tbtt_enable)(struct mt76x02_dev *dev, bool en); |
| 67 | void (*beacon_enable)(struct mt76x02_dev *dev, bool en); |
| 68 | }; |
| 69 | |
| 70 | #define mt76x02_beacon_enable(dev, enable) \ |
| 71 | (dev)->beacon_ops->beacon_enable(dev, enable) |
| 72 | #define mt76x02_pre_tbtt_enable(dev, enable) \ |
| 73 | (dev)->beacon_ops->pre_tbtt_enable(dev, enable) |
| 74 | |
| 75 | struct mt76x02_dev { |
| 76 | union { /* must be first */ |
| 77 | struct mt76_dev mt76; |
| 78 | struct mt76_phy mphy; |
| 79 | }; |
| 80 | |
| 81 | struct mac_address macaddr_list[8]; |
| 82 | |
| 83 | struct mutex phy_mutex; |
| 84 | |
| 85 | u8 txdone_seq; |
| 86 | DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status); |
| 87 | spinlock_t txstatus_fifo_lock; |
| 88 | u32 tx_airtime; |
| 89 | u32 ampdu_ref; |
| 90 | |
| 91 | struct sk_buff *rx_head; |
| 92 | |
| 93 | struct delayed_work cal_work; |
| 94 | struct delayed_work wdt_work; |
| 95 | |
| 96 | struct hrtimer pre_tbtt_timer; |
| 97 | struct work_struct pre_tbtt_work; |
| 98 | |
| 99 | const struct mt76x02_beacon_ops *beacon_ops; |
| 100 | |
| 101 | u8 beacon_data_count; |
| 102 | |
| 103 | u8 tbtt_count; |
| 104 | |
| 105 | u32 tx_hang_reset; |
| 106 | u8 tx_hang_check[4]; |
| 107 | u8 beacon_hang_check; |
| 108 | u8 mcu_timeout; |
| 109 | |
| 110 | struct mt76x02_calibration cal; |
| 111 | |
| 112 | int txpower_conf; |
| 113 | s8 target_power; |
| 114 | s8 target_power_delta[2]; |
| 115 | bool enable_tpc; |
| 116 | |
| 117 | bool no_2ghz; |
| 118 | |
| 119 | s16 coverage_class; |
| 120 | u8 slottime; |
| 121 | |
| 122 | struct mt76x02_dfs_pattern_detector dfs_pd; |
| 123 | |
| 124 | /* edcca monitor */ |
| 125 | unsigned long ed_trigger_timeout; |
| 126 | bool ed_tx_blocked; |
| 127 | bool ed_monitor; |
| 128 | u8 ed_monitor_enabled; |
| 129 | u8 ed_monitor_learning; |
| 130 | u8 ed_trigger; |
| 131 | u8 ed_silent; |
| 132 | ktime_t ed_time; |
| 133 | }; |
| 134 | |
| 135 | extern struct ieee80211_rate mt76x02_rates[12]; |
| 136 | |
| 137 | int mt76x02_init_device(struct mt76x02_dev *dev); |
| 138 | void mt76x02_configure_filter(struct ieee80211_hw *hw, |
| 139 | unsigned int changed_flags, |
| 140 | unsigned int *total_flags, u64 multicast); |
| 141 | int mt76x02_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, |
| 142 | struct ieee80211_sta *sta); |
| 143 | void mt76x02_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, |
| 144 | struct ieee80211_sta *sta); |
| 145 | |
| 146 | void mt76x02_config_mac_addr_list(struct mt76x02_dev *dev); |
| 147 | |
| 148 | int mt76x02_add_interface(struct ieee80211_hw *hw, |
| 149 | struct ieee80211_vif *vif); |
| 150 | void mt76x02_remove_interface(struct ieee80211_hw *hw, |
| 151 | struct ieee80211_vif *vif); |
| 152 | |
| 153 | int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 154 | struct ieee80211_ampdu_params *params); |
| 155 | int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
| 156 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, |
| 157 | struct ieee80211_key_conf *key); |
| 158 | int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 159 | u16 queue, const struct ieee80211_tx_queue_params *params); |
| 160 | void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw, |
| 161 | struct ieee80211_vif *vif, |
| 162 | struct ieee80211_sta *sta); |
| 163 | s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev, |
| 164 | const struct ieee80211_tx_rate *rate); |
| 165 | s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr, |
| 166 | s8 max_txpwr_adj); |
| 167 | void mt76x02_wdt_work(struct work_struct *work); |
| 168 | void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr); |
| 169 | void mt76x02_set_tx_ackto(struct mt76x02_dev *dev); |
| 170 | void mt76x02_set_coverage_class(struct ieee80211_hw *hw, |
| 171 | s16 coverage_class); |
| 172 | int mt76x02_set_rts_threshold(struct ieee80211_hw *hw, u32 val); |
| 173 | void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len); |
| 174 | bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update); |
| 175 | void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, |
| 176 | struct sk_buff *skb); |
| 177 | void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q); |
| 178 | irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance); |
| 179 | void mt76x02_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, |
| 180 | struct sk_buff *skb); |
| 181 | int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi, |
| 182 | enum mt76_txq_id qid, struct mt76_wcid *wcid, |
| 183 | struct ieee80211_sta *sta, |
| 184 | struct mt76_tx_info *tx_info); |
| 185 | void mt76x02_sw_scan_complete(struct ieee80211_hw *hw, |
| 186 | struct ieee80211_vif *vif); |
| 187 | void mt76x02_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps); |
| 188 | void mt76x02_bss_info_changed(struct ieee80211_hw *hw, |
| 189 | struct ieee80211_vif *vif, |
| 190 | struct ieee80211_bss_conf *info, u32 changed); |
| 191 | void mt76x02_reconfig_complete(struct ieee80211_hw *hw, |
| 192 | enum ieee80211_reconfig_type reconfig_type); |
| 193 | |
| 194 | struct beacon_bc_data { |
| 195 | struct mt76x02_dev *dev; |
| 196 | struct sk_buff_head q; |
| 197 | struct sk_buff *tail[8]; |
| 198 | }; |
| 199 | |
| 200 | void mt76x02_init_beacon_config(struct mt76x02_dev *dev); |
| 201 | void mt76x02e_init_beacon_config(struct mt76x02_dev *dev); |
| 202 | void mt76x02_resync_beacon_timer(struct mt76x02_dev *dev); |
| 203 | void mt76x02_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif); |
| 204 | void mt76x02_enqueue_buffered_bc(struct mt76x02_dev *dev, |
| 205 | struct beacon_bc_data *data, |
| 206 | int max_nframes); |
| 207 | |
| 208 | void mt76x02_mac_start(struct mt76x02_dev *dev); |
| 209 | |
| 210 | void mt76x02_init_debugfs(struct mt76x02_dev *dev); |
| 211 | |
| 212 | static inline bool is_mt76x0(struct mt76x02_dev *dev) |
| 213 | { |
| 214 | return mt76_chip(&dev->mt76) == 0x7610 || |
| 215 | mt76_chip(&dev->mt76) == 0x7630 || |
| 216 | mt76_chip(&dev->mt76) == 0x7650; |
| 217 | } |
| 218 | |
| 219 | static inline bool is_mt76x2(struct mt76x02_dev *dev) |
| 220 | { |
| 221 | return mt76_chip(&dev->mt76) == 0x7612 || |
| 222 | mt76_chip(&dev->mt76) == 0x7632 || |
| 223 | mt76_chip(&dev->mt76) == 0x7662 || |
| 224 | mt76_chip(&dev->mt76) == 0x7602; |
| 225 | } |
| 226 | |
| 227 | static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask) |
| 228 | { |
| 229 | mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask); |
| 230 | } |
| 231 | |
| 232 | static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask) |
| 233 | { |
| 234 | mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); |
| 235 | } |
| 236 | |
| 237 | static inline bool |
| 238 | mt76x02_wait_for_txrx_idle(struct mt76_dev *dev) |
| 239 | { |
| 240 | return __mt76_poll_msec(dev, MT_MAC_STATUS, |
| 241 | MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, |
| 242 | 0, 100); |
| 243 | } |
| 244 | |
| 245 | static inline struct mt76x02_sta * |
| 246 | mt76x02_rx_get_sta(struct mt76_dev *dev, u8 idx) |
| 247 | { |
| 248 | struct mt76_wcid *wcid; |
| 249 | |
| 250 | if (idx >= MT76x02_N_WCIDS) |
| 251 | return NULL; |
| 252 | |
| 253 | wcid = rcu_dereference(dev->wcid[idx]); |
| 254 | if (!wcid) |
| 255 | return NULL; |
| 256 | |
| 257 | return container_of(wcid, struct mt76x02_sta, wcid); |
| 258 | } |
| 259 | |
| 260 | static inline struct mt76_wcid * |
| 261 | mt76x02_rx_get_sta_wcid(struct mt76x02_sta *sta, bool unicast) |
| 262 | { |
| 263 | if (!sta) |
| 264 | return NULL; |
| 265 | |
| 266 | if (unicast) |
| 267 | return &sta->wcid; |
| 268 | else |
| 269 | return &sta->vif->group_wcid; |
| 270 | } |
| 271 | |
| 272 | #endif /* __MT76x02_H */ |