developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2019 MediaTek Inc. |
| 3 | * |
| 4 | * Author: Ryder Lee <ryder.lee@mediatek.com> |
| 5 | * Roy Luo <royluo@google.com> |
| 6 | * Felix Fietkau <nbd@nbd.name> |
| 7 | * Lorenzo Bianconi <lorenzo@kernel.org> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/devcoredump.h> |
| 11 | #include <linux/etherdevice.h> |
| 12 | #include <linux/timekeeping.h> |
| 13 | #include "mt7615.h" |
| 14 | #include "../trace.h" |
| 15 | #include "../dma.h" |
| 16 | #include "mt7615_trace.h" |
| 17 | #include "mac.h" |
| 18 | #include "mcu.h" |
| 19 | |
| 20 | #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) |
| 21 | |
| 22 | static const struct mt7615_dfs_radar_spec etsi_radar_specs = { |
| 23 | .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, |
| 24 | .radar_pattern = { |
| 25 | [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 }, |
| 26 | [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 }, |
| 27 | [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 }, |
| 28 | [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 }, |
| 29 | [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 }, |
| 30 | [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 }, |
| 31 | [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 }, |
| 32 | [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 }, |
| 33 | }, |
| 34 | }; |
| 35 | |
| 36 | static const struct mt7615_dfs_radar_spec fcc_radar_specs = { |
| 37 | .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, |
| 38 | .radar_pattern = { |
| 39 | [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 }, |
| 40 | [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, |
| 41 | [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, |
| 42 | [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, |
| 43 | [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 }, |
| 44 | }, |
| 45 | }; |
| 46 | |
| 47 | static const struct mt7615_dfs_radar_spec jp_radar_specs = { |
| 48 | .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, |
| 49 | .radar_pattern = { |
| 50 | [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 }, |
| 51 | [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, |
| 52 | [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, |
| 53 | [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, |
| 54 | [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 }, |
| 55 | [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 }, |
| 56 | [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 }, |
| 57 | }, |
| 58 | }; |
| 59 | |
| 60 | static enum mt76_cipher_type |
| 61 | mt7615_mac_get_cipher(int cipher) |
| 62 | { |
| 63 | switch (cipher) { |
| 64 | case WLAN_CIPHER_SUITE_WEP40: |
| 65 | return MT_CIPHER_WEP40; |
| 66 | case WLAN_CIPHER_SUITE_WEP104: |
| 67 | return MT_CIPHER_WEP104; |
| 68 | case WLAN_CIPHER_SUITE_TKIP: |
| 69 | return MT_CIPHER_TKIP; |
| 70 | case WLAN_CIPHER_SUITE_AES_CMAC: |
| 71 | return MT_CIPHER_BIP_CMAC_128; |
| 72 | case WLAN_CIPHER_SUITE_CCMP: |
| 73 | return MT_CIPHER_AES_CCMP; |
| 74 | case WLAN_CIPHER_SUITE_CCMP_256: |
| 75 | return MT_CIPHER_CCMP_256; |
| 76 | case WLAN_CIPHER_SUITE_GCMP: |
| 77 | return MT_CIPHER_GCMP; |
| 78 | case WLAN_CIPHER_SUITE_GCMP_256: |
| 79 | return MT_CIPHER_GCMP_256; |
| 80 | case WLAN_CIPHER_SUITE_SMS4: |
| 81 | return MT_CIPHER_WAPI; |
| 82 | default: |
| 83 | return MT_CIPHER_NONE; |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev, |
| 88 | u8 idx, bool unicast) |
| 89 | { |
| 90 | struct mt7615_sta *sta; |
| 91 | struct mt76_wcid *wcid; |
| 92 | |
| 93 | if (idx >= MT7615_WTBL_SIZE) |
| 94 | return NULL; |
| 95 | |
| 96 | wcid = rcu_dereference(dev->mt76.wcid[idx]); |
| 97 | if (unicast || !wcid) |
| 98 | return wcid; |
| 99 | |
| 100 | if (!wcid->sta) |
| 101 | return NULL; |
| 102 | |
| 103 | sta = container_of(wcid, struct mt7615_sta, wcid); |
| 104 | if (!sta->vif) |
| 105 | return NULL; |
| 106 | |
| 107 | return &sta->vif->sta.wcid; |
| 108 | } |
| 109 | |
| 110 | void mt7615_mac_reset_counters(struct mt7615_dev *dev) |
| 111 | { |
| 112 | int i; |
| 113 | |
| 114 | for (i = 0; i < 4; i++) { |
| 115 | mt76_rr(dev, MT_TX_AGG_CNT(0, i)); |
| 116 | mt76_rr(dev, MT_TX_AGG_CNT(1, i)); |
| 117 | } |
| 118 | |
| 119 | memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); |
| 120 | dev->mt76.phy.survey_time = ktime_get_boottime(); |
| 121 | if (dev->mt76.phy2) |
| 122 | dev->mt76.phy2->survey_time = ktime_get_boottime(); |
| 123 | |
| 124 | /* reset airtime counters */ |
| 125 | mt76_rr(dev, MT_MIB_SDR9(0)); |
| 126 | mt76_rr(dev, MT_MIB_SDR9(1)); |
| 127 | |
| 128 | mt76_rr(dev, MT_MIB_SDR36(0)); |
| 129 | mt76_rr(dev, MT_MIB_SDR36(1)); |
| 130 | |
| 131 | mt76_rr(dev, MT_MIB_SDR37(0)); |
| 132 | mt76_rr(dev, MT_MIB_SDR37(1)); |
| 133 | |
| 134 | mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); |
| 135 | mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); |
| 136 | } |
| 137 | |
| 138 | void mt7615_mac_set_timing(struct mt7615_phy *phy) |
| 139 | { |
| 140 | s16 coverage_class = phy->coverage_class; |
| 141 | struct mt7615_dev *dev = phy->dev; |
| 142 | bool ext_phy = phy != &dev->phy; |
| 143 | u32 val, reg_offset; |
| 144 | u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | |
| 145 | FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); |
| 146 | u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | |
| 147 | FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); |
| 148 | int sifs, offset; |
| 149 | bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; |
| 150 | |
| 151 | if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) |
| 152 | return; |
| 153 | |
| 154 | if (is_5ghz) |
| 155 | sifs = 16; |
| 156 | else |
| 157 | sifs = 10; |
| 158 | |
| 159 | if (ext_phy) { |
| 160 | coverage_class = max_t(s16, dev->phy.coverage_class, |
| 161 | coverage_class); |
| 162 | mt76_set(dev, MT_ARB_SCR, |
| 163 | MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); |
| 164 | } else { |
| 165 | struct mt7615_phy *phy_ext = mt7615_ext_phy(dev); |
| 166 | |
| 167 | if (phy_ext) |
| 168 | coverage_class = max_t(s16, phy_ext->coverage_class, |
| 169 | coverage_class); |
| 170 | mt76_set(dev, MT_ARB_SCR, |
| 171 | MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); |
| 172 | } |
| 173 | udelay(1); |
| 174 | |
| 175 | offset = 3 * coverage_class; |
| 176 | reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | |
| 177 | FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); |
| 178 | mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); |
| 179 | mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); |
| 180 | |
| 181 | mt76_wr(dev, MT_TMAC_ICR(ext_phy), |
| 182 | FIELD_PREP(MT_IFS_EIFS, 360) | |
| 183 | FIELD_PREP(MT_IFS_RIFS, 2) | |
| 184 | FIELD_PREP(MT_IFS_SIFS, sifs) | |
| 185 | FIELD_PREP(MT_IFS_SLOT, phy->slottime)); |
| 186 | |
| 187 | if (phy->slottime < 20 || is_5ghz) |
| 188 | val = MT7615_CFEND_RATE_DEFAULT; |
| 189 | else |
| 190 | val = MT7615_CFEND_RATE_11B; |
| 191 | |
| 192 | mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val); |
| 193 | if (ext_phy) |
| 194 | mt76_clear(dev, MT_ARB_SCR, |
| 195 | MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); |
| 196 | else |
| 197 | mt76_clear(dev, MT_ARB_SCR, |
| 198 | MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); |
| 199 | |
| 200 | } |
| 201 | |
| 202 | static void |
| 203 | mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy, |
| 204 | struct mt76_rx_status *status, u8 chfreq) |
| 205 | { |
| 206 | if (!test_bit(MT76_HW_SCANNING, &mphy->state) && |
| 207 | !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && |
| 208 | !test_bit(MT76_STATE_ROC, &mphy->state)) { |
| 209 | status->freq = mphy->chandef.chan->center_freq; |
| 210 | status->band = mphy->chandef.chan->band; |
| 211 | return; |
| 212 | } |
| 213 | |
| 214 | status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; |
| 215 | status->freq = ieee80211_channel_to_frequency(chfreq, status->band); |
| 216 | } |
| 217 | |
| 218 | static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv) |
| 219 | { |
| 220 | #ifdef CONFIG_NL80211_TESTMODE |
| 221 | u32 rxv1 = le32_to_cpu(rxv[0]); |
| 222 | u32 rxv3 = le32_to_cpu(rxv[2]); |
| 223 | u32 rxv4 = le32_to_cpu(rxv[3]); |
| 224 | u32 rxv5 = le32_to_cpu(rxv[4]); |
| 225 | u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1); |
| 226 | u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1); |
| 227 | s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5); |
| 228 | u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000; |
| 229 | |
| 230 | if (!mode) { |
| 231 | /* CCK */ |
| 232 | foe &= ~BIT(11); |
| 233 | foe *= 1000; |
| 234 | foe >>= 11; |
| 235 | } else { |
| 236 | if (foe > 2048) |
| 237 | foe -= 4096; |
| 238 | |
| 239 | foe = (foe * foe_const) >> 15; |
| 240 | } |
| 241 | |
| 242 | phy->test.last_freq_offset = foe; |
| 243 | phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4); |
| 244 | phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4); |
| 245 | phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4); |
| 246 | phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4); |
| 247 | phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3); |
| 248 | phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3); |
| 249 | #endif |
| 250 | } |
| 251 | |
| 252 | /* The HW does not translate the mac header to 802.3 for mesh point */ |
| 253 | static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) |
| 254 | { |
| 255 | struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; |
| 256 | struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); |
| 257 | struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid; |
| 258 | __le32 *rxd = (__le32 *)skb->data; |
| 259 | struct ieee80211_sta *sta; |
| 260 | struct ieee80211_vif *vif; |
| 261 | struct ieee80211_hdr hdr; |
| 262 | u16 frame_control; |
| 263 | |
| 264 | if (le32_get_bits(rxd[1], MT_RXD1_NORMAL_ADDR_TYPE) != |
| 265 | MT_RXD1_NORMAL_U2M) |
| 266 | return -EINVAL; |
| 267 | |
| 268 | if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4)) |
| 269 | return -EINVAL; |
| 270 | |
| 271 | if (!msta || !msta->vif) |
| 272 | return -EINVAL; |
| 273 | |
| 274 | sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); |
| 275 | vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); |
| 276 | |
| 277 | /* store the info from RXD and ethhdr to avoid being overridden */ |
| 278 | frame_control = le32_get_bits(rxd[4], MT_RXD4_FRAME_CONTROL); |
| 279 | hdr.frame_control = cpu_to_le16(frame_control); |
| 280 | hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_SEQ_CTRL)); |
| 281 | hdr.duration_id = 0; |
| 282 | |
| 283 | ether_addr_copy(hdr.addr1, vif->addr); |
| 284 | ether_addr_copy(hdr.addr2, sta->addr); |
| 285 | switch (frame_control & (IEEE80211_FCTL_TODS | |
| 286 | IEEE80211_FCTL_FROMDS)) { |
| 287 | case 0: |
| 288 | ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); |
| 289 | break; |
| 290 | case IEEE80211_FCTL_FROMDS: |
| 291 | ether_addr_copy(hdr.addr3, eth_hdr->h_source); |
| 292 | break; |
| 293 | case IEEE80211_FCTL_TODS: |
| 294 | ether_addr_copy(hdr.addr3, eth_hdr->h_dest); |
| 295 | break; |
| 296 | case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: |
| 297 | ether_addr_copy(hdr.addr3, eth_hdr->h_dest); |
| 298 | ether_addr_copy(hdr.addr4, eth_hdr->h_source); |
| 299 | break; |
| 300 | default: |
| 301 | break; |
| 302 | } |
| 303 | |
| 304 | skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); |
| 305 | if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || |
| 306 | eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) |
| 307 | ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); |
| 308 | else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) |
| 309 | ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); |
| 310 | else |
| 311 | skb_pull(skb, 2); |
| 312 | |
| 313 | if (ieee80211_has_order(hdr.frame_control)) |
| 314 | memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[7], |
| 315 | IEEE80211_HT_CTL_LEN); |
| 316 | |
| 317 | if (ieee80211_is_data_qos(hdr.frame_control)) { |
| 318 | __le16 qos_ctrl; |
| 319 | |
| 320 | qos_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_QOS_CTL)); |
| 321 | memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, |
| 322 | IEEE80211_QOS_CTL_LEN); |
| 323 | } |
| 324 | |
| 325 | if (ieee80211_has_a4(hdr.frame_control)) |
| 326 | memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); |
| 327 | else |
| 328 | memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); |
| 329 | |
| 330 | status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU); |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb) |
| 335 | { |
| 336 | struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; |
| 337 | struct mt76_phy *mphy = &dev->mt76.phy; |
| 338 | struct mt7615_phy *phy = &dev->phy; |
| 339 | struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL; |
| 340 | struct ieee80211_supported_band *sband; |
| 341 | struct ieee80211_hdr *hdr; |
| 342 | __le32 *rxd = (__le32 *)skb->data; |
| 343 | u32 rxd0 = le32_to_cpu(rxd[0]); |
| 344 | u32 rxd1 = le32_to_cpu(rxd[1]); |
| 345 | u32 rxd2 = le32_to_cpu(rxd[2]); |
| 346 | u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; |
| 347 | bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false; |
| 348 | u16 hdr_gap; |
| 349 | int phy_idx; |
| 350 | int i, idx; |
| 351 | u8 chfreq, amsdu_info, qos_ctl = 0; |
| 352 | u16 seq_ctrl = 0; |
| 353 | __le16 fc = 0; |
| 354 | |
| 355 | memset(status, 0, sizeof(*status)); |
| 356 | |
| 357 | chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); |
| 358 | if (!phy2) |
| 359 | phy_idx = 0; |
| 360 | else if (phy2->chfreq == phy->chfreq) |
| 361 | phy_idx = -1; |
| 362 | else if (phy->chfreq == chfreq) |
| 363 | phy_idx = 0; |
| 364 | else if (phy2->chfreq == chfreq) |
| 365 | phy_idx = 1; |
| 366 | else |
| 367 | phy_idx = -1; |
| 368 | |
| 369 | if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) |
| 370 | return -EINVAL; |
| 371 | |
| 372 | hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS; |
| 373 | if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM)) |
| 374 | return -EINVAL; |
| 375 | |
| 376 | /* ICV error or CCMP/BIP/WPI MIC error */ |
| 377 | if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) |
| 378 | status->flag |= RX_FLAG_ONLY_MONITOR; |
| 379 | |
| 380 | unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M; |
| 381 | idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); |
| 382 | status->wcid = mt7615_rx_get_wcid(dev, idx, unicast); |
| 383 | |
| 384 | if (status->wcid) { |
| 385 | struct mt7615_sta *msta; |
| 386 | |
| 387 | msta = container_of(status->wcid, struct mt7615_sta, wcid); |
| 388 | spin_lock_bh(&dev->sta_poll_lock); |
| 389 | if (list_empty(&msta->poll_list)) |
| 390 | list_add_tail(&msta->poll_list, &dev->sta_poll_list); |
| 391 | spin_unlock_bh(&dev->sta_poll_lock); |
| 392 | } |
| 393 | |
| 394 | if ((rxd0 & csum_mask) == csum_mask) |
| 395 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 396 | |
| 397 | if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) |
| 398 | status->flag |= RX_FLAG_FAILED_FCS_CRC; |
| 399 | |
| 400 | if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) |
| 401 | status->flag |= RX_FLAG_MMIC_ERROR; |
| 402 | |
| 403 | if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && |
| 404 | !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { |
| 405 | status->flag |= RX_FLAG_DECRYPTED; |
| 406 | status->flag |= RX_FLAG_IV_STRIPPED; |
| 407 | status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; |
| 408 | } |
| 409 | |
| 410 | remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; |
| 411 | |
| 412 | if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) |
| 413 | return -EINVAL; |
| 414 | |
| 415 | rxd += 4; |
| 416 | if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { |
| 417 | u32 v0 = le32_to_cpu(rxd[0]); |
| 418 | u32 v2 = le32_to_cpu(rxd[2]); |
| 419 | |
| 420 | fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0)); |
| 421 | qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2); |
| 422 | seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2); |
| 423 | |
| 424 | rxd += 4; |
| 425 | if ((u8 *)rxd - skb->data >= skb->len) |
| 426 | return -EINVAL; |
| 427 | } |
| 428 | |
| 429 | if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { |
| 430 | u8 *data = (u8 *)rxd; |
| 431 | |
| 432 | if (status->flag & RX_FLAG_DECRYPTED) { |
| 433 | switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { |
| 434 | case MT_CIPHER_AES_CCMP: |
| 435 | case MT_CIPHER_CCMP_CCX: |
| 436 | case MT_CIPHER_CCMP_256: |
| 437 | insert_ccmp_hdr = |
| 438 | FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); |
| 439 | fallthrough; |
| 440 | case MT_CIPHER_TKIP: |
| 441 | case MT_CIPHER_TKIP_NO_MIC: |
| 442 | case MT_CIPHER_GCMP: |
| 443 | case MT_CIPHER_GCMP_256: |
| 444 | status->iv[0] = data[5]; |
| 445 | status->iv[1] = data[4]; |
| 446 | status->iv[2] = data[3]; |
| 447 | status->iv[3] = data[2]; |
| 448 | status->iv[4] = data[1]; |
| 449 | status->iv[5] = data[0]; |
| 450 | break; |
| 451 | default: |
| 452 | break; |
| 453 | } |
| 454 | } |
| 455 | rxd += 4; |
| 456 | if ((u8 *)rxd - skb->data >= skb->len) |
| 457 | return -EINVAL; |
| 458 | } |
| 459 | |
| 460 | if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { |
| 461 | status->timestamp = le32_to_cpu(rxd[0]); |
| 462 | status->flag |= RX_FLAG_MACTIME_START; |
| 463 | |
| 464 | if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | |
| 465 | MT_RXD2_NORMAL_NON_AMPDU))) { |
| 466 | status->flag |= RX_FLAG_AMPDU_DETAILS; |
| 467 | |
| 468 | /* all subframes of an A-MPDU have the same timestamp */ |
| 469 | if (phy->rx_ampdu_ts != status->timestamp) { |
| 470 | if (!++phy->ampdu_ref) |
| 471 | phy->ampdu_ref++; |
| 472 | } |
| 473 | phy->rx_ampdu_ts = status->timestamp; |
| 474 | |
| 475 | status->ampdu_ref = phy->ampdu_ref; |
| 476 | } |
| 477 | |
| 478 | rxd += 2; |
| 479 | if ((u8 *)rxd - skb->data >= skb->len) |
| 480 | return -EINVAL; |
| 481 | } |
| 482 | |
| 483 | if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { |
| 484 | u32 rxdg5 = le32_to_cpu(rxd[5]); |
| 485 | |
| 486 | /* |
| 487 | * If both PHYs are on the same channel and we don't have a WCID, |
| 488 | * we need to figure out which PHY this packet was received on. |
| 489 | * On the primary PHY, the noise value for the chains belonging to the |
| 490 | * second PHY will be set to the noise value of the last packet from |
| 491 | * that PHY. |
| 492 | */ |
| 493 | if (phy_idx < 0) { |
| 494 | int first_chain = ffs(phy2->mt76->chainmask) - 1; |
| 495 | |
| 496 | phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0; |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | if (phy_idx == 1 && phy2) { |
| 501 | mphy = dev->mt76.phy2; |
| 502 | phy = phy2; |
| 503 | status->ext_phy = true; |
| 504 | } |
| 505 | |
| 506 | if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq) |
| 507 | return -EINVAL; |
| 508 | |
| 509 | mt7615_get_status_freq_info(dev, mphy, status, chfreq); |
| 510 | if (status->band == NL80211_BAND_5GHZ) |
| 511 | sband = &mphy->sband_5g.sband; |
| 512 | else |
| 513 | sband = &mphy->sband_2g.sband; |
| 514 | |
| 515 | if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) |
| 516 | return -EINVAL; |
| 517 | |
| 518 | if (!sband->channels) |
| 519 | return -EINVAL; |
| 520 | |
| 521 | if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { |
| 522 | u32 rxdg0 = le32_to_cpu(rxd[0]); |
| 523 | u32 rxdg1 = le32_to_cpu(rxd[1]); |
| 524 | u32 rxdg3 = le32_to_cpu(rxd[3]); |
| 525 | u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0); |
| 526 | bool cck = false; |
| 527 | |
| 528 | i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); |
| 529 | switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { |
| 530 | case MT_PHY_TYPE_CCK: |
| 531 | cck = true; |
| 532 | fallthrough; |
| 533 | case MT_PHY_TYPE_OFDM: |
| 534 | i = mt76_get_rate(&dev->mt76, sband, i, cck); |
| 535 | break; |
| 536 | case MT_PHY_TYPE_HT_GF: |
| 537 | case MT_PHY_TYPE_HT: |
| 538 | status->encoding = RX_ENC_HT; |
| 539 | if (i > 31) |
| 540 | return -EINVAL; |
| 541 | break; |
| 542 | case MT_PHY_TYPE_VHT: |
| 543 | status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1; |
| 544 | status->encoding = RX_ENC_VHT; |
| 545 | break; |
| 546 | default: |
| 547 | return -EINVAL; |
| 548 | } |
| 549 | status->rate_idx = i; |
| 550 | |
| 551 | switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) { |
| 552 | case MT_PHY_BW_20: |
| 553 | break; |
| 554 | case MT_PHY_BW_40: |
| 555 | status->bw = RATE_INFO_BW_40; |
| 556 | break; |
| 557 | case MT_PHY_BW_80: |
| 558 | status->bw = RATE_INFO_BW_80; |
| 559 | break; |
| 560 | case MT_PHY_BW_160: |
| 561 | status->bw = RATE_INFO_BW_160; |
| 562 | break; |
| 563 | default: |
| 564 | return -EINVAL; |
| 565 | } |
| 566 | |
| 567 | if (rxdg0 & MT_RXV1_HT_SHORT_GI) |
| 568 | status->enc_flags |= RX_ENC_FLAG_SHORT_GI; |
| 569 | if (rxdg0 & MT_RXV1_HT_AD_CODE) |
| 570 | status->enc_flags |= RX_ENC_FLAG_LDPC; |
| 571 | |
| 572 | status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; |
| 573 | |
| 574 | status->chains = mphy->antenna_mask; |
| 575 | status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3); |
| 576 | status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3); |
| 577 | status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3); |
| 578 | status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3); |
| 579 | |
| 580 | mt7615_mac_fill_tm_rx(mphy->priv, rxd); |
| 581 | |
| 582 | rxd += 6; |
| 583 | if ((u8 *)rxd - skb->data >= skb->len) |
| 584 | return -EINVAL; |
| 585 | } |
| 586 | |
| 587 | amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1); |
| 588 | status->amsdu = !!amsdu_info; |
| 589 | if (status->amsdu) { |
| 590 | status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME; |
| 591 | status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME; |
| 592 | } |
| 593 | |
| 594 | hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; |
| 595 | if (hdr_trans && ieee80211_has_morefrags(fc)) { |
| 596 | if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap)) |
| 597 | return -EINVAL; |
| 598 | hdr_trans = false; |
| 599 | } else { |
| 600 | int pad_start = 0; |
| 601 | |
| 602 | skb_pull(skb, hdr_gap); |
| 603 | if (!hdr_trans && status->amsdu) { |
| 604 | pad_start = ieee80211_get_hdrlen_from_skb(skb); |
| 605 | } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { |
| 606 | /* |
| 607 | * When header translation failure is indicated, |
| 608 | * the hardware will insert an extra 2-byte field |
| 609 | * containing the data length after the protocol |
| 610 | * type field. |
| 611 | */ |
| 612 | pad_start = 12; |
| 613 | if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) |
| 614 | pad_start += 4; |
| 615 | |
| 616 | if (get_unaligned_be16(skb->data + pad_start) != |
| 617 | skb->len - pad_start - 2) |
| 618 | pad_start = 0; |
| 619 | } |
| 620 | |
| 621 | if (pad_start) { |
| 622 | memmove(skb->data + 2, skb->data, pad_start); |
| 623 | skb_pull(skb, 2); |
| 624 | } |
| 625 | } |
| 626 | |
| 627 | if (insert_ccmp_hdr && !hdr_trans) { |
| 628 | u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); |
| 629 | |
| 630 | mt76_insert_ccmp_hdr(skb, key_id); |
| 631 | } |
| 632 | |
| 633 | if (!hdr_trans) { |
| 634 | hdr = (struct ieee80211_hdr *)skb->data; |
| 635 | fc = hdr->frame_control; |
| 636 | if (ieee80211_is_data_qos(fc)) { |
| 637 | seq_ctrl = le16_to_cpu(hdr->seq_ctrl); |
| 638 | qos_ctl = *ieee80211_get_qos_ctl(hdr); |
| 639 | } |
| 640 | } else { |
| 641 | status->flag |= RX_FLAG_8023; |
| 642 | } |
| 643 | |
| 644 | if (!status->wcid || !ieee80211_is_data_qos(fc)) |
| 645 | return 0; |
| 646 | |
| 647 | status->aggr = unicast && |
| 648 | !ieee80211_is_qos_nullfunc(fc); |
| 649 | status->qos_ctl = qos_ctl; |
| 650 | status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); |
| 651 | |
| 652 | return 0; |
| 653 | } |
| 654 | |
| 655 | void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) |
| 656 | { |
| 657 | } |
| 658 | EXPORT_SYMBOL_GPL(mt7615_sta_ps); |
| 659 | |
| 660 | static u16 |
| 661 | mt7615_mac_tx_rate_val(struct mt7615_dev *dev, |
| 662 | struct mt76_phy *mphy, |
| 663 | const struct ieee80211_tx_rate *rate, |
| 664 | bool stbc, u8 *bw) |
| 665 | { |
| 666 | u8 phy, nss, rate_idx; |
| 667 | u16 rateval = 0; |
| 668 | |
| 669 | *bw = 0; |
| 670 | |
| 671 | if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { |
| 672 | rate_idx = ieee80211_rate_get_vht_mcs(rate); |
| 673 | nss = ieee80211_rate_get_vht_nss(rate); |
| 674 | phy = MT_PHY_TYPE_VHT; |
| 675 | if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) |
| 676 | *bw = 1; |
| 677 | else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) |
| 678 | *bw = 2; |
| 679 | else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) |
| 680 | *bw = 3; |
| 681 | } else if (rate->flags & IEEE80211_TX_RC_MCS) { |
| 682 | rate_idx = rate->idx; |
| 683 | nss = 1 + (rate->idx >> 3); |
| 684 | phy = MT_PHY_TYPE_HT; |
| 685 | if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) |
| 686 | phy = MT_PHY_TYPE_HT_GF; |
| 687 | if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) |
| 688 | *bw = 1; |
| 689 | } else { |
| 690 | const struct ieee80211_rate *r; |
| 691 | int band = mphy->chandef.chan->band; |
| 692 | u16 val; |
| 693 | |
| 694 | nss = 1; |
| 695 | r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx]; |
| 696 | if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) |
| 697 | val = r->hw_value_short; |
| 698 | else |
| 699 | val = r->hw_value; |
| 700 | |
| 701 | phy = val >> 8; |
| 702 | rate_idx = val & 0xff; |
| 703 | } |
| 704 | |
| 705 | if (stbc && nss == 1) { |
| 706 | nss++; |
| 707 | rateval |= MT_TX_RATE_STBC; |
| 708 | } |
| 709 | |
| 710 | rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | |
| 711 | FIELD_PREP(MT_TX_RATE_MODE, phy) | |
| 712 | FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); |
| 713 | |
| 714 | return rateval; |
| 715 | } |
| 716 | |
| 717 | int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi, |
| 718 | struct sk_buff *skb, struct mt76_wcid *wcid, |
| 719 | struct ieee80211_sta *sta, int pid, |
| 720 | struct ieee80211_key_conf *key, bool beacon) |
| 721 | { |
| 722 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 723 | u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; |
| 724 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 725 | struct ieee80211_tx_rate *rate = &info->control.rates[0]; |
| 726 | bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; |
| 727 | bool multicast = is_multicast_ether_addr(hdr->addr1); |
| 728 | struct ieee80211_vif *vif = info->control.vif; |
| 729 | bool is_mmio = mt76_is_mmio(&dev->mt76); |
| 730 | u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE; |
| 731 | struct mt76_phy *mphy = &dev->mphy; |
| 732 | __le16 fc = hdr->frame_control; |
| 733 | int tx_count = 8; |
| 734 | u16 seqno = 0; |
| 735 | |
| 736 | if (vif) { |
| 737 | struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; |
| 738 | |
| 739 | omac_idx = mvif->omac_idx; |
| 740 | wmm_idx = mvif->wmm_idx; |
| 741 | } |
| 742 | |
| 743 | if (sta) { |
| 744 | struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; |
| 745 | |
| 746 | tx_count = msta->rate_count; |
| 747 | } |
| 748 | |
| 749 | if (ext_phy && dev->mt76.phy2) |
| 750 | mphy = dev->mt76.phy2; |
| 751 | |
| 752 | fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; |
| 753 | fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; |
| 754 | |
| 755 | if (beacon) { |
| 756 | p_fmt = MT_TX_TYPE_FW; |
| 757 | q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0; |
| 758 | } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { |
| 759 | p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; |
| 760 | q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0; |
| 761 | } else { |
| 762 | p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; |
| 763 | q_idx = wmm_idx * MT7615_MAX_WMM_SETS + |
| 764 | mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb)); |
| 765 | } |
| 766 | |
| 767 | val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | |
| 768 | FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | |
| 769 | FIELD_PREP(MT_TXD0_Q_IDX, q_idx); |
| 770 | txwi[0] = cpu_to_le32(val); |
| 771 | |
| 772 | val = MT_TXD1_LONG_FORMAT | |
| 773 | FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | |
| 774 | FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | |
| 775 | FIELD_PREP(MT_TXD1_HDR_INFO, |
| 776 | ieee80211_get_hdrlen_from_skb(skb) / 2) | |
| 777 | FIELD_PREP(MT_TXD1_TID, |
| 778 | skb->priority & IEEE80211_QOS_CTL_TID_MASK) | |
| 779 | FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) | |
| 780 | FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); |
| 781 | txwi[1] = cpu_to_le32(val); |
| 782 | |
| 783 | val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | |
| 784 | FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | |
| 785 | FIELD_PREP(MT_TXD2_MULTICAST, multicast); |
| 786 | if (key) { |
| 787 | if (multicast && ieee80211_is_robust_mgmt_frame(skb) && |
| 788 | key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { |
| 789 | val |= MT_TXD2_BIP; |
| 790 | txwi[3] = 0; |
| 791 | } else { |
| 792 | txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME); |
| 793 | } |
| 794 | } else { |
| 795 | txwi[3] = 0; |
| 796 | } |
| 797 | txwi[2] = cpu_to_le32(val); |
| 798 | |
| 799 | if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) |
| 800 | txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); |
| 801 | |
| 802 | txwi[4] = 0; |
| 803 | txwi[6] = 0; |
| 804 | |
| 805 | if (rate->idx >= 0 && rate->count && |
| 806 | !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { |
| 807 | bool stbc = info->flags & IEEE80211_TX_CTL_STBC; |
| 808 | u8 bw; |
| 809 | u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc, |
| 810 | &bw); |
| 811 | |
| 812 | txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); |
| 813 | |
| 814 | val = MT_TXD6_FIXED_BW | |
| 815 | FIELD_PREP(MT_TXD6_BW, bw) | |
| 816 | FIELD_PREP(MT_TXD6_TX_RATE, rateval); |
| 817 | txwi[6] |= cpu_to_le32(val); |
| 818 | |
| 819 | if (rate->flags & IEEE80211_TX_RC_SHORT_GI) |
| 820 | txwi[6] |= cpu_to_le32(MT_TXD6_SGI); |
| 821 | |
| 822 | if (info->flags & IEEE80211_TX_CTL_LDPC) |
| 823 | txwi[6] |= cpu_to_le32(MT_TXD6_LDPC); |
| 824 | |
| 825 | if (!(rate->flags & (IEEE80211_TX_RC_MCS | |
| 826 | IEEE80211_TX_RC_VHT_MCS))) |
| 827 | txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); |
| 828 | |
| 829 | tx_count = rate->count; |
| 830 | } |
| 831 | |
| 832 | if (!ieee80211_is_beacon(fc)) { |
| 833 | struct ieee80211_hw *hw = mt76_hw(dev); |
| 834 | |
| 835 | val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid); |
| 836 | if (!ieee80211_hw_check(hw, SUPPORTS_PS)) |
| 837 | val |= MT_TXD5_SW_POWER_MGMT; |
| 838 | txwi[5] = cpu_to_le32(val); |
| 839 | } else { |
| 840 | txwi[5] = 0; |
| 841 | /* use maximum tx count for beacons */ |
| 842 | tx_count = 0x1f; |
| 843 | } |
| 844 | |
| 845 | val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); |
| 846 | if (info->flags & IEEE80211_TX_CTL_INJECTED) { |
| 847 | seqno = le16_to_cpu(hdr->seq_ctrl); |
| 848 | |
| 849 | if (ieee80211_is_back_req(hdr->frame_control)) { |
| 850 | struct ieee80211_bar *bar; |
| 851 | |
| 852 | bar = (struct ieee80211_bar *)skb->data; |
| 853 | seqno = le16_to_cpu(bar->start_seq_num); |
| 854 | } |
| 855 | |
| 856 | val |= MT_TXD3_SN_VALID | |
| 857 | FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); |
| 858 | } |
| 859 | |
| 860 | txwi[3] |= cpu_to_le32(val); |
| 861 | |
| 862 | if (info->flags & IEEE80211_TX_CTL_NO_ACK) |
| 863 | txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK); |
| 864 | |
| 865 | val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | |
| 866 | FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) | |
| 867 | FIELD_PREP(MT_TXD7_SPE_IDX, 0x18); |
| 868 | txwi[7] = cpu_to_le32(val); |
| 869 | if (!is_mmio) { |
| 870 | val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) | |
| 871 | FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype); |
| 872 | txwi[8] = cpu_to_le32(val); |
| 873 | } |
| 874 | |
| 875 | return 0; |
| 876 | } |
| 877 | EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi); |
| 878 | |
| 879 | static void |
| 880 | mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp) |
| 881 | { |
| 882 | int i; |
| 883 | |
| 884 | for (i = 0; i < txp->nbuf; i++) |
| 885 | dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), |
| 886 | le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); |
| 887 | } |
| 888 | |
| 889 | static void |
| 890 | mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp) |
| 891 | { |
| 892 | u32 last_mask; |
| 893 | int i; |
| 894 | |
| 895 | last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST; |
| 896 | |
| 897 | for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) { |
| 898 | struct mt7615_txp_ptr *ptr = &txp->ptr[i]; |
| 899 | bool last; |
| 900 | u16 len; |
| 901 | |
| 902 | len = le16_to_cpu(ptr->len0); |
| 903 | last = len & last_mask; |
| 904 | len &= MT_TXD_LEN_MASK; |
| 905 | dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len, |
| 906 | DMA_TO_DEVICE); |
| 907 | if (last) |
| 908 | break; |
| 909 | |
| 910 | len = le16_to_cpu(ptr->len1); |
| 911 | last = len & last_mask; |
| 912 | len &= MT_TXD_LEN_MASK; |
| 913 | dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len, |
| 914 | DMA_TO_DEVICE); |
| 915 | if (last) |
| 916 | break; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | void mt7615_txp_skb_unmap(struct mt76_dev *dev, |
| 921 | struct mt76_txwi_cache *t) |
| 922 | { |
| 923 | struct mt7615_txp_common *txp; |
| 924 | |
| 925 | txp = mt7615_txwi_to_txp(dev, t); |
| 926 | if (is_mt7615(dev)) |
| 927 | mt7615_txp_skb_unmap_fw(dev, &txp->fw); |
| 928 | else |
| 929 | mt7615_txp_skb_unmap_hw(dev, &txp->hw); |
| 930 | } |
| 931 | EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap); |
| 932 | |
| 933 | bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask) |
| 934 | { |
| 935 | mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, |
| 936 | FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); |
| 937 | |
| 938 | return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, |
| 939 | 0, 5000); |
| 940 | } |
| 941 | |
| 942 | void mt7615_mac_sta_poll(struct mt7615_dev *dev) |
| 943 | { |
| 944 | static const u8 ac_to_tid[4] = { |
| 945 | [IEEE80211_AC_BE] = 0, |
| 946 | [IEEE80211_AC_BK] = 1, |
| 947 | [IEEE80211_AC_VI] = 4, |
| 948 | [IEEE80211_AC_VO] = 6 |
| 949 | }; |
| 950 | static const u8 hw_queue_map[] = { |
| 951 | [IEEE80211_AC_BK] = 0, |
| 952 | [IEEE80211_AC_BE] = 1, |
| 953 | [IEEE80211_AC_VI] = 2, |
| 954 | [IEEE80211_AC_VO] = 3, |
| 955 | }; |
| 956 | struct ieee80211_sta *sta; |
| 957 | struct mt7615_sta *msta; |
| 958 | u32 addr, tx_time[4], rx_time[4]; |
| 959 | struct list_head sta_poll_list; |
| 960 | int i; |
| 961 | |
| 962 | INIT_LIST_HEAD(&sta_poll_list); |
| 963 | spin_lock_bh(&dev->sta_poll_lock); |
| 964 | list_splice_init(&dev->sta_poll_list, &sta_poll_list); |
| 965 | spin_unlock_bh(&dev->sta_poll_lock); |
| 966 | |
| 967 | while (!list_empty(&sta_poll_list)) { |
| 968 | bool clear = false; |
| 969 | |
| 970 | msta = list_first_entry(&sta_poll_list, struct mt7615_sta, |
| 971 | poll_list); |
| 972 | list_del_init(&msta->poll_list); |
| 973 | |
| 974 | addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4; |
| 975 | |
| 976 | for (i = 0; i < 4; i++, addr += 8) { |
| 977 | u32 tx_last = msta->airtime_ac[i]; |
| 978 | u32 rx_last = msta->airtime_ac[i + 4]; |
| 979 | |
| 980 | msta->airtime_ac[i] = mt76_rr(dev, addr); |
| 981 | msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); |
| 982 | tx_time[i] = msta->airtime_ac[i] - tx_last; |
| 983 | rx_time[i] = msta->airtime_ac[i + 4] - rx_last; |
| 984 | |
| 985 | if ((tx_last | rx_last) & BIT(30)) |
| 986 | clear = true; |
| 987 | } |
| 988 | |
| 989 | if (clear) { |
| 990 | mt7615_mac_wtbl_update(dev, msta->wcid.idx, |
| 991 | MT_WTBL_UPDATE_ADM_COUNT_CLEAR); |
| 992 | memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); |
| 993 | } |
| 994 | |
| 995 | if (!msta->wcid.sta) |
| 996 | continue; |
| 997 | |
| 998 | sta = container_of((void *)msta, struct ieee80211_sta, |
| 999 | drv_priv); |
| 1000 | for (i = 0; i < 4; i++) { |
| 1001 | u32 tx_cur = tx_time[i]; |
| 1002 | u32 rx_cur = rx_time[hw_queue_map[i]]; |
| 1003 | u8 tid = ac_to_tid[i]; |
| 1004 | |
| 1005 | if (!tx_cur && !rx_cur) |
| 1006 | continue; |
| 1007 | |
| 1008 | ieee80211_sta_register_airtime(sta, tid, tx_cur, |
| 1009 | rx_cur); |
| 1010 | } |
| 1011 | } |
| 1012 | } |
| 1013 | EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll); |
| 1014 | |
| 1015 | static void |
| 1016 | mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta, |
| 1017 | struct ieee80211_tx_rate *probe_rate, |
| 1018 | struct ieee80211_tx_rate *rates, |
| 1019 | struct mt7615_rate_desc *rd) |
| 1020 | { |
| 1021 | struct mt7615_dev *dev = phy->dev; |
| 1022 | struct mt76_phy *mphy = phy->mt76; |
| 1023 | struct ieee80211_tx_rate *ref; |
| 1024 | bool rateset, stbc = false; |
| 1025 | int n_rates = sta->n_rates; |
| 1026 | u8 bw, bw_prev; |
| 1027 | int i, j; |
| 1028 | |
| 1029 | for (i = n_rates; i < 4; i++) |
| 1030 | rates[i] = rates[n_rates - 1]; |
| 1031 | |
| 1032 | rateset = !(sta->rate_set_tsf & BIT(0)); |
| 1033 | memcpy(sta->rateset[rateset].rates, rates, |
| 1034 | sizeof(sta->rateset[rateset].rates)); |
| 1035 | if (probe_rate) { |
| 1036 | sta->rateset[rateset].probe_rate = *probe_rate; |
| 1037 | ref = &sta->rateset[rateset].probe_rate; |
| 1038 | } else { |
| 1039 | sta->rateset[rateset].probe_rate.idx = -1; |
| 1040 | ref = &sta->rateset[rateset].rates[0]; |
| 1041 | } |
| 1042 | |
| 1043 | rates = sta->rateset[rateset].rates; |
| 1044 | for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { |
| 1045 | /* |
| 1046 | * We don't support switching between short and long GI |
| 1047 | * within the rate set. For accurate tx status reporting, we |
| 1048 | * need to make sure that flags match. |
| 1049 | * For improved performance, avoid duplicate entries by |
| 1050 | * decrementing the MCS index if necessary |
| 1051 | */ |
| 1052 | if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) |
| 1053 | rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; |
| 1054 | |
| 1055 | for (j = 0; j < i; j++) { |
| 1056 | if (rates[i].idx != rates[j].idx) |
| 1057 | continue; |
| 1058 | if ((rates[i].flags ^ rates[j].flags) & |
| 1059 | (IEEE80211_TX_RC_40_MHZ_WIDTH | |
| 1060 | IEEE80211_TX_RC_80_MHZ_WIDTH | |
| 1061 | IEEE80211_TX_RC_160_MHZ_WIDTH)) |
| 1062 | continue; |
| 1063 | |
| 1064 | if (!rates[i].idx) |
| 1065 | continue; |
| 1066 | |
| 1067 | rates[i].idx--; |
| 1068 | } |
| 1069 | } |
| 1070 | |
| 1071 | rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw); |
| 1072 | bw_prev = bw; |
| 1073 | |
| 1074 | if (probe_rate) { |
| 1075 | rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate, |
| 1076 | stbc, &bw); |
| 1077 | if (bw) |
| 1078 | rd->bw_idx = 1; |
| 1079 | else |
| 1080 | bw_prev = 0; |
| 1081 | } else { |
| 1082 | rd->probe_val = rd->val[0]; |
| 1083 | } |
| 1084 | |
| 1085 | rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw); |
| 1086 | if (bw_prev) { |
| 1087 | rd->bw_idx = 3; |
| 1088 | bw_prev = bw; |
| 1089 | } |
| 1090 | |
| 1091 | rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw); |
| 1092 | if (bw_prev) { |
| 1093 | rd->bw_idx = 5; |
| 1094 | bw_prev = bw; |
| 1095 | } |
| 1096 | |
| 1097 | rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw); |
| 1098 | if (bw_prev) |
| 1099 | rd->bw_idx = 7; |
| 1100 | |
| 1101 | rd->rateset = rateset; |
| 1102 | rd->bw = bw; |
| 1103 | } |
| 1104 | |
| 1105 | static int |
| 1106 | mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta, |
| 1107 | struct ieee80211_tx_rate *probe_rate, |
| 1108 | struct ieee80211_tx_rate *rates) |
| 1109 | { |
| 1110 | struct mt7615_dev *dev = phy->dev; |
| 1111 | struct mt7615_wtbl_rate_desc *wrd; |
| 1112 | |
| 1113 | if (work_pending(&dev->rate_work)) |
| 1114 | return -EBUSY; |
| 1115 | |
| 1116 | wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC); |
| 1117 | if (!wrd) |
| 1118 | return -ENOMEM; |
| 1119 | |
| 1120 | wrd->sta = sta; |
| 1121 | mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, |
| 1122 | &wrd->rate); |
| 1123 | list_add_tail(&wrd->node, &dev->wrd_head); |
| 1124 | queue_work(dev->mt76.wq, &dev->rate_work); |
| 1125 | |
| 1126 | return 0; |
| 1127 | } |
| 1128 | |
| 1129 | u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid) |
| 1130 | { |
| 1131 | u32 addr, val, val2; |
| 1132 | u8 offset; |
| 1133 | |
| 1134 | addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4; |
| 1135 | |
| 1136 | offset = tid * 12; |
| 1137 | addr += 4 * (offset / 32); |
| 1138 | offset %= 32; |
| 1139 | |
| 1140 | val = mt76_rr(dev, addr); |
| 1141 | val >>= (tid % 32); |
| 1142 | |
| 1143 | if (offset > 20) { |
| 1144 | addr += 4; |
| 1145 | val2 = mt76_rr(dev, addr); |
| 1146 | val |= val2 << (32 - offset); |
| 1147 | } |
| 1148 | |
| 1149 | return val & GENMASK(11, 0); |
| 1150 | } |
| 1151 | |
| 1152 | void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta, |
| 1153 | struct ieee80211_tx_rate *probe_rate, |
| 1154 | struct ieee80211_tx_rate *rates) |
| 1155 | { |
| 1156 | int wcid = sta->wcid.idx, n_rates = sta->n_rates; |
| 1157 | struct mt7615_dev *dev = phy->dev; |
| 1158 | struct mt7615_rate_desc rd; |
| 1159 | u32 w5, w27, addr; |
| 1160 | u16 idx = sta->vif->mt76.omac_idx; |
| 1161 | |
| 1162 | if (!mt76_is_mmio(&dev->mt76)) { |
| 1163 | mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates); |
| 1164 | return; |
| 1165 | } |
| 1166 | |
| 1167 | if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) |
| 1168 | return; |
| 1169 | |
| 1170 | memset(&rd, 0, sizeof(struct mt7615_rate_desc)); |
| 1171 | mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd); |
| 1172 | |
| 1173 | addr = mt7615_mac_wtbl_addr(dev, wcid); |
| 1174 | w27 = mt76_rr(dev, addr + 27 * 4); |
| 1175 | w27 &= ~MT_WTBL_W27_CC_BW_SEL; |
| 1176 | w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw); |
| 1177 | |
| 1178 | w5 = mt76_rr(dev, addr + 5 * 4); |
| 1179 | w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | |
| 1180 | MT_WTBL_W5_MPDU_OK_COUNT | |
| 1181 | MT_WTBL_W5_MPDU_FAIL_COUNT | |
| 1182 | MT_WTBL_W5_RATE_IDX); |
| 1183 | w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) | |
| 1184 | FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, |
| 1185 | rd.bw_idx ? rd.bw_idx - 1 : 7); |
| 1186 | |
| 1187 | mt76_wr(dev, MT_WTBL_RIUCR0, w5); |
| 1188 | |
| 1189 | mt76_wr(dev, MT_WTBL_RIUCR1, |
| 1190 | FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) | |
| 1191 | FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) | |
| 1192 | FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1])); |
| 1193 | |
| 1194 | mt76_wr(dev, MT_WTBL_RIUCR2, |
| 1195 | FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) | |
| 1196 | FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) | |
| 1197 | FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) | |
| 1198 | FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2])); |
| 1199 | |
| 1200 | mt76_wr(dev, MT_WTBL_RIUCR3, |
| 1201 | FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) | |
| 1202 | FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) | |
| 1203 | FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3])); |
| 1204 | |
| 1205 | mt76_wr(dev, MT_WTBL_UPDATE, |
| 1206 | FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | |
| 1207 | MT_WTBL_UPDATE_RATE_UPDATE | |
| 1208 | MT_WTBL_UPDATE_TX_COUNT_CLEAR); |
| 1209 | |
| 1210 | mt76_wr(dev, addr + 27 * 4, w27); |
| 1211 | |
| 1212 | idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx; |
| 1213 | addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx); |
| 1214 | |
| 1215 | mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */ |
| 1216 | sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0); |
| 1217 | sta->rate_set_tsf |= rd.rateset; |
| 1218 | |
| 1219 | if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) |
| 1220 | mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); |
| 1221 | |
| 1222 | sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates; |
| 1223 | sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; |
| 1224 | sta->rate_probe = !!probe_rate; |
| 1225 | } |
| 1226 | EXPORT_SYMBOL_GPL(mt7615_mac_set_rates); |
| 1227 | |
| 1228 | static int |
| 1229 | mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, |
| 1230 | struct ieee80211_key_conf *key, |
| 1231 | enum mt76_cipher_type cipher, u16 cipher_mask, |
| 1232 | enum set_key_cmd cmd) |
| 1233 | { |
| 1234 | u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; |
| 1235 | u8 data[32] = {}; |
| 1236 | |
| 1237 | if (key->keylen > sizeof(data)) |
| 1238 | return -EINVAL; |
| 1239 | |
| 1240 | mt76_rr_copy(dev, addr, data, sizeof(data)); |
| 1241 | if (cmd == SET_KEY) { |
| 1242 | if (cipher == MT_CIPHER_TKIP) { |
| 1243 | /* Rx/Tx MIC keys are swapped */ |
| 1244 | memcpy(data, key->key, 16); |
| 1245 | memcpy(data + 16, key->key + 24, 8); |
| 1246 | memcpy(data + 24, key->key + 16, 8); |
| 1247 | } else { |
| 1248 | if (cipher_mask == BIT(cipher)) |
| 1249 | memcpy(data, key->key, key->keylen); |
| 1250 | else if (cipher != MT_CIPHER_BIP_CMAC_128) |
| 1251 | memcpy(data, key->key, 16); |
| 1252 | if (cipher == MT_CIPHER_BIP_CMAC_128) |
| 1253 | memcpy(data + 16, key->key, 16); |
| 1254 | } |
| 1255 | } else { |
| 1256 | if (cipher == MT_CIPHER_BIP_CMAC_128) |
| 1257 | memset(data + 16, 0, 16); |
| 1258 | else if (cipher_mask) |
| 1259 | memset(data, 0, 16); |
| 1260 | if (!cipher_mask) |
| 1261 | memset(data, 0, sizeof(data)); |
| 1262 | } |
| 1263 | |
| 1264 | mt76_wr_copy(dev, addr, data, sizeof(data)); |
| 1265 | |
| 1266 | return 0; |
| 1267 | } |
| 1268 | |
| 1269 | static int |
| 1270 | mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, |
| 1271 | enum mt76_cipher_type cipher, u16 cipher_mask, |
| 1272 | int keyidx, enum set_key_cmd cmd) |
| 1273 | { |
| 1274 | u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; |
| 1275 | |
| 1276 | if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) |
| 1277 | return -ETIMEDOUT; |
| 1278 | |
| 1279 | w0 = mt76_rr(dev, addr); |
| 1280 | w1 = mt76_rr(dev, addr + 4); |
| 1281 | |
| 1282 | if (cipher_mask) |
| 1283 | w0 |= MT_WTBL_W0_RX_KEY_VALID; |
| 1284 | else |
| 1285 | w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX); |
| 1286 | if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128)) |
| 1287 | w0 |= MT_WTBL_W0_RX_IK_VALID; |
| 1288 | else |
| 1289 | w0 &= ~MT_WTBL_W0_RX_IK_VALID; |
| 1290 | |
| 1291 | if (cmd == SET_KEY && |
| 1292 | (cipher != MT_CIPHER_BIP_CMAC_128 || |
| 1293 | cipher_mask == BIT(cipher))) { |
| 1294 | w0 &= ~MT_WTBL_W0_KEY_IDX; |
| 1295 | w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); |
| 1296 | } |
| 1297 | |
| 1298 | mt76_wr(dev, MT_WTBL_RICR0, w0); |
| 1299 | mt76_wr(dev, MT_WTBL_RICR1, w1); |
| 1300 | |
| 1301 | if (!mt7615_mac_wtbl_update(dev, wcid->idx, |
| 1302 | MT_WTBL_UPDATE_RXINFO_UPDATE)) |
| 1303 | return -ETIMEDOUT; |
| 1304 | |
| 1305 | return 0; |
| 1306 | } |
| 1307 | |
| 1308 | static void |
| 1309 | mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, |
| 1310 | enum mt76_cipher_type cipher, u16 cipher_mask, |
| 1311 | enum set_key_cmd cmd) |
| 1312 | { |
| 1313 | u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); |
| 1314 | |
| 1315 | if (!cipher_mask) { |
| 1316 | mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE); |
| 1317 | return; |
| 1318 | } |
| 1319 | |
| 1320 | if (cmd != SET_KEY) |
| 1321 | return; |
| 1322 | |
| 1323 | if (cipher == MT_CIPHER_BIP_CMAC_128 && |
| 1324 | cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) |
| 1325 | return; |
| 1326 | |
| 1327 | mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE, |
| 1328 | FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher)); |
| 1329 | } |
| 1330 | |
| 1331 | int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, |
| 1332 | struct mt76_wcid *wcid, |
| 1333 | struct ieee80211_key_conf *key, |
| 1334 | enum set_key_cmd cmd) |
| 1335 | { |
| 1336 | enum mt76_cipher_type cipher; |
| 1337 | u16 cipher_mask = wcid->cipher; |
| 1338 | int err; |
| 1339 | |
| 1340 | cipher = mt7615_mac_get_cipher(key->cipher); |
| 1341 | if (cipher == MT_CIPHER_NONE) |
| 1342 | return -EOPNOTSUPP; |
| 1343 | |
| 1344 | if (cmd == SET_KEY) |
| 1345 | cipher_mask |= BIT(cipher); |
| 1346 | else |
| 1347 | cipher_mask &= ~BIT(cipher); |
| 1348 | |
| 1349 | mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd); |
| 1350 | err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask, |
| 1351 | cmd); |
| 1352 | if (err < 0) |
| 1353 | return err; |
| 1354 | |
| 1355 | err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, |
| 1356 | key->keyidx, cmd); |
| 1357 | if (err < 0) |
| 1358 | return err; |
| 1359 | |
| 1360 | wcid->cipher = cipher_mask; |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, |
| 1366 | struct mt76_wcid *wcid, |
| 1367 | struct ieee80211_key_conf *key, |
| 1368 | enum set_key_cmd cmd) |
| 1369 | { |
| 1370 | int err; |
| 1371 | |
| 1372 | spin_lock_bh(&dev->mt76.lock); |
| 1373 | err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); |
| 1374 | spin_unlock_bh(&dev->mt76.lock); |
| 1375 | |
| 1376 | return err; |
| 1377 | } |
| 1378 | |
| 1379 | static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta, |
| 1380 | struct ieee80211_tx_info *info, __le32 *txs_data) |
| 1381 | { |
| 1382 | struct ieee80211_supported_band *sband; |
| 1383 | struct mt7615_rate_set *rs; |
| 1384 | struct mt76_phy *mphy; |
| 1385 | int first_idx = 0, last_idx; |
| 1386 | int i, idx, count; |
| 1387 | bool fixed_rate, ack_timeout; |
| 1388 | bool ampdu, cck = false; |
| 1389 | bool rs_idx; |
| 1390 | u32 rate_set_tsf; |
| 1391 | u32 final_rate, final_rate_flags, final_nss, txs; |
| 1392 | |
| 1393 | txs = le32_to_cpu(txs_data[1]); |
| 1394 | ampdu = txs & MT_TXS1_AMPDU; |
| 1395 | |
| 1396 | txs = le32_to_cpu(txs_data[3]); |
| 1397 | count = FIELD_GET(MT_TXS3_TX_COUNT, txs); |
| 1398 | last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs); |
| 1399 | |
| 1400 | txs = le32_to_cpu(txs_data[0]); |
| 1401 | fixed_rate = txs & MT_TXS0_FIXED_RATE; |
| 1402 | final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); |
| 1403 | ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; |
| 1404 | |
| 1405 | if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) |
| 1406 | return false; |
| 1407 | |
| 1408 | if (txs & MT_TXS0_QUEUE_TIMEOUT) |
| 1409 | return false; |
| 1410 | |
| 1411 | if (!ack_timeout) |
| 1412 | info->flags |= IEEE80211_TX_STAT_ACK; |
| 1413 | |
| 1414 | info->status.ampdu_len = 1; |
| 1415 | info->status.ampdu_ack_len = !!(info->flags & |
| 1416 | IEEE80211_TX_STAT_ACK); |
| 1417 | |
| 1418 | if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) |
| 1419 | info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; |
| 1420 | |
| 1421 | first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY); |
| 1422 | |
| 1423 | if (fixed_rate) { |
| 1424 | info->status.rates[0].count = count; |
| 1425 | i = 0; |
| 1426 | goto out; |
| 1427 | } |
| 1428 | |
| 1429 | rate_set_tsf = READ_ONCE(sta->rate_set_tsf); |
| 1430 | rs_idx = !((u32)(le32_get_bits(txs_data[4], MT_TXS4_F0_TIMESTAMP) - |
| 1431 | rate_set_tsf) < 1000000); |
| 1432 | rs_idx ^= rate_set_tsf & BIT(0); |
| 1433 | rs = &sta->rateset[rs_idx]; |
| 1434 | |
| 1435 | if (!first_idx && rs->probe_rate.idx >= 0) { |
| 1436 | info->status.rates[0] = rs->probe_rate; |
| 1437 | |
| 1438 | spin_lock_bh(&dev->mt76.lock); |
| 1439 | if (sta->rate_probe) { |
| 1440 | struct mt7615_phy *phy = &dev->phy; |
| 1441 | |
| 1442 | if (sta->wcid.ext_phy && dev->mt76.phy2) |
| 1443 | phy = dev->mt76.phy2->priv; |
| 1444 | |
| 1445 | mt7615_mac_set_rates(phy, sta, NULL, sta->rates); |
| 1446 | } |
| 1447 | spin_unlock_bh(&dev->mt76.lock); |
| 1448 | } else { |
| 1449 | info->status.rates[0] = rs->rates[first_idx / 2]; |
| 1450 | } |
| 1451 | info->status.rates[0].count = 0; |
| 1452 | |
| 1453 | for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { |
| 1454 | struct ieee80211_tx_rate *cur_rate; |
| 1455 | int cur_count; |
| 1456 | |
| 1457 | cur_rate = &rs->rates[idx / 2]; |
| 1458 | cur_count = min_t(int, MT7615_RATE_RETRY, count); |
| 1459 | count -= cur_count; |
| 1460 | |
| 1461 | if (idx && (cur_rate->idx != info->status.rates[i].idx || |
| 1462 | cur_rate->flags != info->status.rates[i].flags)) { |
| 1463 | i++; |
| 1464 | if (i == ARRAY_SIZE(info->status.rates)) { |
| 1465 | i--; |
| 1466 | break; |
| 1467 | } |
| 1468 | |
| 1469 | info->status.rates[i] = *cur_rate; |
| 1470 | info->status.rates[i].count = 0; |
| 1471 | } |
| 1472 | |
| 1473 | info->status.rates[i].count += cur_count; |
| 1474 | } |
| 1475 | |
| 1476 | out: |
| 1477 | final_rate_flags = info->status.rates[i].flags; |
| 1478 | |
| 1479 | switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { |
| 1480 | case MT_PHY_TYPE_CCK: |
| 1481 | cck = true; |
| 1482 | fallthrough; |
| 1483 | case MT_PHY_TYPE_OFDM: |
| 1484 | mphy = &dev->mphy; |
| 1485 | if (sta->wcid.ext_phy && dev->mt76.phy2) |
| 1486 | mphy = dev->mt76.phy2; |
| 1487 | |
| 1488 | if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) |
| 1489 | sband = &mphy->sband_5g.sband; |
| 1490 | else |
| 1491 | sband = &mphy->sband_2g.sband; |
| 1492 | final_rate &= MT_TX_RATE_IDX; |
| 1493 | final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, |
| 1494 | cck); |
| 1495 | final_rate_flags = 0; |
| 1496 | break; |
| 1497 | case MT_PHY_TYPE_HT_GF: |
| 1498 | case MT_PHY_TYPE_HT: |
| 1499 | final_rate_flags |= IEEE80211_TX_RC_MCS; |
| 1500 | final_rate &= MT_TX_RATE_IDX; |
| 1501 | if (final_rate > 31) |
| 1502 | return false; |
| 1503 | break; |
| 1504 | case MT_PHY_TYPE_VHT: |
| 1505 | final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate); |
| 1506 | |
| 1507 | if ((final_rate & MT_TX_RATE_STBC) && final_nss) |
| 1508 | final_nss--; |
| 1509 | |
| 1510 | final_rate_flags |= IEEE80211_TX_RC_VHT_MCS; |
| 1511 | final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4); |
| 1512 | break; |
| 1513 | default: |
| 1514 | return false; |
| 1515 | } |
| 1516 | |
| 1517 | info->status.rates[i].idx = final_rate; |
| 1518 | info->status.rates[i].flags = final_rate_flags; |
| 1519 | |
| 1520 | return true; |
| 1521 | } |
| 1522 | |
| 1523 | static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev, |
| 1524 | struct mt7615_sta *sta, int pid, |
| 1525 | __le32 *txs_data) |
| 1526 | { |
| 1527 | struct mt76_dev *mdev = &dev->mt76; |
| 1528 | struct sk_buff_head list; |
| 1529 | struct sk_buff *skb; |
| 1530 | |
| 1531 | if (pid < MT_PACKET_ID_FIRST) |
| 1532 | return false; |
| 1533 | |
| 1534 | trace_mac_txdone(mdev, sta->wcid.idx, pid); |
| 1535 | |
| 1536 | mt76_tx_status_lock(mdev, &list); |
| 1537 | skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); |
| 1538 | if (skb) { |
| 1539 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 1540 | |
| 1541 | if (!mt7615_fill_txs(dev, sta, info, txs_data)) { |
| 1542 | info->status.rates[0].count = 0; |
| 1543 | info->status.rates[0].idx = -1; |
| 1544 | } |
| 1545 | |
| 1546 | mt76_tx_status_skb_done(mdev, skb, &list); |
| 1547 | } |
| 1548 | mt76_tx_status_unlock(mdev, &list); |
| 1549 | |
| 1550 | return !!skb; |
| 1551 | } |
| 1552 | |
| 1553 | static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data) |
| 1554 | { |
| 1555 | struct ieee80211_tx_info info = {}; |
| 1556 | struct ieee80211_sta *sta = NULL; |
| 1557 | struct mt7615_sta *msta = NULL; |
| 1558 | struct mt76_wcid *wcid; |
| 1559 | struct mt76_phy *mphy = &dev->mt76.phy; |
| 1560 | __le32 *txs_data = data; |
| 1561 | u8 wcidx; |
| 1562 | u8 pid; |
| 1563 | |
| 1564 | pid = le32_get_bits(txs_data[0], MT_TXS0_PID); |
| 1565 | wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); |
| 1566 | |
| 1567 | if (pid == MT_PACKET_ID_NO_ACK) |
| 1568 | return; |
| 1569 | |
| 1570 | if (wcidx >= MT7615_WTBL_SIZE) |
| 1571 | return; |
| 1572 | |
| 1573 | rcu_read_lock(); |
| 1574 | |
| 1575 | wcid = rcu_dereference(dev->mt76.wcid[wcidx]); |
| 1576 | if (!wcid) |
| 1577 | goto out; |
| 1578 | |
| 1579 | msta = container_of(wcid, struct mt7615_sta, wcid); |
| 1580 | sta = wcid_to_sta(wcid); |
| 1581 | |
| 1582 | spin_lock_bh(&dev->sta_poll_lock); |
| 1583 | if (list_empty(&msta->poll_list)) |
| 1584 | list_add_tail(&msta->poll_list, &dev->sta_poll_list); |
| 1585 | spin_unlock_bh(&dev->sta_poll_lock); |
| 1586 | |
| 1587 | if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data)) |
| 1588 | goto out; |
| 1589 | |
| 1590 | if (wcidx >= MT7615_WTBL_STA || !sta) |
| 1591 | goto out; |
| 1592 | |
| 1593 | if (wcid->ext_phy && dev->mt76.phy2) |
| 1594 | mphy = dev->mt76.phy2; |
| 1595 | |
| 1596 | if (mt7615_fill_txs(dev, msta, &info, txs_data)) |
| 1597 | ieee80211_tx_status_noskb(mphy->hw, sta, &info); |
| 1598 | |
| 1599 | out: |
| 1600 | rcu_read_unlock(); |
| 1601 | } |
| 1602 | |
| 1603 | static void |
| 1604 | mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi) |
| 1605 | { |
| 1606 | struct mt76_dev *mdev = &dev->mt76; |
| 1607 | __le32 *txwi_data; |
| 1608 | u32 val; |
| 1609 | u8 wcid; |
| 1610 | |
| 1611 | mt7615_txp_skb_unmap(mdev, txwi); |
| 1612 | if (!txwi->skb) |
| 1613 | goto out; |
| 1614 | |
| 1615 | txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi); |
| 1616 | val = le32_to_cpu(txwi_data[1]); |
| 1617 | wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val); |
| 1618 | mt76_tx_complete_skb(mdev, wcid, txwi->skb); |
| 1619 | |
| 1620 | out: |
| 1621 | txwi->skb = NULL; |
| 1622 | mt76_put_txwi(mdev, txwi); |
| 1623 | } |
| 1624 | |
| 1625 | static void |
| 1626 | mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token) |
| 1627 | { |
| 1628 | struct mt76_dev *mdev = &dev->mt76; |
| 1629 | struct mt76_txwi_cache *txwi; |
| 1630 | |
| 1631 | trace_mac_tx_free(dev, token); |
| 1632 | txwi = mt76_token_put(mdev, token); |
| 1633 | if (!txwi) |
| 1634 | return; |
| 1635 | |
| 1636 | mt7615_txwi_free(dev, txwi); |
| 1637 | } |
| 1638 | |
| 1639 | static void mt7615_mac_tx_free(struct mt7615_dev *dev, void *data, int len) |
| 1640 | { |
| 1641 | struct mt7615_tx_free *free = (struct mt7615_tx_free *)data; |
| 1642 | void *end = data + len; |
| 1643 | u8 i, count; |
| 1644 | |
| 1645 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); |
| 1646 | if (is_mt7615(&dev->mt76)) { |
| 1647 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); |
| 1648 | } else { |
| 1649 | for (i = 0; i < IEEE80211_NUM_ACS; i++) |
| 1650 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); |
| 1651 | } |
| 1652 | |
| 1653 | count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_ID_CNT); |
| 1654 | if (is_mt7615(&dev->mt76)) { |
| 1655 | __le16 *token = &free->token[0]; |
| 1656 | |
| 1657 | if (WARN_ON_ONCE((void *)&token[count] > end)) |
| 1658 | return; |
| 1659 | |
| 1660 | for (i = 0; i < count; i++) |
| 1661 | mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i])); |
| 1662 | } else { |
| 1663 | __le32 *token = (__le32 *)&free->token[0]; |
| 1664 | |
| 1665 | if (WARN_ON_ONCE((void *)&token[count] > end)) |
| 1666 | return; |
| 1667 | |
| 1668 | for (i = 0; i < count; i++) |
| 1669 | mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i])); |
| 1670 | } |
| 1671 | |
| 1672 | rcu_read_lock(); |
| 1673 | mt7615_mac_sta_poll(dev); |
| 1674 | rcu_read_unlock(); |
| 1675 | |
| 1676 | mt76_worker_schedule(&dev->mt76.tx_worker); |
| 1677 | } |
| 1678 | |
| 1679 | bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len) |
| 1680 | { |
| 1681 | struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); |
| 1682 | __le32 *rxd = (__le32 *)data; |
| 1683 | __le32 *end = (__le32 *)&rxd[len / 4]; |
| 1684 | enum rx_pkt_type type; |
| 1685 | |
| 1686 | type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); |
| 1687 | |
| 1688 | switch (type) { |
| 1689 | case PKT_TYPE_TXRX_NOTIFY: |
| 1690 | mt7615_mac_tx_free(dev, data, len); |
| 1691 | return false; |
| 1692 | case PKT_TYPE_TXS: |
| 1693 | for (rxd++; rxd + 7 <= end; rxd += 7) |
| 1694 | mt7615_mac_add_txs(dev, rxd); |
| 1695 | return false; |
| 1696 | default: |
| 1697 | return true; |
| 1698 | } |
| 1699 | } |
| 1700 | EXPORT_SYMBOL_GPL(mt7615_rx_check); |
| 1701 | |
| 1702 | void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, |
| 1703 | struct sk_buff *skb) |
| 1704 | { |
| 1705 | struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); |
| 1706 | __le32 *rxd = (__le32 *)skb->data; |
| 1707 | __le32 *end = (__le32 *)&skb->data[skb->len]; |
| 1708 | enum rx_pkt_type type; |
| 1709 | u16 flag; |
| 1710 | |
| 1711 | type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); |
| 1712 | flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG); |
| 1713 | if (type == PKT_TYPE_RX_EVENT && flag == 0x1) |
| 1714 | type = PKT_TYPE_NORMAL_MCU; |
| 1715 | |
| 1716 | switch (type) { |
| 1717 | case PKT_TYPE_TXS: |
| 1718 | for (rxd++; rxd + 7 <= end; rxd += 7) |
| 1719 | mt7615_mac_add_txs(dev, rxd); |
| 1720 | dev_kfree_skb(skb); |
| 1721 | break; |
| 1722 | case PKT_TYPE_TXRX_NOTIFY: |
| 1723 | mt7615_mac_tx_free(dev, skb->data, skb->len); |
| 1724 | dev_kfree_skb(skb); |
| 1725 | break; |
| 1726 | case PKT_TYPE_RX_EVENT: |
| 1727 | mt7615_mcu_rx_event(dev, skb); |
| 1728 | break; |
| 1729 | case PKT_TYPE_NORMAL_MCU: |
| 1730 | case PKT_TYPE_NORMAL: |
| 1731 | if (!mt7615_mac_fill_rx(dev, skb)) { |
| 1732 | mt76_rx(&dev->mt76, q, skb); |
| 1733 | return; |
| 1734 | } |
| 1735 | fallthrough; |
| 1736 | default: |
| 1737 | dev_kfree_skb(skb); |
| 1738 | break; |
| 1739 | } |
| 1740 | } |
| 1741 | EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb); |
| 1742 | |
| 1743 | static void |
| 1744 | mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm) |
| 1745 | { |
| 1746 | struct mt7615_dev *dev = phy->dev; |
| 1747 | bool ext_phy = phy != &dev->phy; |
| 1748 | |
| 1749 | if (is_mt7663(&dev->mt76)) { |
| 1750 | if (ofdm) |
| 1751 | mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy), |
| 1752 | MT_WF_PHY_PD_OFDM_MASK(0), |
| 1753 | MT_WF_PHY_PD_OFDM(0, val)); |
| 1754 | else |
| 1755 | mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy), |
| 1756 | MT_WF_PHY_PD_CCK_MASK(ext_phy), |
| 1757 | MT_WF_PHY_PD_CCK(ext_phy, val)); |
| 1758 | return; |
| 1759 | } |
| 1760 | |
| 1761 | if (ofdm) |
| 1762 | mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy), |
| 1763 | MT_WF_PHY_PD_OFDM_MASK(ext_phy), |
| 1764 | MT_WF_PHY_PD_OFDM(ext_phy, val)); |
| 1765 | else |
| 1766 | mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy), |
| 1767 | MT_WF_PHY_PD_CCK_MASK(ext_phy), |
| 1768 | MT_WF_PHY_PD_CCK(ext_phy, val)); |
| 1769 | } |
| 1770 | |
| 1771 | static void |
| 1772 | mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy) |
| 1773 | { |
| 1774 | /* ofdm */ |
| 1775 | mt7615_mac_set_sensitivity(phy, 0x13c, true); |
| 1776 | /* cck */ |
| 1777 | mt7615_mac_set_sensitivity(phy, 0x92, false); |
| 1778 | |
| 1779 | phy->ofdm_sensitivity = -98; |
| 1780 | phy->cck_sensitivity = -110; |
| 1781 | phy->last_cca_adj = jiffies; |
| 1782 | } |
| 1783 | |
| 1784 | void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable) |
| 1785 | { |
| 1786 | struct mt7615_dev *dev = phy->dev; |
| 1787 | bool ext_phy = phy != &dev->phy; |
| 1788 | u32 reg, mask; |
| 1789 | |
| 1790 | mt7615_mutex_acquire(dev); |
| 1791 | |
| 1792 | if (phy->scs_en == enable) |
| 1793 | goto out; |
| 1794 | |
| 1795 | if (is_mt7663(&dev->mt76)) { |
| 1796 | reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy); |
| 1797 | mask = MT_WF_PHY_PD_BLK(0); |
| 1798 | } else { |
| 1799 | reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy); |
| 1800 | mask = MT_WF_PHY_PD_BLK(ext_phy); |
| 1801 | } |
| 1802 | |
| 1803 | if (enable) { |
| 1804 | mt76_set(dev, reg, mask); |
| 1805 | if (is_mt7622(&dev->mt76)) { |
| 1806 | mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); |
| 1807 | mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); |
| 1808 | } |
| 1809 | } else { |
| 1810 | mt76_clear(dev, reg, mask); |
| 1811 | } |
| 1812 | |
| 1813 | mt7615_mac_set_default_sensitivity(phy); |
| 1814 | phy->scs_en = enable; |
| 1815 | |
| 1816 | out: |
| 1817 | mt7615_mutex_release(dev); |
| 1818 | } |
| 1819 | |
| 1820 | void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) |
| 1821 | { |
| 1822 | u32 rxtd, reg; |
| 1823 | |
| 1824 | if (is_mt7663(&dev->mt76)) |
| 1825 | reg = MT7663_WF_PHY_R0_PHYMUX_5; |
| 1826 | else |
| 1827 | reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); |
| 1828 | |
| 1829 | if (ext_phy) |
| 1830 | rxtd = MT_WF_PHY_RXTD2(10); |
| 1831 | else |
| 1832 | rxtd = MT_WF_PHY_RXTD(12); |
| 1833 | |
| 1834 | mt76_set(dev, rxtd, BIT(18) | BIT(29)); |
| 1835 | mt76_set(dev, reg, 0x5 << 12); |
| 1836 | } |
| 1837 | |
| 1838 | void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy) |
| 1839 | { |
| 1840 | struct mt7615_dev *dev = phy->dev; |
| 1841 | bool ext_phy = phy != &dev->phy; |
| 1842 | u32 reg; |
| 1843 | |
| 1844 | if (is_mt7663(&dev->mt76)) |
| 1845 | reg = MT7663_WF_PHY_R0_PHYMUX_5; |
| 1846 | else |
| 1847 | reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); |
| 1848 | |
| 1849 | /* reset PD and MDRDY counters */ |
| 1850 | mt76_clear(dev, reg, GENMASK(22, 20)); |
| 1851 | mt76_set(dev, reg, BIT(22) | BIT(20)); |
| 1852 | } |
| 1853 | |
| 1854 | static void |
| 1855 | mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy, |
| 1856 | u32 rts_err_rate, bool ofdm) |
| 1857 | { |
| 1858 | struct mt7615_dev *dev = phy->dev; |
| 1859 | int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck; |
| 1860 | bool ext_phy = phy != &dev->phy; |
| 1861 | s16 def_th = ofdm ? -98 : -110; |
| 1862 | bool update = false; |
| 1863 | s8 *sensitivity; |
| 1864 | int signal; |
| 1865 | |
| 1866 | sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity; |
| 1867 | signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy); |
| 1868 | if (!signal) { |
| 1869 | mt7615_mac_set_default_sensitivity(phy); |
| 1870 | return; |
| 1871 | } |
| 1872 | |
| 1873 | signal = min(signal, -72); |
| 1874 | if (false_cca > 500) { |
| 1875 | if (rts_err_rate > MT_FRAC(40, 100)) |
| 1876 | return; |
| 1877 | |
| 1878 | /* decrease coverage */ |
| 1879 | if (*sensitivity == def_th && signal > -90) { |
| 1880 | *sensitivity = -90; |
| 1881 | update = true; |
| 1882 | } else if (*sensitivity + 2 < signal) { |
| 1883 | *sensitivity += 2; |
| 1884 | update = true; |
| 1885 | } |
| 1886 | } else if ((false_cca > 0 && false_cca < 50) || |
| 1887 | rts_err_rate > MT_FRAC(60, 100)) { |
| 1888 | /* increase coverage */ |
| 1889 | if (*sensitivity - 2 >= def_th) { |
| 1890 | *sensitivity -= 2; |
| 1891 | update = true; |
| 1892 | } |
| 1893 | } |
| 1894 | |
| 1895 | if (*sensitivity > signal) { |
| 1896 | *sensitivity = signal; |
| 1897 | update = true; |
| 1898 | } |
| 1899 | |
| 1900 | if (update) { |
| 1901 | u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256; |
| 1902 | |
| 1903 | mt7615_mac_set_sensitivity(phy, val, ofdm); |
| 1904 | phy->last_cca_adj = jiffies; |
| 1905 | } |
| 1906 | } |
| 1907 | |
| 1908 | static void |
| 1909 | mt7615_mac_scs_check(struct mt7615_phy *phy) |
| 1910 | { |
| 1911 | struct mt7615_dev *dev = phy->dev; |
| 1912 | struct mib_stats *mib = &phy->mib; |
| 1913 | u32 val, rts_err_rate = 0; |
| 1914 | u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm; |
| 1915 | bool ext_phy = phy != &dev->phy; |
| 1916 | |
| 1917 | if (!phy->scs_en) |
| 1918 | return; |
| 1919 | |
| 1920 | if (is_mt7663(&dev->mt76)) |
| 1921 | val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); |
| 1922 | else |
| 1923 | val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); |
| 1924 | pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); |
| 1925 | pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); |
| 1926 | |
| 1927 | if (is_mt7663(&dev->mt76)) |
| 1928 | val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); |
| 1929 | else |
| 1930 | val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); |
| 1931 | mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); |
| 1932 | mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); |
| 1933 | |
| 1934 | phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; |
| 1935 | phy->false_cca_cck = pd_cck - mdrdy_cck; |
| 1936 | mt7615_mac_cca_stats_reset(phy); |
| 1937 | |
| 1938 | if (mib->rts_cnt + mib->rts_retries_cnt) |
| 1939 | rts_err_rate = MT_FRAC(mib->rts_retries_cnt, |
| 1940 | mib->rts_cnt + mib->rts_retries_cnt); |
| 1941 | |
| 1942 | /* cck */ |
| 1943 | mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false); |
| 1944 | /* ofdm */ |
| 1945 | mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true); |
| 1946 | |
| 1947 | if (time_after(jiffies, phy->last_cca_adj + 10 * HZ)) |
| 1948 | mt7615_mac_set_default_sensitivity(phy); |
| 1949 | } |
| 1950 | |
| 1951 | static u8 |
| 1952 | mt7615_phy_get_nf(struct mt7615_dev *dev, int idx) |
| 1953 | { |
| 1954 | static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; |
| 1955 | u32 reg, val, sum = 0, n = 0; |
| 1956 | int i; |
| 1957 | |
| 1958 | if (is_mt7663(&dev->mt76)) |
| 1959 | reg = MT7663_WF_PHY_RXTD(20); |
| 1960 | else |
| 1961 | reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20); |
| 1962 | |
| 1963 | for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { |
| 1964 | val = mt76_rr(dev, reg); |
| 1965 | sum += val * nf_power[i]; |
| 1966 | n += val; |
| 1967 | } |
| 1968 | |
| 1969 | if (!n) |
| 1970 | return 0; |
| 1971 | |
| 1972 | return sum / n; |
| 1973 | } |
| 1974 | |
| 1975 | static void |
| 1976 | mt7615_phy_update_channel(struct mt76_phy *mphy, int idx) |
| 1977 | { |
| 1978 | struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); |
| 1979 | struct mt7615_phy *phy = mphy->priv; |
| 1980 | struct mt76_channel_state *state; |
| 1981 | u64 busy_time, tx_time, rx_time, obss_time; |
| 1982 | u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5; |
| 1983 | int nf; |
| 1984 | |
| 1985 | busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), |
| 1986 | MT_MIB_SDR9_BUSY_MASK); |
| 1987 | tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), |
| 1988 | MT_MIB_SDR36_TXTIME_MASK); |
| 1989 | rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), |
| 1990 | MT_MIB_SDR37_RXTIME_MASK); |
| 1991 | obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK); |
| 1992 | |
| 1993 | nf = mt7615_phy_get_nf(dev, idx); |
| 1994 | if (!phy->noise) |
| 1995 | phy->noise = nf << 4; |
| 1996 | else if (nf) |
| 1997 | phy->noise += nf - (phy->noise >> 4); |
| 1998 | |
| 1999 | state = mphy->chan_state; |
| 2000 | state->cc_busy += busy_time; |
| 2001 | state->cc_tx += tx_time; |
| 2002 | state->cc_rx += rx_time + obss_time; |
| 2003 | state->cc_bss_rx += rx_time; |
| 2004 | state->noise = -(phy->noise >> 4); |
| 2005 | } |
| 2006 | |
| 2007 | static void mt7615_update_survey(struct mt7615_dev *dev) |
| 2008 | { |
| 2009 | struct mt76_dev *mdev = &dev->mt76; |
| 2010 | ktime_t cur_time; |
| 2011 | |
| 2012 | /* MT7615 can only update both phys simultaneously |
| 2013 | * since some reisters are shared across bands. |
| 2014 | */ |
| 2015 | |
| 2016 | mt7615_phy_update_channel(&mdev->phy, 0); |
| 2017 | if (mdev->phy2) |
| 2018 | mt7615_phy_update_channel(mdev->phy2, 1); |
| 2019 | |
| 2020 | cur_time = ktime_get_boottime(); |
| 2021 | |
| 2022 | mt76_update_survey_active_time(&mdev->phy, cur_time); |
| 2023 | if (mdev->phy2) |
| 2024 | mt76_update_survey_active_time(mdev->phy2, cur_time); |
| 2025 | |
| 2026 | /* reset obss airtime */ |
| 2027 | mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); |
| 2028 | } |
| 2029 | |
| 2030 | void mt7615_update_channel(struct mt76_phy *mphy) |
| 2031 | { |
| 2032 | struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); |
| 2033 | |
| 2034 | if (mt76_connac_pm_wake(&dev->mphy, &dev->pm)) |
| 2035 | return; |
| 2036 | |
| 2037 | mt7615_update_survey(dev); |
| 2038 | mt76_connac_power_save_sched(&dev->mphy, &dev->pm); |
| 2039 | } |
| 2040 | EXPORT_SYMBOL_GPL(mt7615_update_channel); |
| 2041 | |
| 2042 | static void |
| 2043 | mt7615_mac_update_mib_stats(struct mt7615_phy *phy) |
| 2044 | { |
| 2045 | struct mt7615_dev *dev = phy->dev; |
| 2046 | struct mib_stats *mib = &phy->mib; |
| 2047 | bool ext_phy = phy != &dev->phy; |
| 2048 | int i, aggr; |
| 2049 | u32 val, val2; |
| 2050 | |
| 2051 | mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), |
| 2052 | MT_MIB_SDR3_FCS_ERR_MASK); |
| 2053 | |
| 2054 | val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy), |
| 2055 | MT_MIB_AMPDU_MPDU_COUNT); |
| 2056 | if (val) { |
| 2057 | val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy), |
| 2058 | MT_MIB_AMPDU_ACK_COUNT); |
| 2059 | mib->aggr_per = 1000 * (val - val2) / val; |
| 2060 | } |
| 2061 | |
| 2062 | aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; |
| 2063 | for (i = 0; i < 4; i++) { |
| 2064 | val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); |
| 2065 | mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); |
| 2066 | mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, |
| 2067 | val); |
| 2068 | |
| 2069 | val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); |
| 2070 | mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); |
| 2071 | mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, |
| 2072 | val); |
| 2073 | |
| 2074 | val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); |
| 2075 | dev->mt76.aggr_stats[aggr++] += val & 0xffff; |
| 2076 | dev->mt76.aggr_stats[aggr++] += val >> 16; |
| 2077 | } |
| 2078 | } |
| 2079 | |
| 2080 | void mt7615_pm_wake_work(struct work_struct *work) |
| 2081 | { |
| 2082 | struct mt7615_dev *dev; |
| 2083 | struct mt76_phy *mphy; |
| 2084 | |
| 2085 | dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, |
| 2086 | pm.wake_work); |
| 2087 | mphy = dev->phy.mt76; |
| 2088 | |
| 2089 | if (!mt7615_mcu_set_drv_ctrl(dev)) { |
| 2090 | struct mt76_dev *mdev = &dev->mt76; |
| 2091 | int i; |
| 2092 | |
| 2093 | if (mt76_is_sdio(mdev)) { |
| 2094 | mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); |
| 2095 | mt76_worker_schedule(&mdev->sdio.txrx_worker); |
| 2096 | } else { |
| 2097 | mt76_for_each_q_rx(mdev, i) |
| 2098 | napi_schedule(&mdev->napi[i]); |
| 2099 | mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); |
| 2100 | mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM], |
| 2101 | false); |
| 2102 | } |
| 2103 | |
| 2104 | if (test_bit(MT76_STATE_RUNNING, &mphy->state)) { |
| 2105 | unsigned long timeout; |
| 2106 | |
| 2107 | timeout = mt7615_get_macwork_timeout(dev); |
| 2108 | ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, |
| 2109 | timeout); |
| 2110 | } |
| 2111 | } |
| 2112 | |
| 2113 | ieee80211_wake_queues(mphy->hw); |
| 2114 | wake_up(&dev->pm.wait); |
| 2115 | } |
| 2116 | |
| 2117 | void mt7615_pm_power_save_work(struct work_struct *work) |
| 2118 | { |
| 2119 | struct mt7615_dev *dev; |
| 2120 | unsigned long delta; |
| 2121 | |
| 2122 | dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, |
| 2123 | pm.ps_work.work); |
| 2124 | |
| 2125 | delta = dev->pm.idle_timeout; |
| 2126 | if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) || |
| 2127 | test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state)) |
| 2128 | goto out; |
| 2129 | |
| 2130 | if (mutex_is_locked(&dev->mt76.mutex)) |
| 2131 | /* if mt76 mutex is held we should not put the device |
| 2132 | * to sleep since we are currently accessing device |
| 2133 | * register map. We need to wait for the next power_save |
| 2134 | * trigger. |
| 2135 | */ |
| 2136 | goto out; |
| 2137 | |
| 2138 | if (time_is_after_jiffies(dev->pm.last_activity + delta)) { |
| 2139 | delta = dev->pm.last_activity + delta - jiffies; |
| 2140 | goto out; |
| 2141 | } |
| 2142 | |
| 2143 | if (!mt7615_mcu_set_fw_ctrl(dev)) |
| 2144 | return; |
| 2145 | out: |
| 2146 | queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); |
| 2147 | } |
| 2148 | |
| 2149 | void mt7615_mac_work(struct work_struct *work) |
| 2150 | { |
| 2151 | struct mt7615_phy *phy; |
| 2152 | struct mt76_phy *mphy; |
| 2153 | unsigned long timeout; |
| 2154 | |
| 2155 | mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, |
| 2156 | mac_work.work); |
| 2157 | phy = mphy->priv; |
| 2158 | |
| 2159 | mt7615_mutex_acquire(phy->dev); |
| 2160 | |
| 2161 | mt7615_update_survey(phy->dev); |
| 2162 | if (++mphy->mac_work_count == 5) { |
| 2163 | mphy->mac_work_count = 0; |
| 2164 | |
| 2165 | mt7615_mac_update_mib_stats(phy); |
| 2166 | mt7615_mac_scs_check(phy); |
| 2167 | } |
| 2168 | |
| 2169 | mt7615_mutex_release(phy->dev); |
| 2170 | |
| 2171 | mt76_tx_status_check(mphy->dev, false); |
| 2172 | |
| 2173 | timeout = mt7615_get_macwork_timeout(phy->dev); |
| 2174 | ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout); |
| 2175 | } |
| 2176 | |
| 2177 | void mt7615_tx_token_put(struct mt7615_dev *dev) |
| 2178 | { |
| 2179 | struct mt76_txwi_cache *txwi; |
| 2180 | int id; |
| 2181 | |
| 2182 | spin_lock_bh(&dev->mt76.token_lock); |
| 2183 | idr_for_each_entry(&dev->mt76.token, txwi, id) |
| 2184 | mt7615_txwi_free(dev, txwi); |
| 2185 | spin_unlock_bh(&dev->mt76.token_lock); |
| 2186 | idr_destroy(&dev->mt76.token); |
| 2187 | } |
| 2188 | EXPORT_SYMBOL_GPL(mt7615_tx_token_put); |
| 2189 | |
| 2190 | static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy) |
| 2191 | { |
| 2192 | struct mt7615_dev *dev = phy->dev; |
| 2193 | |
| 2194 | if (phy->rdd_state & BIT(0)) |
| 2195 | mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, |
| 2196 | MT_RX_SEL0, 0); |
| 2197 | if (phy->rdd_state & BIT(1)) |
| 2198 | mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, |
| 2199 | MT_RX_SEL0, 0); |
| 2200 | } |
| 2201 | |
| 2202 | static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain) |
| 2203 | { |
| 2204 | int err; |
| 2205 | |
| 2206 | err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, |
| 2207 | MT_RX_SEL0, 0); |
| 2208 | if (err < 0) |
| 2209 | return err; |
| 2210 | |
| 2211 | return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, |
| 2212 | MT_RX_SEL0, 1); |
| 2213 | } |
| 2214 | |
| 2215 | static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy) |
| 2216 | { |
| 2217 | struct cfg80211_chan_def *chandef = &phy->mt76->chandef; |
| 2218 | struct mt7615_dev *dev = phy->dev; |
| 2219 | bool ext_phy = phy != &dev->phy; |
| 2220 | int err; |
| 2221 | |
| 2222 | /* start CAC */ |
| 2223 | err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy, |
| 2224 | MT_RX_SEL0, 0); |
| 2225 | if (err < 0) |
| 2226 | return err; |
| 2227 | |
| 2228 | err = mt7615_dfs_start_rdd(dev, ext_phy); |
| 2229 | if (err < 0) |
| 2230 | return err; |
| 2231 | |
| 2232 | phy->rdd_state |= BIT(ext_phy); |
| 2233 | |
| 2234 | if (chandef->width == NL80211_CHAN_WIDTH_160 || |
| 2235 | chandef->width == NL80211_CHAN_WIDTH_80P80) { |
| 2236 | err = mt7615_dfs_start_rdd(dev, 1); |
| 2237 | if (err < 0) |
| 2238 | return err; |
| 2239 | |
| 2240 | phy->rdd_state |= BIT(1); |
| 2241 | } |
| 2242 | |
| 2243 | return 0; |
| 2244 | } |
| 2245 | |
| 2246 | static int |
| 2247 | mt7615_dfs_init_radar_specs(struct mt7615_phy *phy) |
| 2248 | { |
| 2249 | const struct mt7615_dfs_radar_spec *radar_specs; |
| 2250 | struct mt7615_dev *dev = phy->dev; |
| 2251 | int err, i, lpn = 500; |
| 2252 | |
| 2253 | switch (dev->mt76.region) { |
| 2254 | case NL80211_DFS_FCC: |
| 2255 | radar_specs = &fcc_radar_specs; |
| 2256 | lpn = 8; |
| 2257 | break; |
| 2258 | case NL80211_DFS_ETSI: |
| 2259 | radar_specs = &etsi_radar_specs; |
| 2260 | break; |
| 2261 | case NL80211_DFS_JP: |
| 2262 | radar_specs = &jp_radar_specs; |
| 2263 | break; |
| 2264 | default: |
| 2265 | return -EINVAL; |
| 2266 | } |
| 2267 | |
| 2268 | /* avoid FCC radar detection in non-FCC region */ |
| 2269 | err = mt7615_mcu_set_fcc5_lpn(dev, lpn); |
| 2270 | if (err < 0) |
| 2271 | return err; |
| 2272 | |
| 2273 | for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { |
| 2274 | err = mt7615_mcu_set_radar_th(dev, i, |
| 2275 | &radar_specs->radar_pattern[i]); |
| 2276 | if (err < 0) |
| 2277 | return err; |
| 2278 | } |
| 2279 | |
| 2280 | return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th); |
| 2281 | } |
| 2282 | |
| 2283 | int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy) |
| 2284 | { |
| 2285 | struct mt7615_dev *dev = phy->dev; |
| 2286 | bool ext_phy = phy != &dev->phy; |
| 2287 | enum mt76_dfs_state dfs_state, prev_state; |
| 2288 | int err; |
| 2289 | |
| 2290 | if (is_mt7663(&dev->mt76)) |
| 2291 | return 0; |
| 2292 | |
| 2293 | prev_state = phy->mt76->dfs_state; |
| 2294 | dfs_state = mt76_phy_dfs_state(phy->mt76); |
| 2295 | |
| 2296 | if (prev_state == dfs_state) |
| 2297 | return 0; |
| 2298 | |
| 2299 | if (prev_state == MT_DFS_STATE_UNKNOWN) |
| 2300 | mt7615_dfs_stop_radar_detector(phy); |
| 2301 | |
| 2302 | if (dfs_state == MT_DFS_STATE_DISABLED) |
| 2303 | goto stop; |
| 2304 | |
| 2305 | if (prev_state <= MT_DFS_STATE_DISABLED) { |
| 2306 | err = mt7615_dfs_init_radar_specs(phy); |
| 2307 | if (err < 0) |
| 2308 | return err; |
| 2309 | |
| 2310 | err = mt7615_dfs_start_radar_detector(phy); |
| 2311 | if (err < 0) |
| 2312 | return err; |
| 2313 | |
| 2314 | phy->mt76->dfs_state = MT_DFS_STATE_CAC; |
| 2315 | } |
| 2316 | |
| 2317 | if (dfs_state == MT_DFS_STATE_CAC) |
| 2318 | return 0; |
| 2319 | |
| 2320 | err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, |
| 2321 | ext_phy, MT_RX_SEL0, 0); |
| 2322 | if (err < 0) { |
| 2323 | phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; |
| 2324 | return err; |
| 2325 | } |
| 2326 | |
| 2327 | phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; |
| 2328 | return 0; |
| 2329 | |
| 2330 | stop: |
| 2331 | err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy, |
| 2332 | MT_RX_SEL0, 0); |
| 2333 | if (err < 0) |
| 2334 | return err; |
| 2335 | |
| 2336 | mt7615_dfs_stop_radar_detector(phy); |
| 2337 | phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; |
| 2338 | |
| 2339 | return 0; |
| 2340 | } |
| 2341 | |
| 2342 | int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy, |
| 2343 | struct ieee80211_vif *vif, |
| 2344 | bool enable) |
| 2345 | { |
| 2346 | struct mt7615_dev *dev = phy->dev; |
| 2347 | bool ext_phy = phy != &dev->phy; |
| 2348 | int err; |
| 2349 | |
| 2350 | if (!mt7615_firmware_offload(dev)) |
| 2351 | return -EOPNOTSUPP; |
| 2352 | |
| 2353 | switch (vif->type) { |
| 2354 | case NL80211_IFTYPE_MONITOR: |
| 2355 | return 0; |
| 2356 | case NL80211_IFTYPE_MESH_POINT: |
| 2357 | case NL80211_IFTYPE_ADHOC: |
| 2358 | case NL80211_IFTYPE_AP: |
| 2359 | if (enable) |
| 2360 | phy->n_beacon_vif++; |
| 2361 | else |
| 2362 | phy->n_beacon_vif--; |
| 2363 | fallthrough; |
| 2364 | default: |
| 2365 | break; |
| 2366 | } |
| 2367 | |
| 2368 | err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif); |
| 2369 | if (err) |
| 2370 | return err; |
| 2371 | |
| 2372 | if (phy->n_beacon_vif) { |
| 2373 | vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER; |
| 2374 | mt76_clear(dev, MT_WF_RFCR(ext_phy), |
| 2375 | MT_WF_RFCR_DROP_OTHER_BEACON); |
| 2376 | } else { |
| 2377 | vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER; |
| 2378 | mt76_set(dev, MT_WF_RFCR(ext_phy), |
| 2379 | MT_WF_RFCR_DROP_OTHER_BEACON); |
| 2380 | } |
| 2381 | |
| 2382 | return 0; |
| 2383 | } |
| 2384 | |
| 2385 | void mt7615_coredump_work(struct work_struct *work) |
| 2386 | { |
| 2387 | struct mt7615_dev *dev; |
| 2388 | char *dump, *data; |
| 2389 | |
| 2390 | dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, |
| 2391 | coredump.work.work); |
| 2392 | |
| 2393 | if (time_is_after_jiffies(dev->coredump.last_activity + |
| 2394 | 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { |
| 2395 | queue_delayed_work(dev->mt76.wq, &dev->coredump.work, |
| 2396 | MT76_CONNAC_COREDUMP_TIMEOUT); |
| 2397 | return; |
| 2398 | } |
| 2399 | |
| 2400 | dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); |
| 2401 | data = dump; |
| 2402 | |
| 2403 | while (true) { |
| 2404 | struct sk_buff *skb; |
| 2405 | |
| 2406 | spin_lock_bh(&dev->mt76.lock); |
| 2407 | skb = __skb_dequeue(&dev->coredump.msg_list); |
| 2408 | spin_unlock_bh(&dev->mt76.lock); |
| 2409 | |
| 2410 | if (!skb) |
| 2411 | break; |
| 2412 | |
| 2413 | skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); |
| 2414 | if (data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { |
| 2415 | dev_kfree_skb(skb); |
| 2416 | continue; |
| 2417 | } |
| 2418 | |
| 2419 | memcpy(data, skb->data, skb->len); |
| 2420 | data += skb->len; |
| 2421 | |
| 2422 | dev_kfree_skb(skb); |
| 2423 | } |
| 2424 | dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, |
| 2425 | GFP_KERNEL); |
| 2426 | } |