developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MT76_H |
| 7 | #define __MT76_H |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <linux/spinlock.h> |
| 12 | #include <linux/skbuff.h> |
| 13 | #include <linux/leds.h> |
| 14 | #include <linux/usb.h> |
| 15 | #include <linux/average.h> |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 16 | #include <linux/soc/mediatek/mtk_wed.h> |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 17 | #include <net/mac80211.h> |
| 18 | #include "util.h" |
| 19 | #include "testmode.h" |
| 20 | |
| 21 | #define MT_MCU_RING_SIZE 32 |
| 22 | #define MT_RX_BUF_SIZE 2048 |
| 23 | #define MT_SKB_HEAD_LEN 256 |
| 24 | |
| 25 | #define MT_MAX_NON_AQL_PKT 16 |
| 26 | #define MT_TXQ_FREE_THR 32 |
| 27 | |
| 28 | #define MT76_TOKEN_FREE_THR 64 |
| 29 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 30 | #define MT_QFLAG_WED_RING GENMASK(1, 0) |
| 31 | #define MT_QFLAG_WED_TYPE GENMASK(3, 2) |
| 32 | #define MT_QFLAG_WED BIT(4) |
| 33 | |
| 34 | #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ |
| 35 | FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ |
| 36 | FIELD_PREP(MT_QFLAG_WED_RING, _n)) |
| 37 | #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) |
| 38 | #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) |
| 39 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 40 | struct mt76_dev; |
| 41 | struct mt76_phy; |
| 42 | struct mt76_wcid; |
| 43 | struct mt76s_intr; |
| 44 | |
| 45 | struct mt76_reg_pair { |
| 46 | u32 reg; |
| 47 | u32 value; |
| 48 | }; |
| 49 | |
| 50 | enum mt76_bus_type { |
| 51 | MT76_BUS_MMIO, |
| 52 | MT76_BUS_USB, |
| 53 | MT76_BUS_SDIO, |
| 54 | }; |
| 55 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 56 | enum mt76_wed_type { |
| 57 | MT76_WED_Q_TX, |
| 58 | MT76_WED_Q_TXFREE, |
| 59 | }; |
| 60 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 61 | struct mt76_bus_ops { |
| 62 | u32 (*rr)(struct mt76_dev *dev, u32 offset); |
| 63 | void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); |
| 64 | u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); |
| 65 | void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, |
| 66 | int len); |
| 67 | void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, |
| 68 | int len); |
| 69 | int (*wr_rp)(struct mt76_dev *dev, u32 base, |
| 70 | const struct mt76_reg_pair *rp, int len); |
| 71 | int (*rd_rp)(struct mt76_dev *dev, u32 base, |
| 72 | struct mt76_reg_pair *rp, int len); |
| 73 | enum mt76_bus_type type; |
| 74 | }; |
| 75 | |
| 76 | #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) |
| 77 | #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) |
| 78 | #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) |
| 79 | |
| 80 | enum mt76_band_id { |
| 81 | MT_BAND0 = 0, |
| 82 | MT_BAND1, |
| 83 | MT_BAND2, |
| 84 | __MT_MAX_BAND, |
| 85 | }; |
| 86 | |
| 87 | enum mt76_phy_id { |
| 88 | MT_MAIN_PHY = 0, |
| 89 | MT_EXT_PHY, |
| 90 | MT_TRI_PHY, |
| 91 | __MT_MAX_PHY_ID, |
| 92 | }; |
| 93 | |
| 94 | enum mt76_txq_id { |
| 95 | MT_TXQ_VO = IEEE80211_AC_VO, |
| 96 | MT_TXQ_VI = IEEE80211_AC_VI, |
| 97 | MT_TXQ_BE = IEEE80211_AC_BE, |
| 98 | MT_TXQ_BK = IEEE80211_AC_BK, |
| 99 | MT_TXQ_PSD, |
| 100 | MT_TXQ_BEACON, |
| 101 | MT_TXQ_CAB, |
| 102 | __MT_TXQ_MAX |
| 103 | }; |
| 104 | |
| 105 | enum mt76_mcuq_id { |
| 106 | MT_MCUQ_WM, |
| 107 | MT_MCUQ_WA, |
| 108 | MT_MCUQ_FWDL, |
| 109 | __MT_MCUQ_MAX |
| 110 | }; |
| 111 | |
| 112 | enum mt76_rxq_id { |
| 113 | MT_RXQ_MAIN, |
| 114 | MT_RXQ_MCU, |
| 115 | MT_RXQ_MCU_WA, |
| 116 | MT_RXQ_EXT, |
| 117 | MT_RXQ_EXT_WA, |
| 118 | MT_RXQ_MAIN_WA, |
| 119 | MT_RXQ_TRI, |
| 120 | MT_RXQ_TRI_WA, |
| 121 | __MT_RXQ_MAX |
| 122 | }; |
| 123 | |
| 124 | enum mt76_cipher_type { |
| 125 | MT_CIPHER_NONE, |
| 126 | MT_CIPHER_WEP40, |
| 127 | MT_CIPHER_TKIP, |
| 128 | MT_CIPHER_TKIP_NO_MIC, |
| 129 | MT_CIPHER_AES_CCMP, |
| 130 | MT_CIPHER_WEP104, |
| 131 | MT_CIPHER_BIP_CMAC_128, |
| 132 | MT_CIPHER_WEP128, |
| 133 | MT_CIPHER_WAPI, |
| 134 | MT_CIPHER_CCMP_CCX, |
| 135 | MT_CIPHER_CCMP_256, |
| 136 | MT_CIPHER_GCMP, |
| 137 | MT_CIPHER_GCMP_256, |
| 138 | }; |
| 139 | |
| 140 | enum mt76_dfs_state { |
| 141 | MT_DFS_STATE_UNKNOWN, |
| 142 | MT_DFS_STATE_DISABLED, |
| 143 | MT_DFS_STATE_CAC, |
| 144 | MT_DFS_STATE_ACTIVE, |
| 145 | }; |
| 146 | |
| 147 | struct mt76_queue_buf { |
| 148 | dma_addr_t addr; |
| 149 | u16 len; |
| 150 | bool skip_unmap; |
| 151 | }; |
| 152 | |
| 153 | struct mt76_tx_info { |
| 154 | struct mt76_queue_buf buf[32]; |
| 155 | struct sk_buff *skb; |
| 156 | int nbuf; |
| 157 | u32 info; |
| 158 | }; |
| 159 | |
| 160 | struct mt76_queue_entry { |
| 161 | union { |
| 162 | void *buf; |
| 163 | struct sk_buff *skb; |
| 164 | }; |
| 165 | union { |
| 166 | struct mt76_txwi_cache *txwi; |
| 167 | struct urb *urb; |
| 168 | int buf_sz; |
| 169 | }; |
| 170 | u32 dma_addr[2]; |
| 171 | u16 dma_len[2]; |
| 172 | u16 wcid; |
| 173 | bool skip_buf0:1; |
| 174 | bool skip_buf1:1; |
| 175 | bool done:1; |
| 176 | }; |
| 177 | |
| 178 | struct mt76_queue_regs { |
| 179 | u32 desc_base; |
| 180 | u32 ring_size; |
| 181 | u32 cpu_idx; |
| 182 | u32 dma_idx; |
| 183 | } __packed __aligned(4); |
| 184 | |
| 185 | struct mt76_queue { |
| 186 | struct mt76_queue_regs __iomem *regs; |
| 187 | |
| 188 | spinlock_t lock; |
| 189 | spinlock_t cleanup_lock; |
| 190 | struct mt76_queue_entry *entry; |
| 191 | struct mt76_desc *desc; |
| 192 | |
| 193 | u16 first; |
| 194 | u16 head; |
| 195 | u16 tail; |
| 196 | int ndesc; |
| 197 | int queued; |
| 198 | int buf_size; |
| 199 | bool stopped; |
| 200 | bool blocked; |
| 201 | |
| 202 | u8 buf_offset; |
| 203 | u8 hw_idx; |
| 204 | u8 qid; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 205 | u8 flags; |
| 206 | |
| 207 | u32 wed_regs; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 208 | |
| 209 | dma_addr_t desc_dma; |
| 210 | struct sk_buff *rx_head; |
| 211 | struct page_frag_cache rx_page; |
| 212 | }; |
| 213 | |
| 214 | struct mt76_mcu_ops { |
| 215 | u32 headroom; |
| 216 | u32 tailroom; |
| 217 | |
| 218 | int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, |
| 219 | int len, bool wait_resp); |
| 220 | int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, |
| 221 | int cmd, int *seq); |
| 222 | int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, |
| 223 | struct sk_buff *skb, int seq); |
| 224 | u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); |
| 225 | void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); |
| 226 | int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, |
| 227 | const struct mt76_reg_pair *rp, int len); |
| 228 | int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, |
| 229 | struct mt76_reg_pair *rp, int len); |
| 230 | int (*mcu_restart)(struct mt76_dev *dev); |
| 231 | }; |
| 232 | |
| 233 | struct mt76_queue_ops { |
| 234 | int (*init)(struct mt76_dev *dev, |
| 235 | int (*poll)(struct napi_struct *napi, int budget)); |
| 236 | |
| 237 | int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, |
| 238 | int idx, int n_desc, int bufsize, |
| 239 | u32 ring_base); |
| 240 | |
| 241 | int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, |
| 242 | struct sk_buff *skb, struct mt76_wcid *wcid, |
| 243 | struct ieee80211_sta *sta); |
| 244 | |
| 245 | int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, |
| 246 | struct sk_buff *skb, u32 tx_info); |
| 247 | |
| 248 | void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, |
| 249 | int *len, u32 *info, bool *more); |
| 250 | |
| 251 | void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); |
| 252 | |
| 253 | void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, |
| 254 | bool flush); |
| 255 | |
| 256 | void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); |
| 257 | |
| 258 | void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); |
| 259 | |
| 260 | void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); |
| 261 | }; |
| 262 | |
| 263 | enum mt76_wcid_flags { |
| 264 | MT_WCID_FLAG_CHECK_PS, |
| 265 | MT_WCID_FLAG_PS, |
| 266 | MT_WCID_FLAG_4ADDR, |
| 267 | MT_WCID_FLAG_HDR_TRANS, |
| 268 | }; |
| 269 | |
| 270 | #define MT76_N_WCIDS 544 |
| 271 | |
| 272 | /* stored in ieee80211_tx_info::hw_queue */ |
| 273 | #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) |
| 274 | #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) |
| 275 | |
| 276 | DECLARE_EWMA(signal, 10, 8); |
| 277 | |
| 278 | #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) |
| 279 | #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) |
| 280 | #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) |
| 281 | #define MT_WCID_TX_INFO_SET BIT(31) |
| 282 | |
| 283 | struct mt76_wcid { |
| 284 | struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; |
| 285 | |
| 286 | atomic_t non_aql_packets; |
| 287 | unsigned long flags; |
| 288 | |
| 289 | struct ewma_signal rssi; |
| 290 | int inactive_count; |
| 291 | |
| 292 | struct rate_info rate; |
| 293 | |
| 294 | u16 idx; |
| 295 | u8 hw_key_idx; |
| 296 | u8 hw_key_idx2; |
| 297 | |
| 298 | u8 sta:1; |
| 299 | u8 phy_idx:2; |
| 300 | u8 amsdu:1; |
| 301 | |
| 302 | u8 rx_check_pn; |
| 303 | u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; |
| 304 | u16 cipher; |
| 305 | |
| 306 | u32 tx_info; |
| 307 | bool sw_iv; |
| 308 | |
| 309 | struct list_head list; |
| 310 | struct idr pktid; |
| 311 | }; |
| 312 | |
| 313 | struct mt76_txq { |
| 314 | u16 wcid; |
| 315 | |
| 316 | u16 agg_ssn; |
| 317 | bool send_bar; |
| 318 | bool aggr; |
| 319 | }; |
| 320 | |
| 321 | struct mt76_txwi_cache { |
| 322 | struct list_head list; |
| 323 | dma_addr_t dma_addr; |
| 324 | |
| 325 | struct sk_buff *skb; |
| 326 | }; |
| 327 | |
| 328 | struct mt76_rx_tid { |
| 329 | struct rcu_head rcu_head; |
| 330 | |
| 331 | struct mt76_dev *dev; |
| 332 | |
| 333 | spinlock_t lock; |
| 334 | struct delayed_work reorder_work; |
| 335 | |
| 336 | u16 head; |
| 337 | u16 size; |
| 338 | u16 nframes; |
| 339 | |
| 340 | u8 num; |
| 341 | |
| 342 | u8 started:1, stopped:1, timer_pending:1; |
| 343 | |
| 344 | struct sk_buff *reorder_buf[]; |
| 345 | }; |
| 346 | |
| 347 | #define MT_TX_CB_DMA_DONE BIT(0) |
| 348 | #define MT_TX_CB_TXS_DONE BIT(1) |
| 349 | #define MT_TX_CB_TXS_FAILED BIT(2) |
| 350 | |
| 351 | #define MT_PACKET_ID_MASK GENMASK(6, 0) |
| 352 | #define MT_PACKET_ID_NO_ACK 0 |
| 353 | #define MT_PACKET_ID_NO_SKB 1 |
| 354 | #define MT_PACKET_ID_FIRST 2 |
| 355 | #define MT_PACKET_ID_HAS_RATE BIT(7) |
| 356 | /* This is timer for when to give up when waiting for TXS callback, |
| 357 | * with starting time being the time at which the DMA_DONE callback |
| 358 | * was seen (so, we know packet was processed then, it should not take |
| 359 | * long after that for firmware to send the TXS callback if it is going |
| 360 | * to do so.) |
| 361 | */ |
| 362 | #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) |
| 363 | |
| 364 | struct mt76_tx_cb { |
| 365 | unsigned long jiffies; |
| 366 | u16 wcid; |
| 367 | u8 pktid; |
| 368 | u8 flags; |
| 369 | }; |
| 370 | |
| 371 | enum { |
| 372 | MT76_STATE_INITIALIZED, |
| 373 | MT76_STATE_RUNNING, |
| 374 | MT76_STATE_MCU_RUNNING, |
| 375 | MT76_SCANNING, |
| 376 | MT76_HW_SCANNING, |
| 377 | MT76_HW_SCHED_SCANNING, |
| 378 | MT76_RESTART, |
| 379 | MT76_RESET, |
| 380 | MT76_MCU_RESET, |
| 381 | MT76_REMOVED, |
| 382 | MT76_READING_STATS, |
| 383 | MT76_STATE_POWER_OFF, |
| 384 | MT76_STATE_SUSPEND, |
| 385 | MT76_STATE_ROC, |
| 386 | MT76_STATE_PM, |
| 387 | }; |
| 388 | |
| 389 | struct mt76_hw_cap { |
| 390 | bool has_2ghz; |
| 391 | bool has_5ghz; |
| 392 | bool has_6ghz; |
| 393 | }; |
| 394 | |
| 395 | #define MT_DRV_TXWI_NO_FREE BIT(0) |
| 396 | #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) |
| 397 | #define MT_DRV_SW_RX_AIRTIME BIT(2) |
| 398 | #define MT_DRV_RX_DMA_HDR BIT(3) |
| 399 | #define MT_DRV_HW_MGMT_TXQ BIT(4) |
| 400 | |
| 401 | struct mt76_driver_ops { |
| 402 | u32 drv_flags; |
| 403 | u32 survey_flags; |
| 404 | u16 txwi_size; |
| 405 | u16 token_size; |
| 406 | u8 mcs_rates; |
| 407 | |
| 408 | void (*update_survey)(struct mt76_phy *phy); |
| 409 | |
| 410 | int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, |
| 411 | enum mt76_txq_id qid, struct mt76_wcid *wcid, |
| 412 | struct ieee80211_sta *sta, |
| 413 | struct mt76_tx_info *tx_info); |
| 414 | |
| 415 | void (*tx_complete_skb)(struct mt76_dev *dev, |
| 416 | struct mt76_queue_entry *e); |
| 417 | |
| 418 | bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); |
| 419 | |
| 420 | bool (*rx_check)(struct mt76_dev *dev, enum mt76_rxq_id q, void *data, int len); |
| 421 | |
| 422 | void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, |
| 423 | struct sk_buff *skb); |
| 424 | |
| 425 | void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); |
| 426 | |
| 427 | void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, |
| 428 | bool ps); |
| 429 | |
| 430 | int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 431 | struct ieee80211_sta *sta); |
| 432 | |
| 433 | void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 434 | struct ieee80211_sta *sta); |
| 435 | |
| 436 | void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 437 | struct ieee80211_sta *sta); |
| 438 | }; |
| 439 | |
| 440 | struct mt76_channel_state { |
| 441 | u64 cc_active; |
| 442 | u64 cc_busy; |
| 443 | u64 cc_rx; |
| 444 | u64 cc_bss_rx; |
| 445 | u64 cc_tx; |
| 446 | |
| 447 | s8 noise; |
| 448 | }; |
| 449 | |
| 450 | struct mt76_sband { |
| 451 | struct ieee80211_supported_band sband; |
| 452 | struct mt76_channel_state *chan; |
| 453 | }; |
| 454 | |
| 455 | struct mt76_rate_power { |
| 456 | union { |
| 457 | struct { |
| 458 | s8 cck[4]; |
| 459 | s8 ofdm[8]; |
| 460 | s8 stbc[10]; |
| 461 | s8 ht[16]; |
| 462 | s8 vht[10]; |
| 463 | }; |
| 464 | s8 all[48]; |
| 465 | }; |
| 466 | }; |
| 467 | |
| 468 | /* addr req mask */ |
| 469 | #define MT_VEND_TYPE_EEPROM BIT(31) |
| 470 | #define MT_VEND_TYPE_CFG BIT(30) |
| 471 | #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) |
| 472 | |
| 473 | #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) |
| 474 | enum mt_vendor_req { |
| 475 | MT_VEND_DEV_MODE = 0x1, |
| 476 | MT_VEND_WRITE = 0x2, |
| 477 | MT_VEND_POWER_ON = 0x4, |
| 478 | MT_VEND_MULTI_WRITE = 0x6, |
| 479 | MT_VEND_MULTI_READ = 0x7, |
| 480 | MT_VEND_READ_EEPROM = 0x9, |
| 481 | MT_VEND_WRITE_FCE = 0x42, |
| 482 | MT_VEND_WRITE_CFG = 0x46, |
| 483 | MT_VEND_READ_CFG = 0x47, |
| 484 | MT_VEND_READ_EXT = 0x63, |
| 485 | MT_VEND_WRITE_EXT = 0x66, |
| 486 | MT_VEND_FEATURE_SET = 0x91, |
| 487 | }; |
| 488 | |
| 489 | enum mt76u_in_ep { |
| 490 | MT_EP_IN_PKT_RX, |
| 491 | MT_EP_IN_CMD_RESP, |
| 492 | __MT_EP_IN_MAX, |
| 493 | }; |
| 494 | |
| 495 | enum mt76u_out_ep { |
| 496 | MT_EP_OUT_INBAND_CMD, |
| 497 | MT_EP_OUT_AC_BE, |
| 498 | MT_EP_OUT_AC_BK, |
| 499 | MT_EP_OUT_AC_VI, |
| 500 | MT_EP_OUT_AC_VO, |
| 501 | MT_EP_OUT_HCCA, |
| 502 | __MT_EP_OUT_MAX, |
| 503 | }; |
| 504 | |
| 505 | struct mt76_mcu { |
| 506 | struct mutex mutex; |
| 507 | u32 msg_seq; |
| 508 | int timeout; |
| 509 | |
| 510 | struct sk_buff_head res_q; |
| 511 | wait_queue_head_t wait; |
| 512 | }; |
| 513 | |
| 514 | #define MT_TX_SG_MAX_SIZE 8 |
| 515 | #define MT_RX_SG_MAX_SIZE 4 |
| 516 | #define MT_NUM_TX_ENTRIES 256 |
| 517 | #define MT_NUM_RX_ENTRIES 128 |
| 518 | #define MCU_RESP_URB_SIZE 1024 |
| 519 | struct mt76_usb { |
| 520 | struct mutex usb_ctrl_mtx; |
| 521 | u8 *data; |
| 522 | u16 data_len; |
| 523 | |
| 524 | struct mt76_worker status_worker; |
| 525 | struct mt76_worker rx_worker; |
| 526 | |
| 527 | struct work_struct stat_work; |
| 528 | |
| 529 | u8 out_ep[__MT_EP_OUT_MAX]; |
| 530 | u8 in_ep[__MT_EP_IN_MAX]; |
| 531 | bool sg_en; |
| 532 | |
| 533 | struct mt76u_mcu { |
| 534 | u8 *data; |
| 535 | /* multiple reads */ |
| 536 | struct mt76_reg_pair *rp; |
| 537 | int rp_len; |
| 538 | u32 base; |
| 539 | bool burst; |
| 540 | } mcu; |
| 541 | }; |
| 542 | |
| 543 | #define MT76S_XMIT_BUF_SZ 0x3fe00 |
| 544 | #define MT76S_NUM_TX_ENTRIES 256 |
| 545 | #define MT76S_NUM_RX_ENTRIES 512 |
| 546 | struct mt76_sdio { |
| 547 | struct mt76_worker txrx_worker; |
| 548 | struct mt76_worker status_worker; |
| 549 | struct mt76_worker net_worker; |
| 550 | |
| 551 | struct work_struct stat_work; |
| 552 | |
| 553 | u8 *xmit_buf; |
| 554 | u32 xmit_buf_sz; |
| 555 | |
| 556 | struct sdio_func *func; |
| 557 | void *intr_data; |
| 558 | u8 hw_ver; |
| 559 | wait_queue_head_t wait; |
| 560 | |
| 561 | struct { |
| 562 | int pse_data_quota; |
| 563 | int ple_data_quota; |
| 564 | int pse_mcu_quota; |
| 565 | int pse_page_size; |
| 566 | int deficit; |
| 567 | } sched; |
| 568 | |
| 569 | int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); |
| 570 | }; |
| 571 | |
| 572 | struct mt76_mmio { |
| 573 | void __iomem *regs; |
| 574 | spinlock_t irq_lock; |
| 575 | u32 irqmask; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 576 | |
| 577 | struct mtk_wed_device wed; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 578 | }; |
| 579 | |
| 580 | struct mt76_rx_status { |
| 581 | union { |
| 582 | struct mt76_wcid *wcid; |
| 583 | u16 wcid_idx; |
| 584 | }; |
| 585 | |
| 586 | u32 reorder_time; |
| 587 | |
| 588 | u32 ampdu_ref; |
| 589 | u32 timestamp; |
| 590 | |
| 591 | u8 iv[6]; |
| 592 | |
| 593 | u8 phy_idx:2; |
| 594 | u8 aggr:1; |
| 595 | u8 qos_ctl; |
| 596 | u16 seqno; |
| 597 | |
| 598 | u16 freq; |
| 599 | u32 flag; |
| 600 | u8 enc_flags; |
| 601 | u8 encoding:2, bw:3, he_ru:3; |
| 602 | u8 he_gi:2, he_dcm:1; |
| 603 | u8 amsdu:1, first_amsdu:1, last_amsdu:1; |
| 604 | u8 rate_idx; |
| 605 | u8 nss; |
| 606 | u8 band; |
| 607 | s8 signal; |
| 608 | u8 chains; |
| 609 | s8 chain_signal[IEEE80211_MAX_CHAINS]; |
| 610 | }; |
| 611 | |
| 612 | struct mt76_freq_range_power { |
| 613 | const struct cfg80211_sar_freq_ranges *range; |
| 614 | s8 power; |
| 615 | }; |
| 616 | |
| 617 | struct mt76_testmode_ops { |
| 618 | int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); |
| 619 | int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, |
| 620 | enum mt76_testmode_state new_state); |
| 621 | int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); |
| 622 | }; |
| 623 | |
| 624 | struct mt76_testmode_data { |
| 625 | enum mt76_testmode_state state; |
| 626 | |
| 627 | u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; |
| 628 | struct sk_buff *tx_skb; |
| 629 | |
| 630 | u32 tx_count; |
| 631 | u16 tx_mpdu_len; |
| 632 | |
| 633 | u8 tx_rate_mode; |
| 634 | u8 tx_rate_idx; |
| 635 | u8 tx_rate_nss; |
| 636 | u8 tx_rate_sgi; |
| 637 | u8 tx_rate_ldpc; |
| 638 | u8 tx_rate_stbc; |
| 639 | u8 tx_ltf; |
| 640 | |
| 641 | u8 tx_antenna_mask; |
| 642 | u8 tx_spe_idx; |
| 643 | |
| 644 | u8 tx_duty_cycle; |
| 645 | u32 tx_time; |
| 646 | u32 tx_ipg; |
| 647 | |
| 648 | u32 freq_offset; |
| 649 | |
| 650 | u8 tx_power[4]; |
| 651 | u8 tx_power_control; |
| 652 | |
| 653 | u8 addr[3][ETH_ALEN]; |
| 654 | |
| 655 | u32 tx_pending; |
| 656 | u32 tx_queued; |
| 657 | u16 tx_queued_limit; |
| 658 | u32 tx_done; |
| 659 | struct { |
| 660 | u64 packets[__MT_RXQ_MAX]; |
| 661 | u64 fcs_error[__MT_RXQ_MAX]; |
| 662 | } rx_stats; |
| 663 | }; |
| 664 | |
| 665 | struct mt76_vif { |
| 666 | u8 idx; |
| 667 | u8 omac_idx; |
| 668 | u8 band_idx; |
| 669 | u8 wmm_idx; |
| 670 | u8 scan_seq_num; |
| 671 | u8 cipher; |
| 672 | }; |
| 673 | |
| 674 | struct mt76_phy { |
| 675 | struct ieee80211_hw *hw; |
| 676 | struct mt76_dev *dev; |
| 677 | void *priv; |
| 678 | |
| 679 | unsigned long state; |
| 680 | |
| 681 | struct mt76_queue *q_tx[__MT_TXQ_MAX]; |
| 682 | |
| 683 | struct cfg80211_chan_def chandef; |
| 684 | struct ieee80211_channel *main_chan; |
| 685 | |
| 686 | struct mt76_channel_state *chan_state; |
| 687 | enum mt76_dfs_state dfs_state; |
| 688 | ktime_t survey_time; |
| 689 | |
| 690 | struct mt76_hw_cap cap; |
| 691 | struct mt76_sband sband_2g; |
| 692 | struct mt76_sband sband_5g; |
| 693 | struct mt76_sband sband_6g; |
| 694 | u8 band_idx; |
| 695 | |
| 696 | u8 macaddr[ETH_ALEN]; |
| 697 | |
| 698 | int txpower_cur; |
| 699 | u8 antenna_mask; |
| 700 | u32 chainmask; |
| 701 | |
| 702 | #ifdef CONFIG_NL80211_TESTMODE |
| 703 | struct mt76_testmode_data test; |
| 704 | #endif |
| 705 | |
| 706 | struct delayed_work mac_work; |
| 707 | u8 mac_work_count; |
| 708 | |
| 709 | struct { |
| 710 | struct sk_buff *head; |
| 711 | struct sk_buff **tail; |
| 712 | u16 seqno; |
| 713 | } rx_amsdu[__MT_RXQ_MAX]; |
| 714 | |
| 715 | struct mt76_freq_range_power *frp; |
| 716 | }; |
| 717 | |
| 718 | struct mt76_dev { |
| 719 | struct mt76_phy phy; /* must be first */ |
| 720 | |
| 721 | struct mt76_phy *phy2; |
| 722 | struct mt76_phy *phy3; |
| 723 | |
| 724 | struct ieee80211_hw *hw; |
| 725 | |
| 726 | spinlock_t lock; |
| 727 | spinlock_t cc_lock; |
| 728 | |
| 729 | u32 cur_cc_bss_rx; |
| 730 | |
| 731 | struct mt76_rx_status rx_ampdu_status; |
| 732 | u32 rx_ampdu_len; |
| 733 | u32 rx_ampdu_ref; |
| 734 | |
| 735 | struct mutex mutex; |
| 736 | |
| 737 | const struct mt76_bus_ops *bus; |
| 738 | const struct mt76_driver_ops *drv; |
| 739 | const struct mt76_mcu_ops *mcu_ops; |
| 740 | struct device *dev; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 741 | struct device *dma_dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 742 | |
| 743 | struct mt76_mcu mcu; |
| 744 | |
| 745 | struct net_device napi_dev; |
| 746 | struct net_device tx_napi_dev; |
| 747 | spinlock_t rx_lock; |
| 748 | struct napi_struct napi[__MT_RXQ_MAX]; |
| 749 | struct sk_buff_head rx_skb[__MT_RXQ_MAX]; |
| 750 | |
| 751 | struct list_head txwi_cache; |
| 752 | struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; |
| 753 | struct mt76_queue q_rx[__MT_RXQ_MAX]; |
| 754 | const struct mt76_queue_ops *queue_ops; |
| 755 | int tx_dma_idx[4]; |
| 756 | |
| 757 | struct mt76_worker tx_worker; |
| 758 | struct napi_struct tx_napi; |
| 759 | |
| 760 | spinlock_t token_lock; |
| 761 | struct idr token; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 762 | u16 wed_token_count; |
| 763 | u16 token_count; |
| 764 | u16 token_size; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 765 | |
| 766 | wait_queue_head_t tx_wait; |
| 767 | /* spinclock used to protect wcid pktid linked list */ |
| 768 | spinlock_t status_lock; |
| 769 | |
| 770 | u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; |
| 771 | u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; |
| 772 | u32 wcid_phy3_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; |
| 773 | |
| 774 | u64 vif_mask; |
| 775 | |
| 776 | struct mt76_wcid global_wcid; |
| 777 | struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; |
| 778 | struct list_head wcid_list; |
| 779 | |
| 780 | u32 rev; |
| 781 | |
| 782 | u32 aggr_stats[32]; |
| 783 | |
| 784 | struct tasklet_struct pre_tbtt_tasklet; |
| 785 | int beacon_int; |
| 786 | u8 beacon_mask; |
| 787 | |
| 788 | struct debugfs_blob_wrapper eeprom; |
| 789 | struct debugfs_blob_wrapper otp; |
| 790 | |
| 791 | struct mt76_rate_power rate_power; |
| 792 | |
| 793 | char alpha2[3]; |
| 794 | enum nl80211_dfs_regions region; |
| 795 | |
| 796 | u32 debugfs_reg; |
| 797 | |
| 798 | struct led_classdev led_cdev; |
| 799 | char led_name[32]; |
| 800 | bool led_al; |
| 801 | u8 led_pin; |
| 802 | |
| 803 | u8 csa_complete; |
| 804 | |
| 805 | u32 rxfilter; |
| 806 | |
| 807 | #ifdef CONFIG_NL80211_TESTMODE |
| 808 | const struct mt76_testmode_ops *test_ops; |
| 809 | struct { |
| 810 | const char *name; |
| 811 | u32 offset; |
| 812 | } test_mtd; |
| 813 | #endif |
| 814 | struct workqueue_struct *wq; |
| 815 | |
| 816 | union { |
| 817 | struct mt76_mmio mmio; |
| 818 | struct mt76_usb usb; |
| 819 | struct mt76_sdio sdio; |
| 820 | }; |
| 821 | }; |
| 822 | |
| 823 | struct mt76_power_limits { |
| 824 | s8 cck[4]; |
| 825 | s8 ofdm[8]; |
| 826 | s8 mcs[4][10]; |
| 827 | s8 ru[7][12]; |
| 828 | }; |
| 829 | |
| 830 | enum mt76_phy_type { |
| 831 | MT_PHY_TYPE_CCK, |
| 832 | MT_PHY_TYPE_OFDM, |
| 833 | MT_PHY_TYPE_HT, |
| 834 | MT_PHY_TYPE_HT_GF, |
| 835 | MT_PHY_TYPE_VHT, |
| 836 | MT_PHY_TYPE_HE_SU = 8, |
| 837 | MT_PHY_TYPE_HE_EXT_SU, |
| 838 | MT_PHY_TYPE_HE_TB, |
| 839 | MT_PHY_TYPE_HE_MU, |
| 840 | __MT_PHY_TYPE_HE_MAX, |
| 841 | }; |
| 842 | |
| 843 | struct mt76_sta_stats { |
| 844 | u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; |
| 845 | u64 tx_bw[4]; /* 20, 40, 80, 160 */ |
| 846 | u64 tx_nss[4]; /* 1, 2, 3, 4 */ |
| 847 | u64 tx_mcs[16]; /* mcs idx */ |
| 848 | }; |
| 849 | |
| 850 | struct mt76_ethtool_worker_info { |
| 851 | u64 *data; |
| 852 | int idx; |
| 853 | int initial_stat_idx; |
| 854 | int worker_stat_count; |
| 855 | int sta_count; |
| 856 | }; |
| 857 | |
| 858 | #define CCK_RATE(_idx, _rate) { \ |
| 859 | .bitrate = _rate, \ |
| 860 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ |
| 861 | .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ |
| 862 | .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ |
| 863 | } |
| 864 | |
| 865 | #define OFDM_RATE(_idx, _rate) { \ |
| 866 | .bitrate = _rate, \ |
| 867 | .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ |
| 868 | .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ |
| 869 | } |
| 870 | |
| 871 | extern struct ieee80211_rate mt76_rates[12]; |
| 872 | |
| 873 | #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) |
| 874 | #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) |
| 875 | #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) |
| 876 | #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) |
| 877 | #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) |
| 878 | |
| 879 | #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) |
| 880 | #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) |
| 881 | |
| 882 | #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) |
| 883 | #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) |
| 884 | #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) |
| 885 | #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) |
| 886 | #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) |
| 887 | #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) |
| 888 | #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) |
| 889 | |
| 890 | |
| 891 | #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) |
| 892 | #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) |
| 893 | |
| 894 | #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) |
| 895 | #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) |
| 896 | |
| 897 | #define mt76_get_field(_dev, _reg, _field) \ |
| 898 | FIELD_GET(_field, mt76_rr(dev, _reg)) |
| 899 | |
| 900 | #define mt76_rmw_field(_dev, _reg, _field, _val) \ |
| 901 | mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) |
| 902 | |
| 903 | #define __mt76_rmw_field(_dev, _reg, _field, _val) \ |
| 904 | __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) |
| 905 | |
| 906 | #define mt76_hw(dev) (dev)->mphy.hw |
| 907 | |
| 908 | static inline struct ieee80211_hw * |
| 909 | mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) |
| 910 | { |
| 911 | if (wcid <= MT76_N_WCIDS && |
| 912 | mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) |
| 913 | return dev->phy2->hw; |
| 914 | |
| 915 | if (wcid <= MT76_N_WCIDS && |
| 916 | mt76_wcid_mask_test(dev->wcid_phy3_mask, wcid)) |
| 917 | return dev->phy3->hw; |
| 918 | |
| 919 | return dev->phy.hw; |
| 920 | } |
| 921 | |
| 922 | bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, |
| 923 | int timeout); |
| 924 | |
| 925 | #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) |
| 926 | |
| 927 | bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, |
| 928 | int timeout); |
| 929 | |
| 930 | #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) |
| 931 | |
| 932 | void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); |
| 933 | void mt76_pci_disable_aspm(struct pci_dev *pdev); |
| 934 | |
| 935 | static inline u16 mt76_chip(struct mt76_dev *dev) |
| 936 | { |
| 937 | return dev->rev >> 16; |
| 938 | } |
| 939 | |
| 940 | static inline u16 mt76_rev(struct mt76_dev *dev) |
| 941 | { |
| 942 | return dev->rev & 0xffff; |
| 943 | } |
| 944 | |
| 945 | static inline u8 mt76_get_phy_id(struct mt76_phy *phy) |
| 946 | { |
| 947 | if (phy == &phy->dev->phy) |
| 948 | return MT_MAIN_PHY; |
| 949 | |
| 950 | if (phy == phy->dev->phy2) |
| 951 | return MT_EXT_PHY; |
| 952 | |
| 953 | return MT_TRI_PHY; |
| 954 | } |
| 955 | |
| 956 | #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) |
| 957 | #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) |
| 958 | |
| 959 | #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) |
| 960 | #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) |
| 961 | #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) |
| 962 | #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) |
| 963 | #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) |
| 964 | #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) |
| 965 | #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) |
| 966 | #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) |
| 967 | #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) |
| 968 | |
| 969 | #define mt76_for_each_q_rx(dev, i) \ |
| 970 | for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ |
| 971 | if ((dev)->q_rx[i].ndesc) |
| 972 | |
| 973 | struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, |
| 974 | const struct ieee80211_ops *ops, |
| 975 | const struct mt76_driver_ops *drv_ops); |
| 976 | int mt76_register_device(struct mt76_dev *dev, bool vht, |
| 977 | struct ieee80211_rate *rates, int n_rates); |
| 978 | void mt76_unregister_device(struct mt76_dev *dev); |
| 979 | void mt76_free_device(struct mt76_dev *dev); |
| 980 | void mt76_unregister_phy(struct mt76_phy *phy); |
| 981 | |
| 982 | struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, |
| 983 | const struct ieee80211_ops *ops, u8 idx); |
| 984 | int mt76_register_phy(struct mt76_phy *phy, bool vht, |
| 985 | struct ieee80211_rate *rates, int n_rates); |
| 986 | |
| 987 | struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, |
| 988 | const struct file_operations *ops); |
| 989 | static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) |
| 990 | { |
| 991 | return mt76_register_debugfs_fops(&dev->phy, NULL); |
| 992 | } |
| 993 | |
| 994 | int mt76_queues_read(struct seq_file *s, void *data); |
| 995 | void mt76_seq_puts_array(struct seq_file *file, const char *str, |
| 996 | s8 *val, int len); |
| 997 | |
| 998 | int mt76_eeprom_init(struct mt76_dev *dev, int len); |
| 999 | void mt76_eeprom_override(struct mt76_phy *phy); |
| 1000 | int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); |
| 1001 | |
| 1002 | struct mt76_queue * |
| 1003 | mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1004 | int ring_base, u32 flags); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1005 | u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); |
| 1006 | static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1007 | int n_desc, int ring_base, u32 flags) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1008 | { |
| 1009 | struct mt76_queue *q; |
| 1010 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1011 | q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1012 | if (IS_ERR(q)) |
| 1013 | return PTR_ERR(q); |
| 1014 | |
| 1015 | q->qid = qid; |
| 1016 | phy->q_tx[qid] = q; |
| 1017 | |
| 1018 | return 0; |
| 1019 | } |
| 1020 | |
| 1021 | static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, |
| 1022 | int n_desc, int ring_base) |
| 1023 | { |
| 1024 | struct mt76_queue *q; |
| 1025 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1026 | q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1027 | if (IS_ERR(q)) |
| 1028 | return PTR_ERR(q); |
| 1029 | |
| 1030 | q->qid = __MT_TXQ_MAX + qid; |
| 1031 | dev->q_mcu[qid] = q; |
| 1032 | |
| 1033 | return 0; |
| 1034 | } |
| 1035 | |
| 1036 | static inline struct mt76_phy * |
| 1037 | mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) |
| 1038 | { |
| 1039 | if ((phy_idx == MT_EXT_PHY) && dev->phy2) |
| 1040 | return dev->phy2; |
| 1041 | |
| 1042 | if ((phy_idx == MT_TRI_PHY) && dev->phy3) |
| 1043 | return dev->phy3; |
| 1044 | |
| 1045 | return &dev->phy; |
| 1046 | } |
| 1047 | |
| 1048 | static inline struct ieee80211_hw * |
| 1049 | mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) |
| 1050 | { |
| 1051 | return mt76_dev_phy(dev, phy_idx)->hw; |
| 1052 | } |
| 1053 | |
| 1054 | static inline struct mt76_phy * |
| 1055 | mt76_dev_phy_by_band(struct mt76_dev *dev, u8 band_idx) |
| 1056 | { |
| 1057 | if (dev->phy3 && band_idx == dev->phy3->band_idx) |
| 1058 | return dev->phy3; |
| 1059 | |
| 1060 | if (dev->phy2 && band_idx == dev->phy2->band_idx) |
| 1061 | return dev->phy2; |
| 1062 | |
| 1063 | return &dev->phy; |
| 1064 | } |
| 1065 | |
| 1066 | static inline u8 * |
| 1067 | mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) |
| 1068 | { |
| 1069 | return (u8 *)t - dev->drv->txwi_size; |
| 1070 | } |
| 1071 | |
| 1072 | /* increment with wrap-around */ |
| 1073 | static inline int mt76_incr(int val, int size) |
| 1074 | { |
| 1075 | return (val + 1) & (size - 1); |
| 1076 | } |
| 1077 | |
| 1078 | /* decrement with wrap-around */ |
| 1079 | static inline int mt76_decr(int val, int size) |
| 1080 | { |
| 1081 | return (val - 1) & (size - 1); |
| 1082 | } |
| 1083 | |
| 1084 | u8 mt76_ac_to_hwq(u8 ac); |
| 1085 | |
| 1086 | static inline struct ieee80211_txq * |
| 1087 | mtxq_to_txq(struct mt76_txq *mtxq) |
| 1088 | { |
| 1089 | void *ptr = mtxq; |
| 1090 | |
| 1091 | return container_of(ptr, struct ieee80211_txq, drv_priv); |
| 1092 | } |
| 1093 | |
| 1094 | static inline struct ieee80211_sta * |
| 1095 | wcid_to_sta(struct mt76_wcid *wcid) |
| 1096 | { |
| 1097 | void *ptr = wcid; |
| 1098 | |
| 1099 | if (!wcid || !wcid->sta) |
| 1100 | return NULL; |
| 1101 | |
| 1102 | return container_of(ptr, struct ieee80211_sta, drv_priv); |
| 1103 | } |
| 1104 | |
| 1105 | static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) |
| 1106 | { |
| 1107 | BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > |
| 1108 | sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); |
| 1109 | return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); |
| 1110 | } |
| 1111 | |
| 1112 | static inline void *mt76_skb_get_hdr(struct sk_buff *skb) |
| 1113 | { |
| 1114 | struct mt76_rx_status mstat; |
| 1115 | u8 *data = skb->data; |
| 1116 | |
| 1117 | /* Alignment concerns */ |
| 1118 | BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); |
| 1119 | BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); |
| 1120 | |
| 1121 | mstat = *((struct mt76_rx_status *)skb->cb); |
| 1122 | |
| 1123 | if (mstat.flag & RX_FLAG_RADIOTAP_HE) |
| 1124 | data += sizeof(struct ieee80211_radiotap_he); |
| 1125 | if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) |
| 1126 | data += sizeof(struct ieee80211_radiotap_he_mu); |
| 1127 | |
| 1128 | return data; |
| 1129 | } |
| 1130 | |
| 1131 | static inline void mt76_insert_hdr_pad(struct sk_buff *skb) |
| 1132 | { |
| 1133 | int len = ieee80211_get_hdrlen_from_skb(skb); |
| 1134 | |
| 1135 | if (len % 4 == 0) |
| 1136 | return; |
| 1137 | |
| 1138 | skb_push(skb, 2); |
| 1139 | memmove(skb->data, skb->data + 2, len); |
| 1140 | |
| 1141 | skb->data[len] = 0; |
| 1142 | skb->data[len + 1] = 0; |
| 1143 | } |
| 1144 | |
| 1145 | static inline bool mt76_is_skb_pktid(u8 pktid) |
| 1146 | { |
| 1147 | if (pktid & MT_PACKET_ID_HAS_RATE) |
| 1148 | return false; |
| 1149 | |
| 1150 | return pktid >= MT_PACKET_ID_FIRST; |
| 1151 | } |
| 1152 | |
| 1153 | static inline u8 mt76_tx_power_nss_delta(u8 nss) |
| 1154 | { |
| 1155 | static const u8 nss_delta[4] = { 0, 6, 9, 12 }; |
| 1156 | |
| 1157 | return nss_delta[nss - 1]; |
| 1158 | } |
| 1159 | |
| 1160 | static inline bool mt76_testmode_enabled(struct mt76_phy *phy) |
| 1161 | { |
| 1162 | #ifdef CONFIG_NL80211_TESTMODE |
| 1163 | return phy->test.state != MT76_TM_STATE_OFF; |
| 1164 | #else |
| 1165 | return false; |
| 1166 | #endif |
| 1167 | } |
| 1168 | |
| 1169 | static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, |
| 1170 | struct sk_buff *skb, |
| 1171 | struct ieee80211_hw **hw) |
| 1172 | { |
| 1173 | #ifdef CONFIG_NL80211_TESTMODE |
| 1174 | if (skb == dev->phy.test.tx_skb) |
| 1175 | *hw = dev->phy.hw; |
| 1176 | else if (dev->phy2 && skb == dev->phy2->test.tx_skb) |
| 1177 | *hw = dev->phy2->hw; |
| 1178 | else if (dev->phy3 && skb == dev->phy3->test.tx_skb) |
| 1179 | *hw = dev->phy3->hw; |
| 1180 | else |
| 1181 | return false; |
| 1182 | return true; |
| 1183 | #else |
| 1184 | return false; |
| 1185 | #endif |
| 1186 | } |
| 1187 | |
| 1188 | void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); |
| 1189 | void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, |
| 1190 | struct mt76_wcid *wcid, struct sk_buff *skb); |
| 1191 | void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); |
| 1192 | void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, |
| 1193 | bool send_bar); |
| 1194 | void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); |
| 1195 | void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); |
| 1196 | void mt76_txq_schedule_all(struct mt76_phy *phy); |
| 1197 | void mt76_tx_worker_run(struct mt76_dev *dev); |
| 1198 | void mt76_tx_worker(struct mt76_worker *w); |
| 1199 | void mt76_release_buffered_frames(struct ieee80211_hw *hw, |
| 1200 | struct ieee80211_sta *sta, |
| 1201 | u16 tids, int nframes, |
| 1202 | enum ieee80211_frame_release_type reason, |
| 1203 | bool more_data); |
| 1204 | bool mt76_has_tx_pending(struct mt76_phy *phy); |
| 1205 | void mt76_set_channel(struct mt76_phy *phy); |
| 1206 | void mt76_update_survey(struct mt76_phy *phy); |
| 1207 | void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); |
| 1208 | int mt76_get_survey(struct ieee80211_hw *hw, int idx, |
| 1209 | struct survey_info *survey); |
| 1210 | void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); |
| 1211 | |
| 1212 | int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, |
| 1213 | u16 ssn, u16 size); |
| 1214 | void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); |
| 1215 | |
| 1216 | void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, |
| 1217 | struct ieee80211_key_conf *key); |
| 1218 | |
| 1219 | void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) |
| 1220 | __acquires(&dev->status_lock); |
| 1221 | void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) |
| 1222 | __releases(&dev->status_lock); |
| 1223 | |
| 1224 | int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, |
| 1225 | struct sk_buff *skb); |
| 1226 | struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, |
| 1227 | struct mt76_wcid *wcid, int pktid, |
| 1228 | struct sk_buff_head *list); |
| 1229 | void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, |
| 1230 | struct sk_buff_head *list); |
| 1231 | void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, |
| 1232 | struct list_head *free_list); |
| 1233 | static inline void |
| 1234 | mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) |
| 1235 | { |
| 1236 | __mt76_tx_complete_skb(dev, wcid, skb, NULL); |
| 1237 | } |
| 1238 | |
| 1239 | void mt76_tx_status_check(struct mt76_dev *dev, bool flush); |
| 1240 | int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1241 | struct ieee80211_sta *sta, |
| 1242 | enum ieee80211_sta_state old_state, |
| 1243 | enum ieee80211_sta_state new_state); |
| 1244 | void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 1245 | struct ieee80211_sta *sta); |
| 1246 | void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1247 | struct ieee80211_sta *sta); |
| 1248 | |
| 1249 | int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 band); |
| 1250 | |
| 1251 | int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1252 | int *dbm); |
| 1253 | int mt76_init_sar_power(struct ieee80211_hw *hw, |
| 1254 | const struct cfg80211_sar_specs *sar); |
| 1255 | int mt76_get_sar_power(struct mt76_phy *phy, |
| 1256 | struct ieee80211_channel *chan, |
| 1257 | int power); |
| 1258 | |
| 1259 | void mt76_csa_check(struct mt76_dev *dev); |
| 1260 | void mt76_csa_finish(struct mt76_dev *dev); |
| 1261 | |
| 1262 | int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); |
| 1263 | int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); |
| 1264 | void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); |
| 1265 | int mt76_get_rate(struct mt76_dev *dev, |
| 1266 | struct ieee80211_supported_band *sband, |
| 1267 | int idx, bool cck); |
| 1268 | void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1269 | const u8 *mac); |
| 1270 | void mt76_sw_scan_complete(struct ieee80211_hw *hw, |
| 1271 | struct ieee80211_vif *vif); |
| 1272 | enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); |
| 1273 | int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1274 | void *data, int len); |
| 1275 | int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, |
| 1276 | struct netlink_callback *cb, void *data, int len); |
| 1277 | int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); |
| 1278 | int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); |
| 1279 | |
| 1280 | static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) |
| 1281 | { |
| 1282 | #ifdef CONFIG_NL80211_TESTMODE |
| 1283 | enum mt76_testmode_state state = MT76_TM_STATE_IDLE; |
| 1284 | |
| 1285 | if (disable || phy->test.state == MT76_TM_STATE_OFF) |
| 1286 | state = MT76_TM_STATE_OFF; |
| 1287 | |
| 1288 | mt76_testmode_set_state(phy, state); |
| 1289 | #endif |
| 1290 | } |
| 1291 | |
| 1292 | |
| 1293 | /* internal */ |
| 1294 | static inline struct ieee80211_hw * |
| 1295 | mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) |
| 1296 | { |
| 1297 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 1298 | struct ieee80211_hw *hw = dev->phy.hw; |
| 1299 | u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; |
| 1300 | |
| 1301 | hw = mt76_phy_hw(dev, phy_idx); |
| 1302 | |
| 1303 | info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; |
| 1304 | |
| 1305 | return hw; |
| 1306 | } |
| 1307 | |
| 1308 | void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); |
| 1309 | void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, |
| 1310 | struct napi_struct *napi); |
| 1311 | void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, |
| 1312 | struct napi_struct *napi); |
| 1313 | void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); |
| 1314 | void mt76_testmode_tx_pending(struct mt76_phy *phy); |
| 1315 | void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, |
| 1316 | struct mt76_queue_entry *e); |
| 1317 | |
| 1318 | /* usb */ |
| 1319 | static inline bool mt76u_urb_error(struct urb *urb) |
| 1320 | { |
| 1321 | return urb->status && |
| 1322 | urb->status != -ECONNRESET && |
| 1323 | urb->status != -ESHUTDOWN && |
| 1324 | urb->status != -ENOENT; |
| 1325 | } |
| 1326 | |
| 1327 | /* Map hardware queues to usb endpoints */ |
| 1328 | static inline u8 q2ep(u8 qid) |
| 1329 | { |
| 1330 | /* TODO: take management packets to queue 5 */ |
| 1331 | return qid + 1; |
| 1332 | } |
| 1333 | |
| 1334 | static inline int |
| 1335 | mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, |
| 1336 | int timeout, int ep) |
| 1337 | { |
| 1338 | struct usb_interface *uintf = to_usb_interface(dev->dev); |
| 1339 | struct usb_device *udev = interface_to_usbdev(uintf); |
| 1340 | struct mt76_usb *usb = &dev->usb; |
| 1341 | unsigned int pipe; |
| 1342 | |
| 1343 | if (actual_len) |
| 1344 | pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); |
| 1345 | else |
| 1346 | pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); |
| 1347 | |
| 1348 | return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); |
| 1349 | } |
| 1350 | |
| 1351 | void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, |
| 1352 | struct mt76_sta_stats *stats); |
| 1353 | int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); |
| 1354 | int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, |
| 1355 | u16 val, u16 offset, void *buf, size_t len); |
| 1356 | int mt76u_vendor_request(struct mt76_dev *dev, u8 req, |
| 1357 | u8 req_type, u16 val, u16 offset, |
| 1358 | void *buf, size_t len); |
| 1359 | void mt76u_single_wr(struct mt76_dev *dev, const u8 req, |
| 1360 | const u16 offset, const u32 val); |
| 1361 | void mt76u_read_copy(struct mt76_dev *dev, u32 offset, |
| 1362 | void *data, int len); |
| 1363 | u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); |
| 1364 | void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, |
| 1365 | u32 addr, u32 val); |
| 1366 | int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, |
| 1367 | struct mt76_bus_ops *ops); |
| 1368 | int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); |
| 1369 | int mt76u_alloc_mcu_queue(struct mt76_dev *dev); |
| 1370 | int mt76u_alloc_queues(struct mt76_dev *dev); |
| 1371 | void mt76u_stop_tx(struct mt76_dev *dev); |
| 1372 | void mt76u_stop_rx(struct mt76_dev *dev); |
| 1373 | int mt76u_resume_rx(struct mt76_dev *dev); |
| 1374 | void mt76u_queues_deinit(struct mt76_dev *dev); |
| 1375 | |
| 1376 | int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, |
| 1377 | const struct mt76_bus_ops *bus_ops); |
| 1378 | int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); |
| 1379 | int mt76s_alloc_tx(struct mt76_dev *dev); |
| 1380 | void mt76s_deinit(struct mt76_dev *dev); |
| 1381 | void mt76s_sdio_irq(struct sdio_func *func); |
| 1382 | void mt76s_txrx_worker(struct mt76_sdio *sdio); |
| 1383 | bool mt76s_txqs_empty(struct mt76_dev *dev); |
| 1384 | int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, |
| 1385 | int hw_ver); |
| 1386 | u32 mt76s_rr(struct mt76_dev *dev, u32 offset); |
| 1387 | void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); |
| 1388 | u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); |
| 1389 | u32 mt76s_read_pcr(struct mt76_dev *dev); |
| 1390 | void mt76s_write_copy(struct mt76_dev *dev, u32 offset, |
| 1391 | const void *data, int len); |
| 1392 | void mt76s_read_copy(struct mt76_dev *dev, u32 offset, |
| 1393 | void *data, int len); |
| 1394 | int mt76s_wr_rp(struct mt76_dev *dev, u32 base, |
| 1395 | const struct mt76_reg_pair *data, |
| 1396 | int len); |
| 1397 | int mt76s_rd_rp(struct mt76_dev *dev, u32 base, |
| 1398 | struct mt76_reg_pair *data, int len); |
| 1399 | |
| 1400 | struct sk_buff * |
| 1401 | mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, |
| 1402 | int data_len); |
| 1403 | void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); |
| 1404 | struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, |
| 1405 | unsigned long expires); |
| 1406 | int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, |
| 1407 | int len, bool wait_resp, struct sk_buff **ret); |
| 1408 | int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, |
| 1409 | int cmd, bool wait_resp, struct sk_buff **ret); |
| 1410 | int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, |
| 1411 | int len, int max_len); |
| 1412 | static inline int |
| 1413 | mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, |
| 1414 | int len) |
| 1415 | { |
| 1416 | int max_len = 4096 - dev->mcu_ops->headroom; |
| 1417 | |
| 1418 | return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); |
| 1419 | } |
| 1420 | |
| 1421 | static inline int |
| 1422 | mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, |
| 1423 | bool wait_resp) |
| 1424 | { |
| 1425 | return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); |
| 1426 | } |
| 1427 | |
| 1428 | static inline int |
| 1429 | mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, |
| 1430 | bool wait_resp) |
| 1431 | { |
| 1432 | return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); |
| 1433 | } |
| 1434 | |
| 1435 | void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); |
| 1436 | |
| 1437 | s8 mt76_get_rate_power_limits(struct mt76_phy *phy, |
| 1438 | struct ieee80211_channel *chan, |
| 1439 | struct mt76_power_limits *dest, |
| 1440 | s8 target_power); |
| 1441 | |
| 1442 | struct mt76_txwi_cache * |
| 1443 | mt76_token_release(struct mt76_dev *dev, int token, bool *wake); |
| 1444 | int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); |
| 1445 | void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); |
| 1446 | |
| 1447 | static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) |
| 1448 | { |
| 1449 | spin_lock_bh(&dev->token_lock); |
| 1450 | __mt76_set_tx_blocked(dev, blocked); |
| 1451 | spin_unlock_bh(&dev->token_lock); |
| 1452 | } |
| 1453 | |
| 1454 | static inline int |
| 1455 | mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) |
| 1456 | { |
| 1457 | int token; |
| 1458 | |
| 1459 | spin_lock_bh(&dev->token_lock); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1460 | token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1461 | spin_unlock_bh(&dev->token_lock); |
| 1462 | |
| 1463 | return token; |
| 1464 | } |
| 1465 | |
| 1466 | static inline struct mt76_txwi_cache * |
| 1467 | mt76_token_put(struct mt76_dev *dev, int token) |
| 1468 | { |
| 1469 | struct mt76_txwi_cache *txwi; |
| 1470 | |
| 1471 | spin_lock_bh(&dev->token_lock); |
| 1472 | txwi = idr_remove(&dev->token, token); |
| 1473 | spin_unlock_bh(&dev->token_lock); |
| 1474 | |
| 1475 | return txwi; |
| 1476 | } |
| 1477 | |
| 1478 | static inline void mt76_packet_id_init(struct mt76_wcid *wcid) |
| 1479 | { |
| 1480 | INIT_LIST_HEAD(&wcid->list); |
| 1481 | idr_init(&wcid->pktid); |
| 1482 | } |
| 1483 | |
| 1484 | static inline void |
| 1485 | mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) |
| 1486 | { |
| 1487 | struct sk_buff_head list; |
| 1488 | |
| 1489 | mt76_tx_status_lock(dev, &list); |
| 1490 | mt76_tx_status_skb_get(dev, wcid, -1, &list); |
| 1491 | mt76_tx_status_unlock(dev, &list); |
| 1492 | |
| 1493 | idr_destroy(&wcid->pktid); |
| 1494 | } |
| 1495 | |
| 1496 | #endif |