developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #include <linux/kernel.h> |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/platform_device.h> |
| 7 | #include <linux/pci.h> |
| 8 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 9 | #include "besra.h" |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 10 | #include "mac.h" |
| 11 | #include "../trace.h" |
| 12 | |
| 13 | static const struct __base mt7902_reg_base[] = { |
| 14 | [WF_AGG_BASE] = { {0x820e2000, 0x820f2000, 0x830e2000} }, |
| 15 | [WF_MIB_BASE] = { {0x820ed000, 0x820fd000, 0x830ed000} }, |
| 16 | [WF_TMAC_BASE] = { {0x820e4000, 0x820f4000, 0x830e4000} }, |
| 17 | [WF_RMAC_BASE] = { {0x820e5000, 0x820f5000, 0x830e5000} }, |
| 18 | [WF_ARB_BASE] = { {0x820e3000, 0x820f3000, 0x830e3000} }, |
| 19 | [WF_LPON_BASE] = { {0x820eb000, 0x820fb000, 0x830eb000} }, |
| 20 | [WF_ETBF_BASE] = { {0x820ea000, 0x820fa000, 0x830ea000} }, |
| 21 | [WF_DMA_BASE] = { {0x820e7000, 0x820f7000, 0x830e7000} }, |
| 22 | }; |
| 23 | |
| 24 | static const struct __map mt7902_reg_map[] = { |
| 25 | {0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */ |
| 26 | {0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */ |
| 27 | {0x56000000, 0x04000, 0x1000}, /* WFDMA reserved */ |
| 28 | {0x57000000, 0x05000, 0x1000}, /* WFDMA MCU wrap CR */ |
| 29 | {0x58000000, 0x06000, 0x1000}, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ |
| 30 | {0x59000000, 0x07000, 0x1000}, /* WFDMA PCIE1 MCU DMA1 */ |
| 31 | {0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */ |
| 32 | {0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */ |
| 33 | {0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */ |
| 34 | {0x74030000, 0x10000, 0x1000}, /* PCIe MAC */ |
| 35 | {0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */ |
| 36 | {0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */ |
| 37 | {0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */ |
| 38 | {0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */ |
| 39 | {0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */ |
| 40 | {0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */ |
| 41 | {0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */ |
| 42 | {0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */ |
| 43 | {0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */ |
| 44 | {0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ |
| 45 | {0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */ |
| 46 | {0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */ |
| 47 | {0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */ |
| 48 | {0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */ |
| 49 | {0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ |
| 50 | {0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */ |
| 51 | {0x40000000, 0x70000, 0x10000}, /* WF_UMAC_SYSRAM */ |
| 52 | {0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */ |
| 53 | {0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure register) */ |
| 54 | {0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */ |
| 55 | {0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */ |
| 56 | {0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */ |
| 57 | {0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */ |
| 58 | {0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */ |
| 59 | {0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */ |
| 60 | {0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */ |
| 61 | {0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ |
| 62 | {0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */ |
| 63 | {0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */ |
| 64 | {0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */ |
| 65 | {0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */ |
| 66 | {0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ |
| 67 | {0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ |
| 68 | {0x820b0000, 0xae000, 0x1000}, /* [APB2] WFSYS_ON */ |
| 69 | {0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */ |
| 70 | {0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */ |
| 71 | {0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */ |
| 72 | {0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */ |
| 73 | {0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */ |
| 74 | {0x0, 0x0, 0x0}, /* imply end of search */ |
| 75 | }; |
| 76 | |
| 77 | enum { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 78 | BESRA_REG_RR = 0x0, |
| 79 | BESRA_REG_WR, |
| 80 | BESRA_REG_RMW, |
| 81 | __BESRA_REG_OPS_MAX, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 82 | }; |
| 83 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 84 | static u32 besra_reg_wr(struct besra_dev *dev, u32 addr, u32 mask, u32 val, u8 wr) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 85 | { |
| 86 | u32 ret = 0; |
| 87 | |
| 88 | switch (wr) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 89 | case BESRA_REG_RR: |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 90 | ret = dev->bus_ops->rr(&dev->mt76, addr); |
| 91 | break; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 92 | case BESRA_REG_WR: |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 93 | dev->bus_ops->wr(&dev->mt76, addr, val); |
| 94 | break; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 95 | case BESRA_REG_RMW: |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 96 | ret = dev->bus_ops->rmw(&dev->mt76, addr, mask, val); |
| 97 | break; |
| 98 | default: |
| 99 | break; |
| 100 | } |
| 101 | |
| 102 | return ret; |
| 103 | } |
| 104 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 105 | static u32 besra_reg_map_l1(struct besra_dev *dev, u32 addr, u32 mask, u32 val, u8 wr) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 106 | { |
| 107 | u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); |
| 108 | u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); |
| 109 | u32 backup, ret = 0; |
| 110 | |
| 111 | backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); |
| 112 | dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, |
| 113 | MT_HIF_REMAP_L1_MASK, |
| 114 | FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); |
| 115 | /* use read to push write */ |
| 116 | dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); |
| 117 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 118 | ret = besra_reg_wr(dev, MT_HIF_REMAP_BASE_L1 + offset, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 119 | |
| 120 | /* remap to ori status */ |
| 121 | dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, backup); |
| 122 | |
| 123 | return ret; |
| 124 | } |
| 125 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 126 | static u32 besra_reg_map_l2(struct besra_dev *dev, u32 addr, u32 mask, u32 val, u8 wr) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 127 | { |
| 128 | u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); |
| 129 | u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); |
| 130 | u32 backup, ret = 0; |
| 131 | |
| 132 | backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); |
| 133 | dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, |
| 134 | MT_HIF_REMAP_L2_MASK, |
| 135 | FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); |
| 136 | |
| 137 | /* use read to push write */ |
| 138 | dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); |
| 139 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 140 | ret = besra_reg_wr(dev, MT_HIF_REMAP_BASE_L2 + offset, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 141 | |
| 142 | /* remap to ori status */ |
| 143 | dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, backup); |
| 144 | |
| 145 | return ret; |
| 146 | } |
| 147 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 148 | static u32 __besra_reg_addr(struct besra_dev *dev, u32 addr, u32 mask, u32 val, u8 wr) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 149 | { |
| 150 | int i; |
| 151 | |
| 152 | if (addr < 0x100000) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 153 | return besra_reg_wr(dev, addr, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 154 | |
| 155 | for (i = 0; i < dev->reg.map_size; i++) { |
| 156 | u32 ofs; |
| 157 | |
| 158 | if (addr < dev->reg.map[i].phys) |
| 159 | continue; |
| 160 | |
| 161 | ofs = addr - dev->reg.map[i].phys; |
| 162 | if (ofs > dev->reg.map[i].size) |
| 163 | continue; |
| 164 | |
| 165 | addr = dev->reg.map[i].mapped + ofs; |
| 166 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 167 | return besra_reg_wr(dev, addr, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || |
| 171 | (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || |
| 172 | (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 173 | return besra_reg_map_l1(dev, addr, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 174 | |
| 175 | if (dev_is_pci(dev->mt76.dev) && |
| 176 | ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || |
| 177 | (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END))) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 178 | return besra_reg_map_l1(dev, addr, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 179 | |
| 180 | /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ |
| 181 | if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { |
| 182 | addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 183 | return besra_reg_map_l1(dev, addr, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 184 | } |
| 185 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 186 | return besra_reg_map_l2(dev, addr, mask, val, wr); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 187 | } |
| 188 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 189 | static u32 besra_rr(struct mt76_dev *mdev, u32 offset) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 190 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 191 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 192 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 193 | return __besra_reg_addr(dev, offset, 0, 0, BESRA_REG_RR); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 194 | } |
| 195 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 196 | static void besra_wr(struct mt76_dev *mdev, u32 offset, u32 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 197 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 198 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 199 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 200 | __besra_reg_addr(dev, offset, 0, val, BESRA_REG_WR); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 201 | } |
| 202 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 203 | static u32 besra_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 204 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 205 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 206 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 207 | return __besra_reg_addr(dev, offset, mask, val, BESRA_REG_RMW); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 208 | } |
| 209 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 210 | static int besra_mmio_init(struct mt76_dev *mdev, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 211 | void __iomem *mem_base, |
| 212 | u32 device_id) |
| 213 | { |
| 214 | struct mt76_bus_ops *bus_ops; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 215 | struct besra_dev *dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 216 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 217 | dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 218 | mt76_mmio_init(&dev->mt76, mem_base); |
| 219 | |
| 220 | switch (device_id) { |
| 221 | case 0x7902: |
| 222 | dev->reg.base = mt7902_reg_base; |
| 223 | dev->reg.map = mt7902_reg_map; |
| 224 | dev->reg.map_size = ARRAY_SIZE(mt7902_reg_map); |
| 225 | break; |
| 226 | default: |
| 227 | return -EINVAL; |
| 228 | } |
| 229 | |
| 230 | dev->bus_ops = dev->mt76.bus; |
| 231 | bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), |
| 232 | GFP_KERNEL); |
| 233 | if (!bus_ops) |
| 234 | return -ENOMEM; |
| 235 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 236 | bus_ops->rr = besra_rr; |
| 237 | bus_ops->wr = besra_wr; |
| 238 | bus_ops->rmw = besra_rmw; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 239 | dev->mt76.bus = bus_ops; |
| 240 | |
| 241 | mdev->rev = (device_id << 16) | |
| 242 | (mt76_rr(dev, MT_HW_REV) & 0xff); |
| 243 | dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 248 | void besra_dual_hif_set_irq_mask(struct besra_dev *dev, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 249 | bool write_reg, |
| 250 | u32 clear, u32 set) |
| 251 | { |
| 252 | struct mt76_dev *mdev = &dev->mt76; |
| 253 | unsigned long flags; |
| 254 | |
| 255 | spin_lock_irqsave(&mdev->mmio.irq_lock, flags); |
| 256 | |
| 257 | mdev->mmio.irqmask &= ~clear; |
| 258 | mdev->mmio.irqmask |= set; |
| 259 | |
| 260 | if (write_reg) { |
| 261 | mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); |
| 262 | mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); |
| 263 | } |
| 264 | |
| 265 | spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); |
| 266 | } |
| 267 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 268 | static void besra_rx_poll_complete(struct mt76_dev *mdev, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 269 | enum mt76_rxq_id q) |
| 270 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 271 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 272 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 273 | besra_irq_enable(dev, MT_INT_RX(q)); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | /* TODO: support 2/4/6/8 MSI-X vectors */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 277 | static void besra_irq_tasklet(struct tasklet_struct *t) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 278 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 279 | struct besra_dev *dev = from_tasklet(dev, t, irq_tasklet); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 280 | u32 intr, intr1, mask; |
| 281 | |
| 282 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 283 | if (dev->hif2) |
| 284 | mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 285 | |
| 286 | intr = mt76_rr(dev, MT_INT_SOURCE_CSR); |
| 287 | intr &= dev->mt76.mmio.irqmask; |
| 288 | mt76_wr(dev, MT_INT_SOURCE_CSR, intr); |
| 289 | |
| 290 | if (dev->hif2) { |
| 291 | intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); |
| 292 | intr1 &= dev->mt76.mmio.irqmask; |
| 293 | mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); |
| 294 | |
| 295 | intr |= intr1; |
| 296 | } |
| 297 | |
| 298 | trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); |
| 299 | |
| 300 | mask = intr & MT_INT_RX_DONE_ALL; |
| 301 | if (intr & MT_INT_TX_DONE_MCU) |
| 302 | mask |= MT_INT_TX_DONE_MCU; |
| 303 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 304 | besra_irq_disable(dev, mask); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 305 | |
| 306 | if (intr & MT_INT_TX_DONE_MCU) |
| 307 | napi_schedule(&dev->mt76.tx_napi); |
| 308 | |
| 309 | if (intr & MT_INT_RX(MT_RXQ_MAIN) && MT_RXQ_VALID(MT_RXQ_MAIN)) |
| 310 | napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); |
| 311 | |
| 312 | if (intr & MT_INT_RX(MT_RXQ_EXT) && MT_RXQ_VALID(MT_RXQ_EXT)) |
| 313 | napi_schedule(&dev->mt76.napi[MT_RXQ_EXT]); |
| 314 | |
| 315 | if (intr & MT_INT_RX(MT_RXQ_MCU) && MT_RXQ_VALID(MT_RXQ_MCU)) |
| 316 | napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); |
| 317 | |
| 318 | if (intr & MT_INT_RX(MT_RXQ_MCU_WA) && MT_RXQ_VALID(MT_RXQ_MCU_WA)) |
| 319 | napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); |
| 320 | |
| 321 | if (intr & MT_INT_RX(MT_RXQ_MAIN_WA) && MT_RXQ_VALID(MT_RXQ_MAIN_WA)) |
| 322 | napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]); |
| 323 | |
| 324 | if (intr & MT_INT_RX(MT_RXQ_EXT_WA) && MT_RXQ_VALID(MT_RXQ_EXT_WA)) |
| 325 | napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]); |
| 326 | |
| 327 | if (intr & MT_INT_RX(MT_RXQ_TRI) && MT_RXQ_VALID(MT_RXQ_TRI)) |
| 328 | napi_schedule(&dev->mt76.napi[MT_RXQ_TRI]); |
| 329 | |
| 330 | if (intr & MT_INT_RX(MT_RXQ_TRI_WA) && MT_RXQ_VALID(MT_RXQ_TRI_WA)) |
| 331 | napi_schedule(&dev->mt76.napi[MT_RXQ_TRI_WA]); |
| 332 | |
| 333 | if (intr & MT_INT_MCU_CMD) { |
| 334 | u32 val = mt76_rr(dev, MT_MCU_CMD); |
| 335 | |
| 336 | mt76_wr(dev, MT_MCU_CMD, val); |
| 337 | if (val & MT_MCU_CMD_ERROR_MASK) { |
| 338 | dev->reset_state = val; |
| 339 | ieee80211_queue_work(mt76_hw(dev), &dev->reset_work); |
| 340 | wake_up(&dev->reset_wait); |
| 341 | } |
| 342 | } |
| 343 | } |
| 344 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 345 | irqreturn_t besra_irq_handler(int irq, void *dev_instance) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 346 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 347 | struct besra_dev *dev = dev_instance; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 348 | |
| 349 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 350 | if (dev->hif2) |
| 351 | mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 352 | |
| 353 | if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) |
| 354 | return IRQ_NONE; |
| 355 | |
| 356 | tasklet_schedule(&dev->irq_tasklet); |
| 357 | |
| 358 | return IRQ_HANDLED; |
| 359 | } |
| 360 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 361 | struct besra_dev *besra_mmio_probe(struct device *pdev, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 362 | void __iomem *mem_base, u32 device_id) |
| 363 | { |
| 364 | static const struct mt76_driver_ops drv_ops = { |
| 365 | /* txwi_size = txd size + txp size */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 366 | .txwi_size = MT_TXD_SIZE + sizeof(struct besra_txp), |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 367 | .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ, |
| 368 | .survey_flags = SURVEY_INFO_TIME_TX | |
| 369 | SURVEY_INFO_TIME_RX | |
| 370 | SURVEY_INFO_TIME_BSS_RX, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 371 | .token_size = BESRA_TOKEN_SIZE, |
| 372 | .tx_prepare_skb = besra_tx_prepare_skb, |
| 373 | .tx_complete_skb = besra_tx_complete_skb, |
| 374 | .rx_skb = besra_queue_rx_skb, |
| 375 | .rx_check = besra_rx_check, |
| 376 | .rx_poll_complete = besra_rx_poll_complete, |
| 377 | .sta_ps = besra_sta_ps, |
| 378 | .sta_add = besra_mac_sta_add, |
| 379 | .sta_remove = besra_mac_sta_remove, |
| 380 | .update_survey = besra_update_channel, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 381 | }; |
| 382 | struct ieee80211_ops *ops; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 383 | struct besra_dev *dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 384 | struct mt76_dev *mdev; |
| 385 | int ret; |
| 386 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 387 | ops = devm_kmemdup(pdev, &besra_ops, sizeof(besra_ops), GFP_KERNEL); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 388 | if (!ops) |
| 389 | return ERR_PTR(-ENOMEM); |
| 390 | |
| 391 | mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops); |
| 392 | if (!mdev) |
| 393 | return ERR_PTR(-ENOMEM); |
| 394 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 395 | dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 396 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 397 | ret = besra_mmio_init(mdev, mem_base, device_id); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 398 | if (ret) |
| 399 | goto error; |
| 400 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 401 | tasklet_setup(&dev->irq_tasklet, besra_irq_tasklet); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 402 | |
| 403 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 404 | |
| 405 | return dev; |
| 406 | |
| 407 | error: |
| 408 | mt76_free_device(&dev->mt76); |
| 409 | |
| 410 | return ERR_PTR(ret); |
| 411 | } |
| 412 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 413 | static int __init besra_init(void) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 414 | { |
| 415 | int ret; |
| 416 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 417 | ret = pci_register_driver(&besra_hif_driver); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 418 | if (ret) |
| 419 | return ret; |
| 420 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 421 | ret = pci_register_driver(&besra_pci_driver); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 422 | if (ret) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 423 | pci_unregister_driver(&besra_hif_driver); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 424 | |
| 425 | return ret; |
| 426 | } |
| 427 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 428 | static void __exit besra_exit(void) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 429 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 430 | pci_unregister_driver(&besra_pci_driver); |
| 431 | pci_unregister_driver(&besra_hif_driver); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 432 | } |
| 433 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 434 | module_init(besra_init); |
| 435 | module_exit(besra_exit); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 436 | MODULE_LICENSE("Dual BSD/GPL"); |