developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
| 4 | #include <linux/etherdevice.h> |
| 5 | #include <linux/timekeeping.h> |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6 | #include "besra.h" |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7 | #include "../dma.h" |
| 8 | #include "mac.h" |
| 9 | #include "mcu.h" |
| 10 | |
| 11 | #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) |
| 12 | |
| 13 | #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) |
| 14 | #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ |
| 15 | IEEE80211_RADIOTAP_HE_##f) |
| 16 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 17 | static const struct besra_dfs_radar_spec etsi_radar_specs = { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 18 | .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, |
| 19 | .radar_pattern = { |
| 20 | [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, |
| 21 | [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, |
| 22 | [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, |
| 23 | [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, |
| 24 | [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, |
| 25 | [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, |
| 26 | [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, |
| 27 | [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, |
| 28 | }, |
| 29 | }; |
| 30 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 31 | static const struct besra_dfs_radar_spec fcc_radar_specs = { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 32 | .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, |
| 33 | .radar_pattern = { |
| 34 | [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, |
| 35 | [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, |
| 36 | [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, |
| 37 | [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, |
| 38 | [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, |
| 39 | }, |
| 40 | }; |
| 41 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 42 | static const struct besra_dfs_radar_spec jp_radar_specs = { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 43 | .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, |
| 44 | .radar_pattern = { |
| 45 | [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, |
| 46 | [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, |
| 47 | [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, |
| 48 | [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, |
| 49 | [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, |
| 50 | [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, |
| 51 | [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, |
| 52 | [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, |
| 53 | }, |
| 54 | }; |
| 55 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 56 | static struct mt76_wcid *besra_rx_get_wcid(struct besra_dev *dev, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 57 | u16 idx, bool unicast) |
| 58 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 59 | struct besra_sta *sta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 60 | struct mt76_wcid *wcid; |
| 61 | |
| 62 | if (idx >= ARRAY_SIZE(dev->mt76.wcid)) |
| 63 | return NULL; |
| 64 | |
| 65 | wcid = rcu_dereference(dev->mt76.wcid[idx]); |
| 66 | if (unicast || !wcid) |
| 67 | return wcid; |
| 68 | |
| 69 | if (!wcid->sta) |
| 70 | return NULL; |
| 71 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 72 | sta = container_of(wcid, struct besra_sta, wcid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 73 | if (!sta->vif) |
| 74 | return NULL; |
| 75 | |
| 76 | return &sta->vif->sta.wcid; |
| 77 | } |
| 78 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 79 | void besra_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 80 | { |
| 81 | } |
| 82 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 83 | bool besra_mac_wtbl_update(struct besra_dev *dev, int idx, u32 mask) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 84 | { |
| 85 | mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, |
| 86 | FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); |
| 87 | |
| 88 | return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, |
| 89 | 0, 5000); |
| 90 | } |
| 91 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 92 | u32 besra_mac_wtbl_lmac_addr(struct besra_dev *dev, u16 wcid, u8 dw) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 93 | { |
| 94 | mt76_wr(dev, MT_WTBLON_TOP_WDUCR, |
| 95 | FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); |
| 96 | |
| 97 | return MT_WTBL_LMAC_OFFS(wcid, dw); |
| 98 | } |
| 99 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 100 | static void besra_mac_sta_poll(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 101 | { |
| 102 | static const u8 ac_to_tid[] = { |
| 103 | [IEEE80211_AC_BE] = 0, |
| 104 | [IEEE80211_AC_BK] = 1, |
| 105 | [IEEE80211_AC_VI] = 4, |
| 106 | [IEEE80211_AC_VO] = 6 |
| 107 | }; |
| 108 | struct ieee80211_sta *sta; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 109 | struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 110 | struct rate_info *rate; |
| 111 | u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; |
| 112 | LIST_HEAD(sta_poll_list); |
| 113 | int i; |
| 114 | |
| 115 | spin_lock_bh(&dev->sta_poll_lock); |
| 116 | list_splice_init(&dev->sta_poll_list, &sta_poll_list); |
| 117 | spin_unlock_bh(&dev->sta_poll_lock); |
| 118 | |
| 119 | rcu_read_lock(); |
| 120 | |
| 121 | while (true) { |
| 122 | bool clear = false; |
| 123 | u32 addr, val; |
| 124 | u16 idx; |
| 125 | u8 bw; |
| 126 | |
| 127 | spin_lock_bh(&dev->sta_poll_lock); |
| 128 | if (list_empty(&sta_poll_list)) { |
| 129 | spin_unlock_bh(&dev->sta_poll_lock); |
| 130 | break; |
| 131 | } |
| 132 | msta = list_first_entry(&sta_poll_list, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 133 | struct besra_sta, poll_list); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 134 | list_del_init(&msta->poll_list); |
| 135 | spin_unlock_bh(&dev->sta_poll_lock); |
| 136 | |
| 137 | idx = msta->wcid.idx; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 138 | addr = besra_mac_wtbl_lmac_addr(dev, idx, 20); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 139 | |
| 140 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
| 141 | u32 tx_last = msta->airtime_ac[i]; |
| 142 | u32 rx_last = msta->airtime_ac[i + 4]; |
| 143 | |
| 144 | msta->airtime_ac[i] = mt76_rr(dev, addr); |
| 145 | msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); |
| 146 | |
| 147 | tx_time[i] = msta->airtime_ac[i] - tx_last; |
| 148 | rx_time[i] = msta->airtime_ac[i + 4] - rx_last; |
| 149 | |
| 150 | if ((tx_last | rx_last) & BIT(30)) |
| 151 | clear = true; |
| 152 | |
| 153 | addr += 8; |
| 154 | } |
| 155 | |
| 156 | if (clear) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 157 | besra_mac_wtbl_update(dev, idx, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 158 | MT_WTBL_UPDATE_ADM_COUNT_CLEAR); |
| 159 | memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); |
| 160 | } |
| 161 | |
| 162 | if (!msta->wcid.sta) |
| 163 | continue; |
| 164 | |
| 165 | sta = container_of((void *)msta, struct ieee80211_sta, |
| 166 | drv_priv); |
| 167 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
| 168 | u8 q = mt76_connac_lmac_mapping(i); |
| 169 | u32 tx_cur = tx_time[q]; |
| 170 | u32 rx_cur = rx_time[q]; |
| 171 | u8 tid = ac_to_tid[i]; |
| 172 | |
| 173 | if (!tx_cur && !rx_cur) |
| 174 | continue; |
| 175 | |
| 176 | ieee80211_sta_register_airtime(sta, tid, tx_cur, |
| 177 | rx_cur); |
| 178 | } |
| 179 | |
| 180 | /* |
| 181 | * We don't support reading GI info from txs packets. |
| 182 | * For accurate tx status reporting and AQL improvement, |
| 183 | * we need to make sure that flags match so polling GI |
| 184 | * from per-sta counters directly. |
| 185 | */ |
| 186 | rate = &msta->wcid.rate; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 187 | addr = besra_mac_wtbl_lmac_addr(dev, idx, 6); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 188 | val = mt76_rr(dev, addr); |
| 189 | |
| 190 | switch (rate->bw) { |
| 191 | case RATE_INFO_BW_160: |
| 192 | bw = IEEE80211_STA_RX_BW_160; |
| 193 | break; |
| 194 | case RATE_INFO_BW_80: |
| 195 | bw = IEEE80211_STA_RX_BW_80; |
| 196 | break; |
| 197 | case RATE_INFO_BW_40: |
| 198 | bw = IEEE80211_STA_RX_BW_40; |
| 199 | break; |
| 200 | default: |
| 201 | bw = IEEE80211_STA_RX_BW_20; |
| 202 | break; |
| 203 | } |
| 204 | |
| 205 | if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { |
| 206 | u8 offs = 24 + 2 * bw; |
| 207 | |
| 208 | rate->he_gi = (val & (0x3 << offs)) >> offs; |
| 209 | } else if (rate->flags & |
| 210 | (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { |
| 211 | if (val & BIT(12 + bw)) |
| 212 | rate->flags |= RATE_INFO_FLAGS_SHORT_GI; |
| 213 | else |
| 214 | rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | rcu_read_unlock(); |
| 219 | } |
| 220 | |
| 221 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 222 | besra_mac_decode_he_radiotap_ru(struct mt76_rx_status *status, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 223 | struct ieee80211_radiotap_he *he, |
| 224 | __le32 *rxv) |
| 225 | { |
| 226 | u32 ru_h, ru_l; |
| 227 | u8 ru, offs = 0; |
| 228 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 229 | ru_l = le32_get_bits(rxv[0], MT_PRXV_HE_RU_ALLOC_L); |
| 230 | ru_h = le32_get_bits(rxv[1], MT_PRXV_HE_RU_ALLOC_H); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 231 | ru = (u8)(ru_l | ru_h << 4); |
| 232 | |
| 233 | status->bw = RATE_INFO_BW_HE_RU; |
| 234 | |
| 235 | switch (ru) { |
| 236 | case 0 ... 36: |
| 237 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26; |
| 238 | offs = ru; |
| 239 | break; |
| 240 | case 37 ... 52: |
| 241 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52; |
| 242 | offs = ru - 37; |
| 243 | break; |
| 244 | case 53 ... 60: |
| 245 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; |
| 246 | offs = ru - 53; |
| 247 | break; |
| 248 | case 61 ... 64: |
| 249 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242; |
| 250 | offs = ru - 61; |
| 251 | break; |
| 252 | case 65 ... 66: |
| 253 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484; |
| 254 | offs = ru - 65; |
| 255 | break; |
| 256 | case 67: |
| 257 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996; |
| 258 | break; |
| 259 | case 68: |
| 260 | status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; |
| 261 | break; |
| 262 | } |
| 263 | |
| 264 | he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); |
| 265 | he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) | |
| 266 | le16_encode_bits(offs, |
| 267 | IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET); |
| 268 | } |
| 269 | |
| 270 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 271 | besra_mac_decode_he_mu_radiotap(struct sk_buff *skb, __le32 *rxv) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 272 | { |
| 273 | struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; |
| 274 | static const struct ieee80211_radiotap_he_mu mu_known = { |
| 275 | .flags1 = HE_BITS(MU_FLAGS1_SIG_B_MCS_KNOWN) | |
| 276 | HE_BITS(MU_FLAGS1_SIG_B_DCM_KNOWN) | |
| 277 | HE_BITS(MU_FLAGS1_CH1_RU_KNOWN) | |
| 278 | HE_BITS(MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN), |
| 279 | .flags2 = HE_BITS(MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN), |
| 280 | }; |
| 281 | struct ieee80211_radiotap_he_mu *he_mu = NULL; |
| 282 | |
| 283 | status->flag |= RX_FLAG_RADIOTAP_HE_MU; |
| 284 | |
| 285 | he_mu = skb_push(skb, sizeof(mu_known)); |
| 286 | memcpy(he_mu, &mu_known, sizeof(mu_known)); |
| 287 | |
| 288 | #define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f) |
| 289 | |
| 290 | he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_MCS, status->rate_idx); |
| 291 | if (status->he_dcm) |
| 292 | he_mu->flags1 |= MU_PREP(FLAGS1_SIG_B_DCM, status->he_dcm); |
| 293 | |
| 294 | he_mu->flags2 |= MU_PREP(FLAGS2_BW_FROM_SIG_A_BW, status->bw) | |
| 295 | MU_PREP(FLAGS2_SIG_B_SYMS_USERS, |
| 296 | le32_get_bits(rxv[2], MT_CRXV_HE_NUM_USER)); |
| 297 | |
| 298 | he_mu->ru_ch1[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU0); |
| 299 | |
| 300 | if (status->bw >= RATE_INFO_BW_40) { |
| 301 | he_mu->flags1 |= HE_BITS(MU_FLAGS1_CH2_RU_KNOWN); |
| 302 | he_mu->ru_ch2[0] = le32_get_bits(rxv[3], MT_CRXV_HE_RU1); |
| 303 | } |
| 304 | |
| 305 | if (status->bw >= RATE_INFO_BW_80) { |
| 306 | he_mu->ru_ch1[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU2); |
| 307 | he_mu->ru_ch2[1] = le32_get_bits(rxv[3], MT_CRXV_HE_RU3); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 312 | besra_mac_decode_he_radiotap(struct sk_buff *skb, __le32 *rxv, u8 mode) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 313 | { |
| 314 | struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; |
| 315 | static const struct ieee80211_radiotap_he known = { |
| 316 | .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) | |
| 317 | HE_BITS(DATA1_DATA_DCM_KNOWN) | |
| 318 | HE_BITS(DATA1_STBC_KNOWN) | |
| 319 | HE_BITS(DATA1_CODING_KNOWN) | |
| 320 | HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) | |
| 321 | HE_BITS(DATA1_DOPPLER_KNOWN) | |
| 322 | HE_BITS(DATA1_SPTL_REUSE_KNOWN) | |
| 323 | HE_BITS(DATA1_BSS_COLOR_KNOWN), |
| 324 | .data2 = HE_BITS(DATA2_GI_KNOWN) | |
| 325 | HE_BITS(DATA2_TXBF_KNOWN) | |
| 326 | HE_BITS(DATA2_PE_DISAMBIG_KNOWN) | |
| 327 | HE_BITS(DATA2_TXOP_KNOWN), |
| 328 | }; |
| 329 | struct ieee80211_radiotap_he *he = NULL; |
| 330 | u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1; |
| 331 | |
| 332 | status->flag |= RX_FLAG_RADIOTAP_HE; |
| 333 | |
| 334 | he = skb_push(skb, sizeof(known)); |
| 335 | memcpy(he, &known, sizeof(known)); |
| 336 | |
| 337 | he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) | |
| 338 | HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]); |
| 339 | he->data4 = HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]); |
| 340 | he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) | |
| 341 | le16_encode_bits(ltf_size, |
| 342 | IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE); |
| 343 | if (le32_to_cpu(rxv[0]) & MT_PRXV_TXBF) |
| 344 | he->data5 |= HE_BITS(DATA5_TXBF); |
| 345 | he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) | |
| 346 | HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]); |
| 347 | |
| 348 | switch (mode) { |
| 349 | case MT_PHY_TYPE_HE_SU: |
| 350 | he->data1 |= HE_BITS(DATA1_FORMAT_SU) | |
| 351 | HE_BITS(DATA1_UL_DL_KNOWN) | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 352 | HE_BITS(DATA1_BEAM_CHANGE_KNOWN) | |
| 353 | HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 354 | |
| 355 | he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) | |
| 356 | HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); |
| 357 | break; |
| 358 | case MT_PHY_TYPE_HE_EXT_SU: |
| 359 | he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 360 | HE_BITS(DATA1_UL_DL_KNOWN) | |
| 361 | HE_BITS(DATA1_BW_RU_ALLOC_KNOWN); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 362 | |
| 363 | he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); |
| 364 | break; |
| 365 | case MT_PHY_TYPE_HE_MU: |
| 366 | he->data1 |= HE_BITS(DATA1_FORMAT_MU) | |
| 367 | HE_BITS(DATA1_UL_DL_KNOWN); |
| 368 | |
| 369 | he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]); |
| 370 | he->data4 |= HE_PREP(DATA4_MU_STA_ID, MU_AID, rxv[7]); |
| 371 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 372 | besra_mac_decode_he_radiotap_ru(status, he, rxv); |
| 373 | besra_mac_decode_he_mu_radiotap(skb, rxv); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 374 | break; |
| 375 | case MT_PHY_TYPE_HE_TB: |
| 376 | he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) | |
| 377 | HE_BITS(DATA1_SPTL_REUSE2_KNOWN) | |
| 378 | HE_BITS(DATA1_SPTL_REUSE3_KNOWN) | |
| 379 | HE_BITS(DATA1_SPTL_REUSE4_KNOWN); |
| 380 | |
| 381 | he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) | |
| 382 | HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) | |
| 383 | HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) | |
| 384 | HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]); |
| 385 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 386 | besra_mac_decode_he_radiotap_ru(status, he, rxv); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 387 | break; |
| 388 | default: |
| 389 | break; |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | /* The HW does not translate the mac header to 802.3 for mesh point */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 394 | static int besra_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 395 | { |
| 396 | struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; |
| 397 | struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 398 | struct besra_sta *msta = (struct besra_sta *)status->wcid; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 399 | __le32 *rxd = (__le32 *)skb->data; |
| 400 | struct ieee80211_sta *sta; |
| 401 | struct ieee80211_vif *vif; |
| 402 | struct ieee80211_hdr hdr; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 403 | u16 frame_control; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 404 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 405 | if (le32_get_bits(rxd[3], MT_RXD3_NORMAL_ADDR_TYPE) != |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 406 | MT_RXD3_NORMAL_U2M) |
| 407 | return -EINVAL; |
| 408 | |
| 409 | if (!(le32_to_cpu(rxd[1]) & MT_RXD1_NORMAL_GROUP_4)) |
| 410 | return -EINVAL; |
| 411 | |
| 412 | if (!msta || !msta->vif) |
| 413 | return -EINVAL; |
| 414 | |
| 415 | sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); |
| 416 | vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); |
| 417 | |
| 418 | /* store the info from RXD and ethhdr to avoid being overridden */ |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 419 | frame_control = le32_get_bits(rxd[6], MT_RXD6_FRAME_CONTROL); |
| 420 | hdr.frame_control = cpu_to_le16(frame_control); |
| 421 | hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_SEQ_CTRL)); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 422 | hdr.duration_id = 0; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 423 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 424 | ether_addr_copy(hdr.addr1, vif->addr); |
| 425 | ether_addr_copy(hdr.addr2, sta->addr); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 426 | switch (frame_control & (IEEE80211_FCTL_TODS | |
| 427 | IEEE80211_FCTL_FROMDS)) { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 428 | case 0: |
| 429 | ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); |
| 430 | break; |
| 431 | case IEEE80211_FCTL_FROMDS: |
| 432 | ether_addr_copy(hdr.addr3, eth_hdr->h_source); |
| 433 | break; |
| 434 | case IEEE80211_FCTL_TODS: |
| 435 | ether_addr_copy(hdr.addr3, eth_hdr->h_dest); |
| 436 | break; |
| 437 | case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: |
| 438 | ether_addr_copy(hdr.addr3, eth_hdr->h_dest); |
| 439 | ether_addr_copy(hdr.addr4, eth_hdr->h_source); |
| 440 | break; |
| 441 | default: |
| 442 | break; |
| 443 | } |
| 444 | |
| 445 | skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); |
| 446 | if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || |
| 447 | eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) |
| 448 | ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 449 | else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 450 | ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); |
| 451 | else |
| 452 | skb_pull(skb, 2); |
| 453 | |
| 454 | if (ieee80211_has_order(hdr.frame_control)) |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 455 | memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[9], |
| 456 | IEEE80211_HT_CTL_LEN); |
| 457 | if (ieee80211_is_data_qos(hdr.frame_control)) { |
| 458 | __le16 qos_ctrl; |
| 459 | |
| 460 | qos_ctrl = cpu_to_le16(le32_get_bits(rxd[8], MT_RXD8_QOS_CTL)); |
| 461 | memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, |
| 462 | IEEE80211_QOS_CTL_LEN); |
| 463 | } |
| 464 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 465 | if (ieee80211_has_a4(hdr.frame_control)) |
| 466 | memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); |
| 467 | else |
| 468 | memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); |
| 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 474 | besra_mac_fill_rx_rate(struct besra_dev *dev, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 475 | struct mt76_rx_status *status, |
| 476 | struct ieee80211_supported_band *sband, |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 477 | __le32 *rxv, u8 *mode) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 478 | { |
| 479 | u32 v0, v2; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 480 | u8 stbc, gi, bw, dcm, nss; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 481 | int i, idx; |
| 482 | bool cck = false; |
| 483 | |
| 484 | v0 = le32_to_cpu(rxv[0]); |
| 485 | v2 = le32_to_cpu(rxv[2]); |
| 486 | |
| 487 | idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); |
| 488 | nss = FIELD_GET(MT_PRXV_NSTS, v0) + 1; |
| 489 | |
| 490 | stbc = FIELD_GET(MT_PRXV_HT_STBC, v2); |
| 491 | gi = FIELD_GET(MT_PRXV_HT_SHORT_GI, v2); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 492 | *mode = FIELD_GET(MT_PRXV_TX_MODE, v2); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 493 | dcm = FIELD_GET(MT_PRXV_DCM, v2); |
| 494 | bw = FIELD_GET(MT_PRXV_FRAME_MODE, v2); |
| 495 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 496 | switch (*mode) { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 497 | case MT_PHY_TYPE_CCK: |
| 498 | cck = true; |
| 499 | fallthrough; |
| 500 | case MT_PHY_TYPE_OFDM: |
| 501 | i = mt76_get_rate(&dev->mt76, sband, i, cck); |
| 502 | break; |
| 503 | case MT_PHY_TYPE_HT_GF: |
| 504 | case MT_PHY_TYPE_HT: |
| 505 | status->encoding = RX_ENC_HT; |
| 506 | if (gi) |
| 507 | status->enc_flags |= RX_ENC_FLAG_SHORT_GI; |
| 508 | if (i > 31) |
| 509 | return -EINVAL; |
| 510 | break; |
| 511 | case MT_PHY_TYPE_VHT: |
| 512 | status->nss = nss; |
| 513 | status->encoding = RX_ENC_VHT; |
| 514 | if (gi) |
| 515 | status->enc_flags |= RX_ENC_FLAG_SHORT_GI; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 516 | if (i > 11) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 517 | return -EINVAL; |
| 518 | break; |
| 519 | case MT_PHY_TYPE_HE_MU: |
| 520 | case MT_PHY_TYPE_HE_SU: |
| 521 | case MT_PHY_TYPE_HE_EXT_SU: |
| 522 | case MT_PHY_TYPE_HE_TB: |
| 523 | status->nss = nss; |
| 524 | status->encoding = RX_ENC_HE; |
| 525 | i &= GENMASK(3, 0); |
| 526 | |
| 527 | if (gi <= NL80211_RATE_INFO_HE_GI_3_2) |
| 528 | status->he_gi = gi; |
| 529 | |
| 530 | status->he_dcm = dcm; |
| 531 | break; |
| 532 | default: |
| 533 | return -EINVAL; |
| 534 | } |
| 535 | status->rate_idx = i; |
| 536 | |
| 537 | switch (bw) { |
| 538 | case IEEE80211_STA_RX_BW_20: |
| 539 | break; |
| 540 | case IEEE80211_STA_RX_BW_40: |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 541 | if (*mode & MT_PHY_TYPE_HE_EXT_SU && |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 542 | (idx & MT_PRXV_TX_ER_SU_106T)) { |
| 543 | status->bw = RATE_INFO_BW_HE_RU; |
| 544 | status->he_ru = |
| 545 | NL80211_RATE_INFO_HE_RU_ALLOC_106; |
| 546 | } else { |
| 547 | status->bw = RATE_INFO_BW_40; |
| 548 | } |
| 549 | break; |
| 550 | case IEEE80211_STA_RX_BW_80: |
| 551 | status->bw = RATE_INFO_BW_80; |
| 552 | break; |
| 553 | case IEEE80211_STA_RX_BW_160: |
| 554 | status->bw = RATE_INFO_BW_160; |
| 555 | break; |
| 556 | default: |
| 557 | return -EINVAL; |
| 558 | } |
| 559 | |
| 560 | status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 561 | if (*mode < MT_PHY_TYPE_HE_SU && gi) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 562 | status->enc_flags |= RX_ENC_FLAG_SHORT_GI; |
| 563 | |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 568 | besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 569 | { |
| 570 | struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; |
| 571 | struct mt76_phy *mphy = &dev->mt76.phy; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 572 | struct besra_phy *phy = &dev->phy; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 573 | struct ieee80211_supported_band *sband; |
| 574 | __le32 *rxd = (__le32 *)skb->data; |
| 575 | __le32 *rxv = NULL; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 576 | u32 rxd0 = le32_to_cpu(rxd[0]); |
| 577 | u32 rxd1 = le32_to_cpu(rxd[1]); |
| 578 | u32 rxd2 = le32_to_cpu(rxd[2]); |
| 579 | u32 rxd3 = le32_to_cpu(rxd[3]); |
| 580 | u32 rxd4 = le32_to_cpu(rxd[4]); |
| 581 | u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; |
| 582 | bool unicast, insert_ccmp_hdr = false; |
| 583 | u8 remove_pad, amsdu_info; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 584 | u8 mode = 0, qos_ctl = 0; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 585 | bool hdr_trans; |
| 586 | u16 hdr_gap; |
| 587 | u16 seq_ctrl = 0; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 588 | __le16 fc = 0; |
| 589 | int idx; |
| 590 | u8 band_idx; |
| 591 | |
| 592 | memset(status, 0, sizeof(*status)); |
| 593 | |
| 594 | band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); |
| 595 | mphy = mt76_dev_phy_by_band(&dev->mt76, band_idx); |
| 596 | phy = mphy->priv; |
| 597 | status->phy_idx = mt76_get_phy_id(mphy); |
| 598 | |
| 599 | if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) |
| 600 | return -EINVAL; |
| 601 | |
| 602 | if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) |
| 603 | return -EINVAL; |
| 604 | |
| 605 | hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; |
| 606 | if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) |
| 607 | return -EINVAL; |
| 608 | |
| 609 | /* ICV error or CCMP/BIP/WPI MIC error */ |
| 610 | if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) |
| 611 | status->flag |= RX_FLAG_ONLY_MONITOR; |
| 612 | |
| 613 | unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; |
| 614 | idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 615 | status->wcid = besra_rx_get_wcid(dev, idx, unicast); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 616 | |
| 617 | if (status->wcid) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 618 | struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 619 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 620 | msta = container_of(status->wcid, struct besra_sta, wcid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 621 | spin_lock_bh(&dev->sta_poll_lock); |
| 622 | if (list_empty(&msta->poll_list)) |
| 623 | list_add_tail(&msta->poll_list, &dev->sta_poll_list); |
| 624 | spin_unlock_bh(&dev->sta_poll_lock); |
| 625 | } |
| 626 | |
| 627 | status->freq = mphy->chandef.chan->center_freq; |
| 628 | status->band = mphy->chandef.chan->band; |
| 629 | if (status->band == NL80211_BAND_5GHZ) |
| 630 | sband = &mphy->sband_5g.sband; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 631 | else if (status->band == NL80211_BAND_6GHZ) |
| 632 | sband = &mphy->sband_6g.sband; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 633 | else |
| 634 | sband = &mphy->sband_2g.sband; |
| 635 | |
| 636 | if (!sband->channels) |
| 637 | return -EINVAL; |
| 638 | |
| 639 | if ((rxd0 & csum_mask) == csum_mask) |
| 640 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 641 | |
| 642 | if (rxd1 & MT_RXD3_NORMAL_FCS_ERR) |
| 643 | status->flag |= RX_FLAG_FAILED_FCS_CRC; |
| 644 | |
| 645 | if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) |
| 646 | status->flag |= RX_FLAG_MMIC_ERROR; |
| 647 | |
| 648 | if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && |
| 649 | !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { |
| 650 | status->flag |= RX_FLAG_DECRYPTED; |
| 651 | status->flag |= RX_FLAG_IV_STRIPPED; |
| 652 | status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; |
| 653 | } |
| 654 | |
| 655 | remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); |
| 656 | |
| 657 | if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) |
| 658 | return -EINVAL; |
| 659 | |
| 660 | rxd += 8; |
| 661 | if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { |
| 662 | u32 v0 = le32_to_cpu(rxd[0]); |
| 663 | u32 v2 = le32_to_cpu(rxd[2]); |
| 664 | |
| 665 | fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); |
| 666 | qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); |
| 667 | seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); |
| 668 | |
| 669 | rxd += 4; |
| 670 | if ((u8 *)rxd - skb->data >= skb->len) |
| 671 | return -EINVAL; |
| 672 | } |
| 673 | |
| 674 | if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { |
| 675 | u8 *data = (u8 *)rxd; |
| 676 | |
| 677 | if (status->flag & RX_FLAG_DECRYPTED) { |
| 678 | switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { |
| 679 | case MT_CIPHER_AES_CCMP: |
| 680 | case MT_CIPHER_CCMP_CCX: |
| 681 | case MT_CIPHER_CCMP_256: |
| 682 | insert_ccmp_hdr = |
| 683 | FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); |
| 684 | fallthrough; |
| 685 | case MT_CIPHER_TKIP: |
| 686 | case MT_CIPHER_TKIP_NO_MIC: |
| 687 | case MT_CIPHER_GCMP: |
| 688 | case MT_CIPHER_GCMP_256: |
| 689 | status->iv[0] = data[5]; |
| 690 | status->iv[1] = data[4]; |
| 691 | status->iv[2] = data[3]; |
| 692 | status->iv[3] = data[2]; |
| 693 | status->iv[4] = data[1]; |
| 694 | status->iv[5] = data[0]; |
| 695 | break; |
| 696 | default: |
| 697 | break; |
| 698 | } |
| 699 | } |
| 700 | rxd += 4; |
| 701 | if ((u8 *)rxd - skb->data >= skb->len) |
| 702 | return -EINVAL; |
| 703 | } |
| 704 | |
| 705 | if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { |
| 706 | status->timestamp = le32_to_cpu(rxd[0]); |
| 707 | status->flag |= RX_FLAG_MACTIME_START; |
| 708 | |
| 709 | if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { |
| 710 | status->flag |= RX_FLAG_AMPDU_DETAILS; |
| 711 | |
| 712 | /* all subframes of an A-MPDU have the same timestamp */ |
| 713 | if (phy->rx_ampdu_ts != status->timestamp) { |
| 714 | if (!++phy->ampdu_ref) |
| 715 | phy->ampdu_ref++; |
| 716 | } |
| 717 | phy->rx_ampdu_ts = status->timestamp; |
| 718 | |
| 719 | status->ampdu_ref = phy->ampdu_ref; |
| 720 | } |
| 721 | |
| 722 | rxd += 4; |
| 723 | if ((u8 *)rxd - skb->data >= skb->len) |
| 724 | return -EINVAL; |
| 725 | } |
| 726 | |
| 727 | /* RXD Group 3 - P-RXV */ |
| 728 | if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { |
| 729 | u32 v3; |
| 730 | int ret; |
| 731 | |
| 732 | rxv = rxd; |
| 733 | rxd += 4; |
| 734 | if ((u8 *)rxd - skb->data >= skb->len) |
| 735 | return -EINVAL; |
| 736 | |
| 737 | v3 = le32_to_cpu(rxv[3]); |
| 738 | |
| 739 | status->chains = mphy->antenna_mask; |
| 740 | status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v3); |
| 741 | status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v3); |
| 742 | status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v3); |
| 743 | status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v3); |
| 744 | |
| 745 | /* RXD Group 5 - C-RXV */ |
| 746 | if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { |
| 747 | rxd += 24; |
| 748 | if ((u8 *)rxd - skb->data >= skb->len) |
| 749 | return -EINVAL; |
| 750 | } |
| 751 | |
| 752 | /* TODO: parse rx rate from rxv */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 753 | ret = besra_mac_fill_rx_rate(dev, status, sband, rxv, &mode); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 754 | if (ret < 0) |
| 755 | return ret; |
| 756 | } |
| 757 | |
| 758 | amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); |
| 759 | status->amsdu = !!amsdu_info; |
| 760 | if (status->amsdu) { |
| 761 | status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; |
| 762 | status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; |
| 763 | } |
| 764 | |
| 765 | hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; |
| 766 | if (hdr_trans && ieee80211_has_morefrags(fc)) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 767 | if (besra_reverse_frag0_hdr_trans(skb, hdr_gap)) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 768 | return -EINVAL; |
| 769 | hdr_trans = false; |
| 770 | } else { |
| 771 | int pad_start = 0; |
| 772 | |
| 773 | skb_pull(skb, hdr_gap); |
| 774 | if (!hdr_trans && status->amsdu) { |
| 775 | pad_start = ieee80211_get_hdrlen_from_skb(skb); |
| 776 | } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { |
| 777 | /* |
| 778 | * When header translation failure is indicated, |
| 779 | * the hardware will insert an extra 2-byte field |
| 780 | * containing the data length after the protocol |
| 781 | * type field. |
| 782 | */ |
| 783 | pad_start = 12; |
| 784 | if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) |
| 785 | pad_start += 4; |
| 786 | |
| 787 | if (get_unaligned_be16(skb->data + pad_start) != |
| 788 | skb->len - pad_start - 2) |
| 789 | pad_start = 0; |
| 790 | } |
| 791 | |
| 792 | if (pad_start) { |
| 793 | memmove(skb->data + 2, skb->data, pad_start); |
| 794 | skb_pull(skb, 2); |
| 795 | } |
| 796 | } |
| 797 | |
| 798 | if (!hdr_trans) { |
| 799 | struct ieee80211_hdr *hdr; |
| 800 | |
| 801 | if (insert_ccmp_hdr) { |
| 802 | u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); |
| 803 | |
| 804 | mt76_insert_ccmp_hdr(skb, key_id); |
| 805 | } |
| 806 | |
| 807 | hdr = mt76_skb_get_hdr(skb); |
| 808 | fc = hdr->frame_control; |
| 809 | if (ieee80211_is_data_qos(fc)) { |
| 810 | seq_ctrl = le16_to_cpu(hdr->seq_ctrl); |
| 811 | qos_ctl = *ieee80211_get_qos_ctl(hdr); |
| 812 | } |
| 813 | } else { |
| 814 | status->flag |= RX_FLAG_8023; |
| 815 | } |
| 816 | |
| 817 | if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 818 | besra_mac_decode_he_radiotap(skb, rxv, mode); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 819 | |
| 820 | if (!status->wcid || !ieee80211_is_data_qos(fc)) |
| 821 | return 0; |
| 822 | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 823 | status->aggr = unicast && |
| 824 | !ieee80211_is_qos_nullfunc(fc); |
| 825 | status->qos_ctl = qos_ctl; |
| 826 | status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); |
| 827 | |
| 828 | return 0; |
| 829 | } |
| 830 | |
| 831 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 832 | besra_mac_fill_rx_vector(struct besra_dev *dev, struct sk_buff *skb) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 833 | { |
| 834 | #ifdef CONFIG_NL80211_TESTMODE |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 835 | struct besra_phy *phy = &dev->phy; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 836 | __le32 *rxd = (__le32 *)skb->data; |
| 837 | __le32 *rxv_hdr = rxd + 2; |
| 838 | __le32 *rxv = rxd + 4; |
| 839 | u32 rcpi, ib_rssi, wb_rssi, v20, v21; |
| 840 | u8 phy_idx; |
| 841 | s32 foe; |
| 842 | u8 snr; |
| 843 | int i; |
| 844 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 845 | phy_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); |
| 846 | if (phy_idx == MT_EXT_PHY) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 847 | phy = besra_ext_phy(dev); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 848 | if (!phy) |
| 849 | goto out; |
| 850 | } |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 851 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 852 | if (phy_idx == MT_TRI_PHY) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 853 | phy = besra_tri_phy(dev); |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 854 | if (!phy) |
| 855 | goto out; |
| 856 | } |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 857 | |
| 858 | rcpi = le32_to_cpu(rxv[6]); |
| 859 | ib_rssi = le32_to_cpu(rxv[7]); |
| 860 | wb_rssi = le32_to_cpu(rxv[8]) >> 5; |
| 861 | |
| 862 | for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { |
| 863 | if (i == 3) |
| 864 | wb_rssi = le32_to_cpu(rxv[9]); |
| 865 | |
| 866 | phy->test.last_rcpi[i] = rcpi & 0xff; |
| 867 | phy->test.last_ib_rssi[i] = ib_rssi & 0xff; |
| 868 | phy->test.last_wb_rssi[i] = wb_rssi & 0xff; |
| 869 | } |
| 870 | |
| 871 | v20 = le32_to_cpu(rxv[20]); |
| 872 | v21 = le32_to_cpu(rxv[21]); |
| 873 | |
| 874 | foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | |
| 875 | (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); |
| 876 | |
| 877 | snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; |
| 878 | |
| 879 | phy->test.last_freq_offset = foe; |
| 880 | phy->test.last_snr = snr; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 881 | out: |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 882 | #endif |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 883 | dev_kfree_skb(skb); |
| 884 | } |
| 885 | |
| 886 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 887 | besra_mac_write_txwi_tm(struct besra_phy *phy, __le32 *txwi, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 888 | struct sk_buff *skb) |
| 889 | { |
| 890 | #ifdef CONFIG_NL80211_TESTMODE |
| 891 | struct mt76_testmode_data *td = &phy->mt76->test; |
| 892 | const struct ieee80211_rate *r; |
| 893 | u8 bw, mode, nss = td->tx_rate_nss; |
| 894 | u8 rate_idx = td->tx_rate_idx; |
| 895 | u16 rateval = 0; |
| 896 | u32 val; |
| 897 | bool cck = false; |
| 898 | int band; |
| 899 | |
| 900 | if (skb != phy->mt76->test.tx_skb) |
| 901 | return; |
| 902 | |
| 903 | switch (td->tx_rate_mode) { |
| 904 | case MT76_TM_TX_MODE_HT: |
| 905 | nss = 1 + (rate_idx >> 3); |
| 906 | mode = MT_PHY_TYPE_HT; |
| 907 | break; |
| 908 | case MT76_TM_TX_MODE_VHT: |
| 909 | mode = MT_PHY_TYPE_VHT; |
| 910 | break; |
| 911 | case MT76_TM_TX_MODE_HE_SU: |
| 912 | mode = MT_PHY_TYPE_HE_SU; |
| 913 | break; |
| 914 | case MT76_TM_TX_MODE_HE_EXT_SU: |
| 915 | mode = MT_PHY_TYPE_HE_EXT_SU; |
| 916 | break; |
| 917 | case MT76_TM_TX_MODE_HE_TB: |
| 918 | mode = MT_PHY_TYPE_HE_TB; |
| 919 | break; |
| 920 | case MT76_TM_TX_MODE_HE_MU: |
| 921 | mode = MT_PHY_TYPE_HE_MU; |
| 922 | break; |
| 923 | case MT76_TM_TX_MODE_CCK: |
| 924 | cck = true; |
| 925 | fallthrough; |
| 926 | case MT76_TM_TX_MODE_OFDM: |
| 927 | band = phy->mt76->chandef.chan->band; |
| 928 | if (band == NL80211_BAND_2GHZ && !cck) |
| 929 | rate_idx += 4; |
| 930 | |
| 931 | r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; |
| 932 | val = cck ? r->hw_value_short : r->hw_value; |
| 933 | |
| 934 | mode = val >> 8; |
| 935 | rate_idx = val & 0xff; |
| 936 | break; |
| 937 | default: |
| 938 | mode = MT_PHY_TYPE_OFDM; |
| 939 | break; |
| 940 | } |
| 941 | |
| 942 | switch (phy->mt76->chandef.width) { |
| 943 | case NL80211_CHAN_WIDTH_40: |
| 944 | bw = 1; |
| 945 | break; |
| 946 | case NL80211_CHAN_WIDTH_80: |
| 947 | bw = 2; |
| 948 | break; |
| 949 | case NL80211_CHAN_WIDTH_80P80: |
| 950 | case NL80211_CHAN_WIDTH_160: |
| 951 | bw = 3; |
| 952 | break; |
| 953 | default: |
| 954 | bw = 0; |
| 955 | break; |
| 956 | } |
| 957 | |
| 958 | if (td->tx_rate_stbc && nss == 1) { |
| 959 | nss++; |
| 960 | rateval |= MT_TX_RATE_STBC; |
| 961 | } |
| 962 | |
| 963 | rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | |
| 964 | FIELD_PREP(MT_TX_RATE_MODE, mode) | |
| 965 | FIELD_PREP(MT_TX_RATE_NSS, nss - 1); |
| 966 | |
| 967 | //txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); |
| 968 | |
| 969 | le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); |
| 970 | if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) |
| 971 | txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); |
| 972 | |
| 973 | val = MT_TXD6_BW | |
| 974 | FIELD_PREP(MT_TXD6_BW, bw) | |
| 975 | FIELD_PREP(MT_TXD6_TX_RATE, rateval); // | |
| 976 | // FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); |
| 977 | |
| 978 | /* for HE_SU/HE_EXT_SU PPDU |
| 979 | * - 1x, 2x, 4x LTF + 0.8us GI |
| 980 | * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI |
| 981 | * for HE_MU PPDU |
| 982 | * - 2x, 4x LTF + 0.8us GI |
| 983 | * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI |
| 984 | * for HE_TB PPDU |
| 985 | * - 1x, 2x LTF + 1.6us GI |
| 986 | * - 4x LTF + 3.2us GI |
| 987 | */ |
| 988 | // if (mode >= MT_PHY_TYPE_HE_SU) |
| 989 | // val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); |
| 990 | |
| 991 | // if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) |
| 992 | // val |= MT_TXD6_LDPC; |
| 993 | |
| 994 | txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); |
| 995 | txwi[6] |= cpu_to_le32(val); |
| 996 | // txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, |
| 997 | // phy->test.spe_idx)); |
| 998 | #endif |
| 999 | } |
| 1000 | |
| 1001 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1002 | besra_mac_write_txwi_8023(struct besra_dev *dev, __le32 *txwi, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1003 | struct sk_buff *skb, struct mt76_wcid *wcid) |
| 1004 | { |
| 1005 | |
| 1006 | u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; |
| 1007 | u8 fc_type, fc_stype; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1008 | u16 ethertype; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1009 | bool wmm = false; |
| 1010 | u32 val; |
| 1011 | |
| 1012 | if (wcid->sta) { |
| 1013 | struct ieee80211_sta *sta; |
| 1014 | |
| 1015 | sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv); |
| 1016 | wmm = sta->wme; |
| 1017 | } |
| 1018 | |
| 1019 | val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) | |
| 1020 | FIELD_PREP(MT_TXD1_TID, tid); |
| 1021 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1022 | ethertype = get_unaligned_be16(&skb->data[12]); |
| 1023 | if (ethertype >= ETH_P_802_3_MIN) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1024 | val |= MT_TXD1_ETH_802_3; |
| 1025 | |
| 1026 | txwi[1] |= cpu_to_le32(val); |
| 1027 | |
| 1028 | fc_type = IEEE80211_FTYPE_DATA >> 2; |
| 1029 | fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0; |
| 1030 | |
| 1031 | val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | |
| 1032 | FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); |
| 1033 | |
| 1034 | txwi[2] |= cpu_to_le32(val); |
| 1035 | } |
| 1036 | |
| 1037 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1038 | besra_mac_write_txwi_80211(struct besra_dev *dev, __le32 *txwi, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1039 | struct sk_buff *skb, struct ieee80211_key_conf *key, |
| 1040 | bool *mcast) |
| 1041 | { |
| 1042 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 1043 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; |
| 1044 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 1045 | u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK; |
| 1046 | __le16 fc = hdr->frame_control; |
| 1047 | u8 fc_type, fc_stype; |
| 1048 | u32 val; |
| 1049 | |
| 1050 | *mcast = is_multicast_ether_addr(hdr->addr1); |
| 1051 | |
| 1052 | if (ieee80211_is_action(fc) && |
| 1053 | mgmt->u.action.category == WLAN_CATEGORY_BACK && |
| 1054 | mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) |
| 1055 | tid = MT_TX_ADDBA; |
| 1056 | else if (ieee80211_is_mgmt(hdr->frame_control)) |
| 1057 | tid = MT_TX_NORMAL; |
| 1058 | |
| 1059 | val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | |
| 1060 | FIELD_PREP(MT_TXD1_HDR_INFO, |
| 1061 | ieee80211_get_hdrlen_from_skb(skb) / 2) | |
| 1062 | FIELD_PREP(MT_TXD1_TID, tid); |
| 1063 | |
| 1064 | if (!ieee80211_is_data(fc) || *mcast || |
| 1065 | info->flags & IEEE80211_TX_CTL_USE_MINRATE) |
| 1066 | val |= MT_TXD1_FIXED_RATE; |
| 1067 | |
| 1068 | if (key && *mcast && ieee80211_is_robust_mgmt_frame(skb) && |
| 1069 | key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { |
| 1070 | val |= MT_TXD1_BIP; |
| 1071 | txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME); |
| 1072 | } |
| 1073 | |
| 1074 | txwi[1] |= cpu_to_le32(val); |
| 1075 | |
| 1076 | fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; |
| 1077 | fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; |
| 1078 | |
| 1079 | val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | |
| 1080 | FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype); |
| 1081 | |
| 1082 | txwi[2] |= cpu_to_le32(val); |
| 1083 | |
| 1084 | txwi[3] |= FIELD_PREP(MT_TXD3_BCM, *mcast); |
| 1085 | if (ieee80211_is_beacon(fc)) { |
| 1086 | txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT); |
| 1087 | txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT); |
| 1088 | } |
| 1089 | |
| 1090 | if (info->flags & IEEE80211_TX_CTL_INJECTED) { |
| 1091 | u16 seqno = le16_to_cpu(hdr->seq_ctrl); |
| 1092 | |
| 1093 | if (ieee80211_is_back_req(hdr->frame_control)) { |
| 1094 | struct ieee80211_bar *bar; |
| 1095 | |
| 1096 | bar = (struct ieee80211_bar *)skb->data; |
| 1097 | seqno = le16_to_cpu(bar->start_seq_num); |
| 1098 | } |
| 1099 | |
| 1100 | val = MT_TXD3_SN_VALID | |
| 1101 | FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); |
| 1102 | txwi[3] |= cpu_to_le32(val); |
| 1103 | txwi[3] &= ~cpu_to_le32(MT_TXD3_HW_AMSDU); |
| 1104 | } |
| 1105 | } |
| 1106 | |
| 1107 | static u16 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1108 | besra_mac_tx_rate_val(struct mt76_phy *mphy, struct ieee80211_vif *vif, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1109 | bool beacon, bool mcast) |
| 1110 | { |
| 1111 | u8 mode = 0, band = mphy->chandef.chan->band; |
| 1112 | int rateidx = 0, mcast_rate; |
| 1113 | |
| 1114 | if (beacon) { |
| 1115 | struct cfg80211_bitrate_mask *mask; |
| 1116 | |
| 1117 | mask = &vif->bss_conf.beacon_tx_rate; |
| 1118 | if (hweight16(mask->control[band].he_mcs[0]) == 1) { |
| 1119 | rateidx = ffs(mask->control[band].he_mcs[0]) - 1; |
| 1120 | mode = MT_PHY_TYPE_HE_SU; |
| 1121 | goto out; |
| 1122 | } else if (hweight16(mask->control[band].vht_mcs[0]) == 1) { |
| 1123 | rateidx = ffs(mask->control[band].vht_mcs[0]) - 1; |
| 1124 | mode = MT_PHY_TYPE_VHT; |
| 1125 | goto out; |
| 1126 | } else if (hweight8(mask->control[band].ht_mcs[0]) == 1) { |
| 1127 | rateidx = ffs(mask->control[band].ht_mcs[0]) - 1; |
| 1128 | mode = MT_PHY_TYPE_HT; |
| 1129 | goto out; |
| 1130 | } else if (hweight32(mask->control[band].legacy) == 1) { |
| 1131 | rateidx = ffs(mask->control[band].legacy) - 1; |
| 1132 | goto legacy; |
| 1133 | } |
| 1134 | } |
| 1135 | |
| 1136 | mcast_rate = vif->bss_conf.mcast_rate[band]; |
| 1137 | if (mcast && mcast_rate > 0) |
| 1138 | rateidx = mcast_rate - 1; |
| 1139 | else |
| 1140 | rateidx = ffs(vif->bss_conf.basic_rates) - 1; |
| 1141 | |
| 1142 | legacy: |
| 1143 | rateidx = mt76_calculate_default_rate(mphy, rateidx); |
| 1144 | mode = rateidx >> 8; |
| 1145 | rateidx &= GENMASK(7, 0); |
| 1146 | |
| 1147 | out: |
| 1148 | return FIELD_PREP(MT_TX_RATE_IDX, rateidx) | |
| 1149 | FIELD_PREP(MT_TX_RATE_MODE, mode); |
| 1150 | } |
| 1151 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1152 | void besra_mac_write_txwi(struct besra_dev *dev, __le32 *txwi, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1153 | struct sk_buff *skb, struct mt76_wcid *wcid, int pid, |
| 1154 | struct ieee80211_key_conf *key, bool beacon) |
| 1155 | { |
| 1156 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 1157 | struct ieee80211_vif *vif = info->control.vif; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1158 | struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1159 | struct mt76_phy *mphy = &dev->mphy; |
| 1160 | u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; |
| 1161 | u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0, band_idx = 0; |
| 1162 | bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; |
| 1163 | bool mcast = false; |
| 1164 | u16 tx_count = 15; |
| 1165 | u32 val; |
| 1166 | |
| 1167 | if (vif) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1168 | struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1169 | |
| 1170 | omac_idx = mvif->mt76.omac_idx; |
| 1171 | wmm_idx = mvif->mt76.wmm_idx; |
| 1172 | band_idx = mvif->mt76.band_idx; |
| 1173 | } |
| 1174 | |
| 1175 | mphy = mt76_dev_phy(&dev->mt76, phy_idx); |
| 1176 | |
| 1177 | if (beacon) { |
| 1178 | p_fmt = MT_TX_TYPE_FW; |
| 1179 | q_idx = MT_LMAC_BCN0; |
| 1180 | } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { |
| 1181 | p_fmt = MT_TX_TYPE_CT; |
| 1182 | q_idx = MT_LMAC_ALTX0; |
| 1183 | } else { |
| 1184 | p_fmt = MT_TX_TYPE_CT; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1185 | q_idx = wmm_idx * BESRA_MAX_WMM_SETS + |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1186 | mt76_connac_lmac_mapping(skb_get_queue_mapping(skb)); |
| 1187 | } |
| 1188 | |
| 1189 | val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | |
| 1190 | FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) | |
| 1191 | FIELD_PREP(MT_TXD0_Q_IDX, q_idx); |
| 1192 | txwi[0] = cpu_to_le32(val); |
| 1193 | |
| 1194 | val = FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | |
| 1195 | FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); |
| 1196 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1197 | if (band_idx) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1198 | val |= FIELD_PREP(MT_TXD1_TGID, band_idx); |
| 1199 | |
| 1200 | txwi[1] = cpu_to_le32(val); |
| 1201 | |
| 1202 | txwi[2] = 0; |
| 1203 | |
| 1204 | val = MT_TXD3_SW_POWER_MGMT | |
| 1205 | FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); |
| 1206 | if (key) |
| 1207 | val |= MT_TXD3_PROTECT_FRAME; |
| 1208 | if (info->flags & IEEE80211_TX_CTL_NO_ACK) |
| 1209 | val |= MT_TXD3_NO_ACK; |
| 1210 | if (wcid->amsdu) |
| 1211 | val |= MT_TXD3_HW_AMSDU; |
| 1212 | |
| 1213 | txwi[3] = cpu_to_le32(val); |
| 1214 | txwi[4] = 0; |
| 1215 | |
| 1216 | val = FIELD_PREP(MT_TXD5_PID, pid); |
| 1217 | if (pid >= MT_PACKET_ID_FIRST) |
| 1218 | val |= MT_TXD5_TX_STATUS_HOST; |
| 1219 | txwi[5] = cpu_to_le32(val); |
| 1220 | |
| 1221 | /* Todo: check MT_TXD6_DIS_MAT for MLD to Link Address Translation */ |
| 1222 | /* val = MT_TXD6_DIS_MAT | MT_TXD6_VTA | */ |
| 1223 | val = MT_TXD6_DIS_MAT | MT_TXD6_DAS | |
| 1224 | FIELD_PREP(MT_TXD6_MSDU_CNT, 1); |
| 1225 | txwi[6] = cpu_to_le32(val); |
| 1226 | txwi[7] = 0; |
| 1227 | |
| 1228 | if (is_8023) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1229 | besra_mac_write_txwi_8023(dev, txwi, skb, wcid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1230 | else |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1231 | besra_mac_write_txwi_80211(dev, txwi, skb, key, &mcast); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1232 | |
| 1233 | if (txwi[1] & cpu_to_le32(MT_TXD1_FIXED_RATE)) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1234 | u16 rate = besra_mac_tx_rate_val(mphy, vif, beacon, mcast); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1235 | |
| 1236 | /* hardware won't add HTC for mgmt/ctrl frame */ |
| 1237 | /* txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD); */ |
| 1238 | |
| 1239 | val = FIELD_PREP(MT_TXD6_BW, 8) | |
| 1240 | FIELD_PREP(MT_TXD6_TX_RATE, 1); |
| 1241 | txwi[6] |= cpu_to_le32(val); |
| 1242 | //txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); |
| 1243 | } |
| 1244 | |
| 1245 | if (mt76_testmode_enabled(mphy)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1246 | besra_mac_write_txwi_tm(mphy->priv, txwi, skb); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1247 | } |
| 1248 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1249 | int besra_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1250 | enum mt76_txq_id qid, struct mt76_wcid *wcid, |
| 1251 | struct ieee80211_sta *sta, |
| 1252 | struct mt76_tx_info *tx_info) |
| 1253 | { |
| 1254 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1255 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1256 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); |
| 1257 | struct ieee80211_key_conf *key = info->control.hw_key; |
| 1258 | struct ieee80211_vif *vif = info->control.vif; |
| 1259 | struct mt76_txwi_cache *t; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1260 | struct besra_txp *txp; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1261 | int id, i, nbuf = tx_info->nbuf - 1; |
| 1262 | bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP; |
| 1263 | u8 *txwi = (u8 *)txwi_ptr; |
| 1264 | int pid; |
| 1265 | |
| 1266 | if (unlikely(tx_info->skb->len <= ETH_HLEN)) |
| 1267 | return -EINVAL; |
| 1268 | |
| 1269 | if (!wcid) |
| 1270 | wcid = &dev->mt76.global_wcid; |
| 1271 | |
| 1272 | if (sta) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1273 | struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1274 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1275 | msta = (struct besra_sta *)sta->drv_priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1276 | |
| 1277 | if (time_after(jiffies, msta->jiffies + HZ / 4)) { |
| 1278 | info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; |
| 1279 | msta->jiffies = jiffies; |
| 1280 | } |
| 1281 | } |
| 1282 | |
| 1283 | t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); |
| 1284 | t->skb = tx_info->skb; |
| 1285 | |
| 1286 | id = mt76_token_consume(mdev, &t); |
| 1287 | if (id < 0) |
| 1288 | return id; |
| 1289 | |
| 1290 | pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); |
| 1291 | memset(txwi_ptr, 0, MT_TXD_SIZE); |
| 1292 | /* Transmit non qos data by 802.11 header and need to fill txd by host*/ |
| 1293 | if (!is_8023 || pid >= MT_PACKET_ID_FIRST) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1294 | besra_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, pid, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1295 | key, false); |
| 1296 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1297 | txp = (struct besra_txp *)(txwi + MT_TXD_SIZE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1298 | for (i = 0; i < nbuf; i++) { |
| 1299 | txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); |
| 1300 | txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); |
| 1301 | } |
| 1302 | txp->nbuf = nbuf; |
| 1303 | |
| 1304 | txp->flags = cpu_to_le16(MT_CT_INFO_FROM_HOST); |
| 1305 | |
| 1306 | if (!is_8023 || pid >= MT_PACKET_ID_FIRST) |
| 1307 | txp->flags |= cpu_to_le16(MT_CT_INFO_APPLY_TXD); |
| 1308 | |
| 1309 | if (!key) |
| 1310 | txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); |
| 1311 | |
| 1312 | if (!is_8023 && ieee80211_is_mgmt(hdr->frame_control)) |
| 1313 | txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); |
| 1314 | |
| 1315 | if (vif) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1316 | struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1317 | |
| 1318 | txp->bss_idx = mvif->mt76.idx; |
| 1319 | } |
| 1320 | |
| 1321 | txp->token = cpu_to_le16(id); |
| 1322 | if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) |
| 1323 | txp->rept_wds_wcid = cpu_to_le16(wcid->idx); |
| 1324 | else |
| 1325 | txp->rept_wds_wcid = cpu_to_le16(0xfff); |
| 1326 | tx_info->skb = DMA_DUMMY_DATA; |
| 1327 | |
| 1328 | /* pass partial skb header to fw */ |
| 1329 | tx_info->buf[1].len = MT_CT_PARSE_LEN; |
| 1330 | tx_info->buf[1].skip_unmap = true; |
| 1331 | tx_info->nbuf = MT_CT_DMA_BUF_NUM; |
| 1332 | |
| 1333 | return 0; |
| 1334 | } |
| 1335 | |
| 1336 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1337 | besra_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1338 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1339 | struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1340 | u16 fc, tid; |
| 1341 | u32 val; |
| 1342 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1343 | if (!sta || !(sta->ht_cap.ht_supported || sta->he_cap.has_he)) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1344 | return; |
| 1345 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1346 | tid = le32_get_bits(txwi[1], MT_TXD1_TID); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1347 | if (tid >= 6) /* skip VO queue */ |
| 1348 | return; |
| 1349 | |
| 1350 | val = le32_to_cpu(txwi[2]); |
| 1351 | fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 | |
| 1352 | FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4; |
| 1353 | if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA))) |
| 1354 | return; |
| 1355 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1356 | msta = (struct besra_sta *)sta->drv_priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1357 | if (!test_and_set_bit(tid, &msta->ampdu_state)) |
| 1358 | ieee80211_start_tx_ba_session(sta, tid, 0); |
| 1359 | } |
| 1360 | |
| 1361 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1362 | besra_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1363 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1364 | struct besra_txp *txp; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1365 | int i; |
| 1366 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1367 | txp = besra_txwi_to_txp(dev, t); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1368 | for (i = 0; i < txp->nbuf; i++) |
| 1369 | dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), |
| 1370 | le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); |
| 1371 | } |
| 1372 | |
| 1373 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1374 | besra_txwi_free(struct besra_dev *dev, struct mt76_txwi_cache *t, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1375 | struct ieee80211_sta *sta, struct list_head *free_list) |
| 1376 | { |
| 1377 | struct mt76_dev *mdev = &dev->mt76; |
| 1378 | struct mt76_wcid *wcid; |
| 1379 | __le32 *txwi; |
| 1380 | u16 wcid_idx; |
| 1381 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1382 | besra_txp_skb_unmap(mdev, t); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1383 | if (!t->skb) |
| 1384 | goto out; |
| 1385 | |
| 1386 | txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t); |
| 1387 | if (sta) { |
| 1388 | wcid = (struct mt76_wcid *)sta->drv_priv; |
| 1389 | wcid_idx = wcid->idx; |
| 1390 | |
| 1391 | if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1392 | besra_tx_check_aggr(sta, txwi); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1393 | } else { |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1394 | wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1395 | } |
| 1396 | |
| 1397 | __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); |
| 1398 | |
| 1399 | out: |
| 1400 | t->skb = NULL; |
| 1401 | mt76_put_txwi(mdev, t); |
| 1402 | } |
| 1403 | |
| 1404 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1405 | besra_mac_tx_free(struct besra_dev *dev, void *data, int len) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1406 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1407 | struct besra_tx_free *free = (struct besra_tx_free *)data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1408 | struct mt76_dev *mdev = &dev->mt76; |
| 1409 | struct mt76_phy *mphy_ext = mdev->phy2; |
| 1410 | struct mt76_phy *mphy_tri = mdev->phy3; |
| 1411 | struct mt76_txwi_cache *txwi; |
| 1412 | struct ieee80211_sta *sta = NULL; |
| 1413 | LIST_HEAD(free_list); |
| 1414 | struct sk_buff *skb, *tmp; |
| 1415 | void *end = data + len; |
| 1416 | bool v3, wake = false; |
| 1417 | u16 total, count = 0; |
| 1418 | u32 txd = le32_to_cpu(free->txd); |
| 1419 | __le32 *cur_info; |
| 1420 | |
| 1421 | /* clean DMA queues and unmap buffers first */ |
| 1422 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); |
| 1423 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); |
| 1424 | if (mphy_ext) { |
| 1425 | mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); |
| 1426 | mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); |
| 1427 | } |
| 1428 | if (mphy_tri) { |
| 1429 | mt76_queue_tx_cleanup(dev, mphy_tri->q_tx[MT_TXQ_PSD], false); |
| 1430 | mt76_queue_tx_cleanup(dev, mphy_tri->q_tx[MT_TXQ_BE], false); |
| 1431 | } |
| 1432 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1433 | total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1434 | v3 = (FIELD_GET(MT_TX_FREE_VER, txd) >= 0x4); |
| 1435 | if (WARN_ON_ONCE((void *)&free->info[total >> v3] > end)) |
| 1436 | return; |
| 1437 | |
| 1438 | for (cur_info = &free->info[0]; count < total; cur_info++) { |
| 1439 | u32 msdu, info = le32_to_cpu(*cur_info); |
| 1440 | u8 i; |
| 1441 | |
| 1442 | /* |
| 1443 | * 1'b1: new wcid pair. |
| 1444 | * 1'b0: msdu_id with the same 'wcid pair' as above. |
| 1445 | */ |
| 1446 | if (info & MT_TX_FREE_PAIR) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1447 | struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1448 | struct mt76_wcid *wcid; |
| 1449 | u16 idx; |
| 1450 | |
| 1451 | idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); |
| 1452 | wcid = rcu_dereference(dev->mt76.wcid[idx]); |
| 1453 | sta = wcid_to_sta(wcid); |
| 1454 | if (!sta) |
| 1455 | continue; |
| 1456 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1457 | msta = container_of(wcid, struct besra_sta, wcid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1458 | spin_lock_bh(&dev->sta_poll_lock); |
| 1459 | if (list_empty(&msta->poll_list)) |
| 1460 | list_add_tail(&msta->poll_list, &dev->sta_poll_list); |
| 1461 | spin_unlock_bh(&dev->sta_poll_lock); |
| 1462 | continue; |
| 1463 | } |
| 1464 | |
| 1465 | if (v3 && (info & MT_TX_FREE_MPDU_HEADER)) |
| 1466 | continue; |
| 1467 | |
| 1468 | for (i = 0; i < 1 + v3; i++) { |
| 1469 | if (v3) { |
| 1470 | msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; |
| 1471 | if (msdu == MT_TX_FREE_MSDU_ID_V3) |
| 1472 | continue; |
| 1473 | } else { |
| 1474 | msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); |
| 1475 | } |
| 1476 | count++; |
| 1477 | txwi = mt76_token_release(mdev, msdu, &wake); |
| 1478 | if (!txwi) |
| 1479 | continue; |
| 1480 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1481 | besra_txwi_free(dev, txwi, sta, &free_list); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1482 | } |
| 1483 | } |
| 1484 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1485 | besra_mac_sta_poll(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1486 | |
| 1487 | if (wake) |
| 1488 | mt76_set_tx_blocked(&dev->mt76, false); |
| 1489 | |
| 1490 | mt76_worker_schedule(&dev->mt76.tx_worker); |
| 1491 | |
| 1492 | list_for_each_entry_safe(skb, tmp, &free_list, list) { |
| 1493 | skb_list_del_init(skb); |
| 1494 | napi_consume_skb(skb, 1); |
| 1495 | } |
| 1496 | } |
| 1497 | |
| 1498 | static bool |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1499 | besra_mac_add_txs_skb(struct besra_dev *dev, struct mt76_wcid *wcid, int pid, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1500 | __le32 *txs_data, struct mt76_sta_stats *stats) |
| 1501 | { |
| 1502 | struct ieee80211_supported_band *sband; |
| 1503 | struct mt76_dev *mdev = &dev->mt76; |
| 1504 | struct mt76_phy *mphy; |
| 1505 | struct ieee80211_tx_info *info; |
| 1506 | struct sk_buff_head list; |
| 1507 | struct rate_info rate = {}; |
| 1508 | struct sk_buff *skb; |
| 1509 | bool cck = false; |
| 1510 | u32 txrate, txs, mode; |
| 1511 | |
| 1512 | mt76_tx_status_lock(mdev, &list); |
| 1513 | skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list); |
| 1514 | if (!skb) |
| 1515 | goto out_no_skb; |
| 1516 | |
| 1517 | txs = le32_to_cpu(txs_data[0]); |
| 1518 | |
| 1519 | info = IEEE80211_SKB_CB(skb); |
| 1520 | if (!(txs & MT_TXS0_ACK_ERROR_MASK)) |
| 1521 | info->flags |= IEEE80211_TX_STAT_ACK; |
| 1522 | |
| 1523 | info->status.ampdu_len = 1; |
| 1524 | info->status.ampdu_ack_len = !!(info->flags & |
| 1525 | IEEE80211_TX_STAT_ACK); |
| 1526 | |
| 1527 | info->status.rates[0].idx = -1; |
| 1528 | |
| 1529 | txrate = FIELD_GET(MT_TXS0_TX_RATE, txs); |
| 1530 | |
| 1531 | rate.mcs = FIELD_GET(MT_TX_RATE_IDX, txrate); |
| 1532 | rate.nss = FIELD_GET(MT_TX_RATE_NSS, txrate) + 1; |
| 1533 | |
| 1534 | if (rate.nss - 1 < ARRAY_SIZE(stats->tx_nss)) |
| 1535 | stats->tx_nss[rate.nss - 1]++; |
| 1536 | if (rate.mcs < ARRAY_SIZE(stats->tx_mcs)) |
| 1537 | stats->tx_mcs[rate.mcs]++; |
| 1538 | |
| 1539 | mode = FIELD_GET(MT_TX_RATE_MODE, txrate); |
| 1540 | switch (mode) { |
| 1541 | case MT_PHY_TYPE_CCK: |
| 1542 | cck = true; |
| 1543 | fallthrough; |
| 1544 | case MT_PHY_TYPE_OFDM: |
| 1545 | mphy = mt76_dev_phy(mdev, wcid->phy_idx); |
| 1546 | |
| 1547 | if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) |
| 1548 | sband = &mphy->sband_5g.sband; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1549 | else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ) |
| 1550 | sband = &mphy->sband_6g.sband; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1551 | else |
| 1552 | sband = &mphy->sband_2g.sband; |
| 1553 | |
| 1554 | rate.mcs = mt76_get_rate(mphy->dev, sband, rate.mcs, cck); |
| 1555 | rate.legacy = sband->bitrates[rate.mcs].bitrate; |
| 1556 | break; |
| 1557 | case MT_PHY_TYPE_HT: |
| 1558 | case MT_PHY_TYPE_HT_GF: |
| 1559 | if (rate.mcs > 31) |
| 1560 | goto out; |
| 1561 | |
| 1562 | rate.flags = RATE_INFO_FLAGS_MCS; |
| 1563 | if (wcid->rate.flags & RATE_INFO_FLAGS_SHORT_GI) |
| 1564 | rate.flags |= RATE_INFO_FLAGS_SHORT_GI; |
| 1565 | break; |
| 1566 | case MT_PHY_TYPE_VHT: |
| 1567 | if (rate.mcs > 9) |
| 1568 | goto out; |
| 1569 | |
| 1570 | rate.flags = RATE_INFO_FLAGS_VHT_MCS; |
| 1571 | break; |
| 1572 | case MT_PHY_TYPE_HE_SU: |
| 1573 | case MT_PHY_TYPE_HE_EXT_SU: |
| 1574 | case MT_PHY_TYPE_HE_TB: |
| 1575 | case MT_PHY_TYPE_HE_MU: |
| 1576 | if (rate.mcs > 11) |
| 1577 | goto out; |
| 1578 | |
| 1579 | rate.he_gi = wcid->rate.he_gi; |
| 1580 | rate.he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate); |
| 1581 | rate.flags = RATE_INFO_FLAGS_HE_MCS; |
| 1582 | break; |
| 1583 | default: |
| 1584 | goto out; |
| 1585 | } |
| 1586 | |
| 1587 | stats->tx_mode[mode]++; |
| 1588 | |
| 1589 | switch (FIELD_GET(MT_TXS0_BW, txs)) { |
| 1590 | case IEEE80211_STA_RX_BW_160: |
| 1591 | rate.bw = RATE_INFO_BW_160; |
| 1592 | stats->tx_bw[3]++; |
| 1593 | break; |
| 1594 | case IEEE80211_STA_RX_BW_80: |
| 1595 | rate.bw = RATE_INFO_BW_80; |
| 1596 | stats->tx_bw[2]++; |
| 1597 | break; |
| 1598 | case IEEE80211_STA_RX_BW_40: |
| 1599 | rate.bw = RATE_INFO_BW_40; |
| 1600 | stats->tx_bw[1]++; |
| 1601 | break; |
| 1602 | default: |
| 1603 | rate.bw = RATE_INFO_BW_20; |
| 1604 | stats->tx_bw[0]++; |
| 1605 | break; |
| 1606 | } |
| 1607 | wcid->rate = rate; |
| 1608 | |
| 1609 | out: |
| 1610 | mt76_tx_status_skb_done(mdev, skb, &list); |
| 1611 | |
| 1612 | out_no_skb: |
| 1613 | mt76_tx_status_unlock(mdev, &list); |
| 1614 | |
| 1615 | return !!skb; |
| 1616 | } |
| 1617 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1618 | static void besra_mac_add_txs(struct besra_dev *dev, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1619 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1620 | struct besra_sta *msta = NULL; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1621 | struct mt76_wcid *wcid; |
| 1622 | __le32 *txs_data = data; |
| 1623 | u16 wcidx; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1624 | u8 pid; |
| 1625 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1626 | if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1627 | return; |
| 1628 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1629 | wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); |
| 1630 | pid = le32_get_bits(txs_data[3], MT_TXS3_PID); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1631 | |
| 1632 | if (pid < MT_PACKET_ID_FIRST) |
| 1633 | return; |
| 1634 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1635 | if (wcidx >= BESRA_WTBL_SIZE) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1636 | return; |
| 1637 | |
| 1638 | rcu_read_lock(); |
| 1639 | |
| 1640 | wcid = rcu_dereference(dev->mt76.wcid[wcidx]); |
| 1641 | if (!wcid) |
| 1642 | goto out; |
| 1643 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1644 | msta = container_of(wcid, struct besra_sta, wcid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1645 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1646 | besra_mac_add_txs_skb(dev, wcid, pid, txs_data, &msta->stats); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1647 | |
| 1648 | if (!wcid->sta) |
| 1649 | goto out; |
| 1650 | |
| 1651 | spin_lock_bh(&dev->sta_poll_lock); |
| 1652 | if (list_empty(&msta->poll_list)) |
| 1653 | list_add_tail(&msta->poll_list, &dev->sta_poll_list); |
| 1654 | spin_unlock_bh(&dev->sta_poll_lock); |
| 1655 | |
| 1656 | out: |
| 1657 | rcu_read_unlock(); |
| 1658 | } |
| 1659 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1660 | bool besra_rx_check(struct mt76_dev *mdev, enum mt76_rxq_id q, void *data, int len) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1661 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1662 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1663 | __le32 *rxd = (__le32 *)data; |
| 1664 | __le32 *end = (__le32 *)&rxd[len / 4]; |
| 1665 | enum rx_pkt_type type; |
| 1666 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1667 | type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1668 | if (q == MT_RXQ_MCU || q == MT_RXQ_MCU_WA || |
| 1669 | q == MT_RXQ_MAIN_WA || q == MT_RXQ_EXT_WA || q == MT_RXQ_TRI_WA) { |
| 1670 | enum rx_pkt_type sw_type = FIELD_GET(MT_RXD0_SW_PKT_TYPE_MASK, le32_to_cpu(rxd[0])); |
| 1671 | |
| 1672 | if ((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == MT_RXD0_SW_PKT_TYPE_FRAME) |
| 1673 | type = PKT_TYPE_NORMAL; |
| 1674 | } |
| 1675 | |
| 1676 | switch (type) { |
| 1677 | case PKT_TYPE_TXRX_NOTIFY: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1678 | besra_mac_tx_free(dev, data, len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1679 | return false; |
| 1680 | case PKT_TYPE_TXS: |
| 1681 | for (rxd += 4; rxd + 8 <= end; rxd += 8) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1682 | besra_mac_add_txs(dev, rxd); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1683 | return false; |
| 1684 | case PKT_TYPE_RX_FW_MONITOR: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1685 | besra_debugfs_rx_fw_monitor(dev, data, len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1686 | return false; |
| 1687 | default: |
| 1688 | return true; |
| 1689 | } |
| 1690 | } |
| 1691 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1692 | void besra_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1693 | struct sk_buff *skb) |
| 1694 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1695 | struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1696 | __le32 *rxd = (__le32 *)skb->data; |
| 1697 | __le32 *end = (__le32 *)&skb->data[skb->len]; |
| 1698 | enum rx_pkt_type type; |
| 1699 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1700 | type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1701 | if (q == MT_RXQ_MCU || q == MT_RXQ_MCU_WA || |
| 1702 | q == MT_RXQ_MAIN_WA || q == MT_RXQ_EXT_WA || q == MT_RXQ_TRI_WA) { |
| 1703 | enum rx_pkt_type sw_type = FIELD_GET(MT_RXD0_SW_PKT_TYPE_MASK, le32_to_cpu(rxd[0])); |
| 1704 | |
| 1705 | if ((sw_type & MT_RXD0_SW_PKT_TYPE_MAP) == MT_RXD0_SW_PKT_TYPE_FRAME) |
| 1706 | type = PKT_TYPE_NORMAL; |
| 1707 | } |
| 1708 | |
| 1709 | switch (type) { |
| 1710 | case PKT_TYPE_TXRX_NOTIFY: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1711 | besra_mac_tx_free(dev, skb->data, skb->len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1712 | napi_consume_skb(skb, 1); |
| 1713 | break; |
| 1714 | case PKT_TYPE_RX_EVENT: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1715 | besra_mcu_rx_event(dev, skb); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1716 | break; |
| 1717 | case PKT_TYPE_TXRXV: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1718 | besra_mac_fill_rx_vector(dev, skb); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1719 | break; |
| 1720 | case PKT_TYPE_TXS: |
| 1721 | for (rxd += 4; rxd + 8 <= end; rxd += 8) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1722 | besra_mac_add_txs(dev, rxd); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1723 | dev_kfree_skb(skb); |
| 1724 | break; |
| 1725 | case PKT_TYPE_RX_FW_MONITOR: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1726 | besra_debugfs_rx_fw_monitor(dev, skb->data, skb->len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1727 | dev_kfree_skb(skb); |
| 1728 | break; |
| 1729 | case PKT_TYPE_NORMAL: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1730 | if (!besra_mac_fill_rx(dev, skb)) { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1731 | mt76_rx(&dev->mt76, q, skb); |
| 1732 | return; |
| 1733 | } |
| 1734 | fallthrough; |
| 1735 | default: |
| 1736 | dev_kfree_skb(skb); |
| 1737 | break; |
| 1738 | } |
| 1739 | } |
| 1740 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1741 | void besra_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1742 | { |
| 1743 | if (!e->txwi) { |
| 1744 | dev_kfree_skb_any(e->skb); |
| 1745 | return; |
| 1746 | } |
| 1747 | |
| 1748 | /* error path */ |
| 1749 | if (e->skb == DMA_DUMMY_DATA) { |
| 1750 | struct mt76_txwi_cache *t; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1751 | struct besra_txp *txp; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1752 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1753 | txp = besra_txwi_to_txp(mdev, e->txwi); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1754 | t = mt76_token_put(mdev, le16_to_cpu(txp->token)); |
| 1755 | e->skb = t ? t->skb : NULL; |
| 1756 | } |
| 1757 | |
| 1758 | if (e->skb) |
| 1759 | mt76_tx_complete_skb(mdev, e->wcid, e->skb); |
| 1760 | } |
| 1761 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1762 | void besra_mac_cca_stats_reset(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1763 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1764 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1765 | u32 reg = MT_WF_PHY_RX_CTRL1(phy->band_idx); |
| 1766 | |
| 1767 | mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); |
| 1768 | mt76_set(dev, reg, BIT(11) | BIT(9)); |
| 1769 | } |
| 1770 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1771 | void besra_mac_reset_counters(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1772 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1773 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1774 | int i; |
| 1775 | |
| 1776 | for (i = 0; i < 4; i++) { |
| 1777 | mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i)); |
| 1778 | mt76_rr(dev, MT_TX_AGG_CNT2(phy->band_idx, i)); |
| 1779 | } |
| 1780 | |
| 1781 | i = 0; |
| 1782 | phy->mt76->survey_time = ktime_get_boottime(); |
| 1783 | if (phy->band_idx) |
| 1784 | i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2; |
| 1785 | |
| 1786 | memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2); |
| 1787 | |
| 1788 | /* reset airtime counters */ |
| 1789 | mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->band_idx), |
| 1790 | MT_WF_RMAC_MIB_RXTIME_CLR); |
| 1791 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1792 | besra_mcu_get_chan_mib_info(phy, true); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1793 | } |
| 1794 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1795 | void besra_mac_set_timing(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1796 | { |
| 1797 | s16 coverage_class = phy->coverage_class; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1798 | struct besra_dev *dev = phy->dev; |
| 1799 | struct besra_phy *ext_phy = besra_ext_phy(dev); |
| 1800 | struct besra_phy *tri_phy = besra_tri_phy(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1801 | u32 val, reg_offset; |
| 1802 | u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | |
| 1803 | FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); |
| 1804 | u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | |
| 1805 | FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); |
| 1806 | int offset; |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1807 | bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1808 | |
| 1809 | if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) |
| 1810 | return; |
| 1811 | |
| 1812 | if (ext_phy) |
| 1813 | coverage_class = max_t(s16, dev->phy.coverage_class, |
| 1814 | ext_phy->coverage_class); |
| 1815 | |
| 1816 | if (tri_phy) |
| 1817 | coverage_class = max_t(s16, coverage_class, |
| 1818 | tri_phy->coverage_class); |
| 1819 | |
| 1820 | mt76_set(dev, MT_ARB_SCR(phy->band_idx), |
| 1821 | MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); |
| 1822 | udelay(1); |
| 1823 | |
| 1824 | offset = 3 * coverage_class; |
| 1825 | reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | |
| 1826 | FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); |
| 1827 | |
| 1828 | mt76_wr(dev, MT_TMAC_CDTR(phy->band_idx), cck + reg_offset); |
| 1829 | mt76_wr(dev, MT_TMAC_ODTR(phy->band_idx), ofdm + reg_offset); |
| 1830 | mt76_wr(dev, MT_TMAC_ICR0(phy->band_idx), |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1831 | FIELD_PREP(MT_IFS_EIFS_OFDM, a_band ? 84 : 78) | |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1832 | FIELD_PREP(MT_IFS_RIFS, 2) | |
| 1833 | FIELD_PREP(MT_IFS_SIFS, 10) | |
| 1834 | FIELD_PREP(MT_IFS_SLOT, phy->slottime)); |
| 1835 | |
| 1836 | mt76_wr(dev, MT_TMAC_ICR1(phy->band_idx), |
| 1837 | FIELD_PREP(MT_IFS_EIFS_CCK, 314)); |
| 1838 | |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 1839 | if (phy->slottime < 20 || a_band) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1840 | val = BESRA_CFEND_RATE_DEFAULT; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1841 | else |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1842 | val = BESRA_CFEND_RATE_11B; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1843 | |
| 1844 | mt76_rmw_field(dev, MT_AGG_ACR0(phy->band_idx), MT_AGG_ACR_CFEND_RATE, val); |
| 1845 | mt76_clear(dev, MT_ARB_SCR(phy->band_idx), |
| 1846 | MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); |
| 1847 | } |
| 1848 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1849 | void besra_mac_enable_nf(struct besra_dev *dev, u8 band) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1850 | { |
| 1851 | mt76_set(dev, MT_WF_PHY_RXTD12(band), |
| 1852 | MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | |
| 1853 | MT_WF_PHY_RXTD12_IRPI_SW_CLR); |
| 1854 | |
| 1855 | mt76_set(dev, MT_WF_PHY_RX_CTRL1(band), |
| 1856 | FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); |
| 1857 | } |
| 1858 | |
| 1859 | static u8 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1860 | besra_phy_get_nf(struct besra_phy *phy, int idx) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1861 | { |
| 1862 | static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1863 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1864 | u32 val, sum = 0, n = 0; |
| 1865 | int nss, i; |
| 1866 | |
| 1867 | for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { |
| 1868 | u32 reg = MT_WF_IRPI_NSS(idx, nss); |
| 1869 | |
| 1870 | for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { |
| 1871 | val = mt76_rr(dev, reg); |
| 1872 | sum += val * nf_power[i]; |
| 1873 | n += val; |
| 1874 | } |
| 1875 | } |
| 1876 | |
| 1877 | if (!n) |
| 1878 | return 0; |
| 1879 | |
| 1880 | return sum / n; |
| 1881 | } |
| 1882 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1883 | void besra_update_channel(struct mt76_phy *mphy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1884 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1885 | struct besra_phy *phy = (struct besra_phy *)mphy->priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1886 | struct mt76_channel_state *state = mphy->chan_state; |
| 1887 | int nf; |
| 1888 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1889 | besra_mcu_get_chan_mib_info(phy, false); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1890 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1891 | nf = besra_phy_get_nf(phy, phy->band_idx); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1892 | if (!phy->noise) |
| 1893 | phy->noise = nf << 4; |
| 1894 | else if (nf) |
| 1895 | phy->noise += nf - (phy->noise >> 4); |
| 1896 | |
| 1897 | state->noise = -(phy->noise >> 4); |
| 1898 | } |
| 1899 | |
| 1900 | static bool |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1901 | besra_wait_reset_state(struct besra_dev *dev, u32 state) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1902 | { |
| 1903 | bool ret; |
| 1904 | |
| 1905 | ret = wait_event_timeout(dev->reset_wait, |
| 1906 | (READ_ONCE(dev->reset_state) & state), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1907 | BESRA_RESET_TIMEOUT); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1908 | |
| 1909 | WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); |
| 1910 | return ret; |
| 1911 | } |
| 1912 | |
| 1913 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1914 | besra_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1915 | { |
| 1916 | struct ieee80211_hw *hw = priv; |
| 1917 | |
| 1918 | switch (vif->type) { |
| 1919 | case NL80211_IFTYPE_MESH_POINT: |
| 1920 | case NL80211_IFTYPE_ADHOC: |
| 1921 | case NL80211_IFTYPE_AP: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1922 | besra_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1923 | break; |
| 1924 | default: |
| 1925 | break; |
| 1926 | } |
| 1927 | } |
| 1928 | |
| 1929 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1930 | besra_update_beacons(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1931 | { |
| 1932 | ieee80211_iterate_active_interfaces(dev->mt76.hw, |
| 1933 | IEEE80211_IFACE_ITER_RESUME_ALL, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1934 | besra_update_vif_beacon, dev->mt76.hw); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1935 | |
| 1936 | if (!dev->mt76.phy2) |
| 1937 | return; |
| 1938 | |
| 1939 | ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw, |
| 1940 | IEEE80211_IFACE_ITER_RESUME_ALL, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1941 | besra_update_vif_beacon, dev->mt76.phy2->hw); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1942 | |
| 1943 | if (!dev->mt76.phy3) |
| 1944 | return; |
| 1945 | |
| 1946 | ieee80211_iterate_active_interfaces(dev->mt76.phy3->hw, |
| 1947 | IEEE80211_IFACE_ITER_RESUME_ALL, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1948 | besra_update_vif_beacon, dev->mt76.phy3->hw); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1949 | } |
| 1950 | |
| 1951 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1952 | besra_dma_reset(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1953 | { |
| 1954 | struct mt76_phy *mphy_ext = dev->mt76.phy2; |
| 1955 | struct mt76_phy *mphy_tri = dev->mt76.phy3; |
| 1956 | u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 1957 | int i; |
| 1958 | |
| 1959 | mt76_clear(dev, MT_WFDMA0_GLO_CFG, |
| 1960 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 1961 | MT_WFDMA0_GLO_CFG_RX_DMA_EN); |
| 1962 | |
| 1963 | if (dev->hif2) |
| 1964 | mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, |
| 1965 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 1966 | MT_WFDMA0_GLO_CFG_RX_DMA_EN); |
| 1967 | |
| 1968 | usleep_range(1000, 2000); |
| 1969 | |
| 1970 | for (i = 0; i < __MT_TXQ_MAX; i++) { |
| 1971 | mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); |
| 1972 | if (mphy_ext) |
| 1973 | mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true); |
| 1974 | if (mphy_tri) |
| 1975 | mt76_queue_tx_cleanup(dev, mphy_tri->q_tx[i], true); |
| 1976 | } |
| 1977 | |
| 1978 | for (i = 0; i < __MT_MCUQ_MAX; i++) |
| 1979 | mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); |
| 1980 | |
| 1981 | mt76_for_each_q_rx(&dev->mt76, i) |
| 1982 | mt76_queue_rx_reset(dev, i); |
| 1983 | |
| 1984 | mt76_tx_status_check(&dev->mt76, true); |
| 1985 | |
| 1986 | /* re-init prefetch settings after reset */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1987 | besra_dma_prefetch(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1988 | |
| 1989 | mt76_set(dev, MT_WFDMA0_GLO_CFG, |
| 1990 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); |
| 1991 | |
| 1992 | if (dev->hif2) |
| 1993 | mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, |
| 1994 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 1995 | MT_WFDMA0_GLO_CFG_RX_DMA_EN); |
| 1996 | } |
| 1997 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 1998 | void besra_tx_token_put(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1999 | { |
| 2000 | struct mt76_txwi_cache *txwi; |
| 2001 | int id; |
| 2002 | |
| 2003 | spin_lock_bh(&dev->mt76.token_lock); |
| 2004 | idr_for_each_entry(&dev->mt76.token, txwi, id) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2005 | besra_txwi_free(dev, txwi, NULL, NULL); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2006 | dev->mt76.token_count--; |
| 2007 | } |
| 2008 | spin_unlock_bh(&dev->mt76.token_lock); |
| 2009 | idr_destroy(&dev->mt76.token); |
| 2010 | } |
| 2011 | |
| 2012 | /* system error recovery */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2013 | void besra_mac_reset_work(struct work_struct *work) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2014 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2015 | struct besra_phy *phy2, *phy3; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2016 | struct mt76_phy *ext_phy, *tri_phy; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2017 | struct besra_dev *dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2018 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2019 | dev = container_of(work, struct besra_dev, reset_work); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2020 | ext_phy = dev->mt76.phy2; |
| 2021 | phy2 = ext_phy ? ext_phy->priv : NULL; |
| 2022 | |
| 2023 | tri_phy = dev->mt76.phy3; |
| 2024 | phy3 = tri_phy ? tri_phy->priv : NULL; |
| 2025 | |
| 2026 | if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA)) |
| 2027 | return; |
| 2028 | |
| 2029 | ieee80211_stop_queues(mt76_hw(dev)); |
| 2030 | if (ext_phy) |
| 2031 | ieee80211_stop_queues(ext_phy->hw); |
| 2032 | if (tri_phy) |
| 2033 | ieee80211_stop_queues(tri_phy->hw); |
| 2034 | |
| 2035 | set_bit(MT76_RESET, &dev->mphy.state); |
| 2036 | set_bit(MT76_MCU_RESET, &dev->mphy.state); |
| 2037 | wake_up(&dev->mt76.mcu.wait); |
| 2038 | cancel_delayed_work_sync(&dev->mphy.mac_work); |
| 2039 | if (phy2) { |
| 2040 | set_bit(MT76_RESET, &phy2->mt76->state); |
| 2041 | cancel_delayed_work_sync(&phy2->mt76->mac_work); |
| 2042 | } |
| 2043 | if (phy3) { |
| 2044 | set_bit(MT76_RESET, &phy3->mt76->state); |
| 2045 | cancel_delayed_work_sync(&phy3->mt76->mac_work); |
| 2046 | } |
| 2047 | mt76_worker_disable(&dev->mt76.tx_worker); |
| 2048 | napi_disable(&dev->mt76.napi[0]); |
| 2049 | napi_disable(&dev->mt76.napi[1]); |
| 2050 | napi_disable(&dev->mt76.napi[2]); |
| 2051 | napi_disable(&dev->mt76.tx_napi); |
| 2052 | |
| 2053 | mutex_lock(&dev->mt76.mutex); |
| 2054 | |
| 2055 | mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); |
| 2056 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2057 | if (besra_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { |
| 2058 | besra_dma_reset(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2059 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2060 | besra_tx_token_put(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2061 | idr_init(&dev->mt76.token); |
| 2062 | |
| 2063 | mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2064 | besra_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2065 | } |
| 2066 | |
| 2067 | clear_bit(MT76_MCU_RESET, &dev->mphy.state); |
| 2068 | clear_bit(MT76_RESET, &dev->mphy.state); |
| 2069 | if (phy2) |
| 2070 | clear_bit(MT76_RESET, &phy2->mt76->state); |
| 2071 | if (phy3) |
| 2072 | clear_bit(MT76_RESET, &phy3->mt76->state); |
| 2073 | |
| 2074 | local_bh_disable(); |
| 2075 | napi_enable(&dev->mt76.napi[0]); |
| 2076 | napi_schedule(&dev->mt76.napi[0]); |
| 2077 | |
| 2078 | napi_enable(&dev->mt76.napi[1]); |
| 2079 | napi_schedule(&dev->mt76.napi[1]); |
| 2080 | |
| 2081 | napi_enable(&dev->mt76.napi[2]); |
| 2082 | napi_schedule(&dev->mt76.napi[2]); |
| 2083 | local_bh_enable(); |
| 2084 | |
| 2085 | tasklet_schedule(&dev->irq_tasklet); |
| 2086 | |
| 2087 | mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2088 | besra_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2089 | |
| 2090 | mt76_worker_enable(&dev->mt76.tx_worker); |
| 2091 | |
| 2092 | napi_enable(&dev->mt76.tx_napi); |
| 2093 | napi_schedule(&dev->mt76.tx_napi); |
| 2094 | |
| 2095 | ieee80211_wake_queues(mt76_hw(dev)); |
| 2096 | if (ext_phy) |
| 2097 | ieee80211_wake_queues(ext_phy->hw); |
| 2098 | if (tri_phy) |
| 2099 | ieee80211_wake_queues(tri_phy->hw); |
| 2100 | |
| 2101 | mutex_unlock(&dev->mt76.mutex); |
| 2102 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2103 | besra_update_beacons(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2104 | |
| 2105 | ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2106 | BESRA_WATCHDOG_TIME); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2107 | if (phy2) |
| 2108 | ieee80211_queue_delayed_work(ext_phy->hw, |
| 2109 | &phy2->mt76->mac_work, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2110 | BESRA_WATCHDOG_TIME); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2111 | if (phy3) |
| 2112 | ieee80211_queue_delayed_work(tri_phy->hw, |
| 2113 | &phy3->mt76->mac_work, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2114 | BESRA_WATCHDOG_TIME); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2115 | } |
| 2116 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2117 | void besra_mac_update_stats(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2118 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2119 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2120 | struct mib_stats *mib = &phy->mib; |
| 2121 | int i, aggr0, cnt; |
| 2122 | u32 val; |
| 2123 | |
| 2124 | cnt = mt76_rr(dev, MT_MIB_SDR3(phy->band_idx)); |
| 2125 | mib->fcs_err_cnt += |
| 2126 | FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt); |
| 2127 | |
| 2128 | cnt = mt76_rr(dev, MT_MIB_SDR4(phy->band_idx)); |
| 2129 | mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); |
| 2130 | |
| 2131 | cnt = mt76_rr(dev, MT_MIB_SDR5(phy->band_idx)); |
| 2132 | mib->rx_mpdu_cnt += cnt; |
| 2133 | |
| 2134 | cnt = mt76_rr(dev, MT_MIB_SDR6(phy->band_idx)); |
| 2135 | mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); |
| 2136 | |
| 2137 | cnt = mt76_rr(dev, MT_MIB_SDR7(phy->band_idx)); |
| 2138 | mib->rx_vector_mismatch_cnt += FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); |
| 2139 | |
| 2140 | cnt = mt76_rr(dev, MT_MIB_SDR8(phy->band_idx)); |
| 2141 | mib->rx_delimiter_fail_cnt += FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); |
| 2142 | |
| 2143 | cnt = mt76_rr(dev, MT_MIB_SDR11(phy->band_idx)); |
| 2144 | mib->rx_len_mismatch_cnt += FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); |
| 2145 | |
| 2146 | cnt = mt76_rr(dev, MT_MIB_SDR12(phy->band_idx)); |
| 2147 | mib->tx_ampdu_cnt += cnt; |
| 2148 | |
| 2149 | cnt = mt76_rr(dev, MT_MIB_SDR13(phy->band_idx)); |
| 2150 | mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); |
| 2151 | |
| 2152 | cnt = mt76_rr(dev, MT_MIB_SDR14(phy->band_idx)); |
| 2153 | mib->tx_mpdu_attempts_cnt += |
| 2154 | FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt); |
| 2155 | |
| 2156 | cnt = mt76_rr(dev, MT_MIB_SDR15(phy->band_idx)); |
| 2157 | mib->tx_mpdu_success_cnt += |
| 2158 | FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt); |
| 2159 | |
| 2160 | cnt = mt76_rr(dev, MT_MIB_SDR22(phy->band_idx)); |
| 2161 | mib->rx_ampdu_cnt += cnt; |
| 2162 | |
| 2163 | cnt = mt76_rr(dev, MT_MIB_SDR23(phy->band_idx)); |
| 2164 | mib->rx_ampdu_bytes_cnt += cnt; |
| 2165 | |
| 2166 | cnt = mt76_rr(dev, MT_MIB_SDR24(phy->band_idx)); |
| 2167 | mib->rx_ampdu_valid_subframe_cnt += |
| 2168 | FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt); |
| 2169 | |
| 2170 | cnt = mt76_rr(dev, MT_MIB_SDR25(phy->band_idx)); |
| 2171 | mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; |
| 2172 | |
| 2173 | cnt = mt76_rr(dev, MT_MIB_SDR27(phy->band_idx)); |
| 2174 | mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); |
| 2175 | |
| 2176 | cnt = mt76_rr(dev, MT_MIB_SDR28(phy->band_idx)); |
| 2177 | mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); |
| 2178 | |
| 2179 | cnt = mt76_rr(dev, MT_MIB_SDR29(phy->band_idx)); |
| 2180 | mib->rx_pfdrop_cnt += |
| 2181 | FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt); |
| 2182 | |
| 2183 | cnt = mt76_rr(dev, MT_MIB_SDRVEC(phy->band_idx)); |
| 2184 | mib->rx_vec_queue_overflow_drop_cnt += |
| 2185 | FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt); |
| 2186 | |
| 2187 | cnt = mt76_rr(dev, MT_MIB_SDR31(phy->band_idx)); |
| 2188 | mib->rx_ba_cnt += cnt; |
| 2189 | |
| 2190 | cnt = mt76_rr(dev, MT_MIB_SDR32(phy->band_idx)); |
| 2191 | mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK, cnt); |
| 2192 | mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT_MASK, cnt); |
| 2193 | |
| 2194 | cnt = mt76_rr(dev, MT_MIB_SDRMUBF(phy->band_idx)); |
| 2195 | mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); |
| 2196 | |
| 2197 | cnt = mt76_rr(dev, MT_MIB_DR8(phy->band_idx)); |
| 2198 | mib->tx_mu_mpdu_cnt += cnt; |
| 2199 | |
| 2200 | cnt = mt76_rr(dev, MT_MIB_DR9(phy->band_idx)); |
| 2201 | mib->tx_mu_acked_mpdu_cnt += cnt; |
| 2202 | |
| 2203 | cnt = mt76_rr(dev, MT_MIB_DR11(phy->band_idx)); |
| 2204 | mib->tx_su_acked_mpdu_cnt += cnt; |
| 2205 | |
| 2206 | cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(phy->band_idx)); |
| 2207 | mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); |
| 2208 | mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); |
| 2209 | |
| 2210 | cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(phy->band_idx)); |
| 2211 | mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); |
| 2212 | mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); |
| 2213 | mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); |
| 2214 | mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); |
| 2215 | |
| 2216 | cnt = mt76_rr(dev, MT_ETBF_RX_FB_CONT(phy->band_idx)); |
| 2217 | mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_RX_FB_BW, cnt); |
| 2218 | mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_RX_FB_NC, cnt); |
| 2219 | mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_RX_FB_NR, cnt); |
| 2220 | |
| 2221 | cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(phy->band_idx)); |
| 2222 | mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); |
| 2223 | mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); |
| 2224 | |
| 2225 | for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { |
| 2226 | cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); |
| 2227 | mib->tx_amsdu[i] += cnt; |
| 2228 | mib->tx_amsdu_cnt += cnt; |
| 2229 | } |
| 2230 | |
| 2231 | aggr0 = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; |
| 2232 | for (i = 0; i < 2; i++) { |
| 2233 | /* rts count */ |
| 2234 | val = mt76_rr(dev, MT_MIB_MB_SDR0(phy->band_idx, (i << 2))); |
| 2235 | mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); |
| 2236 | mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); |
| 2237 | |
| 2238 | /* rts retry count */ |
| 2239 | val = mt76_rr(dev, MT_MIB_MB_SDR1(phy->band_idx, (i << 2))); |
| 2240 | mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); |
| 2241 | mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); |
| 2242 | |
| 2243 | /* ba miss count */ |
| 2244 | val = mt76_rr(dev, MT_MIB_MB_SDR2(phy->band_idx, (i << 2))); |
| 2245 | mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); |
| 2246 | mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); |
| 2247 | |
| 2248 | /* ack fail count */ |
| 2249 | val = mt76_rr(dev, MT_MIB_MB_BFTF(phy->band_idx, (i << 2))); |
| 2250 | mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); |
| 2251 | mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); |
| 2252 | } |
| 2253 | |
| 2254 | for (i = 0; i < 8; i++) { |
| 2255 | val = mt76_rr(dev, MT_TX_AGG_CNT(phy->band_idx, i)); |
| 2256 | dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); |
| 2257 | dev->mt76.aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); |
| 2258 | } |
| 2259 | } |
| 2260 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2261 | void besra_mac_sta_rc_work(struct work_struct *work) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2262 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2263 | struct besra_dev *dev = container_of(work, struct besra_dev, rc_work); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2264 | struct ieee80211_sta *sta; |
| 2265 | struct ieee80211_vif *vif; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2266 | struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2267 | u32 changed; |
| 2268 | LIST_HEAD(list); |
| 2269 | |
| 2270 | spin_lock_bh(&dev->sta_poll_lock); |
| 2271 | list_splice_init(&dev->sta_rc_list, &list); |
| 2272 | |
| 2273 | while (!list_empty(&list)) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2274 | msta = list_first_entry(&list, struct besra_sta, rc_list); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2275 | list_del_init(&msta->rc_list); |
| 2276 | changed = msta->changed; |
| 2277 | msta->changed = 0; |
| 2278 | spin_unlock_bh(&dev->sta_poll_lock); |
| 2279 | |
| 2280 | sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); |
| 2281 | vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); |
| 2282 | |
| 2283 | if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | |
| 2284 | IEEE80211_RC_NSS_CHANGED | |
| 2285 | IEEE80211_RC_BW_CHANGED)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2286 | besra_mcu_add_rate_ctrl(dev, vif, sta, true); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2287 | |
| 2288 | if (changed & IEEE80211_RC_SMPS_CHANGED) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2289 | besra_mcu_add_smps(dev, vif, sta); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2290 | |
| 2291 | spin_lock_bh(&dev->sta_poll_lock); |
| 2292 | } |
| 2293 | |
| 2294 | spin_unlock_bh(&dev->sta_poll_lock); |
| 2295 | } |
| 2296 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2297 | void besra_mac_work(struct work_struct *work) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2298 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2299 | struct besra_phy *phy; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2300 | struct mt76_phy *mphy; |
| 2301 | |
| 2302 | mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, |
| 2303 | mac_work.work); |
| 2304 | phy = mphy->priv; |
| 2305 | |
| 2306 | mutex_lock(&mphy->dev->mutex); |
| 2307 | |
| 2308 | /* TODO: to be checked */ |
| 2309 | /* mt76_update_survey(mphy); */ |
| 2310 | /* if (++mphy->mac_work_count == 5) { */ |
| 2311 | /* mphy->mac_work_count = 0; */ |
| 2312 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2313 | /* besra_mac_update_stats(phy); */ |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2314 | /* } */ |
| 2315 | |
| 2316 | mutex_unlock(&mphy->dev->mutex); |
| 2317 | |
| 2318 | mt76_tx_status_check(mphy->dev, false); |
| 2319 | |
| 2320 | ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2321 | BESRA_WATCHDOG_TIME); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2322 | } |
| 2323 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2324 | static void besra_dfs_stop_radar_detector(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2325 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2326 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2327 | |
| 2328 | if (phy->rdd_state & BIT(0)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2329 | besra_mcu_rdd_cmd(dev, RDD_STOP, 0, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2330 | MT_RX_SEL0, 0); |
| 2331 | if (phy->rdd_state & BIT(1)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2332 | besra_mcu_rdd_cmd(dev, RDD_STOP, 1, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2333 | MT_RX_SEL0, 0); |
| 2334 | } |
| 2335 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2336 | static int besra_dfs_start_rdd(struct besra_dev *dev, int chain) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2337 | { |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 2338 | int err, region; |
| 2339 | |
| 2340 | switch (dev->mt76.region) { |
| 2341 | case NL80211_DFS_ETSI: |
| 2342 | region = 0; |
| 2343 | break; |
| 2344 | case NL80211_DFS_JP: |
| 2345 | region = 2; |
| 2346 | break; |
| 2347 | case NL80211_DFS_FCC: |
| 2348 | default: |
| 2349 | region = 1; |
| 2350 | break; |
| 2351 | } |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2352 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2353 | err = besra_mcu_rdd_cmd(dev, RDD_START, chain, |
developer | 66cd209 | 2022-05-10 15:43:01 +0800 | [diff] [blame] | 2354 | MT_RX_SEL0, region); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2355 | if (err < 0) |
| 2356 | return err; |
| 2357 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2358 | return besra_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2359 | MT_RX_SEL0, 1); |
| 2360 | } |
| 2361 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2362 | static int besra_dfs_start_radar_detector(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2363 | { |
| 2364 | struct cfg80211_chan_def *chandef = &phy->mt76->chandef; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2365 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2366 | int err; |
| 2367 | |
| 2368 | /* start CAC */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2369 | err = besra_mcu_rdd_cmd(dev, RDD_CAC_START, phy->band_idx, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2370 | MT_RX_SEL0, 0); |
| 2371 | if (err < 0) |
| 2372 | return err; |
| 2373 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2374 | err = besra_dfs_start_rdd(dev, phy->band_idx); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2375 | if (err < 0) |
| 2376 | return err; |
| 2377 | |
| 2378 | phy->rdd_state |= BIT(phy->band_idx); |
| 2379 | |
| 2380 | if (is_mt7916(&dev->mt76)) |
| 2381 | return 0; |
| 2382 | |
| 2383 | if (chandef->width == NL80211_CHAN_WIDTH_160 || |
| 2384 | chandef->width == NL80211_CHAN_WIDTH_80P80) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2385 | err = besra_dfs_start_rdd(dev, 1); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2386 | if (err < 0) |
| 2387 | return err; |
| 2388 | |
| 2389 | phy->rdd_state |= BIT(1); |
| 2390 | } |
| 2391 | |
| 2392 | return 0; |
| 2393 | } |
| 2394 | |
| 2395 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2396 | besra_dfs_init_radar_specs(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2397 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2398 | const struct besra_dfs_radar_spec *radar_specs; |
| 2399 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2400 | int err, i; |
| 2401 | |
| 2402 | switch (dev->mt76.region) { |
| 2403 | case NL80211_DFS_FCC: |
| 2404 | radar_specs = &fcc_radar_specs; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2405 | err = besra_mcu_set_fcc5_lpn(dev, 8); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2406 | if (err < 0) |
| 2407 | return err; |
| 2408 | break; |
| 2409 | case NL80211_DFS_ETSI: |
| 2410 | radar_specs = &etsi_radar_specs; |
| 2411 | break; |
| 2412 | case NL80211_DFS_JP: |
| 2413 | radar_specs = &jp_radar_specs; |
| 2414 | break; |
| 2415 | default: |
| 2416 | return -EINVAL; |
| 2417 | } |
| 2418 | |
| 2419 | for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2420 | err = besra_mcu_set_radar_th(dev, i, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2421 | &radar_specs->radar_pattern[i]); |
| 2422 | if (err < 0) |
| 2423 | return err; |
| 2424 | } |
| 2425 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2426 | return besra_mcu_set_pulse_th(dev, &radar_specs->pulse_th); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2427 | } |
| 2428 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2429 | int besra_dfs_init_radar_detector(struct besra_phy *phy) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2430 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2431 | struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2432 | enum mt76_dfs_state dfs_state, prev_state; |
| 2433 | int err; |
| 2434 | |
| 2435 | prev_state = phy->mt76->dfs_state; |
| 2436 | dfs_state = mt76_phy_dfs_state(phy->mt76); |
| 2437 | |
| 2438 | if (prev_state == dfs_state) |
| 2439 | return 0; |
| 2440 | |
| 2441 | if (prev_state == MT_DFS_STATE_UNKNOWN) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2442 | besra_dfs_stop_radar_detector(phy); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2443 | |
| 2444 | if (dfs_state == MT_DFS_STATE_DISABLED) |
| 2445 | goto stop; |
| 2446 | |
| 2447 | if (prev_state <= MT_DFS_STATE_DISABLED) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2448 | err = besra_dfs_init_radar_specs(phy); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2449 | if (err < 0) |
| 2450 | return err; |
| 2451 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2452 | err = besra_dfs_start_radar_detector(phy); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2453 | if (err < 0) |
| 2454 | return err; |
| 2455 | |
| 2456 | phy->mt76->dfs_state = MT_DFS_STATE_CAC; |
| 2457 | } |
| 2458 | |
| 2459 | if (dfs_state == MT_DFS_STATE_CAC) |
| 2460 | return 0; |
| 2461 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2462 | err = besra_mcu_rdd_cmd(dev, RDD_CAC_END, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2463 | phy->band_idx, MT_RX_SEL0, 0); |
| 2464 | if (err < 0) { |
| 2465 | phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; |
| 2466 | return err; |
| 2467 | } |
| 2468 | |
| 2469 | phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; |
| 2470 | return 0; |
| 2471 | |
| 2472 | stop: |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2473 | err = besra_mcu_rdd_cmd(dev, RDD_NORMAL_START, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2474 | phy->band_idx, MT_RX_SEL0, 0); |
| 2475 | if (err < 0) |
| 2476 | return err; |
| 2477 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2478 | besra_dfs_stop_radar_detector(phy); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2479 | phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; |
| 2480 | |
| 2481 | return 0; |
| 2482 | } |
| 2483 | |
| 2484 | static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2485 | besra_mac_twt_duration_align(int duration) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2486 | { |
| 2487 | return duration << 8; |
| 2488 | } |
| 2489 | |
| 2490 | static u64 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2491 | besra_mac_twt_sched_list_add(struct besra_dev *dev, |
| 2492 | struct besra_twt_flow *flow) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2493 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2494 | struct besra_twt_flow *iter, *iter_next; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2495 | u32 duration = flow->duration << 8; |
| 2496 | u64 start_tsf; |
| 2497 | |
| 2498 | iter = list_first_entry_or_null(&dev->twt_list, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2499 | struct besra_twt_flow, list); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2500 | if (!iter || !iter->sched || iter->start_tsf > duration) { |
| 2501 | /* add flow as first entry in the list */ |
| 2502 | list_add(&flow->list, &dev->twt_list); |
| 2503 | return 0; |
| 2504 | } |
| 2505 | |
| 2506 | list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { |
| 2507 | start_tsf = iter->start_tsf + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2508 | besra_mac_twt_duration_align(iter->duration); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2509 | if (list_is_last(&iter->list, &dev->twt_list)) |
| 2510 | break; |
| 2511 | |
| 2512 | if (!iter_next->sched || |
| 2513 | iter_next->start_tsf > start_tsf + duration) { |
| 2514 | list_add(&flow->list, &iter->list); |
| 2515 | goto out; |
| 2516 | } |
| 2517 | } |
| 2518 | |
| 2519 | /* add flow as last entry in the list */ |
| 2520 | list_add_tail(&flow->list, &dev->twt_list); |
| 2521 | out: |
| 2522 | return start_tsf; |
| 2523 | } |
| 2524 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2525 | static int besra_mac_check_twt_req(struct ieee80211_twt_setup *twt) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2526 | { |
| 2527 | struct ieee80211_twt_params *twt_agrt; |
| 2528 | u64 interval, duration; |
| 2529 | u16 mantissa; |
| 2530 | u8 exp; |
| 2531 | |
| 2532 | /* only individual agreement supported */ |
| 2533 | if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) |
| 2534 | return -EOPNOTSUPP; |
| 2535 | |
| 2536 | /* only 256us unit supported */ |
| 2537 | if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) |
| 2538 | return -EOPNOTSUPP; |
| 2539 | |
| 2540 | twt_agrt = (struct ieee80211_twt_params *)twt->params; |
| 2541 | |
| 2542 | /* explicit agreement not supported */ |
| 2543 | if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) |
| 2544 | return -EOPNOTSUPP; |
| 2545 | |
| 2546 | exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, |
| 2547 | le16_to_cpu(twt_agrt->req_type)); |
| 2548 | mantissa = le16_to_cpu(twt_agrt->mantissa); |
| 2549 | duration = twt_agrt->min_twt_dur << 8; |
| 2550 | |
| 2551 | interval = (u64)mantissa << exp; |
| 2552 | if (interval < duration) |
| 2553 | return -EOPNOTSUPP; |
| 2554 | |
| 2555 | return 0; |
| 2556 | } |
| 2557 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2558 | void besra_mac_add_twt_setup(struct ieee80211_hw *hw, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2559 | struct ieee80211_sta *sta, |
| 2560 | struct ieee80211_twt_setup *twt) |
| 2561 | { |
| 2562 | enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2563 | struct besra_sta *msta = (struct besra_sta *)sta->drv_priv; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2564 | struct ieee80211_twt_params *twt_agrt = (void *)twt->params; |
| 2565 | u16 req_type = le16_to_cpu(twt_agrt->req_type); |
| 2566 | enum ieee80211_twt_setup_cmd sta_setup_cmd; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2567 | struct besra_dev *dev = besra_hw_dev(hw); |
| 2568 | struct besra_twt_flow *flow; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2569 | int flowid, table_id; |
| 2570 | u8 exp; |
| 2571 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2572 | if (besra_mac_check_twt_req(twt)) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2573 | goto out; |
| 2574 | |
| 2575 | mutex_lock(&dev->mt76.mutex); |
| 2576 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2577 | if (dev->twt.n_agrt == BESRA_MAX_TWT_AGRT) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2578 | goto unlock; |
| 2579 | |
| 2580 | if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) |
| 2581 | goto unlock; |
| 2582 | |
| 2583 | flowid = ffs(~msta->twt.flowid_mask) - 1; |
| 2584 | le16p_replace_bits(&twt_agrt->req_type, flowid, |
| 2585 | IEEE80211_TWT_REQTYPE_FLOWID); |
| 2586 | |
| 2587 | table_id = ffs(~dev->twt.table_mask) - 1; |
| 2588 | exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); |
| 2589 | sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); |
| 2590 | |
| 2591 | flow = &msta->twt.flow[flowid]; |
| 2592 | memset(flow, 0, sizeof(*flow)); |
| 2593 | INIT_LIST_HEAD(&flow->list); |
| 2594 | flow->wcid = msta->wcid.idx; |
| 2595 | flow->table_id = table_id; |
| 2596 | flow->id = flowid; |
| 2597 | flow->duration = twt_agrt->min_twt_dur; |
| 2598 | flow->mantissa = twt_agrt->mantissa; |
| 2599 | flow->exp = exp; |
| 2600 | flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); |
| 2601 | flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); |
| 2602 | flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); |
| 2603 | |
| 2604 | if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || |
| 2605 | sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { |
| 2606 | u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; |
| 2607 | u64 flow_tsf, curr_tsf; |
| 2608 | u32 rem; |
| 2609 | |
| 2610 | flow->sched = true; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2611 | flow->start_tsf = besra_mac_twt_sched_list_add(dev, flow); |
| 2612 | curr_tsf = __besra_get_tsf(hw, msta->vif); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2613 | div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); |
| 2614 | flow_tsf = curr_tsf + interval - rem; |
| 2615 | twt_agrt->twt = cpu_to_le64(flow_tsf); |
| 2616 | } else { |
| 2617 | list_add_tail(&flow->list, &dev->twt_list); |
| 2618 | } |
| 2619 | flow->tsf = le64_to_cpu(twt_agrt->twt); |
| 2620 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2621 | if (besra_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2622 | goto unlock; |
| 2623 | |
| 2624 | setup_cmd = TWT_SETUP_CMD_ACCEPT; |
| 2625 | dev->twt.table_mask |= BIT(table_id); |
| 2626 | msta->twt.flowid_mask |= BIT(flowid); |
| 2627 | dev->twt.n_agrt++; |
| 2628 | |
| 2629 | unlock: |
| 2630 | mutex_unlock(&dev->mt76.mutex); |
| 2631 | out: |
| 2632 | le16p_replace_bits(&twt_agrt->req_type, setup_cmd, |
| 2633 | IEEE80211_TWT_REQTYPE_SETUP_CMD); |
| 2634 | twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | |
| 2635 | (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); |
| 2636 | } |
| 2637 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2638 | void besra_mac_twt_teardown_flow(struct besra_dev *dev, |
| 2639 | struct besra_sta *msta, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2640 | u8 flowid) |
| 2641 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2642 | struct besra_twt_flow *flow; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2643 | |
| 2644 | lockdep_assert_held(&dev->mt76.mutex); |
| 2645 | |
| 2646 | if (flowid >= ARRAY_SIZE(msta->twt.flow)) |
| 2647 | return; |
| 2648 | |
| 2649 | if (!(msta->twt.flowid_mask & BIT(flowid))) |
| 2650 | return; |
| 2651 | |
| 2652 | flow = &msta->twt.flow[flowid]; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 2653 | if (besra_mcu_twt_agrt_update(dev, msta->vif, flow, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2654 | MCU_TWT_AGRT_DELETE)) |
| 2655 | return; |
| 2656 | |
| 2657 | list_del_init(&flow->list); |
| 2658 | msta->twt.flowid_mask &= ~BIT(flowid); |
| 2659 | dev->twt.table_mask &= ~BIT(flow->table_id); |
| 2660 | dev->twt.n_agrt--; |
| 2661 | } |