developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | /* Copyright (C) 2020 MediaTek Inc. */ |
| 3 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4 | #include "besra.h" |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5 | #include "../dma.h" |
| 6 | #include "mac.h" |
| 7 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 8 | int besra_init_tx_queues(struct besra_phy *phy, int idx, int n_desc, int ring_base) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 9 | { |
| 10 | int i, err; |
| 11 | |
| 12 | err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base); |
| 13 | if (err < 0) |
| 14 | return err; |
| 15 | |
| 16 | for (i = 0; i <= MT_TXQ_PSD; i++) |
| 17 | phy->mt76->q_tx[i] = phy->mt76->q_tx[0]; |
| 18 | |
| 19 | return 0; |
| 20 | } |
| 21 | |
| 22 | static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 23 | besra_tx_cleanup(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 24 | { |
| 25 | mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); |
| 26 | mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], false); |
| 27 | } |
| 28 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 29 | static int besra_poll_tx(struct napi_struct *napi, int budget) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 30 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 31 | struct besra_dev *dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 32 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 33 | dev = container_of(napi, struct besra_dev, mt76.tx_napi); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 34 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 35 | besra_tx_cleanup(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 36 | |
| 37 | if (napi_complete_done(napi, 0)) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 38 | besra_irq_enable(dev, MT_INT_TX_DONE_MCU); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 39 | |
| 40 | return 0; |
| 41 | } |
| 42 | |
| 43 | #define Q_CONFIG(q, wfdma, int, id) do { \ |
| 44 | if (wfdma) \ |
| 45 | dev->wfdma_mask |= (1 << (q)); \ |
| 46 | dev->q_int_mask[(q)] = int; \ |
| 47 | dev->q_id[(q)] = id; \ |
| 48 | } while (0) |
| 49 | |
| 50 | #define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id)) |
| 51 | #define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id)) |
| 52 | #define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id)) |
| 53 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 54 | static void besra_dma_config(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 55 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 56 | RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, BESRA_RXQ_BAND0); |
| 57 | RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, BESRA_RXQ_MCU_WM); |
| 58 | RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, BESRA_RXQ_MCU_WA); |
| 59 | RXQ_CONFIG(MT_RXQ_EXT, WFDMA0, MT_INT_RX_DONE_BAND1, BESRA_RXQ_BAND1); |
| 60 | RXQ_CONFIG(MT_RXQ_EXT_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT, BESRA_RXQ_MCU_WA_EXT); |
| 61 | RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, BESRA_RXQ_MCU_WA_MAIN); |
| 62 | RXQ_CONFIG(MT_RXQ_TRI, WFDMA0, MT_INT_RX_DONE_BAND2, BESRA_RXQ_BAND2); |
| 63 | RXQ_CONFIG(MT_RXQ_TRI_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, BESRA_RXQ_MCU_WA_TRI); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 64 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 65 | TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, BESRA_TXQ_BAND0); |
| 66 | TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, BESRA_TXQ_BAND1); |
| 67 | TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, BESRA_TXQ_BAND2); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 68 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 69 | MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, BESRA_TXQ_MCU_WM); |
| 70 | MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA, BESRA_TXQ_MCU_WA); |
| 71 | MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, BESRA_TXQ_FWDL); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 72 | } |
| 73 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 74 | static void __besra_dma_prefetch(struct besra_dev *dev, u32 ofs) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 75 | { |
| 76 | #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) |
| 77 | |
| 78 | /* prefetch SRAM wrapping boundary for tx/rx ring. */ |
| 79 | mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x4)); |
| 80 | mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x40, 0x4)); |
| 81 | mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x80, 0x4)); |
| 82 | mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0xc0, 0x4)); |
| 83 | mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x100, 0x4)); |
| 84 | mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0x140, 0x4)); |
| 85 | |
| 86 | mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x180, 0x4)); |
| 87 | mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x1c0, 0x4)); |
| 88 | //mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x1c0, 0x4)); |
| 89 | mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT_WA) + ofs, PREFETCH(0x200, 0x4)); |
| 90 | mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x240, 0x4)); |
| 91 | mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_EXT) + ofs, PREFETCH(0x280, 0x4)); |
| 92 | mt76_wr(dev, MT_RXQ_EXT_CTRL(MT_RXQ_TRI) + ofs, PREFETCH(0x2c0, 0x4)); |
| 93 | } |
| 94 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 95 | void besra_dma_prefetch(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 96 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 97 | __besra_dma_prefetch(dev, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 98 | if (dev->hif2) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 99 | __besra_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 100 | } |
| 101 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 102 | static void besra_dma_disable(struct besra_dev *dev, bool rst) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 103 | { |
| 104 | u32 hif1_ofs = 0; |
| 105 | |
| 106 | if (dev->hif2) |
| 107 | hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 108 | |
| 109 | /* reset */ |
| 110 | if (rst) { |
| 111 | mt76_clear(dev, MT_WFDMA0_RST, |
| 112 | MT_WFDMA0_RST_DMASHDL_ALL_RST | |
| 113 | MT_WFDMA0_RST_LOGIC_RST); |
| 114 | |
| 115 | mt76_set(dev, MT_WFDMA0_RST, |
| 116 | MT_WFDMA0_RST_DMASHDL_ALL_RST | |
| 117 | MT_WFDMA0_RST_LOGIC_RST); |
| 118 | |
| 119 | if (dev->hif2) { |
| 120 | mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs, |
| 121 | MT_WFDMA0_RST_DMASHDL_ALL_RST | |
| 122 | MT_WFDMA0_RST_LOGIC_RST); |
| 123 | |
| 124 | mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, |
| 125 | MT_WFDMA0_RST_DMASHDL_ALL_RST | |
| 126 | MT_WFDMA0_RST_LOGIC_RST); |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | /* disable */ |
| 131 | mt76_clear(dev, MT_WFDMA0_GLO_CFG, |
| 132 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 133 | MT_WFDMA0_GLO_CFG_RX_DMA_EN | |
| 134 | MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | |
| 135 | MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | |
| 136 | MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); |
| 137 | |
| 138 | if (dev->hif2) { |
| 139 | mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, |
| 140 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 141 | MT_WFDMA0_GLO_CFG_RX_DMA_EN | |
| 142 | MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | |
| 143 | MT_WFDMA0_GLO_CFG_OMIT_RX_INFO | |
| 144 | MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); |
| 145 | } |
| 146 | } |
| 147 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 148 | static int besra_dma_enable(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 149 | { |
| 150 | u32 hif1_ofs = 0; |
| 151 | u32 irq_mask; |
| 152 | |
| 153 | if (dev->hif2) |
| 154 | hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 155 | |
| 156 | /* reset dma idx */ |
| 157 | mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); |
| 158 | if (dev->hif2) |
| 159 | mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); |
| 160 | |
| 161 | /* configure delay interrupt off */ |
| 162 | mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); |
| 163 | mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0); |
| 164 | mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0); |
| 165 | |
| 166 | if (dev->hif2) { |
| 167 | mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); |
| 168 | mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0); |
| 169 | mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0); |
| 170 | } |
| 171 | |
| 172 | /* configure perfetch settings */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 173 | besra_dma_prefetch(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 174 | |
| 175 | /* hif wait WFDMA idle */ |
| 176 | mt76_set(dev, MT_WFDMA0_BUSY_ENA, |
| 177 | MT_WFDMA0_BUSY_ENA_TX_FIFO0 | |
| 178 | MT_WFDMA0_BUSY_ENA_TX_FIFO1 | |
| 179 | MT_WFDMA0_BUSY_ENA_RX_FIFO); |
| 180 | |
| 181 | if (dev->hif2) |
| 182 | mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs, |
| 183 | MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 | |
| 184 | MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 | |
| 185 | MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO); |
| 186 | |
| 187 | mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, |
| 188 | MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000); |
| 189 | |
| 190 | /* set WFDMA Tx/Rx */ |
| 191 | mt76_set(dev, MT_WFDMA0_GLO_CFG, |
| 192 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 193 | MT_WFDMA0_GLO_CFG_RX_DMA_EN | |
| 194 | MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | |
| 195 | MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); |
| 196 | |
| 197 | if (dev->hif2) { |
| 198 | mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, |
| 199 | MT_WFDMA0_GLO_CFG_TX_DMA_EN | |
| 200 | MT_WFDMA0_GLO_CFG_RX_DMA_EN | |
| 201 | MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | |
| 202 | MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); |
| 203 | |
| 204 | mt76_set(dev, MT_WFDMA_HOST_CONFIG, |
| 205 | MT_WFDMA_HOST_CONFIG_PDMA_BAND); |
| 206 | } |
| 207 | |
| 208 | /* enable interrupts for TX/RX rings */ |
| 209 | irq_mask = MT_INT_RX_DONE_MCU | |
| 210 | MT_INT_TX_DONE_MCU | |
| 211 | MT_INT_MCU_CMD; |
| 212 | |
| 213 | if (!dev->phy.band_idx) |
| 214 | irq_mask |= MT_INT_BAND0_RX_DONE; |
| 215 | |
| 216 | if (dev->dbdc_support) |
| 217 | irq_mask |= MT_INT_BAND1_RX_DONE; |
| 218 | |
| 219 | if (dev->tbtc_support) |
| 220 | irq_mask |= MT_INT_BAND2_RX_DONE; |
| 221 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 222 | besra_irq_enable(dev, irq_mask); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 223 | |
| 224 | return 0; |
| 225 | } |
| 226 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 227 | int besra_dma_init(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 228 | { |
| 229 | u32 hif1_ofs = 0; |
| 230 | int ret; |
| 231 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 232 | besra_dma_config(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 233 | |
| 234 | mt76_dma_attach(&dev->mt76); |
| 235 | |
| 236 | if (dev->hif2) |
| 237 | hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 238 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 239 | besra_dma_disable(dev, true); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 240 | |
| 241 | /* init tx queue */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 242 | ret = besra_init_tx_queues(&dev->phy, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 243 | MT_TXQ_ID(dev->phy.band_idx), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 244 | BESRA_TX_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 245 | MT_TXQ_RING_BASE(0)); |
| 246 | if (ret) |
| 247 | return ret; |
| 248 | |
| 249 | /* command to WM */ |
| 250 | ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, |
| 251 | MT_MCUQ_ID(MT_MCUQ_WM), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 252 | BESRA_TX_MCU_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 253 | MT_MCUQ_RING_BASE(MT_MCUQ_WM)); |
| 254 | if (ret) |
| 255 | return ret; |
| 256 | |
| 257 | /* command to WA */ |
| 258 | ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, |
| 259 | MT_MCUQ_ID(MT_MCUQ_WA), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 260 | BESRA_TX_MCU_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 261 | MT_MCUQ_RING_BASE(MT_MCUQ_WA)); |
| 262 | if (ret) |
| 263 | return ret; |
| 264 | |
| 265 | /* firmware download */ |
| 266 | ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, |
| 267 | MT_MCUQ_ID(MT_MCUQ_FWDL), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 268 | BESRA_TX_FWDL_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 269 | MT_MCUQ_RING_BASE(MT_MCUQ_FWDL)); |
| 270 | if (ret) |
| 271 | return ret; |
| 272 | |
| 273 | /* event from WM */ |
| 274 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], |
| 275 | MT_RXQ_ID(MT_RXQ_MCU), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 276 | BESRA_RX_MCU_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 277 | MT_RX_BUF_SIZE, |
| 278 | MT_RXQ_RING_BASE(MT_RXQ_MCU)); |
| 279 | if (ret) |
| 280 | return ret; |
| 281 | |
| 282 | /* event from WA */ |
| 283 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], |
| 284 | MT_RXQ_ID(MT_RXQ_MCU_WA), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 285 | BESRA_RX_MCU_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 286 | MT_RX_BUF_SIZE, |
| 287 | MT_RXQ_RING_BASE(MT_RXQ_MCU_WA)); |
| 288 | if (ret) |
| 289 | return ret; |
| 290 | |
| 291 | /* rx data queue for band0 */ |
| 292 | if (!dev->phy.band_idx) { |
| 293 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], |
| 294 | MT_RXQ_ID(MT_RXQ_MAIN), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 295 | BESRA_RX_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 296 | MT_RX_BUF_SIZE, |
| 297 | MT_RXQ_RING_BASE(MT_RXQ_MAIN)); |
| 298 | if (ret) |
| 299 | return ret; |
| 300 | } |
| 301 | |
| 302 | /* tx free notify event from WA for band0 */ |
| 303 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], |
| 304 | MT_RXQ_ID(MT_RXQ_MAIN_WA), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 305 | BESRA_RX_MCU_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 306 | MT_RX_BUF_SIZE, |
| 307 | MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA)); |
| 308 | if (ret) |
| 309 | return ret; |
| 310 | |
| 311 | if (dev->dbdc_support || (dev->phy.band_idx == MT_BAND1)) { |
| 312 | /* rx data queue for band1 */ |
| 313 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT], |
| 314 | MT_RXQ_ID(MT_RXQ_EXT), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 315 | BESRA_RX_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 316 | MT_RX_BUF_SIZE, |
| 317 | MT_RXQ_RING_BASE(MT_RXQ_EXT) + hif1_ofs); |
| 318 | if (ret) |
| 319 | return ret; |
| 320 | |
| 321 | /* tx free notify event from WA for band1 */ |
| 322 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_EXT_WA], |
| 323 | MT_RXQ_ID(MT_RXQ_EXT_WA), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 324 | BESRA_RX_MCU_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 325 | MT_RX_BUF_SIZE, |
| 326 | MT_RXQ_RING_BASE(MT_RXQ_EXT_WA) + hif1_ofs); |
| 327 | if (ret) |
| 328 | return ret; |
| 329 | } |
| 330 | |
| 331 | if (dev->tbtc_support || (dev->phy.band_idx == MT_BAND2)) { |
| 332 | /* rx data queue for band2 */ |
| 333 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TRI], |
| 334 | MT_RXQ_ID(MT_RXQ_TRI), |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 335 | BESRA_RX_RING_SIZE, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 336 | MT_RX_BUF_SIZE, |
| 337 | MT_RXQ_RING_BASE(MT_RXQ_TRI) + hif1_ofs); |
| 338 | if (ret) |
| 339 | return ret; |
| 340 | } |
| 341 | |
| 342 | ret = mt76_init_queues(dev, mt76_dma_rx_poll); |
| 343 | if (ret < 0) |
| 344 | return ret; |
| 345 | |
| 346 | netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 347 | besra_poll_tx, NAPI_POLL_WEIGHT); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 348 | napi_enable(&dev->mt76.tx_napi); |
| 349 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 350 | besra_dma_enable(dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 351 | |
| 352 | return 0; |
| 353 | } |
| 354 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 355 | void besra_dma_cleanup(struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 356 | { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 357 | besra_dma_disable(dev, true); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 358 | |
| 359 | mt76_dma_cleanup(&dev->mt76); |
| 360 | } |