developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 1 | From 650cb1ed09a37bcb426ec5f27ae0e65f1d65df94 Mon Sep 17 00:00:00 2001 |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 2 | From: Shayne Chen <shayne.chen@mediatek.com> |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 3 | Date: Mon, 9 May 2022 15:12:22 +0800 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4 | Subject: [PATCH] mt76: besra: add internal debug patch |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7 | besra/Makefile | 5 +- |
| 8 | besra/besra.h | 35 + |
| 9 | besra/debugfs.c | 25 +- |
| 10 | besra/mac.c | 18 + |
| 11 | besra/mcu.c | 4 + |
| 12 | besra/mtk_debug.h | 3716 +++++++++++++++++++++++++++++++++++++++++++ |
| 13 | besra/mtk_debugfs.c | 3576 +++++++++++++++++++++++++++++++++++++++++ |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 14 | tools/fwlog.c | 25 +- |
| 15 | 8 files changed, 7393 insertions(+), 11 deletions(-) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 16 | mode change 100755 => 100644 besra/Makefile |
| 17 | create mode 100644 besra/mtk_debug.h |
| 18 | create mode 100644 besra/mtk_debugfs.c |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 19 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 20 | diff --git a/besra/Makefile b/besra/Makefile |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 21 | old mode 100755 |
| 22 | new mode 100644 |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 23 | index a51abe0c..edb7800a |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 24 | --- a/besra/Makefile |
| 25 | +++ b/besra/Makefile |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 26 | @@ -1,8 +1,11 @@ |
| 27 | # SPDX-License-Identifier: ISC |
| 28 | +EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG |
| 29 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 30 | obj-$(CONFIG_BESRA) += besra.o |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 31 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 32 | besra-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \ |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 33 | debugfs.o mmio.o |
| 34 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 35 | -besra-$(CONFIG_NL80211_TESTMODE) += testmode.o |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 36 | \ No newline at end of file |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 37 | +besra-$(CONFIG_NL80211_TESTMODE) += testmode.o |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 38 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 39 | +besra-y += mtk_debugfs.o |
| 40 | diff --git a/besra/besra.h b/besra/besra.h |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 41 | index 63a97363..30c3a79b 100644 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 42 | --- a/besra/besra.h |
| 43 | +++ b/besra/besra.h |
| 44 | @@ -301,6 +301,23 @@ struct besra_dev { |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 45 | u8 table_mask; |
| 46 | u8 n_agrt; |
| 47 | } twt; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 48 | + |
| 49 | +#ifdef CONFIG_MTK_DEBUG |
| 50 | + u16 wlan_idx; |
| 51 | + struct { |
| 52 | + bool dump_mcu_pkt; |
| 53 | + bool dump_txd; |
| 54 | + bool dump_tx_pkt; |
| 55 | + bool dump_rx_pkt; |
| 56 | + bool dump_rx_raw; |
| 57 | + u32 fw_dbg_module; |
| 58 | + u8 fw_dbg_lv; |
| 59 | + u32 bcn_total_cnt[__MT_MAX_BAND]; |
| 60 | + u32 token_idx; |
| 61 | + u32 rxd_read_cnt; |
| 62 | + u32 txd_read_cnt; |
| 63 | + } dbg; |
| 64 | +#endif |
| 65 | }; |
| 66 | |
| 67 | enum { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 68 | @@ -571,4 +588,22 @@ void besra_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 69 | struct ieee80211_sta *sta, struct dentry *dir); |
| 70 | #endif |
| 71 | |
| 72 | +#ifdef CONFIG_MTK_DEBUG |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 73 | +void besra_packet_log_to_host(struct besra_dev *dev, const void *data, int len, int type, int des_len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 74 | + |
| 75 | +#define PKT_BIN_DEBUG_MAGIC 0xc8763123 |
| 76 | +enum { |
| 77 | + PKT_BIN_DEBUG_MCU, |
| 78 | + PKT_BIN_DEBUG_TXD, |
| 79 | + PKT_BIN_DEBUG_TX, |
| 80 | + PKT_BIN_DEBUG_RX, |
| 81 | + PKT_BIN_DEBUG_RX_RAW, |
| 82 | +}; |
| 83 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 84 | +int besra_mtk_init_debugfs(struct besra_phy *phy, struct dentry *dir); |
| 85 | +void besra_dump_bmac_rxd_info(struct besra_dev *dev, __le32 *rxd); |
| 86 | +void besra_dump_bmac_txd_info(struct besra_dev *dev, __le32 *txd, bool dump_txp); |
| 87 | +void besra_dump_bmac_txp_info(struct besra_dev *dev, __le32 *txp); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 88 | +#endif |
| 89 | + |
| 90 | #endif |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 91 | diff --git a/besra/debugfs.c b/besra/debugfs.c |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 92 | index 4be253ea..9f3e11a8 100644 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 93 | --- a/besra/debugfs.c |
| 94 | +++ b/besra/debugfs.c |
| 95 | @@ -371,6 +371,9 @@ besra_fw_debug_wm_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 96 | int ret; |
| 97 | |
| 98 | dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; |
| 99 | +#ifdef CONFIG_MTK_DEBUG |
| 100 | + dev->fw_debug_wm = val; |
| 101 | +#endif |
| 102 | |
| 103 | if (dev->fw_debug_bin) |
| 104 | val = MCU_FW_LOG_RELAY; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 105 | @@ -494,6 +497,16 @@ besra_fw_debug_bin_set(void *data, u64 val) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 106 | |
| 107 | relay_reset(dev->relay_fwlog); |
| 108 | |
| 109 | +#ifdef CONFIG_MTK_DEBUG |
| 110 | + dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false; |
| 111 | + dev->dbg.dump_txd = val & BIT(5) ? true : false; |
| 112 | + dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false; |
| 113 | + dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false; |
| 114 | + dev->dbg.dump_rx_raw = val & BIT(8) ? true : false; |
| 115 | + if (!(val & GENMASK(3, 0))) |
| 116 | + return 0; |
| 117 | +#endif |
| 118 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 119 | return besra_fw_debug_wm_set(dev, dev->fw_debug_wm); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 120 | } |
| 121 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 122 | @@ -942,8 +955,13 @@ int besra_init_debugfs(struct besra_phy *phy) |
| 123 | besra_rdd_monitor); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | - if (phy == &dev->phy) |
| 127 | + if (phy == &dev->phy) { |
| 128 | dev->debugfs_dir = dir; |
| 129 | +#ifdef CONFIG_MTK_DEBUG |
| 130 | + debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 131 | + besra_mtk_init_debugfs(phy, dir); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 132 | +#endif |
| 133 | + } |
| 134 | |
| 135 | return 0; |
| 136 | } |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 137 | @@ -1000,7 +1018,12 @@ void besra_debugfs_rx_fw_monitor(struct besra_dev *dev, const void *data, int le |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 138 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 139 | bool besra_debugfs_rx_log(struct besra_dev *dev, const void *data, int len) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 140 | { |
| 141 | +#ifdef CONFIG_MTK_DEBUG |
| 142 | + if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC && |
| 143 | + get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC) |
| 144 | +#else |
| 145 | if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) |
| 146 | +#endif |
| 147 | return false; |
| 148 | |
| 149 | if (dev->relay_fwlog) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 150 | diff --git a/besra/mac.c b/besra/mac.c |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 151 | index 2d48a1a4..b726e2d8 100644 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 152 | --- a/besra/mac.c |
| 153 | +++ b/besra/mac.c |
| 154 | @@ -589,6 +589,11 @@ besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 155 | int idx; |
| 156 | u8 band_idx; |
| 157 | |
| 158 | +#ifdef CONFIG_MTK_DEBUG |
| 159 | + if (dev->dbg.dump_rx_raw) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 160 | + besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0); |
| 161 | + besra_dump_bmac_rxd_info(dev, rxd); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 162 | +#endif |
| 163 | memset(status, 0, sizeof(*status)); |
| 164 | |
| 165 | band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 166 | @@ -763,6 +768,10 @@ besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; |
| 170 | +#ifdef CONFIG_MTK_DEBUG |
| 171 | + if (dev->dbg.dump_rx_pkt) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 172 | + besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 173 | +#endif |
| 174 | if (hdr_trans && ieee80211_has_morefrags(fc)) { |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 175 | if (besra_reverse_frag0_hdr_trans(skb, hdr_gap)) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 176 | return -EINVAL; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 177 | @@ -1330,6 +1339,15 @@ int besra_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 178 | tx_info->buf[1].skip_unmap = true; |
| 179 | tx_info->nbuf = MT_CT_DMA_BUF_NUM; |
| 180 | |
| 181 | +#ifdef CONFIG_MTK_DEBUG |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 182 | + besra_dump_bmac_txd_info(dev, (__le32 *)txwi, true); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 183 | + |
| 184 | + if (dev->dbg.dump_txd) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 185 | + besra_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 186 | + if (dev->dbg.dump_tx_pkt) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 187 | + besra_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 188 | +#endif |
| 189 | + |
| 190 | return 0; |
| 191 | } |
| 192 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 193 | diff --git a/besra/mcu.c b/besra/mcu.c |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 194 | index 5276552c..6fc175c6 100644 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 195 | --- a/besra/mcu.c |
| 196 | +++ b/besra/mcu.c |
| 197 | @@ -299,6 +299,10 @@ besra_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 198 | mcu_txd->s2d_index = MCU_S2D_H2N; |
| 199 | |
| 200 | exit: |
| 201 | +#ifdef CONFIG_MTK_DEBUG |
| 202 | + if (dev->dbg.dump_mcu_pkt) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 203 | + besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 204 | +#endif |
| 205 | if (wait_seq) |
| 206 | *wait_seq = seq; |
| 207 | |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 208 | diff --git a/besra/mtk_debug.h b/besra/mtk_debug.h |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 209 | new file mode 100644 |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 210 | index 00000000..1a797c81 |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 211 | --- /dev/null |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 212 | +++ b/besra/mtk_debug.h |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 213 | @@ -0,0 +1,3716 @@ |
| 214 | +#ifndef __MTK_DEBUG_H |
| 215 | +#define __MTK_DEBUG_H |
| 216 | + |
| 217 | +#ifdef CONFIG_MTK_DEBUG |
| 218 | + |
| 219 | +struct bin_debug_hdr { |
| 220 | + __le32 magic_num; |
| 221 | + __le16 serial_id; |
| 222 | + __le16 msg_type; |
| 223 | + __le16 len; |
| 224 | + __le16 des_len; /* descriptor len for rxd */ |
| 225 | +} __packed; |
| 226 | + |
| 227 | +#define NO_SHIFT_DEFINE 0xFFFFFFFF |
| 228 | +#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n))) |
| 229 | + |
| 230 | +#define GET_FIELD(_field, _reg) \ |
| 231 | + ({ \ |
| 232 | + (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \ |
| 233 | + }) |
| 234 | + |
| 235 | +struct queue_desc { |
| 236 | + u32 hw_desc_base; |
| 237 | + u16 ring_size; |
| 238 | + char *const ring_info; |
| 239 | +}; |
| 240 | + |
| 241 | +enum umac_port { |
| 242 | + ENUM_UMAC_HIF_PORT_0 = 0, |
| 243 | + ENUM_UMAC_CPU_PORT_1 = 1, |
| 244 | + ENUM_UMAC_LMAC_PORT_2 = 2, |
| 245 | + ENUM_PLE_CTRL_PSE_PORT_3 = 3, |
| 246 | + ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4 |
| 247 | +}; |
| 248 | + |
| 249 | +/* N9 MCU QUEUE LIST */ |
| 250 | +enum umac_cpu_port_queue_idx { |
| 251 | + ENUM_UMAC_CTX_Q_0 = 0, |
| 252 | + ENUM_UMAC_CTX_Q_1 = 1, |
| 253 | + ENUM_UMAC_CTX_Q_2 = 2, |
| 254 | + ENUM_UMAC_CTX_Q_3 = 3, |
| 255 | + ENUM_UMAC_CRX = 0, |
| 256 | + ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4 |
| 257 | +}; |
| 258 | + |
| 259 | +/* LMAC PLE For PSE Control P3 */ |
| 260 | +enum umac_ple_ctrl_port3_queue_idx { |
| 261 | + ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e, |
| 262 | + ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f, |
| 263 | + ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2 |
| 264 | +}; |
| 265 | + |
| 266 | +/* PSE PLE QUEUE */ |
| 267 | +#define CR_NUM_OF_AC 9 |
| 268 | +#define ALL_CR_NUM_OF_ALL_AC (CR_NUM_OF_AC * 4) |
| 269 | +struct bmac_queue_info { |
| 270 | + char *QueueName; |
| 271 | + u32 Portid; |
| 272 | + u32 Queueid; |
| 273 | + u32 tgid; |
| 274 | +}; |
| 275 | + |
| 276 | +struct bmac_queue_info_t { |
| 277 | + char *QueueName; |
| 278 | + u32 Portid; |
| 279 | + u32 Queueid; |
| 280 | +}; |
| 281 | + |
| 282 | +/* WTBL */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 283 | +enum besra_wtbl_type { |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 284 | + WTBL_TYPE_LMAC, /* WTBL in LMAC */ |
| 285 | + WTBL_TYPE_UMAC, /* WTBL in UMAC */ |
| 286 | + WTBL_TYPE_KEY, /* Key Table */ |
| 287 | + MAX_NUM_WTBL_TYPE |
| 288 | +}; |
| 289 | + |
| 290 | +struct berse_wtbl_parse { |
| 291 | + u8 *name; |
| 292 | + u32 mask; |
| 293 | + u32 shift; |
| 294 | + u8 new_line; |
| 295 | +}; |
| 296 | + |
| 297 | +enum muar_idx { |
| 298 | + MUAR_INDEX_OWN_MAC_ADDR_0 = 0, |
| 299 | + MUAR_INDEX_OWN_MAC_ADDR_1, |
| 300 | + MUAR_INDEX_OWN_MAC_ADDR_2, |
| 301 | + MUAR_INDEX_OWN_MAC_ADDR_3, |
| 302 | + MUAR_INDEX_OWN_MAC_ADDR_4, |
| 303 | + MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE, |
| 304 | + MUAR_INDEX_UNMATCHED = 0xF, |
| 305 | + MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11, |
| 306 | + MUAR_INDEX_OWN_MAC_ADDR_12, |
| 307 | + MUAR_INDEX_OWN_MAC_ADDR_13, |
| 308 | + MUAR_INDEX_OWN_MAC_ADDR_14, |
| 309 | + MUAR_INDEX_OWN_MAC_ADDR_15, |
| 310 | + MUAR_INDEX_OWN_MAC_ADDR_16, |
| 311 | + MUAR_INDEX_OWN_MAC_ADDR_17, |
| 312 | + MUAR_INDEX_OWN_MAC_ADDR_18, |
| 313 | + MUAR_INDEX_OWN_MAC_ADDR_19, |
| 314 | + MUAR_INDEX_OWN_MAC_ADDR_1A, |
| 315 | + MUAR_INDEX_OWN_MAC_ADDR_1B, |
| 316 | + MUAR_INDEX_OWN_MAC_ADDR_1C, |
| 317 | + MUAR_INDEX_OWN_MAC_ADDR_1D, |
| 318 | + MUAR_INDEX_OWN_MAC_ADDR_1E, |
| 319 | + MUAR_INDEX_OWN_MAC_ADDR_1F, |
| 320 | + MUAR_INDEX_OWN_MAC_ADDR_20, |
| 321 | + MUAR_INDEX_OWN_MAC_ADDR_21, |
| 322 | + MUAR_INDEX_OWN_MAC_ADDR_22, |
| 323 | + MUAR_INDEX_OWN_MAC_ADDR_23, |
| 324 | + MUAR_INDEX_OWN_MAC_ADDR_24, |
| 325 | + MUAR_INDEX_OWN_MAC_ADDR_25, |
| 326 | + MUAR_INDEX_OWN_MAC_ADDR_26, |
| 327 | + MUAR_INDEX_OWN_MAC_ADDR_27, |
| 328 | + MUAR_INDEX_OWN_MAC_ADDR_28, |
| 329 | + MUAR_INDEX_OWN_MAC_ADDR_29, |
| 330 | + MUAR_INDEX_OWN_MAC_ADDR_2A, |
| 331 | + MUAR_INDEX_OWN_MAC_ADDR_2B, |
| 332 | + MUAR_INDEX_OWN_MAC_ADDR_2C, |
| 333 | + MUAR_INDEX_OWN_MAC_ADDR_2D, |
| 334 | + MUAR_INDEX_OWN_MAC_ADDR_2E, |
| 335 | + MUAR_INDEX_OWN_MAC_ADDR_2F |
| 336 | +}; |
| 337 | + |
| 338 | +enum cipher_suit { |
| 339 | + IGTK_CIPHER_SUIT_NONE = 0, |
| 340 | + IGTK_CIPHER_SUIT_BIP, |
| 341 | + IGTK_CIPHER_SUIT_BIP_256 |
| 342 | +}; |
| 343 | + |
| 344 | +#define LWTBL_LEN_IN_DW 36 |
| 345 | +#define UWTBL_LEN_IN_DW 10 |
| 346 | + |
| 347 | +#define MT_DBG_WTBL_BASE 0x820D8000 |
| 348 | + |
| 349 | +#define MT_DBG_WTBLON_TOP_BASE 0x820d4000 |
| 350 | +#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370 |
| 351 | +#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) |
| 352 | + |
| 353 | +#define MT_DBG_UWTBL_TOP_BASE 0x820c4000 |
| 354 | +#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104 |
| 355 | +#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0) |
| 356 | +#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31) |
| 357 | + |
| 358 | +#define LWTBL_IDX2BASE_ID GENMASK(14, 8) |
| 359 | +#define LWTBL_IDX2BASE_DW GENMASK(7, 2) |
| 360 | +#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \ |
| 361 | + FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \ |
| 362 | + FIELD_PREP(LWTBL_IDX2BASE_DW, _dw)) |
| 363 | + |
| 364 | +#define UWTBL_IDX2BASE_ID GENMASK(12, 6) |
| 365 | +#define UWTBL_IDX2BASE_DW GENMASK(5, 2) |
| 366 | +#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \ |
| 367 | + FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \ |
| 368 | + FIELD_PREP(UWTBL_IDX2BASE_DW, _dw)) |
| 369 | + |
| 370 | +#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6) |
| 371 | +#define KEYTBL_IDX2BASE_DW GENMASK(5, 2) |
| 372 | +#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \ |
| 373 | + FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \ |
| 374 | + FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw)) |
| 375 | + |
| 376 | +// UMAC WTBL |
| 377 | +// DW0 |
| 378 | +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0 |
| 379 | +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0 |
| 380 | +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0 |
| 381 | +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0 |
| 382 | +#define WF_UWTBL_OWN_MLD_ID_DW 0 |
| 383 | +#define WF_UWTBL_OWN_MLD_ID_ADDR 0 |
| 384 | +#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16 |
| 385 | +#define WF_UWTBL_OWN_MLD_ID_SHIFT 16 |
| 386 | +// DW1 |
| 387 | +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1 |
| 388 | +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4 |
| 389 | +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0 |
| 390 | +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0 |
| 391 | +// DW2 |
| 392 | +#define WF_UWTBL_PN_31_0__DW 2 |
| 393 | +#define WF_UWTBL_PN_31_0__ADDR 8 |
| 394 | +#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0 |
| 395 | +#define WF_UWTBL_PN_31_0__SHIFT 0 |
| 396 | +// DW3 |
| 397 | +#define WF_UWTBL_PN_47_32__DW 3 |
| 398 | +#define WF_UWTBL_PN_47_32__ADDR 12 |
| 399 | +#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0 |
| 400 | +#define WF_UWTBL_PN_47_32__SHIFT 0 |
| 401 | +#define WF_UWTBL_COM_SN_DW 3 |
| 402 | +#define WF_UWTBL_COM_SN_ADDR 12 |
| 403 | +#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16 |
| 404 | +#define WF_UWTBL_COM_SN_SHIFT 16 |
| 405 | +// DW4 |
| 406 | +#define WF_UWTBL_TID0_SN_DW 4 |
| 407 | +#define WF_UWTBL_TID0_SN_ADDR 16 |
| 408 | +#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0 |
| 409 | +#define WF_UWTBL_TID0_SN_SHIFT 0 |
| 410 | +#define WF_UWTBL_RX_BIPN_31_0__DW 4 |
| 411 | +#define WF_UWTBL_RX_BIPN_31_0__ADDR 16 |
| 412 | +#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0 |
| 413 | +#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0 |
| 414 | +#define WF_UWTBL_TID1_SN_DW 4 |
| 415 | +#define WF_UWTBL_TID1_SN_ADDR 16 |
| 416 | +#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12 |
| 417 | +#define WF_UWTBL_TID1_SN_SHIFT 12 |
| 418 | +#define WF_UWTBL_TID2_SN_7_0__DW 4 |
| 419 | +#define WF_UWTBL_TID2_SN_7_0__ADDR 16 |
| 420 | +#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24 |
| 421 | +#define WF_UWTBL_TID2_SN_7_0__SHIFT 24 |
| 422 | +// DW5 |
| 423 | +#define WF_UWTBL_TID2_SN_11_8__DW 5 |
| 424 | +#define WF_UWTBL_TID2_SN_11_8__ADDR 20 |
| 425 | +#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0 |
| 426 | +#define WF_UWTBL_TID2_SN_11_8__SHIFT 0 |
| 427 | +#define WF_UWTBL_RX_BIPN_47_32__DW 5 |
| 428 | +#define WF_UWTBL_RX_BIPN_47_32__ADDR 20 |
| 429 | +#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0 |
| 430 | +#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0 |
| 431 | +#define WF_UWTBL_TID3_SN_DW 5 |
| 432 | +#define WF_UWTBL_TID3_SN_ADDR 20 |
| 433 | +#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4 |
| 434 | +#define WF_UWTBL_TID3_SN_SHIFT 4 |
| 435 | +#define WF_UWTBL_TID4_SN_DW 5 |
| 436 | +#define WF_UWTBL_TID4_SN_ADDR 20 |
| 437 | +#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16 |
| 438 | +#define WF_UWTBL_TID4_SN_SHIFT 16 |
| 439 | +#define WF_UWTBL_TID5_SN_3_0__DW 5 |
| 440 | +#define WF_UWTBL_TID5_SN_3_0__ADDR 20 |
| 441 | +#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28 |
| 442 | +#define WF_UWTBL_TID5_SN_3_0__SHIFT 28 |
| 443 | +// DW6 |
| 444 | +#define WF_UWTBL_TID5_SN_11_4__DW 6 |
| 445 | +#define WF_UWTBL_TID5_SN_11_4__ADDR 24 |
| 446 | +#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0 |
| 447 | +#define WF_UWTBL_TID5_SN_11_4__SHIFT 0 |
| 448 | +#define WF_UWTBL_KEY_LOC2_DW 6 |
| 449 | +#define WF_UWTBL_KEY_LOC2_ADDR 24 |
| 450 | +#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0 |
| 451 | +#define WF_UWTBL_KEY_LOC2_SHIFT 0 |
| 452 | +#define WF_UWTBL_TID6_SN_DW 6 |
| 453 | +#define WF_UWTBL_TID6_SN_ADDR 24 |
| 454 | +#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8 |
| 455 | +#define WF_UWTBL_TID6_SN_SHIFT 8 |
| 456 | +#define WF_UWTBL_TID7_SN_DW 6 |
| 457 | +#define WF_UWTBL_TID7_SN_ADDR 24 |
| 458 | +#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20 |
| 459 | +#define WF_UWTBL_TID7_SN_SHIFT 20 |
| 460 | +// DW7 |
| 461 | +#define WF_UWTBL_KEY_LOC0_DW 7 |
| 462 | +#define WF_UWTBL_KEY_LOC0_ADDR 28 |
| 463 | +#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0 |
| 464 | +#define WF_UWTBL_KEY_LOC0_SHIFT 0 |
| 465 | +#define WF_UWTBL_KEY_LOC1_DW 7 |
| 466 | +#define WF_UWTBL_KEY_LOC1_ADDR 28 |
| 467 | +#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16 |
| 468 | +#define WF_UWTBL_KEY_LOC1_SHIFT 16 |
| 469 | +// DW8 |
| 470 | +#define WF_UWTBL_AMSDU_CFG_DW 8 |
| 471 | +#define WF_UWTBL_AMSDU_CFG_ADDR 32 |
| 472 | +#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0 |
| 473 | +#define WF_UWTBL_AMSDU_CFG_SHIFT 0 |
| 474 | +#define WF_UWTBL_WMM_Q_DW 8 |
| 475 | +#define WF_UWTBL_WMM_Q_ADDR 32 |
| 476 | +#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25 |
| 477 | +#define WF_UWTBL_WMM_Q_SHIFT 25 |
| 478 | +#define WF_UWTBL_QOS_DW 8 |
| 479 | +#define WF_UWTBL_QOS_ADDR 32 |
| 480 | +#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27 |
| 481 | +#define WF_UWTBL_QOS_SHIFT 27 |
| 482 | +#define WF_UWTBL_HT_DW 8 |
| 483 | +#define WF_UWTBL_HT_ADDR 32 |
| 484 | +#define WF_UWTBL_HT_MASK 0x10000000 // 28-28 |
| 485 | +#define WF_UWTBL_HT_SHIFT 28 |
| 486 | +#define WF_UWTBL_HDRT_MODE_DW 8 |
| 487 | +#define WF_UWTBL_HDRT_MODE_ADDR 32 |
| 488 | +#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29 |
| 489 | +#define WF_UWTBL_HDRT_MODE_SHIFT 29 |
| 490 | +// DW9 |
| 491 | +#define WF_UWTBL_RELATED_IDX0_DW 9 |
| 492 | +#define WF_UWTBL_RELATED_IDX0_ADDR 36 |
| 493 | +#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0 |
| 494 | +#define WF_UWTBL_RELATED_IDX0_SHIFT 0 |
| 495 | +#define WF_UWTBL_RELATED_BAND0_DW 9 |
| 496 | +#define WF_UWTBL_RELATED_BAND0_ADDR 36 |
| 497 | +#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12 |
| 498 | +#define WF_UWTBL_RELATED_BAND0_SHIFT 12 |
| 499 | +#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9 |
| 500 | +#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36 |
| 501 | +#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14 |
| 502 | +#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14 |
| 503 | +#define WF_UWTBL_RELATED_IDX1_DW 9 |
| 504 | +#define WF_UWTBL_RELATED_IDX1_ADDR 36 |
| 505 | +#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16 |
| 506 | +#define WF_UWTBL_RELATED_IDX1_SHIFT 16 |
| 507 | +#define WF_UWTBL_RELATED_BAND1_DW 9 |
| 508 | +#define WF_UWTBL_RELATED_BAND1_ADDR 36 |
| 509 | +#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28 |
| 510 | +#define WF_UWTBL_RELATED_BAND1_SHIFT 28 |
| 511 | +#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9 |
| 512 | +#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36 |
| 513 | +#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30 |
| 514 | +#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30 |
| 515 | + |
| 516 | +/* LMAC WTBL */ |
| 517 | +// DW0 |
| 518 | +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0 |
| 519 | +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0 |
| 520 | +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \ |
| 521 | + 0x0000ffff // 15- 0 |
| 522 | +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0 |
| 523 | +#define WF_LWTBL_MUAR_DW 0 |
| 524 | +#define WF_LWTBL_MUAR_ADDR 0 |
| 525 | +#define WF_LWTBL_MUAR_MASK \ |
| 526 | + 0x003f0000 // 21-16 |
| 527 | +#define WF_LWTBL_MUAR_SHIFT 16 |
| 528 | +#define WF_LWTBL_RCA1_DW 0 |
| 529 | +#define WF_LWTBL_RCA1_ADDR 0 |
| 530 | +#define WF_LWTBL_RCA1_MASK \ |
| 531 | + 0x00400000 // 22-22 |
| 532 | +#define WF_LWTBL_RCA1_SHIFT 22 |
| 533 | +#define WF_LWTBL_KID_DW 0 |
| 534 | +#define WF_LWTBL_KID_ADDR 0 |
| 535 | +#define WF_LWTBL_KID_MASK \ |
| 536 | + 0x01800000 // 24-23 |
| 537 | +#define WF_LWTBL_KID_SHIFT 23 |
| 538 | +#define WF_LWTBL_RCID_DW 0 |
| 539 | +#define WF_LWTBL_RCID_ADDR 0 |
| 540 | +#define WF_LWTBL_RCID_MASK \ |
| 541 | + 0x02000000 // 25-25 |
| 542 | +#define WF_LWTBL_RCID_SHIFT 25 |
| 543 | +#define WF_LWTBL_BAND_DW 0 |
| 544 | +#define WF_LWTBL_BAND_ADDR 0 |
| 545 | +#define WF_LWTBL_BAND_MASK \ |
| 546 | + 0x0c000000 // 27-26 |
| 547 | +#define WF_LWTBL_BAND_SHIFT 26 |
| 548 | +#define WF_LWTBL_RV_DW 0 |
| 549 | +#define WF_LWTBL_RV_ADDR 0 |
| 550 | +#define WF_LWTBL_RV_MASK \ |
| 551 | + 0x10000000 // 28-28 |
| 552 | +#define WF_LWTBL_RV_SHIFT 28 |
| 553 | +#define WF_LWTBL_RCA2_DW 0 |
| 554 | +#define WF_LWTBL_RCA2_ADDR 0 |
| 555 | +#define WF_LWTBL_RCA2_MASK \ |
| 556 | + 0x20000000 // 29-29 |
| 557 | +#define WF_LWTBL_RCA2_SHIFT 29 |
| 558 | +#define WF_LWTBL_WPI_FLAG_DW 0 |
| 559 | +#define WF_LWTBL_WPI_FLAG_ADDR 0 |
| 560 | +#define WF_LWTBL_WPI_FLAG_MASK \ |
| 561 | + 0x40000000 // 30-30 |
| 562 | +#define WF_LWTBL_WPI_FLAG_SHIFT 30 |
| 563 | +// DW1 |
| 564 | +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1 |
| 565 | +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4 |
| 566 | +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \ |
| 567 | + 0xffffffff // 31- 0 |
| 568 | +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0 |
| 569 | +// DW2 |
| 570 | +#define WF_LWTBL_AID_DW 2 |
| 571 | +#define WF_LWTBL_AID_ADDR 8 |
| 572 | +#define WF_LWTBL_AID_MASK \ |
| 573 | + 0x00000fff // 11- 0 |
| 574 | +#define WF_LWTBL_AID_SHIFT 0 |
| 575 | +#define WF_LWTBL_GID_SU_DW 2 |
| 576 | +#define WF_LWTBL_GID_SU_ADDR 8 |
| 577 | +#define WF_LWTBL_GID_SU_MASK \ |
| 578 | + 0x00001000 // 12-12 |
| 579 | +#define WF_LWTBL_GID_SU_SHIFT 12 |
| 580 | +#define WF_LWTBL_SPP_EN_DW 2 |
| 581 | +#define WF_LWTBL_SPP_EN_ADDR 8 |
| 582 | +#define WF_LWTBL_SPP_EN_MASK \ |
| 583 | + 0x00002000 // 13-13 |
| 584 | +#define WF_LWTBL_SPP_EN_SHIFT 13 |
| 585 | +#define WF_LWTBL_WPI_EVEN_DW 2 |
| 586 | +#define WF_LWTBL_WPI_EVEN_ADDR 8 |
| 587 | +#define WF_LWTBL_WPI_EVEN_MASK \ |
| 588 | + 0x00004000 // 14-14 |
| 589 | +#define WF_LWTBL_WPI_EVEN_SHIFT 14 |
| 590 | +#define WF_LWTBL_AAD_OM_DW 2 |
| 591 | +#define WF_LWTBL_AAD_OM_ADDR 8 |
| 592 | +#define WF_LWTBL_AAD_OM_MASK \ |
| 593 | + 0x00008000 // 15-15 |
| 594 | +#define WF_LWTBL_AAD_OM_SHIFT 15 |
| 595 | +#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2 |
| 596 | +#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8 |
| 597 | +#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \ |
| 598 | + 0x001f0000 // 20-16 |
| 599 | +#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16 |
| 600 | +#define WF_LWTBL_FD_DW 2 |
| 601 | +#define WF_LWTBL_FD_ADDR 8 |
| 602 | +#define WF_LWTBL_FD_MASK \ |
| 603 | + 0x00200000 // 21-21 |
| 604 | +#define WF_LWTBL_FD_SHIFT 21 |
| 605 | +#define WF_LWTBL_TD_DW 2 |
| 606 | +#define WF_LWTBL_TD_ADDR 8 |
| 607 | +#define WF_LWTBL_TD_MASK \ |
| 608 | + 0x00400000 // 22-22 |
| 609 | +#define WF_LWTBL_TD_SHIFT 22 |
| 610 | +#define WF_LWTBL_SW_DW 2 |
| 611 | +#define WF_LWTBL_SW_ADDR 8 |
| 612 | +#define WF_LWTBL_SW_MASK \ |
| 613 | + 0x00800000 // 23-23 |
| 614 | +#define WF_LWTBL_SW_SHIFT 23 |
| 615 | +#define WF_LWTBL_UL_DW 2 |
| 616 | +#define WF_LWTBL_UL_ADDR 8 |
| 617 | +#define WF_LWTBL_UL_MASK \ |
| 618 | + 0x01000000 // 24-24 |
| 619 | +#define WF_LWTBL_UL_SHIFT 24 |
| 620 | +#define WF_LWTBL_TX_PS_DW 2 |
| 621 | +#define WF_LWTBL_TX_PS_ADDR 8 |
| 622 | +#define WF_LWTBL_TX_PS_MASK \ |
| 623 | + 0x02000000 // 25-25 |
| 624 | +#define WF_LWTBL_TX_PS_SHIFT 25 |
| 625 | +#define WF_LWTBL_QOS_DW 2 |
| 626 | +#define WF_LWTBL_QOS_ADDR 8 |
| 627 | +#define WF_LWTBL_QOS_MASK \ |
| 628 | + 0x04000000 // 26-26 |
| 629 | +#define WF_LWTBL_QOS_SHIFT 26 |
| 630 | +#define WF_LWTBL_HT_DW 2 |
| 631 | +#define WF_LWTBL_HT_ADDR 8 |
| 632 | +#define WF_LWTBL_HT_MASK \ |
| 633 | + 0x08000000 // 27-27 |
| 634 | +#define WF_LWTBL_HT_SHIFT 27 |
| 635 | +#define WF_LWTBL_VHT_DW 2 |
| 636 | +#define WF_LWTBL_VHT_ADDR 8 |
| 637 | +#define WF_LWTBL_VHT_MASK \ |
| 638 | + 0x10000000 // 28-28 |
| 639 | +#define WF_LWTBL_VHT_SHIFT 28 |
| 640 | +#define WF_LWTBL_HE_DW 2 |
| 641 | +#define WF_LWTBL_HE_ADDR 8 |
| 642 | +#define WF_LWTBL_HE_MASK \ |
| 643 | + 0x20000000 // 29-29 |
| 644 | +#define WF_LWTBL_HE_SHIFT 29 |
| 645 | +#define WF_LWTBL_EHT_DW 2 |
| 646 | +#define WF_LWTBL_EHT_ADDR 8 |
| 647 | +#define WF_LWTBL_EHT_MASK \ |
| 648 | + 0x40000000 // 30-30 |
| 649 | +#define WF_LWTBL_EHT_SHIFT 30 |
| 650 | +#define WF_LWTBL_MESH_DW 2 |
| 651 | +#define WF_LWTBL_MESH_ADDR 8 |
| 652 | +#define WF_LWTBL_MESH_MASK \ |
| 653 | + 0x80000000 // 31-31 |
| 654 | +#define WF_LWTBL_MESH_SHIFT 31 |
| 655 | +// DW3 |
| 656 | +#define WF_LWTBL_WMM_Q_DW 3 |
| 657 | +#define WF_LWTBL_WMM_Q_ADDR 12 |
| 658 | +#define WF_LWTBL_WMM_Q_MASK \ |
| 659 | + 0x00000003 // 1- 0 |
| 660 | +#define WF_LWTBL_WMM_Q_SHIFT 0 |
| 661 | +#define WF_LWTBL_EHT_SIG_MCS_DW 3 |
| 662 | +#define WF_LWTBL_EHT_SIG_MCS_ADDR 12 |
| 663 | +#define WF_LWTBL_EHT_SIG_MCS_MASK \ |
| 664 | + 0x0000000c // 3- 2 |
| 665 | +#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2 |
| 666 | +#define WF_LWTBL_HDRT_MODE_DW 3 |
| 667 | +#define WF_LWTBL_HDRT_MODE_ADDR 12 |
| 668 | +#define WF_LWTBL_HDRT_MODE_MASK \ |
| 669 | + 0x00000010 // 4- 4 |
| 670 | +#define WF_LWTBL_HDRT_MODE_SHIFT 4 |
| 671 | +#define WF_LWTBL_BEAM_CHG_DW 3 |
| 672 | +#define WF_LWTBL_BEAM_CHG_ADDR 12 |
| 673 | +#define WF_LWTBL_BEAM_CHG_MASK \ |
| 674 | + 0x00000020 // 5- 5 |
| 675 | +#define WF_LWTBL_BEAM_CHG_SHIFT 5 |
| 676 | +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3 |
| 677 | +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12 |
| 678 | +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \ |
| 679 | + 0x000000c0 // 7- 6 |
| 680 | +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6 |
| 681 | +#define WF_LWTBL_PFMU_IDX_DW 3 |
| 682 | +#define WF_LWTBL_PFMU_IDX_ADDR 12 |
| 683 | +#define WF_LWTBL_PFMU_IDX_MASK \ |
| 684 | + 0x0000ff00 // 15- 8 |
| 685 | +#define WF_LWTBL_PFMU_IDX_SHIFT 8 |
| 686 | +#define WF_LWTBL_ULPF_IDX_DW 3 |
| 687 | +#define WF_LWTBL_ULPF_IDX_ADDR 12 |
| 688 | +#define WF_LWTBL_ULPF_IDX_MASK \ |
| 689 | + 0x00ff0000 // 23-16 |
| 690 | +#define WF_LWTBL_ULPF_IDX_SHIFT 16 |
| 691 | +#define WF_LWTBL_RIBF_DW 3 |
| 692 | +#define WF_LWTBL_RIBF_ADDR 12 |
| 693 | +#define WF_LWTBL_RIBF_MASK \ |
| 694 | + 0x01000000 // 24-24 |
| 695 | +#define WF_LWTBL_RIBF_SHIFT 24 |
| 696 | +#define WF_LWTBL_ULPF_DW 3 |
| 697 | +#define WF_LWTBL_ULPF_ADDR 12 |
| 698 | +#define WF_LWTBL_ULPF_MASK \ |
| 699 | + 0x02000000 // 25-25 |
| 700 | +#define WF_LWTBL_ULPF_SHIFT 25 |
| 701 | +#define WF_LWTBL_TBF_HT_DW 3 |
| 702 | +#define WF_LWTBL_TBF_HT_ADDR 12 |
| 703 | +#define WF_LWTBL_TBF_HT_MASK \ |
| 704 | + 0x08000000 // 27-27 |
| 705 | +#define WF_LWTBL_TBF_HT_SHIFT 27 |
| 706 | +#define WF_LWTBL_TBF_VHT_DW 3 |
| 707 | +#define WF_LWTBL_TBF_VHT_ADDR 12 |
| 708 | +#define WF_LWTBL_TBF_VHT_MASK \ |
| 709 | + 0x10000000 // 28-28 |
| 710 | +#define WF_LWTBL_TBF_VHT_SHIFT 28 |
| 711 | +#define WF_LWTBL_TBF_HE_DW 3 |
| 712 | +#define WF_LWTBL_TBF_HE_ADDR 12 |
| 713 | +#define WF_LWTBL_TBF_HE_MASK \ |
| 714 | + 0x20000000 // 29-29 |
| 715 | +#define WF_LWTBL_TBF_HE_SHIFT 29 |
| 716 | +#define WF_LWTBL_TBF_EHT_DW 3 |
| 717 | +#define WF_LWTBL_TBF_EHT_ADDR 12 |
| 718 | +#define WF_LWTBL_TBF_EHT_MASK \ |
| 719 | + 0x40000000 // 30-30 |
| 720 | +#define WF_LWTBL_TBF_EHT_SHIFT 30 |
| 721 | +#define WF_LWTBL_IGN_FBK_DW 3 |
| 722 | +#define WF_LWTBL_IGN_FBK_ADDR 12 |
| 723 | +#define WF_LWTBL_IGN_FBK_MASK \ |
| 724 | + 0x80000000 // 31-31 |
| 725 | +#define WF_LWTBL_IGN_FBK_SHIFT 31 |
| 726 | +// DW4 |
| 727 | +#define WF_LWTBL_ANT_ID0_DW 4 |
| 728 | +#define WF_LWTBL_ANT_ID0_ADDR 16 |
| 729 | +#define WF_LWTBL_ANT_ID0_MASK \ |
| 730 | + 0x00000007 // 2- 0 |
| 731 | +#define WF_LWTBL_ANT_ID0_SHIFT 0 |
| 732 | +#define WF_LWTBL_ANT_ID1_DW 4 |
| 733 | +#define WF_LWTBL_ANT_ID1_ADDR 16 |
| 734 | +#define WF_LWTBL_ANT_ID1_MASK \ |
| 735 | + 0x00000038 // 5- 3 |
| 736 | +#define WF_LWTBL_ANT_ID1_SHIFT 3 |
| 737 | +#define WF_LWTBL_ANT_ID2_DW 4 |
| 738 | +#define WF_LWTBL_ANT_ID2_ADDR 16 |
| 739 | +#define WF_LWTBL_ANT_ID2_MASK \ |
| 740 | + 0x000001c0 // 8- 6 |
| 741 | +#define WF_LWTBL_ANT_ID2_SHIFT 6 |
| 742 | +#define WF_LWTBL_ANT_ID3_DW 4 |
| 743 | +#define WF_LWTBL_ANT_ID3_ADDR 16 |
| 744 | +#define WF_LWTBL_ANT_ID3_MASK \ |
| 745 | + 0x00000e00 // 11- 9 |
| 746 | +#define WF_LWTBL_ANT_ID3_SHIFT 9 |
| 747 | +#define WF_LWTBL_ANT_ID4_DW 4 |
| 748 | +#define WF_LWTBL_ANT_ID4_ADDR 16 |
| 749 | +#define WF_LWTBL_ANT_ID4_MASK \ |
| 750 | + 0x00007000 // 14-12 |
| 751 | +#define WF_LWTBL_ANT_ID4_SHIFT 12 |
| 752 | +#define WF_LWTBL_ANT_ID5_DW 4 |
| 753 | +#define WF_LWTBL_ANT_ID5_ADDR 16 |
| 754 | +#define WF_LWTBL_ANT_ID5_MASK \ |
| 755 | + 0x00038000 // 17-15 |
| 756 | +#define WF_LWTBL_ANT_ID5_SHIFT 15 |
| 757 | +#define WF_LWTBL_ANT_ID6_DW 4 |
| 758 | +#define WF_LWTBL_ANT_ID6_ADDR 16 |
| 759 | +#define WF_LWTBL_ANT_ID6_MASK \ |
| 760 | + 0x001c0000 // 20-18 |
| 761 | +#define WF_LWTBL_ANT_ID6_SHIFT 18 |
| 762 | +#define WF_LWTBL_ANT_ID7_DW 4 |
| 763 | +#define WF_LWTBL_ANT_ID7_ADDR 16 |
| 764 | +#define WF_LWTBL_ANT_ID7_MASK \ |
| 765 | + 0x00e00000 // 23-21 |
| 766 | +#define WF_LWTBL_ANT_ID7_SHIFT 21 |
| 767 | +#define WF_LWTBL_PE_DW 4 |
| 768 | +#define WF_LWTBL_PE_ADDR 16 |
| 769 | +#define WF_LWTBL_PE_MASK \ |
| 770 | + 0x03000000 // 25-24 |
| 771 | +#define WF_LWTBL_PE_SHIFT 24 |
| 772 | +#define WF_LWTBL_DIS_RHTR_DW 4 |
| 773 | +#define WF_LWTBL_DIS_RHTR_ADDR 16 |
| 774 | +#define WF_LWTBL_DIS_RHTR_MASK \ |
| 775 | + 0x04000000 // 26-26 |
| 776 | +#define WF_LWTBL_DIS_RHTR_SHIFT 26 |
| 777 | +#define WF_LWTBL_LDPC_HT_DW 4 |
| 778 | +#define WF_LWTBL_LDPC_HT_ADDR 16 |
| 779 | +#define WF_LWTBL_LDPC_HT_MASK \ |
| 780 | + 0x08000000 // 27-27 |
| 781 | +#define WF_LWTBL_LDPC_HT_SHIFT 27 |
| 782 | +#define WF_LWTBL_LDPC_VHT_DW 4 |
| 783 | +#define WF_LWTBL_LDPC_VHT_ADDR 16 |
| 784 | +#define WF_LWTBL_LDPC_VHT_MASK \ |
| 785 | + 0x10000000 // 28-28 |
| 786 | +#define WF_LWTBL_LDPC_VHT_SHIFT 28 |
| 787 | +#define WF_LWTBL_LDPC_HE_DW 4 |
| 788 | +#define WF_LWTBL_LDPC_HE_ADDR 16 |
| 789 | +#define WF_LWTBL_LDPC_HE_MASK \ |
| 790 | + 0x20000000 // 29-29 |
| 791 | +#define WF_LWTBL_LDPC_HE_SHIFT 29 |
| 792 | +#define WF_LWTBL_LDPC_EHT_DW 4 |
| 793 | +#define WF_LWTBL_LDPC_EHT_ADDR 16 |
| 794 | +#define WF_LWTBL_LDPC_EHT_MASK \ |
| 795 | + 0x40000000 // 30-30 |
| 796 | +#define WF_LWTBL_LDPC_EHT_SHIFT 30 |
| 797 | +// DW5 |
| 798 | +#define WF_LWTBL_AF_DW 5 |
| 799 | +#define WF_LWTBL_AF_ADDR 20 |
| 800 | +#define WF_LWTBL_AF_MASK \ |
| 801 | + 0x00000007 // 2- 0 |
| 802 | +#define WF_LWTBL_AF_SHIFT 0 |
| 803 | +#define WF_LWTBL_AF_HE_DW 5 |
| 804 | +#define WF_LWTBL_AF_HE_ADDR 20 |
| 805 | +#define WF_LWTBL_AF_HE_MASK \ |
| 806 | + 0x00000018 // 4- 3 |
| 807 | +#define WF_LWTBL_AF_HE_SHIFT 3 |
| 808 | +#define WF_LWTBL_RTS_DW 5 |
| 809 | +#define WF_LWTBL_RTS_ADDR 20 |
| 810 | +#define WF_LWTBL_RTS_MASK \ |
| 811 | + 0x00000020 // 5- 5 |
| 812 | +#define WF_LWTBL_RTS_SHIFT 5 |
| 813 | +#define WF_LWTBL_SMPS_DW 5 |
| 814 | +#define WF_LWTBL_SMPS_ADDR 20 |
| 815 | +#define WF_LWTBL_SMPS_MASK \ |
| 816 | + 0x00000040 // 6- 6 |
| 817 | +#define WF_LWTBL_SMPS_SHIFT 6 |
| 818 | +#define WF_LWTBL_DYN_BW_DW 5 |
| 819 | +#define WF_LWTBL_DYN_BW_ADDR 20 |
| 820 | +#define WF_LWTBL_DYN_BW_MASK \ |
| 821 | + 0x00000080 // 7- 7 |
| 822 | +#define WF_LWTBL_DYN_BW_SHIFT 7 |
| 823 | +#define WF_LWTBL_MMSS_DW 5 |
| 824 | +#define WF_LWTBL_MMSS_ADDR 20 |
| 825 | +#define WF_LWTBL_MMSS_MASK \ |
| 826 | + 0x00000700 // 10- 8 |
| 827 | +#define WF_LWTBL_MMSS_SHIFT 8 |
| 828 | +#define WF_LWTBL_USR_DW 5 |
| 829 | +#define WF_LWTBL_USR_ADDR 20 |
| 830 | +#define WF_LWTBL_USR_MASK \ |
| 831 | + 0x00000800 // 11-11 |
| 832 | +#define WF_LWTBL_USR_SHIFT 11 |
| 833 | +#define WF_LWTBL_SR_R_DW 5 |
| 834 | +#define WF_LWTBL_SR_R_ADDR 20 |
| 835 | +#define WF_LWTBL_SR_R_MASK \ |
| 836 | + 0x00007000 // 14-12 |
| 837 | +#define WF_LWTBL_SR_R_SHIFT 12 |
| 838 | +#define WF_LWTBL_SR_ABORT_DW 5 |
| 839 | +#define WF_LWTBL_SR_ABORT_ADDR 20 |
| 840 | +#define WF_LWTBL_SR_ABORT_MASK \ |
| 841 | + 0x00008000 // 15-15 |
| 842 | +#define WF_LWTBL_SR_ABORT_SHIFT 15 |
| 843 | +#define WF_LWTBL_TX_POWER_OFFSET_DW 5 |
| 844 | +#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20 |
| 845 | +#define WF_LWTBL_TX_POWER_OFFSET_MASK \ |
| 846 | + 0x003f0000 // 21-16 |
| 847 | +#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16 |
| 848 | +#define WF_LWTBL_LTF_EHT_DW 5 |
| 849 | +#define WF_LWTBL_LTF_EHT_ADDR 20 |
| 850 | +#define WF_LWTBL_LTF_EHT_MASK \ |
| 851 | + 0x00c00000 // 23-22 |
| 852 | +#define WF_LWTBL_LTF_EHT_SHIFT 22 |
| 853 | +#define WF_LWTBL_GI_EHT_DW 5 |
| 854 | +#define WF_LWTBL_GI_EHT_ADDR 20 |
| 855 | +#define WF_LWTBL_GI_EHT_MASK \ |
| 856 | + 0x03000000 // 25-24 |
| 857 | +#define WF_LWTBL_GI_EHT_SHIFT 24 |
| 858 | +#define WF_LWTBL_DOPPL_DW 5 |
| 859 | +#define WF_LWTBL_DOPPL_ADDR 20 |
| 860 | +#define WF_LWTBL_DOPPL_MASK \ |
| 861 | + 0x04000000 // 26-26 |
| 862 | +#define WF_LWTBL_DOPPL_SHIFT 26 |
| 863 | +#define WF_LWTBL_TXOP_PS_CAP_DW 5 |
| 864 | +#define WF_LWTBL_TXOP_PS_CAP_ADDR 20 |
| 865 | +#define WF_LWTBL_TXOP_PS_CAP_MASK \ |
| 866 | + 0x08000000 // 27-27 |
| 867 | +#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27 |
| 868 | +#define WF_LWTBL_DU_I_PSM_DW 5 |
| 869 | +#define WF_LWTBL_DU_I_PSM_ADDR 20 |
| 870 | +#define WF_LWTBL_DU_I_PSM_MASK \ |
| 871 | + 0x10000000 // 28-28 |
| 872 | +#define WF_LWTBL_DU_I_PSM_SHIFT 28 |
| 873 | +#define WF_LWTBL_I_PSM_DW 5 |
| 874 | +#define WF_LWTBL_I_PSM_ADDR 20 |
| 875 | +#define WF_LWTBL_I_PSM_MASK \ |
| 876 | + 0x20000000 // 29-29 |
| 877 | +#define WF_LWTBL_I_PSM_SHIFT 29 |
| 878 | +#define WF_LWTBL_PSM_DW 5 |
| 879 | +#define WF_LWTBL_PSM_ADDR 20 |
| 880 | +#define WF_LWTBL_PSM_MASK \ |
| 881 | + 0x40000000 // 30-30 |
| 882 | +#define WF_LWTBL_PSM_SHIFT 30 |
| 883 | +#define WF_LWTBL_SKIP_TX_DW 5 |
| 884 | +#define WF_LWTBL_SKIP_TX_ADDR 20 |
| 885 | +#define WF_LWTBL_SKIP_TX_MASK \ |
| 886 | + 0x80000000 // 31-31 |
| 887 | +#define WF_LWTBL_SKIP_TX_SHIFT 31 |
| 888 | +// DW6 |
| 889 | +#define WF_LWTBL_CBRN_DW 6 |
| 890 | +#define WF_LWTBL_CBRN_ADDR 24 |
| 891 | +#define WF_LWTBL_CBRN_MASK \ |
| 892 | + 0x00000007 // 2- 0 |
| 893 | +#define WF_LWTBL_CBRN_SHIFT 0 |
| 894 | +#define WF_LWTBL_DBNSS_EN_DW 6 |
| 895 | +#define WF_LWTBL_DBNSS_EN_ADDR 24 |
| 896 | +#define WF_LWTBL_DBNSS_EN_MASK \ |
| 897 | + 0x00000008 // 3- 3 |
| 898 | +#define WF_LWTBL_DBNSS_EN_SHIFT 3 |
| 899 | +#define WF_LWTBL_BAF_EN_DW 6 |
| 900 | +#define WF_LWTBL_BAF_EN_ADDR 24 |
| 901 | +#define WF_LWTBL_BAF_EN_MASK \ |
| 902 | + 0x00000010 // 4- 4 |
| 903 | +#define WF_LWTBL_BAF_EN_SHIFT 4 |
| 904 | +#define WF_LWTBL_RDGBA_DW 6 |
| 905 | +#define WF_LWTBL_RDGBA_ADDR 24 |
| 906 | +#define WF_LWTBL_RDGBA_MASK \ |
| 907 | + 0x00000020 // 5- 5 |
| 908 | +#define WF_LWTBL_RDGBA_SHIFT 5 |
| 909 | +#define WF_LWTBL_R_DW 6 |
| 910 | +#define WF_LWTBL_R_ADDR 24 |
| 911 | +#define WF_LWTBL_R_MASK \ |
| 912 | + 0x00000040 // 6- 6 |
| 913 | +#define WF_LWTBL_R_SHIFT 6 |
| 914 | +#define WF_LWTBL_SPE_IDX_DW 6 |
| 915 | +#define WF_LWTBL_SPE_IDX_ADDR 24 |
| 916 | +#define WF_LWTBL_SPE_IDX_MASK \ |
| 917 | + 0x00000f80 // 11- 7 |
| 918 | +#define WF_LWTBL_SPE_IDX_SHIFT 7 |
| 919 | +#define WF_LWTBL_G2_DW 6 |
| 920 | +#define WF_LWTBL_G2_ADDR 24 |
| 921 | +#define WF_LWTBL_G2_MASK \ |
| 922 | + 0x00001000 // 12-12 |
| 923 | +#define WF_LWTBL_G2_SHIFT 12 |
| 924 | +#define WF_LWTBL_G4_DW 6 |
| 925 | +#define WF_LWTBL_G4_ADDR 24 |
| 926 | +#define WF_LWTBL_G4_MASK \ |
| 927 | + 0x00002000 // 13-13 |
| 928 | +#define WF_LWTBL_G4_SHIFT 13 |
| 929 | +#define WF_LWTBL_G8_DW 6 |
| 930 | +#define WF_LWTBL_G8_ADDR 24 |
| 931 | +#define WF_LWTBL_G8_MASK \ |
| 932 | + 0x00004000 // 14-14 |
| 933 | +#define WF_LWTBL_G8_SHIFT 14 |
| 934 | +#define WF_LWTBL_G16_DW 6 |
| 935 | +#define WF_LWTBL_G16_ADDR 24 |
| 936 | +#define WF_LWTBL_G16_MASK \ |
| 937 | + 0x00008000 // 15-15 |
| 938 | +#define WF_LWTBL_G16_SHIFT 15 |
| 939 | +#define WF_LWTBL_G2_LTF_DW 6 |
| 940 | +#define WF_LWTBL_G2_LTF_ADDR 24 |
| 941 | +#define WF_LWTBL_G2_LTF_MASK \ |
| 942 | + 0x00030000 // 17-16 |
| 943 | +#define WF_LWTBL_G2_LTF_SHIFT 16 |
| 944 | +#define WF_LWTBL_G4_LTF_DW 6 |
| 945 | +#define WF_LWTBL_G4_LTF_ADDR 24 |
| 946 | +#define WF_LWTBL_G4_LTF_MASK \ |
| 947 | + 0x000c0000 // 19-18 |
| 948 | +#define WF_LWTBL_G4_LTF_SHIFT 18 |
| 949 | +#define WF_LWTBL_G8_LTF_DW 6 |
| 950 | +#define WF_LWTBL_G8_LTF_ADDR 24 |
| 951 | +#define WF_LWTBL_G8_LTF_MASK \ |
| 952 | + 0x00300000 // 21-20 |
| 953 | +#define WF_LWTBL_G8_LTF_SHIFT 20 |
| 954 | +#define WF_LWTBL_G16_LTF_DW 6 |
| 955 | +#define WF_LWTBL_G16_LTF_ADDR 24 |
| 956 | +#define WF_LWTBL_G16_LTF_MASK \ |
| 957 | + 0x00c00000 // 23-22 |
| 958 | +#define WF_LWTBL_G16_LTF_SHIFT 22 |
| 959 | +#define WF_LWTBL_G2_HE_DW 6 |
| 960 | +#define WF_LWTBL_G2_HE_ADDR 24 |
| 961 | +#define WF_LWTBL_G2_HE_MASK \ |
| 962 | + 0x03000000 // 25-24 |
| 963 | +#define WF_LWTBL_G2_HE_SHIFT 24 |
| 964 | +#define WF_LWTBL_G4_HE_DW 6 |
| 965 | +#define WF_LWTBL_G4_HE_ADDR 24 |
| 966 | +#define WF_LWTBL_G4_HE_MASK \ |
| 967 | + 0x0c000000 // 27-26 |
| 968 | +#define WF_LWTBL_G4_HE_SHIFT 26 |
| 969 | +#define WF_LWTBL_G8_HE_DW 6 |
| 970 | +#define WF_LWTBL_G8_HE_ADDR 24 |
| 971 | +#define WF_LWTBL_G8_HE_MASK \ |
| 972 | + 0x30000000 // 29-28 |
| 973 | +#define WF_LWTBL_G8_HE_SHIFT 28 |
| 974 | +#define WF_LWTBL_G16_HE_DW 6 |
| 975 | +#define WF_LWTBL_G16_HE_ADDR 24 |
| 976 | +#define WF_LWTBL_G16_HE_MASK \ |
| 977 | + 0xc0000000 // 31-30 |
| 978 | +#define WF_LWTBL_G16_HE_SHIFT 30 |
| 979 | +// DW7 |
| 980 | +#define WF_LWTBL_BA_WIN_SIZE0_DW 7 |
| 981 | +#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28 |
| 982 | +#define WF_LWTBL_BA_WIN_SIZE0_MASK \ |
| 983 | + 0x0000000f // 3- 0 |
| 984 | +#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0 |
| 985 | +#define WF_LWTBL_BA_WIN_SIZE1_DW 7 |
| 986 | +#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28 |
| 987 | +#define WF_LWTBL_BA_WIN_SIZE1_MASK \ |
| 988 | + 0x000000f0 // 7- 4 |
| 989 | +#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4 |
| 990 | +#define WF_LWTBL_BA_WIN_SIZE2_DW 7 |
| 991 | +#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28 |
| 992 | +#define WF_LWTBL_BA_WIN_SIZE2_MASK \ |
| 993 | + 0x00000f00 // 11- 8 |
| 994 | +#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8 |
| 995 | +#define WF_LWTBL_BA_WIN_SIZE3_DW 7 |
| 996 | +#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28 |
| 997 | +#define WF_LWTBL_BA_WIN_SIZE3_MASK \ |
| 998 | + 0x0000f000 // 15-12 |
| 999 | +#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12 |
| 1000 | +#define WF_LWTBL_BA_WIN_SIZE4_DW 7 |
| 1001 | +#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28 |
| 1002 | +#define WF_LWTBL_BA_WIN_SIZE4_MASK \ |
| 1003 | + 0x000f0000 // 19-16 |
| 1004 | +#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16 |
| 1005 | +#define WF_LWTBL_BA_WIN_SIZE5_DW 7 |
| 1006 | +#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28 |
| 1007 | +#define WF_LWTBL_BA_WIN_SIZE5_MASK \ |
| 1008 | + 0x00f00000 // 23-20 |
| 1009 | +#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20 |
| 1010 | +#define WF_LWTBL_BA_WIN_SIZE6_DW 7 |
| 1011 | +#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28 |
| 1012 | +#define WF_LWTBL_BA_WIN_SIZE6_MASK \ |
| 1013 | + 0x0f000000 // 27-24 |
| 1014 | +#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24 |
| 1015 | +#define WF_LWTBL_BA_WIN_SIZE7_DW 7 |
| 1016 | +#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28 |
| 1017 | +#define WF_LWTBL_BA_WIN_SIZE7_MASK \ |
| 1018 | + 0xf0000000 // 31-28 |
| 1019 | +#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28 |
| 1020 | +// DW8 |
| 1021 | +#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8 |
| 1022 | +#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32 |
| 1023 | +#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \ |
| 1024 | + 0x0000001f // 4- 0 |
| 1025 | +#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0 |
| 1026 | +#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8 |
| 1027 | +#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32 |
| 1028 | +#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \ |
| 1029 | + 0x000003e0 // 9- 5 |
| 1030 | +#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5 |
| 1031 | +#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8 |
| 1032 | +#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32 |
| 1033 | +#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \ |
| 1034 | + 0x00007c00 // 14-10 |
| 1035 | +#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10 |
| 1036 | +#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8 |
| 1037 | +#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32 |
| 1038 | +#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \ |
| 1039 | + 0x000f8000 // 19-15 |
| 1040 | +#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15 |
| 1041 | +#define WF_LWTBL_PARTIAL_AID_DW 8 |
| 1042 | +#define WF_LWTBL_PARTIAL_AID_ADDR 32 |
| 1043 | +#define WF_LWTBL_PARTIAL_AID_MASK \ |
| 1044 | + 0x1ff00000 // 28-20 |
| 1045 | +#define WF_LWTBL_PARTIAL_AID_SHIFT 20 |
| 1046 | +#define WF_LWTBL_CHK_PER_DW 8 |
| 1047 | +#define WF_LWTBL_CHK_PER_ADDR 32 |
| 1048 | +#define WF_LWTBL_CHK_PER_MASK \ |
| 1049 | + 0x80000000 // 31-31 |
| 1050 | +#define WF_LWTBL_CHK_PER_SHIFT 31 |
| 1051 | +// DW9 |
| 1052 | +#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9 |
| 1053 | +#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36 |
| 1054 | +#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \ |
| 1055 | + 0x00003fff // 13- 0 |
| 1056 | +#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0 |
| 1057 | +#define WF_LWTBL_PRITX_SW_MODE_DW 9 |
| 1058 | +#define WF_LWTBL_PRITX_SW_MODE_ADDR 36 |
| 1059 | +#define WF_LWTBL_PRITX_SW_MODE_MASK \ |
| 1060 | + 0x00008000 // 15-15 |
| 1061 | +#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15 |
| 1062 | +#define WF_LWTBL_PRITX_ERSU_DW 9 |
| 1063 | +#define WF_LWTBL_PRITX_ERSU_ADDR 36 |
| 1064 | +#define WF_LWTBL_PRITX_ERSU_MASK \ |
| 1065 | + 0x00010000 // 16-16 |
| 1066 | +#define WF_LWTBL_PRITX_ERSU_SHIFT 16 |
| 1067 | +#define WF_LWTBL_PRITX_PLR_DW 9 |
| 1068 | +#define WF_LWTBL_PRITX_PLR_ADDR 36 |
| 1069 | +#define WF_LWTBL_PRITX_PLR_MASK \ |
| 1070 | + 0x00020000 // 17-17 |
| 1071 | +#define WF_LWTBL_PRITX_PLR_SHIFT 17 |
| 1072 | +#define WF_LWTBL_PRITX_DCM_DW 9 |
| 1073 | +#define WF_LWTBL_PRITX_DCM_ADDR 36 |
| 1074 | +#define WF_LWTBL_PRITX_DCM_MASK \ |
| 1075 | + 0x00040000 // 18-18 |
| 1076 | +#define WF_LWTBL_PRITX_DCM_SHIFT 18 |
| 1077 | +#define WF_LWTBL_PRITX_ER106T_DW 9 |
| 1078 | +#define WF_LWTBL_PRITX_ER106T_ADDR 36 |
| 1079 | +#define WF_LWTBL_PRITX_ER106T_MASK \ |
| 1080 | + 0x00080000 // 19-19 |
| 1081 | +#define WF_LWTBL_PRITX_ER106T_SHIFT 19 |
| 1082 | +#define WF_LWTBL_FCAP_DW 9 |
| 1083 | +#define WF_LWTBL_FCAP_ADDR 36 |
| 1084 | +#define WF_LWTBL_FCAP_MASK \ |
| 1085 | + 0x00700000 // 22-20 |
| 1086 | +#define WF_LWTBL_FCAP_SHIFT 20 |
| 1087 | +#define WF_LWTBL_MPDU_FAIL_CNT_DW 9 |
| 1088 | +#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36 |
| 1089 | +#define WF_LWTBL_MPDU_FAIL_CNT_MASK \ |
| 1090 | + 0x03800000 // 25-23 |
| 1091 | +#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23 |
| 1092 | +#define WF_LWTBL_MPDU_OK_CNT_DW 9 |
| 1093 | +#define WF_LWTBL_MPDU_OK_CNT_ADDR 36 |
| 1094 | +#define WF_LWTBL_MPDU_OK_CNT_MASK \ |
| 1095 | + 0x1c000000 // 28-26 |
| 1096 | +#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26 |
| 1097 | +#define WF_LWTBL_RATE_IDX_DW 9 |
| 1098 | +#define WF_LWTBL_RATE_IDX_ADDR 36 |
| 1099 | +#define WF_LWTBL_RATE_IDX_MASK \ |
| 1100 | + 0xe0000000 // 31-29 |
| 1101 | +#define WF_LWTBL_RATE_IDX_SHIFT 29 |
| 1102 | +// DW10 |
| 1103 | +#define WF_LWTBL_RATE1_DW 10 |
| 1104 | +#define WF_LWTBL_RATE1_ADDR 40 |
| 1105 | +#define WF_LWTBL_RATE1_MASK \ |
| 1106 | + 0x00007fff // 14- 0 |
| 1107 | +#define WF_LWTBL_RATE1_SHIFT 0 |
| 1108 | +#define WF_LWTBL_RATE2_DW 10 |
| 1109 | +#define WF_LWTBL_RATE2_ADDR 40 |
| 1110 | +#define WF_LWTBL_RATE2_MASK \ |
| 1111 | + 0x7fff0000 // 30-16 |
| 1112 | +#define WF_LWTBL_RATE2_SHIFT 16 |
| 1113 | +// DW11 |
| 1114 | +#define WF_LWTBL_RATE3_DW 11 |
| 1115 | +#define WF_LWTBL_RATE3_ADDR 44 |
| 1116 | +#define WF_LWTBL_RATE3_MASK \ |
| 1117 | + 0x00007fff // 14- 0 |
| 1118 | +#define WF_LWTBL_RATE3_SHIFT 0 |
| 1119 | +#define WF_LWTBL_RATE4_DW 11 |
| 1120 | +#define WF_LWTBL_RATE4_ADDR 44 |
| 1121 | +#define WF_LWTBL_RATE4_MASK \ |
| 1122 | + 0x7fff0000 // 30-16 |
| 1123 | +#define WF_LWTBL_RATE4_SHIFT 16 |
| 1124 | +// DW12 |
| 1125 | +#define WF_LWTBL_RATE5_DW 12 |
| 1126 | +#define WF_LWTBL_RATE5_ADDR 48 |
| 1127 | +#define WF_LWTBL_RATE5_MASK \ |
| 1128 | + 0x00007fff // 14- 0 |
| 1129 | +#define WF_LWTBL_RATE5_SHIFT 0 |
| 1130 | +#define WF_LWTBL_RATE6_DW 12 |
| 1131 | +#define WF_LWTBL_RATE6_ADDR 48 |
| 1132 | +#define WF_LWTBL_RATE6_MASK \ |
| 1133 | + 0x7fff0000 // 30-16 |
| 1134 | +#define WF_LWTBL_RATE6_SHIFT 16 |
| 1135 | +// DW13 |
| 1136 | +#define WF_LWTBL_RATE7_DW 13 |
| 1137 | +#define WF_LWTBL_RATE7_ADDR 52 |
| 1138 | +#define WF_LWTBL_RATE7_MASK \ |
| 1139 | + 0x00007fff // 14- 0 |
| 1140 | +#define WF_LWTBL_RATE7_SHIFT 0 |
| 1141 | +#define WF_LWTBL_RATE8_DW 13 |
| 1142 | +#define WF_LWTBL_RATE8_ADDR 52 |
| 1143 | +#define WF_LWTBL_RATE8_MASK \ |
| 1144 | + 0x7fff0000 // 30-16 |
| 1145 | +#define WF_LWTBL_RATE8_SHIFT 16 |
| 1146 | +// DW14 |
| 1147 | +#define WF_LWTBL_RATE1_TX_CNT_DW 14 |
| 1148 | +#define WF_LWTBL_RATE1_TX_CNT_ADDR 56 |
| 1149 | +#define WF_LWTBL_RATE1_TX_CNT_MASK \ |
| 1150 | + 0x0000ffff // 15- 0 |
| 1151 | +#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0 |
| 1152 | +#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14 |
| 1153 | +#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56 |
| 1154 | +#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \ |
| 1155 | + 0x00003000 // 13-12 |
| 1156 | +#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12 |
| 1157 | +#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14 |
| 1158 | +#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56 |
| 1159 | +#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \ |
| 1160 | + 0x0000c000 // 15-14 |
| 1161 | +#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14 |
| 1162 | +#define WF_LWTBL_RATE1_FAIL_CNT_DW 14 |
| 1163 | +#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56 |
| 1164 | +#define WF_LWTBL_RATE1_FAIL_CNT_MASK \ |
| 1165 | + 0xffff0000 // 31-16 |
| 1166 | +#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16 |
| 1167 | +// DW15 |
| 1168 | +#define WF_LWTBL_RATE2_OK_CNT_DW 15 |
| 1169 | +#define WF_LWTBL_RATE2_OK_CNT_ADDR 60 |
| 1170 | +#define WF_LWTBL_RATE2_OK_CNT_MASK \ |
| 1171 | + 0x0000ffff // 15- 0 |
| 1172 | +#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0 |
| 1173 | +#define WF_LWTBL_RATE3_OK_CNT_DW 15 |
| 1174 | +#define WF_LWTBL_RATE3_OK_CNT_ADDR 60 |
| 1175 | +#define WF_LWTBL_RATE3_OK_CNT_MASK \ |
| 1176 | + 0xffff0000 // 31-16 |
| 1177 | +#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16 |
| 1178 | +// DW16 |
| 1179 | +#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16 |
| 1180 | +#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64 |
| 1181 | +#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \ |
| 1182 | + 0x0000ffff // 15- 0 |
| 1183 | +#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0 |
| 1184 | +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16 |
| 1185 | +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64 |
| 1186 | +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \ |
| 1187 | + 0xffff0000 // 31-16 |
| 1188 | +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16 |
| 1189 | +// DW17 |
| 1190 | +#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17 |
| 1191 | +#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68 |
| 1192 | +#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \ |
| 1193 | + 0x0000ffff // 15- 0 |
| 1194 | +#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0 |
| 1195 | +#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17 |
| 1196 | +#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68 |
| 1197 | +#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \ |
| 1198 | + 0xffff0000 // 31-16 |
| 1199 | +#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16 |
| 1200 | +// DW18 |
| 1201 | +#define WF_LWTBL_RTS_OK_CNT_DW 18 |
| 1202 | +#define WF_LWTBL_RTS_OK_CNT_ADDR 72 |
| 1203 | +#define WF_LWTBL_RTS_OK_CNT_MASK \ |
| 1204 | + 0x0000ffff // 15- 0 |
| 1205 | +#define WF_LWTBL_RTS_OK_CNT_SHIFT 0 |
| 1206 | +#define WF_LWTBL_RTS_FAIL_CNT_DW 18 |
| 1207 | +#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72 |
| 1208 | +#define WF_LWTBL_RTS_FAIL_CNT_MASK \ |
| 1209 | + 0xffff0000 // 31-16 |
| 1210 | +#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16 |
| 1211 | +// DW19 |
| 1212 | +#define WF_LWTBL_DATA_RETRY_CNT_DW 19 |
| 1213 | +#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76 |
| 1214 | +#define WF_LWTBL_DATA_RETRY_CNT_MASK \ |
| 1215 | + 0x0000ffff // 15- 0 |
| 1216 | +#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0 |
| 1217 | +#define WF_LWTBL_MGNT_RETRY_CNT_DW 19 |
| 1218 | +#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76 |
| 1219 | +#define WF_LWTBL_MGNT_RETRY_CNT_MASK \ |
| 1220 | + 0xffff0000 // 31-16 |
| 1221 | +#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16 |
| 1222 | +// DW20 |
| 1223 | +#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20 |
| 1224 | +#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80 |
| 1225 | +#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \ |
| 1226 | + 0xffffffff // 31- 0 |
| 1227 | +#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0 |
| 1228 | +// DW21 |
| 1229 | +// DO NOT process repeat field(adm[0]) |
| 1230 | +// DW22 |
| 1231 | +#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22 |
| 1232 | +#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88 |
| 1233 | +#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \ |
| 1234 | + 0xffffffff // 31- 0 |
| 1235 | +#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0 |
| 1236 | +// DW23 |
| 1237 | +// DO NOT process repeat field(adm[1]) |
| 1238 | +// DW24 |
| 1239 | +#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24 |
| 1240 | +#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96 |
| 1241 | +#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \ |
| 1242 | + 0xffffffff // 31- 0 |
| 1243 | +#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0 |
| 1244 | +// DW25 |
| 1245 | +// DO NOT process repeat field(adm[2]) |
| 1246 | +// DW26 |
| 1247 | +#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26 |
| 1248 | +#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104 |
| 1249 | +#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \ |
| 1250 | + 0xffffffff // 31- 0 |
| 1251 | +#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0 |
| 1252 | +// DW27 |
| 1253 | +// DO NOT process repeat field(adm[3]) |
| 1254 | +// DW28 |
| 1255 | +#define WF_LWTBL_RELATED_IDX0_DW 28 |
| 1256 | +#define WF_LWTBL_RELATED_IDX0_ADDR 112 |
| 1257 | +#define WF_LWTBL_RELATED_IDX0_MASK \ |
| 1258 | + 0x00000fff // 11- 0 |
| 1259 | +#define WF_LWTBL_RELATED_IDX0_SHIFT 0 |
| 1260 | +#define WF_LWTBL_RELATED_BAND0_DW 28 |
| 1261 | +#define WF_LWTBL_RELATED_BAND0_ADDR 112 |
| 1262 | +#define WF_LWTBL_RELATED_BAND0_MASK \ |
| 1263 | + 0x00003000 // 13-12 |
| 1264 | +#define WF_LWTBL_RELATED_BAND0_SHIFT 12 |
| 1265 | +#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28 |
| 1266 | +#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112 |
| 1267 | +#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \ |
| 1268 | + 0x0000c000 // 15-14 |
| 1269 | +#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14 |
| 1270 | +#define WF_LWTBL_RELATED_IDX1_DW 28 |
| 1271 | +#define WF_LWTBL_RELATED_IDX1_ADDR 112 |
| 1272 | +#define WF_LWTBL_RELATED_IDX1_MASK \ |
| 1273 | + 0x0fff0000 // 27-16 |
| 1274 | +#define WF_LWTBL_RELATED_IDX1_SHIFT 16 |
| 1275 | +#define WF_LWTBL_RELATED_BAND1_DW 28 |
| 1276 | +#define WF_LWTBL_RELATED_BAND1_ADDR 112 |
| 1277 | +#define WF_LWTBL_RELATED_BAND1_MASK \ |
| 1278 | + 0x30000000 // 29-28 |
| 1279 | +#define WF_LWTBL_RELATED_BAND1_SHIFT 28 |
| 1280 | +#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28 |
| 1281 | +#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112 |
| 1282 | +#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \ |
| 1283 | + 0xc0000000 // 31-30 |
| 1284 | +#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30 |
| 1285 | +// DW29 |
| 1286 | +#define WF_LWTBL_DISPATCH_POLICY0_DW 29 |
| 1287 | +#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116 |
| 1288 | +#define WF_LWTBL_DISPATCH_POLICY0_MASK \ |
| 1289 | + 0x00000003 // 1- 0 |
| 1290 | +#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0 |
| 1291 | +#define WF_LWTBL_DISPATCH_POLICY1_DW 29 |
| 1292 | +#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116 |
| 1293 | +#define WF_LWTBL_DISPATCH_POLICY1_MASK \ |
| 1294 | + 0x0000000c // 3- 2 |
| 1295 | +#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2 |
| 1296 | +#define WF_LWTBL_DISPATCH_POLICY2_DW 29 |
| 1297 | +#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116 |
| 1298 | +#define WF_LWTBL_DISPATCH_POLICY2_MASK \ |
| 1299 | + 0x00000030 // 5- 4 |
| 1300 | +#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4 |
| 1301 | +#define WF_LWTBL_DISPATCH_POLICY3_DW 29 |
| 1302 | +#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116 |
| 1303 | +#define WF_LWTBL_DISPATCH_POLICY3_MASK \ |
| 1304 | + 0x000000c0 // 7- 6 |
| 1305 | +#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6 |
| 1306 | +#define WF_LWTBL_DISPATCH_POLICY4_DW 29 |
| 1307 | +#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116 |
| 1308 | +#define WF_LWTBL_DISPATCH_POLICY4_MASK \ |
| 1309 | + 0x00000300 // 9- 8 |
| 1310 | +#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8 |
| 1311 | +#define WF_LWTBL_DISPATCH_POLICY5_DW 29 |
| 1312 | +#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116 |
| 1313 | +#define WF_LWTBL_DISPATCH_POLICY5_MASK \ |
| 1314 | + 0x00000c00 // 11-10 |
| 1315 | +#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10 |
| 1316 | +#define WF_LWTBL_DISPATCH_POLICY6_DW 29 |
| 1317 | +#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116 |
| 1318 | +#define WF_LWTBL_DISPATCH_POLICY6_MASK \ |
| 1319 | + 0x00003000 // 13-12 |
| 1320 | +#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12 |
| 1321 | +#define WF_LWTBL_DISPATCH_POLICY7_DW 29 |
| 1322 | +#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116 |
| 1323 | +#define WF_LWTBL_DISPATCH_POLICY7_MASK \ |
| 1324 | + 0x0000c000 // 15-14 |
| 1325 | +#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14 |
| 1326 | +#define WF_LWTBL_OWN_MLD_ID_DW 29 |
| 1327 | +#define WF_LWTBL_OWN_MLD_ID_ADDR 116 |
| 1328 | +#define WF_LWTBL_OWN_MLD_ID_MASK \ |
| 1329 | + 0x003f0000 // 21-16 |
| 1330 | +#define WF_LWTBL_OWN_MLD_ID_SHIFT 16 |
| 1331 | +#define WF_LWTBL_EMLSR0_DW 29 |
| 1332 | +#define WF_LWTBL_EMLSR0_ADDR 116 |
| 1333 | +#define WF_LWTBL_EMLSR0_MASK \ |
| 1334 | + 0x00400000 // 22-22 |
| 1335 | +#define WF_LWTBL_EMLSR0_SHIFT 22 |
| 1336 | +#define WF_LWTBL_EMLMR0_DW 29 |
| 1337 | +#define WF_LWTBL_EMLMR0_ADDR 116 |
| 1338 | +#define WF_LWTBL_EMLMR0_MASK \ |
| 1339 | + 0x00800000 // 23-23 |
| 1340 | +#define WF_LWTBL_EMLMR0_SHIFT 23 |
| 1341 | +#define WF_LWTBL_EMLSR1_DW 29 |
| 1342 | +#define WF_LWTBL_EMLSR1_ADDR 116 |
| 1343 | +#define WF_LWTBL_EMLSR1_MASK \ |
| 1344 | + 0x01000000 // 24-24 |
| 1345 | +#define WF_LWTBL_EMLSR1_SHIFT 24 |
| 1346 | +#define WF_LWTBL_EMLMR1_DW 29 |
| 1347 | +#define WF_LWTBL_EMLMR1_ADDR 116 |
| 1348 | +#define WF_LWTBL_EMLMR1_MASK \ |
| 1349 | + 0x02000000 // 25-25 |
| 1350 | +#define WF_LWTBL_EMLMR1_SHIFT 25 |
| 1351 | +#define WF_LWTBL_EMLSR2_DW 29 |
| 1352 | +#define WF_LWTBL_EMLSR2_ADDR 116 |
| 1353 | +#define WF_LWTBL_EMLSR2_MASK \ |
| 1354 | + 0x04000000 // 26-26 |
| 1355 | +#define WF_LWTBL_EMLSR2_SHIFT 26 |
| 1356 | +#define WF_LWTBL_EMLMR2_DW 29 |
| 1357 | +#define WF_LWTBL_EMLMR2_ADDR 116 |
| 1358 | +#define WF_LWTBL_EMLMR2_MASK \ |
| 1359 | + 0x08000000 // 27-27 |
| 1360 | +#define WF_LWTBL_EMLMR2_SHIFT 27 |
| 1361 | +#define WF_LWTBL_STR_BITMAP_DW 29 |
| 1362 | +#define WF_LWTBL_STR_BITMAP_ADDR 116 |
| 1363 | +#define WF_LWTBL_STR_BITMAP_MASK \ |
| 1364 | + 0xe0000000 // 31-29 |
| 1365 | +#define WF_LWTBL_STR_BITMAP_SHIFT 29 |
| 1366 | +// DW30 |
| 1367 | +#define WF_LWTBL_DISPATCH_ORDER_DW 30 |
| 1368 | +#define WF_LWTBL_DISPATCH_ORDER_ADDR 120 |
| 1369 | +#define WF_LWTBL_DISPATCH_ORDER_MASK \ |
| 1370 | + 0x0000007f // 6- 0 |
| 1371 | +#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0 |
| 1372 | +#define WF_LWTBL_DISPATCH_RATIO_DW 30 |
| 1373 | +#define WF_LWTBL_DISPATCH_RATIO_ADDR 120 |
| 1374 | +#define WF_LWTBL_DISPATCH_RATIO_MASK \ |
| 1375 | + 0x00003f80 // 13- 7 |
| 1376 | +#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7 |
| 1377 | +#define WF_LWTBL_LINK_MGF_DW 30 |
| 1378 | +#define WF_LWTBL_LINK_MGF_ADDR 120 |
| 1379 | +#define WF_LWTBL_LINK_MGF_MASK \ |
| 1380 | + 0xffff0000 // 31-16 |
| 1381 | +#define WF_LWTBL_LINK_MGF_SHIFT 16 |
| 1382 | +// DW31 |
| 1383 | +#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 31 |
| 1384 | +#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 124 |
| 1385 | +#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \ |
| 1386 | + 0x00000007 // 2- 0 |
| 1387 | +#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0 |
| 1388 | +#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 31 |
| 1389 | +#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 124 |
| 1390 | +#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \ |
| 1391 | + 0x00000038 // 5- 3 |
| 1392 | +#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3 |
| 1393 | +#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 31 |
| 1394 | +#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 124 |
| 1395 | +#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \ |
| 1396 | + 0x000001c0 // 8- 6 |
| 1397 | +#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6 |
| 1398 | +#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 31 |
| 1399 | +#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 124 |
| 1400 | +#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \ |
| 1401 | + 0x00000e00 // 11- 9 |
| 1402 | +#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9 |
| 1403 | +#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 31 |
| 1404 | +#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 124 |
| 1405 | +#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \ |
| 1406 | + 0x00007000 // 14-12 |
| 1407 | +#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12 |
| 1408 | +#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 31 |
| 1409 | +#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 124 |
| 1410 | +#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \ |
| 1411 | + 0x00038000 // 17-15 |
| 1412 | +#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15 |
| 1413 | +#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 31 |
| 1414 | +#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 124 |
| 1415 | +#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \ |
| 1416 | + 0x001c0000 // 20-18 |
| 1417 | +#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18 |
| 1418 | +#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 31 |
| 1419 | +#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 124 |
| 1420 | +#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \ |
| 1421 | + 0x00e00000 // 23-21 |
| 1422 | +#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21 |
| 1423 | +#define WF_LWTBL_CASCAD_DW 31 |
| 1424 | +#define WF_LWTBL_CASCAD_ADDR 124 |
| 1425 | +#define WF_LWTBL_CASCAD_MASK \ |
| 1426 | + 0x02000000 // 25-25 |
| 1427 | +#define WF_LWTBL_CASCAD_SHIFT 25 |
| 1428 | +#define WF_LWTBL_ALL_ACK_DW 31 |
| 1429 | +#define WF_LWTBL_ALL_ACK_ADDR 124 |
| 1430 | +#define WF_LWTBL_ALL_ACK_MASK \ |
| 1431 | + 0x04000000 // 26-26 |
| 1432 | +#define WF_LWTBL_ALL_ACK_SHIFT 26 |
| 1433 | +#define WF_LWTBL_MPDU_SIZE_DW 31 |
| 1434 | +#define WF_LWTBL_MPDU_SIZE_ADDR 124 |
| 1435 | +#define WF_LWTBL_MPDU_SIZE_MASK \ |
| 1436 | + 0x18000000 // 28-27 |
| 1437 | +#define WF_LWTBL_MPDU_SIZE_SHIFT 27 |
| 1438 | +#define WF_LWTBL_BA_MODE_DW 31 |
| 1439 | +#define WF_LWTBL_BA_MODE_ADDR 124 |
| 1440 | +#define WF_LWTBL_BA_MODE_MASK \ |
| 1441 | + 0xe0000000 // 31-29 |
| 1442 | +#define WF_LWTBL_BA_MODE_SHIFT 29 |
| 1443 | +// DW32 |
| 1444 | +#define WF_LWTBL_OM_INFO_DW 32 |
| 1445 | +#define WF_LWTBL_OM_INFO_ADDR 128 |
| 1446 | +#define WF_LWTBL_OM_INFO_MASK \ |
| 1447 | + 0x00000fff // 11- 0 |
| 1448 | +#define WF_LWTBL_OM_INFO_SHIFT 0 |
| 1449 | +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32 |
| 1450 | +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128 |
| 1451 | +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \ |
| 1452 | + 0x00001000 // 12-12 |
| 1453 | +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 12 |
| 1454 | +#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32 |
| 1455 | +#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128 |
| 1456 | +#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \ |
| 1457 | + 0x01ffe000 // 24-13 |
| 1458 | +#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 13 |
| 1459 | +#define WF_LWTBL_RXD_DUP_MODE_DW 32 |
| 1460 | +#define WF_LWTBL_RXD_DUP_MODE_ADDR 128 |
| 1461 | +#define WF_LWTBL_RXD_DUP_MODE_MASK \ |
| 1462 | + 0x06000000 // 26-25 |
| 1463 | +#define WF_LWTBL_RXD_DUP_MODE_SHIFT 25 |
| 1464 | +#define WF_LWTBL_DROP_DW 32 |
| 1465 | +#define WF_LWTBL_DROP_ADDR 128 |
| 1466 | +#define WF_LWTBL_DROP_MASK \ |
| 1467 | + 0x40000000 // 30-30 |
| 1468 | +#define WF_LWTBL_DROP_SHIFT 30 |
| 1469 | +#define WF_LWTBL_ACK_EN_DW 32 |
| 1470 | +#define WF_LWTBL_ACK_EN_ADDR 128 |
| 1471 | +#define WF_LWTBL_ACK_EN_MASK \ |
| 1472 | + 0x80000000 // 31-31 |
| 1473 | +#define WF_LWTBL_ACK_EN_SHIFT 31 |
| 1474 | +// DW33 |
| 1475 | +#define WF_LWTBL_USER_RSSI_DW 33 |
| 1476 | +#define WF_LWTBL_USER_RSSI_ADDR 132 |
| 1477 | +#define WF_LWTBL_USER_RSSI_MASK \ |
| 1478 | + 0x000001ff // 8- 0 |
| 1479 | +#define WF_LWTBL_USER_RSSI_SHIFT 0 |
| 1480 | +#define WF_LWTBL_USER_SNR_DW 33 |
| 1481 | +#define WF_LWTBL_USER_SNR_ADDR 132 |
| 1482 | +#define WF_LWTBL_USER_SNR_MASK \ |
| 1483 | + 0x00007e00 // 14- 9 |
| 1484 | +#define WF_LWTBL_USER_SNR_SHIFT 9 |
| 1485 | +#define WF_LWTBL_RAPID_REACTION_RATE_DW 33 |
| 1486 | +#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132 |
| 1487 | +#define WF_LWTBL_RAPID_REACTION_RATE_MASK \ |
| 1488 | + 0x0fff0000 // 27-16 |
| 1489 | +#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16 |
| 1490 | +#define WF_LWTBL_HT_AMSDU_DW 33 |
| 1491 | +#define WF_LWTBL_HT_AMSDU_ADDR 132 |
| 1492 | +#define WF_LWTBL_HT_AMSDU_MASK \ |
| 1493 | + 0x40000000 // 30-30 |
| 1494 | +#define WF_LWTBL_HT_AMSDU_SHIFT 30 |
| 1495 | +#define WF_LWTBL_AMSDU_CROSS_LG_DW 33 |
| 1496 | +#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132 |
| 1497 | +#define WF_LWTBL_AMSDU_CROSS_LG_MASK \ |
| 1498 | + 0x80000000 // 31-31 |
| 1499 | +#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31 |
| 1500 | +// DW34 |
| 1501 | +#define WF_LWTBL_RESP_RCPI0_DW 34 |
| 1502 | +#define WF_LWTBL_RESP_RCPI0_ADDR 136 |
| 1503 | +#define WF_LWTBL_RESP_RCPI0_MASK \ |
| 1504 | + 0x000000ff // 7- 0 |
| 1505 | +#define WF_LWTBL_RESP_RCPI0_SHIFT 0 |
| 1506 | +#define WF_LWTBL_RESP_RCPI1_DW 34 |
| 1507 | +#define WF_LWTBL_RESP_RCPI1_ADDR 136 |
| 1508 | +#define WF_LWTBL_RESP_RCPI1_MASK \ |
| 1509 | + 0x0000ff00 // 15- 8 |
| 1510 | +#define WF_LWTBL_RESP_RCPI1_SHIFT 8 |
| 1511 | +#define WF_LWTBL_RESP_RCPI2_DW 34 |
| 1512 | +#define WF_LWTBL_RESP_RCPI2_ADDR 136 |
| 1513 | +#define WF_LWTBL_RESP_RCPI2_MASK \ |
| 1514 | + 0x00ff0000 // 23-16 |
| 1515 | +#define WF_LWTBL_RESP_RCPI2_SHIFT 16 |
| 1516 | +#define WF_LWTBL_RESP_RCPI3_DW 34 |
| 1517 | +#define WF_LWTBL_RESP_RCPI3_ADDR 136 |
| 1518 | +#define WF_LWTBL_RESP_RCPI3_MASK \ |
| 1519 | + 0xff000000 // 31-24 |
| 1520 | +#define WF_LWTBL_RESP_RCPI3_SHIFT 24 |
| 1521 | +// DW35 |
| 1522 | +#define WF_LWTBL_SNR_RX0_DW 35 |
| 1523 | +#define WF_LWTBL_SNR_RX0_ADDR 140 |
| 1524 | +#define WF_LWTBL_SNR_RX0_MASK \ |
| 1525 | + 0x0000003f // 5- 0 |
| 1526 | +#define WF_LWTBL_SNR_RX0_SHIFT 0 |
| 1527 | +#define WF_LWTBL_SNR_RX1_DW 35 |
| 1528 | +#define WF_LWTBL_SNR_RX1_ADDR 140 |
| 1529 | +#define WF_LWTBL_SNR_RX1_MASK \ |
| 1530 | + 0x00000fc0 // 11- 6 |
| 1531 | +#define WF_LWTBL_SNR_RX1_SHIFT 6 |
| 1532 | +#define WF_LWTBL_SNR_RX2_DW 35 |
| 1533 | +#define WF_LWTBL_SNR_RX2_ADDR 140 |
| 1534 | +#define WF_LWTBL_SNR_RX2_MASK \ |
| 1535 | + 0x0003f000 // 17-12 |
| 1536 | +#define WF_LWTBL_SNR_RX2_SHIFT 12 |
| 1537 | +#define WF_LWTBL_SNR_RX3_DW 35 |
| 1538 | +#define WF_LWTBL_SNR_RX3_ADDR 140 |
| 1539 | +#define WF_LWTBL_SNR_RX3_MASK \ |
| 1540 | + 0x00fc0000 // 23-18 |
| 1541 | +#define WF_LWTBL_SNR_RX3_SHIFT 18 |
| 1542 | + |
| 1543 | +/* WTBL Group - Packet Number */ |
| 1544 | +/* DW 2 */ |
| 1545 | +#define WTBL_PN0_MASK BITS(0, 7) |
| 1546 | +#define WTBL_PN0_OFFSET 0 |
| 1547 | +#define WTBL_PN1_MASK BITS(8, 15) |
| 1548 | +#define WTBL_PN1_OFFSET 8 |
| 1549 | +#define WTBL_PN2_MASK BITS(16, 23) |
| 1550 | +#define WTBL_PN2_OFFSET 16 |
| 1551 | +#define WTBL_PN3_MASK BITS(24, 31) |
| 1552 | +#define WTBL_PN3_OFFSET 24 |
| 1553 | + |
| 1554 | +/* DW 3 */ |
| 1555 | +#define WTBL_PN4_MASK BITS(0, 7) |
| 1556 | +#define WTBL_PN4_OFFSET 0 |
| 1557 | +#define WTBL_PN5_MASK BITS(8, 15) |
| 1558 | +#define WTBL_PN5_OFFSET 8 |
| 1559 | + |
| 1560 | +/* DW 4 */ |
| 1561 | +#define WTBL_BIPN0_MASK BITS(0, 7) |
| 1562 | +#define WTBL_BIPN0_OFFSET 0 |
| 1563 | +#define WTBL_BIPN1_MASK BITS(8, 15) |
| 1564 | +#define WTBL_BIPN1_OFFSET 8 |
| 1565 | +#define WTBL_BIPN2_MASK BITS(16, 23) |
| 1566 | +#define WTBL_BIPN2_OFFSET 16 |
| 1567 | +#define WTBL_BIPN3_MASK BITS(24, 31) |
| 1568 | +#define WTBL_BIPN3_OFFSET 24 |
| 1569 | + |
| 1570 | +/* DW 5 */ |
| 1571 | +#define WTBL_BIPN4_MASK BITS(0, 7) |
| 1572 | +#define WTBL_BIPN4_OFFSET 0 |
| 1573 | +#define WTBL_BIPN5_MASK BITS(8, 15) |
| 1574 | +#define WTBL_BIPN5_OFFSET 8 |
| 1575 | + |
| 1576 | +/* UWTBL DW 6 */ |
| 1577 | +#define WTBL_AMSDU_LEN_MASK BITS(0, 5) |
| 1578 | +#define WTBL_AMSDU_LEN_OFFSET 0 |
| 1579 | +#define WTBL_AMSDU_NUM_MASK BITS(6, 10) |
| 1580 | +#define WTBL_AMSDU_NUM_OFFSET 6 |
| 1581 | +#define WTBL_AMSDU_EN_MASK BIT(11) |
| 1582 | +#define WTBL_AMSDU_EN_OFFSET 11 |
| 1583 | + |
| 1584 | +/* LWTBL Rate field */ |
| 1585 | +#define WTBL_RATE_TX_RATE_MASK BITS(0, 5) |
| 1586 | +#define WTBL_RATE_TX_RATE_OFFSET 0 |
| 1587 | +#define WTBL_RATE_TX_MODE_MASK BITS(6, 9) |
| 1588 | +#define WTBL_RATE_TX_MODE_OFFSET 6 |
| 1589 | +#define WTBL_RATE_NSTS_MASK BITS(10, 13) |
| 1590 | +#define WTBL_RATE_NSTS_OFFSET 10 |
| 1591 | +#define WTBL_RATE_STBC_MASK BIT(14) |
| 1592 | +#define WTBL_RATE_STBC_OFFSET 14 |
| 1593 | + |
| 1594 | +/***** WTBL(LMAC) DW Offset *****/ |
| 1595 | +/* LMAC WTBL Group - Peer Unique Information */ |
| 1596 | +#define WTBL_GROUP_PEER_INFO_DW_0 0 |
| 1597 | +#define WTBL_GROUP_PEER_INFO_DW_1 1 |
| 1598 | + |
| 1599 | +/* WTBL Group - TxRx Capability/Information */ |
| 1600 | +#define WTBL_GROUP_TRX_CAP_DW_2 2 |
| 1601 | +#define WTBL_GROUP_TRX_CAP_DW_3 3 |
| 1602 | +#define WTBL_GROUP_TRX_CAP_DW_4 4 |
| 1603 | +#define WTBL_GROUP_TRX_CAP_DW_5 5 |
| 1604 | +#define WTBL_GROUP_TRX_CAP_DW_6 6 |
| 1605 | +#define WTBL_GROUP_TRX_CAP_DW_7 7 |
| 1606 | +#define WTBL_GROUP_TRX_CAP_DW_8 8 |
| 1607 | +#define WTBL_GROUP_TRX_CAP_DW_9 9 |
| 1608 | + |
| 1609 | +/* WTBL Group - Auto Rate Table*/ |
| 1610 | +#define WTBL_GROUP_AUTO_RATE_1_2 10 |
| 1611 | +#define WTBL_GROUP_AUTO_RATE_3_4 11 |
| 1612 | +#define WTBL_GROUP_AUTO_RATE_5_6 12 |
| 1613 | +#define WTBL_GROUP_AUTO_RATE_7_8 13 |
| 1614 | + |
| 1615 | +/* WTBL Group - Tx Counter */ |
| 1616 | +#define WTBL_GROUP_TX_CNT_LINE_1 14 |
| 1617 | +#define WTBL_GROUP_TX_CNT_LINE_2 15 |
| 1618 | +#define WTBL_GROUP_TX_CNT_LINE_3 16 |
| 1619 | +#define WTBL_GROUP_TX_CNT_LINE_4 17 |
| 1620 | +#define WTBL_GROUP_TX_CNT_LINE_5 18 |
| 1621 | +#define WTBL_GROUP_TX_CNT_LINE_6 19 |
| 1622 | + |
| 1623 | +/* WTBL Group - Admission Control Counter */ |
| 1624 | +#define WTBL_GROUP_ADM_CNT_LINE_1 20 |
| 1625 | +#define WTBL_GROUP_ADM_CNT_LINE_2 21 |
| 1626 | +#define WTBL_GROUP_ADM_CNT_LINE_3 22 |
| 1627 | +#define WTBL_GROUP_ADM_CNT_LINE_4 23 |
| 1628 | +#define WTBL_GROUP_ADM_CNT_LINE_5 24 |
| 1629 | +#define WTBL_GROUP_ADM_CNT_LINE_6 25 |
| 1630 | +#define WTBL_GROUP_ADM_CNT_LINE_7 26 |
| 1631 | +#define WTBL_GROUP_ADM_CNT_LINE_8 27 |
| 1632 | + |
| 1633 | +/* WTBL Group -MLO Info */ |
| 1634 | +#define WTBL_GROUP_MLO_INFO_LINE_1 28 |
| 1635 | +#define WTBL_GROUP_MLO_INFO_LINE_2 29 |
| 1636 | +#define WTBL_GROUP_MLO_INFO_LINE_3 30 |
| 1637 | + |
| 1638 | +/* WTBL Group -RESP Info */ |
| 1639 | +#define WTBL_GROUP_RESP_INFO_DW_31 31 |
| 1640 | + |
| 1641 | +/* WTBL Group -RX DUP Info */ |
| 1642 | +#define WTBL_GROUP_RX_DUP_INFO_DW_32 32 |
| 1643 | + |
| 1644 | +/* WTBL Group - Rx Statistics Counter */ |
| 1645 | +#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33 |
| 1646 | +#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34 |
| 1647 | +#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35 |
| 1648 | + |
| 1649 | +/* UWTBL Group - HW AMSDU */ |
| 1650 | +#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW |
| 1651 | + |
| 1652 | +/* LWTBL DW 4 */ |
| 1653 | +#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK |
| 1654 | + |
| 1655 | +/* UWTBL DW 5 */ |
| 1656 | +#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10) |
| 1657 | +#define WTBL_PSM WF_LWTBL_PSM_MASK |
| 1658 | + |
| 1659 | +/* Need to sync with FW define */ |
| 1660 | +#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK |
| 1661 | + |
| 1662 | +// RATE |
| 1663 | +#define WTBL_RATE_TX_RATE_MASK BITS(0, 5) |
| 1664 | +#define WTBL_RATE_TX_RATE_OFFSET 0 |
| 1665 | +#define WTBL_RATE_TX_MODE_MASK BITS(6, 9) |
| 1666 | +#define WTBL_RATE_TX_MODE_OFFSET 6 |
| 1667 | +#define WTBL_RATE_NSTS_MASK BITS(10, 13) |
| 1668 | +#define WTBL_RATE_NSTS_OFFSET 10 |
| 1669 | +#define WTBL_RATE_STBC_MASK BIT(14) |
| 1670 | +#define WTBL_RATE_STBC_OFFSET 14 |
| 1671 | + |
| 1672 | +/* DMA */ |
| 1673 | +// HOST DMA |
| 1674 | +//#define CONN_INFRA_REMAPPING_OFFSET 0x64000000 |
| 1675 | +//#define WF_WFDMA_HOST_DMA0_BASE (0x18024000 + CONN_INFRA_REMAPPING_OFFSET) |
| 1676 | +#define WF_WFDMA_HOST_DMA0_BASE 0xd4000 |
| 1677 | + |
| 1678 | +#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \ |
| 1679 | + (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */ |
| 1680 | +#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \ |
| 1681 | + (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */ |
| 1682 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \ |
| 1683 | + (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */ |
| 1684 | + |
| 1685 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \ |
| 1686 | + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| 1687 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \ |
| 1688 | + 0x00000008 /* RX_DMA_BUSY[3] */ |
| 1689 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3 |
| 1690 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \ |
| 1691 | + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| 1692 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \ |
| 1693 | + 0x00000004 /* RX_DMA_EN[2] */ |
| 1694 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2 |
| 1695 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \ |
| 1696 | + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| 1697 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \ |
| 1698 | + 0x00000002 /* TX_DMA_BUSY[1] */ |
| 1699 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1 |
| 1700 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \ |
| 1701 | + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| 1702 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \ |
| 1703 | + 0x00000001 /* TX_DMA_EN[0] */ |
| 1704 | +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0 |
| 1705 | + |
| 1706 | + |
| 1707 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \ |
| 1708 | + (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */ |
| 1709 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \ |
| 1710 | + (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */ |
| 1711 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \ |
| 1712 | + (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */ |
| 1713 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \ |
| 1714 | + (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */ |
| 1715 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \ |
| 1716 | + (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */ |
| 1717 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \ |
| 1718 | + (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */ |
| 1719 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \ |
| 1720 | + (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */ |
| 1721 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \ |
| 1722 | + (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */ |
| 1723 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \ |
| 1724 | + (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */ |
| 1725 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \ |
| 1726 | + (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */ |
| 1727 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \ |
| 1728 | + (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */ |
| 1729 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \ |
| 1730 | + (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */ |
| 1731 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \ |
| 1732 | + (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */ |
| 1733 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \ |
| 1734 | + (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */ |
| 1735 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \ |
| 1736 | + (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */ |
| 1737 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \ |
| 1738 | + (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */ |
| 1739 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \ |
| 1740 | + (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */ |
| 1741 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \ |
| 1742 | + (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */ |
| 1743 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \ |
| 1744 | + (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */ |
| 1745 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \ |
| 1746 | + (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */ |
| 1747 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \ |
| 1748 | + (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */ |
| 1749 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \ |
| 1750 | + (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */ |
| 1751 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \ |
| 1752 | + (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */ |
| 1753 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \ |
| 1754 | + (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */ |
| 1755 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \ |
| 1756 | + (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */ |
| 1757 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \ |
| 1758 | + (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */ |
| 1759 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \ |
| 1760 | + (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */ |
| 1761 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \ |
| 1762 | + (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */ |
| 1763 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \ |
| 1764 | + (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */ |
| 1765 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \ |
| 1766 | + (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */ |
| 1767 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \ |
| 1768 | + (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */ |
| 1769 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \ |
| 1770 | + (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */ |
| 1771 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \ |
| 1772 | + (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */ |
| 1773 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \ |
| 1774 | + (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */ |
| 1775 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \ |
| 1776 | + (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */ |
| 1777 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \ |
| 1778 | + (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */ |
| 1779 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \ |
| 1780 | + (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */ |
| 1781 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \ |
| 1782 | + (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */ |
| 1783 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \ |
| 1784 | + (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */ |
| 1785 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \ |
| 1786 | + (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */ |
| 1787 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \ |
| 1788 | + (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */ |
| 1789 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \ |
| 1790 | + (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */ |
| 1791 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \ |
| 1792 | + (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */ |
| 1793 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \ |
| 1794 | + (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */ |
| 1795 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \ |
| 1796 | + (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */ |
| 1797 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \ |
| 1798 | + (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */ |
| 1799 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \ |
| 1800 | + (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */ |
| 1801 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \ |
| 1802 | + (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */ |
| 1803 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \ |
| 1804 | + (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */ |
| 1805 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \ |
| 1806 | + (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */ |
| 1807 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \ |
| 1808 | + (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */ |
| 1809 | +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \ |
| 1810 | + |
| 1811 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \ |
| 1812 | + (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */ |
| 1813 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \ |
| 1814 | + (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */ |
| 1815 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \ |
| 1816 | + (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */ |
| 1817 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \ |
| 1818 | + (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */ |
| 1819 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \ |
| 1820 | + (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */ |
| 1821 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \ |
| 1822 | + (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */ |
| 1823 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \ |
| 1824 | + (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */ |
| 1825 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \ |
| 1826 | + (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */ |
| 1827 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \ |
| 1828 | + (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */ |
| 1829 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \ |
| 1830 | + (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */ |
| 1831 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \ |
| 1832 | + (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */ |
| 1833 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \ |
| 1834 | + (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */ |
| 1835 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \ |
| 1836 | + (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */ |
| 1837 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \ |
| 1838 | + (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */ |
| 1839 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \ |
| 1840 | + (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */ |
| 1841 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \ |
| 1842 | + (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */ |
| 1843 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \ |
| 1844 | + (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */ |
| 1845 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \ |
| 1846 | + (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */ |
| 1847 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \ |
| 1848 | + (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */ |
| 1849 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \ |
| 1850 | + (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */ |
| 1851 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \ |
| 1852 | + (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */ |
| 1853 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \ |
| 1854 | + (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */ |
| 1855 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \ |
| 1856 | + (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */ |
| 1857 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \ |
| 1858 | + (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */ |
| 1859 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \ |
| 1860 | + (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */ |
| 1861 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \ |
| 1862 | + (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */ |
| 1863 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \ |
| 1864 | + (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */ |
| 1865 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \ |
| 1866 | + (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */ |
| 1867 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \ |
| 1868 | + (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */ |
| 1869 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \ |
| 1870 | + (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */ |
| 1871 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \ |
| 1872 | + (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */ |
| 1873 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \ |
| 1874 | + (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */ |
| 1875 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \ |
| 1876 | + (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */ |
| 1877 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \ |
| 1878 | + (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */ |
| 1879 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \ |
| 1880 | + (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */ |
| 1881 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \ |
| 1882 | + (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */ |
| 1883 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \ |
| 1884 | + (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */ |
| 1885 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \ |
| 1886 | + (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */ |
| 1887 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \ |
| 1888 | + (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */ |
| 1889 | +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \ |
| 1890 | + (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */ |
| 1891 | + |
| 1892 | +//MCU DMA |
| 1893 | +//#define WF_WFDMA_MCU_DMA0_BASE 0x02000 |
| 1894 | +#define WF_WFDMA_MCU_DMA0_BASE 0x54000000 |
| 1895 | + |
| 1896 | +#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200 |
| 1897 | +#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204 |
| 1898 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208 |
| 1899 | + |
| 1900 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| 1901 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3] |
| 1902 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3 |
| 1903 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| 1904 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2] |
| 1905 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2 |
| 1906 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| 1907 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1] |
| 1908 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1 |
| 1909 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| 1910 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0] |
| 1911 | +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0 |
| 1912 | + |
| 1913 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300 |
| 1914 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304 |
| 1915 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308 |
| 1916 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C |
| 1917 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310 |
| 1918 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314 |
| 1919 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318 |
| 1920 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C |
| 1921 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320 |
| 1922 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324 |
| 1923 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328 |
| 1924 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C |
| 1925 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330 |
| 1926 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334 |
| 1927 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338 |
| 1928 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C |
| 1929 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340 |
| 1930 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344 |
| 1931 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348 |
| 1932 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C |
| 1933 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350 |
| 1934 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354 |
| 1935 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358 |
| 1936 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C |
| 1937 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360 |
| 1938 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364 |
| 1939 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368 |
| 1940 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C |
| 1941 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370 |
| 1942 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374 |
| 1943 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378 |
| 1944 | +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C |
| 1945 | + |
| 1946 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500 |
| 1947 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504 |
| 1948 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508 |
| 1949 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C |
| 1950 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510 |
| 1951 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514 |
| 1952 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518 |
| 1953 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C |
| 1954 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520 |
| 1955 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524 |
| 1956 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528 |
| 1957 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C |
| 1958 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530 |
| 1959 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534 |
| 1960 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538 |
| 1961 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C |
| 1962 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540 |
| 1963 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544 |
| 1964 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548 |
| 1965 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C |
| 1966 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550 |
| 1967 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554 |
| 1968 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558 |
| 1969 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C |
| 1970 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560 |
| 1971 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564 |
| 1972 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568 |
| 1973 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C |
| 1974 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570 |
| 1975 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574 |
| 1976 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578 |
| 1977 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C |
| 1978 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580 |
| 1979 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584 |
| 1980 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588 |
| 1981 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C |
| 1982 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590 |
| 1983 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594 |
| 1984 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598 |
| 1985 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C |
| 1986 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0 |
| 1987 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4 |
| 1988 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8 |
| 1989 | +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC |
| 1990 | + |
| 1991 | +// MEM DMA |
| 1992 | +#define WF_WFDMA_MEM_DMA_BASE 0x58000000 |
| 1993 | + |
| 1994 | +#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200 |
| 1995 | +#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204 |
| 1996 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208 |
| 1997 | + |
| 1998 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| 1999 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3] |
| 2000 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3 |
| 2001 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| 2002 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2] |
| 2003 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2 |
| 2004 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| 2005 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1] |
| 2006 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1 |
| 2007 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| 2008 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0] |
| 2009 | +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0 |
| 2010 | + |
| 2011 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300 |
| 2012 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304 |
| 2013 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308 |
| 2014 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C |
| 2015 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310 |
| 2016 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314 |
| 2017 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318 |
| 2018 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C |
| 2019 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320 |
| 2020 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324 |
| 2021 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328 |
| 2022 | +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C |
| 2023 | + |
| 2024 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500 |
| 2025 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504 |
| 2026 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508 |
| 2027 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C |
| 2028 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510 |
| 2029 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514 |
| 2030 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518 |
| 2031 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C |
| 2032 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520 |
| 2033 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524 |
| 2034 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528 |
| 2035 | +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C |
| 2036 | + |
| 2037 | +/* MIB INFO */ |
| 2038 | +#define WF_UMIB_TOP_BASE 0x820cd000 |
| 2039 | +#define BN0_WF_MIB_TOP_BASE 0x820ed000 |
| 2040 | +#define BN1_WF_MIB_TOP_BASE 0x820fd000 |
| 2041 | +#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000 |
| 2042 | + |
| 2043 | +#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x480) // D480 |
| 2044 | +#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D0) // D4D0 |
| 2045 | +#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x520) // D520 |
| 2046 | +#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5B4) // D5B4 |
| 2047 | +#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x6E8) // D6E8 |
| 2048 | + |
| 2049 | +#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000 |
| 2050 | +#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020 |
| 2051 | +#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024 |
| 2052 | +#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030 |
| 2053 | +#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400 |
| 2054 | +#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428 |
| 2055 | +#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0 |
| 2056 | +#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F8) // D4F8 |
| 2057 | +#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D4) // D6D4 |
| 2058 | + |
| 2059 | +#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x670) // D670 |
| 2060 | +#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x67C) // D67C |
| 2061 | +#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x680) // D680 |
| 2062 | +#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x684) // D684 |
| 2063 | +#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688 |
| 2064 | +#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x68C) // D68C |
| 2065 | +#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690 |
| 2066 | + |
| 2067 | +#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6AC) // D6AC |
| 2068 | +#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0 |
| 2069 | +#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B4) // D6B4 |
| 2070 | +#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B8) // D6B8 |
| 2071 | +#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC |
| 2072 | + |
| 2073 | +#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6DC) // D6DC |
| 2074 | +#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E0) // D6E0 |
| 2075 | +#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E4) // D6E4 |
| 2076 | +#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E8) // D6E8 |
| 2077 | +#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC |
| 2078 | + |
| 2079 | +#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0 |
| 2080 | +#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0 |
| 2081 | +#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600 |
| 2082 | +#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610 |
| 2083 | +#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620 |
| 2084 | +#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x73C) // D73C |
| 2085 | +#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x74C) // D74C |
| 2086 | + |
| 2087 | +#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x760) // D760 |
| 2088 | +#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964 |
| 2089 | +#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x9AC) // D9AC |
| 2090 | + |
| 2091 | +#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F4) // D9F4 |
| 2092 | +#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F8) // D9F8 |
| 2093 | +#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9FC) // D9FC |
| 2094 | +#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA00) // DA00 |
| 2095 | +#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA04) // DA04 |
| 2096 | + |
| 2097 | +#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x904) // D904 |
| 2098 | +#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x908) // D908 |
| 2099 | +#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x90C) // D90C |
| 2100 | +#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x918) // D918 |
| 2101 | +#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x920) // D920 |
| 2102 | +#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x928) // D928 |
| 2103 | +#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x92C) // D92C |
| 2104 | + |
| 2105 | +#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0] |
| 2106 | +#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0] |
| 2107 | +#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0] |
| 2108 | +#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0] |
| 2109 | +#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0] |
| 2110 | +#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0] |
| 2111 | +#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0] |
| 2112 | +#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0] |
| 2113 | +#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0] |
| 2114 | +#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0] |
| 2115 | +#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0] |
| 2116 | +#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0] |
| 2117 | +#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0] |
| 2118 | +#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0] |
| 2119 | +#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0] |
| 2120 | +#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0] |
| 2121 | +#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0] |
| 2122 | +#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0] |
| 2123 | +#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0] |
| 2124 | +#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0] |
| 2125 | +#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0] |
| 2126 | +#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0] |
| 2127 | +#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0] |
| 2128 | +#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0] |
| 2129 | +#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0] |
| 2130 | +#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0] |
| 2131 | +#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0] |
| 2132 | +#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0] |
| 2133 | +#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0] |
| 2134 | +#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0] |
| 2135 | +#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0] |
| 2136 | + |
| 2137 | +/* PLE AMSDU */ |
| 2138 | +#define WF_PLE_TOP_BASE 0x820c0000 |
| 2139 | + |
| 2140 | +#define WF_PLE_TOP_AMSDU_PACK_1_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e0) // 10E0 |
| 2141 | +#define WF_PLE_TOP_AMSDU_PACK_2_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e4) // 10E4 |
| 2142 | +#define WF_PLE_TOP_AMSDU_PACK_3_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e8) // 10E8 |
| 2143 | +#define WF_PLE_TOP_AMSDU_PACK_4_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10ec) // 10EC |
| 2144 | +#define WF_PLE_TOP_AMSDU_PACK_5_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f0) // 10F0 |
| 2145 | +#define WF_PLE_TOP_AMSDU_PACK_6_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f4) // 10F4 |
| 2146 | +#define WF_PLE_TOP_AMSDU_PACK_7_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f8) // 10F8 |
| 2147 | +#define WF_PLE_TOP_AMSDU_PACK_8_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10fc) // 10FC |
| 2148 | + |
| 2149 | +/* PLE */ |
| 2150 | +#define WF_PLE_TOP_PBUF_CTRL_ADDR (WF_PLE_TOP_BASE + 0x04) // 0004 |
| 2151 | + |
| 2152 | +#define WF_PLE_TOP_PG_HIF_GROUP_ADDR (WF_PLE_TOP_BASE + 0x0c) // 000C |
| 2153 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x10) // 0010 |
| 2154 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x14) // 0014 |
| 2155 | +#define WF_PLE_TOP_PG_CPU_GROUP_ADDR (WF_PLE_TOP_BASE + 0x18) // 0018 |
| 2156 | +#define WF_PLE_TOP_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x360) // 0360 |
| 2157 | + |
| 2158 | +#define WF_PLE_TOP_DIS_STA_MAP0_ADDR (WF_PLE_TOP_BASE + 0x100) // 0100 |
| 2159 | +#define WF_PLE_TOP_DIS_STA_MAP1_ADDR (WF_PLE_TOP_BASE + 0x104) // 0104 |
| 2160 | +#define WF_PLE_TOP_DIS_STA_MAP2_ADDR (WF_PLE_TOP_BASE + 0x108) // 0108 |
| 2161 | +#define WF_PLE_TOP_DIS_STA_MAP3_ADDR (WF_PLE_TOP_BASE + 0x10c) // 010C |
| 2162 | +#define WF_PLE_TOP_DIS_STA_MAP4_ADDR (WF_PLE_TOP_BASE + 0x110) // 0110 |
| 2163 | +#define WF_PLE_TOP_DIS_STA_MAP5_ADDR (WF_PLE_TOP_BASE + 0x114) // 0114 |
| 2164 | +#define WF_PLE_TOP_DIS_STA_MAP6_ADDR (WF_PLE_TOP_BASE + 0x118) // 0118 |
| 2165 | +#define WF_PLE_TOP_DIS_STA_MAP7_ADDR (WF_PLE_TOP_BASE + 0x11c) // 011C |
| 2166 | +#define WF_PLE_TOP_DIS_STA_MAP8_ADDR (WF_PLE_TOP_BASE + 0x120) // 0120 |
| 2167 | + |
| 2168 | +#define WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x378) // 0378 |
| 2169 | +#define WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x37c) // 037C |
| 2170 | + |
| 2171 | +#define WF_PLE_TOP_FREEPG_CNT_ADDR (WF_PLE_TOP_BASE + 0x3a0) // 03A0 |
| 2172 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PLE_TOP_BASE + 0x3a4) // 03A4 |
| 2173 | +#define WF_PLE_TOP_HIF_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3a8) // 03A8 |
| 2174 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3ac) // 03AC |
| 2175 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b0) // 03B0 |
| 2176 | +#define WF_PLE_TOP_CPU_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b4) // 03B4 |
| 2177 | + |
| 2178 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_ADDR (WF_PLE_TOP_BASE + 0x3e0) // 03E0 |
| 2179 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_ADDR (WF_PLE_TOP_BASE + 0x3e4) // 03E4 |
| 2180 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_ADDR (WF_PLE_TOP_BASE + 0x3e8) // 03E8 |
| 2181 | +#define WF_PLE_TOP_FL_QUE_CTRL_3_ADDR (WF_PLE_TOP_BASE + 0x3ec) // 03EC |
| 2182 | + |
| 2183 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x600) // 0600 |
| 2184 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x604) // 0604 |
| 2185 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x608) // 0608 |
| 2186 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x60c) // 060C |
| 2187 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x610) // 0610 |
| 2188 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x614) // 0614 |
| 2189 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x618) // 0618 |
| 2190 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x61c) // 061C |
| 2191 | +#define WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x620) // 0620 |
| 2192 | + |
| 2193 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x700) // 0700 |
| 2194 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x704) // 0704 |
| 2195 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x708) // 0708 |
| 2196 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x70c) // 070C |
| 2197 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x710) // 0710 |
| 2198 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x714) // 0714 |
| 2199 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x718) // 0718 |
| 2200 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x71c) // 071C |
| 2201 | +#define WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x720) // 0720 |
| 2202 | + |
| 2203 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x800) // 0800 |
| 2204 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x804) // 0804 |
| 2205 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x808) // 0808 |
| 2206 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x80c) // 080C |
| 2207 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x810) // 0810 |
| 2208 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x814) // 0814 |
| 2209 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x818) // 0818 |
| 2210 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x81c) // 081C |
| 2211 | +#define WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x820) // 0820 |
| 2212 | + |
| 2213 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x900) // 0900 |
| 2214 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x904) // 0904 |
| 2215 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x908) // 0908 |
| 2216 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x90c) // 090C |
| 2217 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x910) // 0910 |
| 2218 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x914) // 0914 |
| 2219 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x918) // 0918 |
| 2220 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x91c) // 091C |
| 2221 | +#define WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x920) // 0920 |
| 2222 | + |
| 2223 | +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_ADDR WF_PLE_TOP_QUEUE_EMPTY_ADDR |
| 2224 | +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK 0x01000000 // ALL_AC_EMPTY[24] |
| 2225 | +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_SHFT 24 |
| 2226 | + |
| 2227 | +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR |
| 2228 | +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31] |
| 2229 | +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 |
| 2230 | +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR |
| 2231 | +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17] |
| 2232 | +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 |
| 2233 | +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR |
| 2234 | +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0] |
| 2235 | +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 |
| 2236 | + |
| 2237 | +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR |
| 2238 | +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16] |
| 2239 | +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 |
| 2240 | +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR |
| 2241 | +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0] |
| 2242 | +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 |
| 2243 | + |
| 2244 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR |
| 2245 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16] |
| 2246 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 |
| 2247 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR |
| 2248 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0] |
| 2249 | +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 |
| 2250 | + |
| 2251 | +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR |
| 2252 | +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK 0x0FFF0000 // HIF_MAX_QUOTA[27..16] |
| 2253 | +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT 16 |
| 2254 | +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR |
| 2255 | +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK 0x00000FFF // HIF_MIN_QUOTA[11..0] |
| 2256 | +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT 0 |
| 2257 | + |
| 2258 | +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR |
| 2259 | +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK 0x0FFF0000 // HIF_SRC_CNT[27..16] |
| 2260 | +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT 16 |
| 2261 | +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR |
| 2262 | +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK 0x00000FFF // HIF_RSV_CNT[11..0] |
| 2263 | +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT 0 |
| 2264 | + |
| 2265 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR |
| 2266 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_WMTXD_MAX_QUOTA[27..16] |
| 2267 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT 16 |
| 2268 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR |
| 2269 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK 0x00000FFF // HIF_WMTXD_MIN_QUOTA[11..0] |
| 2270 | +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT 0 |
| 2271 | + |
| 2272 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR |
| 2273 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK 0x0FFF0000 // HIF_WMTXD_SRC_CNT[27..16] |
| 2274 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT 16 |
| 2275 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR |
| 2276 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK 0x00000FFF // HIF_WMTXD_RSV_CNT[11..0] |
| 2277 | +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT 0 |
| 2278 | + |
| 2279 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR |
| 2280 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_TXCMD_MAX_QUOTA[27..16] |
| 2281 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT 16 |
| 2282 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR |
| 2283 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK 0x00000FFF // HIF_TXCMD_MIN_QUOTA[11..0] |
| 2284 | +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT 0 |
| 2285 | + |
| 2286 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR |
| 2287 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK 0x0FFF0000 // HIF_TXCMD_SRC_CNT[27..16] |
| 2288 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT 16 |
| 2289 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR |
| 2290 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK 0x00000FFF // HIF_TXCMD_RSV_CNT[11..0] |
| 2291 | +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT 0 |
| 2292 | + |
| 2293 | +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR |
| 2294 | +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16] |
| 2295 | +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 |
| 2296 | +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR |
| 2297 | +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0] |
| 2298 | +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 |
| 2299 | + |
| 2300 | +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR |
| 2301 | +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16] |
| 2302 | +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 |
| 2303 | +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR |
| 2304 | +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0] |
| 2305 | +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 |
| 2306 | + |
| 2307 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| 2308 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31] |
| 2309 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 |
| 2310 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| 2311 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24] |
| 2312 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 |
| 2313 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| 2314 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 // FL_BUFFER_ADDR[23..12] |
| 2315 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12 |
| 2316 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| 2317 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x00000FFF // Q_BUF_WLANID[11..0] |
| 2318 | +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0 |
| 2319 | + |
| 2320 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR |
| 2321 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_MASK 0xC0000000 // Q_BUF_TGID[31..30] |
| 2322 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT 30 |
| 2323 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR |
| 2324 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28] |
| 2325 | +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28 |
| 2326 | + |
| 2327 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR |
| 2328 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16] |
| 2329 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 |
| 2330 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR |
| 2331 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0] |
| 2332 | +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 |
| 2333 | + |
| 2334 | +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PLE_TOP_FL_QUE_CTRL_3_ADDR |
| 2335 | +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0] |
| 2336 | +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 |
| 2337 | + |
| 2338 | +/* PSE */ |
| 2339 | +#define WF_PSE_TOP_BASE 0x820c8000 |
| 2340 | + |
| 2341 | +#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x04) // 8004 |
| 2342 | +#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) // 80B0 |
| 2343 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_ADDR (WF_PSE_TOP_BASE + 0xBC) // 80BC |
| 2344 | +#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) // 8110 |
| 2345 | +#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x114) // 8114 |
| 2346 | +#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) // 8118 |
| 2347 | +#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x11C) // 811C |
| 2348 | +#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x120) // 8120 |
| 2349 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x124) // 8124 |
| 2350 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x128) // 8128 |
| 2351 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x12C) // 812C |
| 2352 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x130) // 8130 |
| 2353 | +#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x134) // 8134 |
| 2354 | +#define WF_PSE_TOP_PG_MDP2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x13C) // 813C |
| 2355 | +#define WF_PSE_TOP_PG_HIF2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x140) // 8140 |
| 2356 | +#define WF_PSE_TOP_PG_MDP3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x144) // 8144 |
| 2357 | +#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x150) // 8150 |
| 2358 | +#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) // 8154 |
| 2359 | +#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x158) // 8158 |
| 2360 | +#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x15C) // 815C |
| 2361 | +#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x160) // 8160 |
| 2362 | +#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) // 8164 |
| 2363 | +#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x168) // 8168 |
| 2364 | +#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) // 816C |
| 2365 | +#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x170) // 8170 |
| 2366 | +#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) // 8174 |
| 2367 | +#define WF_PSE_TOP_MDP2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) // 817C |
| 2368 | +#define WF_PSE_TOP_HIF2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x180) // 8180 |
| 2369 | +#define WF_PSE_TOP_MDP3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) // 8184 |
| 2370 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) // 81B0 |
| 2371 | +#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) // 81B4 |
| 2372 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) // 81B8 |
| 2373 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) // 81BC |
| 2374 | +#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x380) // 8380 |
| 2375 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x384) // 8384 |
| 2376 | + |
| 2377 | +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR |
| 2378 | +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31] |
| 2379 | +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 |
| 2380 | +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR |
| 2381 | +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17] |
| 2382 | +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 |
| 2383 | +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR |
| 2384 | +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0] |
| 2385 | +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 |
| 2386 | + |
| 2387 | +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2388 | +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 // RLS_Q_EMTPY[31] |
| 2389 | +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31 |
| 2390 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2391 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK 0x10000000 // CPU_Q4_EMPTY[28] |
| 2392 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT 28 |
| 2393 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2394 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK 0x08000000 // MDP_RXIOC1_QUEUE_EMPTY[27] |
| 2395 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT 27 |
| 2396 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2397 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK 0x04000000 // MDP_TXIOC1_QUEUE_EMPTY[26] |
| 2398 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT 26 |
| 2399 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2400 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK 0x02000000 // SEC_TX1_QUEUE_EMPTY[25] |
| 2401 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT 25 |
| 2402 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2403 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK 0x01000000 // MDP_TX1_QUEUE_EMPTY[24] |
| 2404 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT 24 |
| 2405 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2406 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 // MDP_RXIOC_QUEUE_EMPTY[23] |
| 2407 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23 |
| 2408 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2409 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 // MDP_TXIOC_QUEUE_EMPTY[22] |
| 2410 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22 |
| 2411 | +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2412 | +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 // SFD_PARK_QUEUE_EMPTY[21] |
| 2413 | +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21 |
| 2414 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2415 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 // SEC_RX_QUEUE_EMPTY[20] |
| 2416 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20 |
| 2417 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2418 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 // SEC_TX_QUEUE_EMPTY[19] |
| 2419 | +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19 |
| 2420 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2421 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 // MDP_RX_QUEUE_EMPTY[18] |
| 2422 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18 |
| 2423 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2424 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 // MDP_TX_QUEUE_EMPTY[17] |
| 2425 | +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17 |
| 2426 | +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2427 | +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 // LMAC_TX_QUEUE_EMPTY[16] |
| 2428 | +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16 |
| 2429 | + |
| 2430 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2431 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 // CPU_Q3_EMPTY[3] |
| 2432 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3 |
| 2433 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2434 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 // CPU_Q2_EMPTY[2] |
| 2435 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2 |
| 2436 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2437 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 // CPU_Q1_EMPTY[1] |
| 2438 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1 |
| 2439 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| 2440 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 // CPU_Q0_EMPTY[0] |
| 2441 | +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0 |
| 2442 | + |
| 2443 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2444 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK 0x20000000 // HIF_13_EMPTY[29] |
| 2445 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT 29 |
| 2446 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2447 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK 0x10000000 // HIF_12_EMPTY[28] |
| 2448 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT 28 |
| 2449 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2450 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK 0x08000000 // HIF_11_EMPTY[27] |
| 2451 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT 27 |
| 2452 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2453 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK 0x04000000 // HIF_10_EMPTY[26] |
| 2454 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT 26 |
| 2455 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2456 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK 0x02000000 // HIF_9_EMPTY[25] |
| 2457 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT 25 |
| 2458 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2459 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK 0x01000000 // HIF_8_EMPTY[24] |
| 2460 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT 24 |
| 2461 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2462 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK 0x00800000 // HIF_7_EMPTY[23] |
| 2463 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT 23 |
| 2464 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2465 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK 0x00400000 // HIF_6_EMPTY[22] |
| 2466 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT 22 |
| 2467 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2468 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK 0x00200000 // HIF_5_EMPTY[21] |
| 2469 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT 21 |
| 2470 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2471 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK 0x00100000 // HIF_4_EMPTY[20] |
| 2472 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT 20 |
| 2473 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2474 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK 0x00080000 // HIF_3_EMPTY[19] |
| 2475 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT 19 |
| 2476 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2477 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK 0x00040000 // HIF_2_EMPTY[18] |
| 2478 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT 18 |
| 2479 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2480 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK 0x00020000 // HIF_1_EMPTY[17] |
| 2481 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT 17 |
| 2482 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2483 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK 0x00010000 // HIF_0_EMPTY[16] |
| 2484 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT 16 |
| 2485 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2486 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK 0x00008000 // MDP_RXIOC3_QUEUE_EMPTY[15] |
| 2487 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT 15 |
| 2488 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2489 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK 0x00000800 // MDP_RXIOC2_QUEUE_EMPTY[11] |
| 2490 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT 11 |
| 2491 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2492 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK 0x00000400 // MDP_TXIOC2_QUEUE_EMPTY[10] |
| 2493 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT 10 |
| 2494 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2495 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK 0x00000200 // SEC_TX2_QUEUE_EMPTY[9] |
| 2496 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT 9 |
| 2497 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| 2498 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK 0x00000100 // MDP_TX2_QUEUE_EMPTY[8] |
| 2499 | +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT 8 |
| 2500 | + |
| 2501 | +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR |
| 2502 | +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 // HIF0_MAX_QUOTA[27..16] |
| 2503 | +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16 |
| 2504 | +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR |
| 2505 | +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF // HIF0_MIN_QUOTA[11..0] |
| 2506 | +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0 |
| 2507 | + |
| 2508 | + |
| 2509 | +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR |
| 2510 | +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 // HIF1_MAX_QUOTA[27..16] |
| 2511 | +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16 |
| 2512 | +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR |
| 2513 | +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF // HIF1_MIN_QUOTA[11..0] |
| 2514 | +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0 |
| 2515 | + |
| 2516 | +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR |
| 2517 | +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16] |
| 2518 | +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 |
| 2519 | +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR |
| 2520 | +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0] |
| 2521 | +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 |
| 2522 | + |
| 2523 | +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR |
| 2524 | +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 // PLE_MAX_QUOTA[27..16] |
| 2525 | +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16 |
| 2526 | +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR |
| 2527 | +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK 0x00000FFF // PLE_MIN_QUOTA[11..0] |
| 2528 | +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT 0 |
| 2529 | + |
| 2530 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR |
| 2531 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK 0x0FFF0000 // LMAC0_MAX_QUOTA[27..16] |
| 2532 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT 16 |
| 2533 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR |
| 2534 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK 0x00000FFF // LMAC0_MIN_QUOTA[11..0] |
| 2535 | +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT 0 |
| 2536 | + |
| 2537 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR |
| 2538 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK 0x0FFF0000 // LMAC1_MAX_QUOTA[27..16] |
| 2539 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT 16 |
| 2540 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR |
| 2541 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK 0x00000FFF // LMAC1_MIN_QUOTA[11..0] |
| 2542 | +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT 0 |
| 2543 | + |
| 2544 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR |
| 2545 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK 0x0FFF0000 // LMAC2_MAX_QUOTA[27..16] |
| 2546 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT 16 |
| 2547 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR |
| 2548 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK 0x00000FFF // LMAC2_MIN_QUOTA[11..0] |
| 2549 | +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT 0 |
| 2550 | + |
| 2551 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR |
| 2552 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK 0x0FFF0000 // LMAC3_MAX_QUOTA[27..16] |
| 2553 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT 16 |
| 2554 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR |
| 2555 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK 0x00000FFF // LMAC3_MIN_QUOTA[11..0] |
| 2556 | +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT 0 |
| 2557 | + |
| 2558 | +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR |
| 2559 | +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK 0x0FFF0000 // MDP_MAX_QUOTA[27..16] |
| 2560 | +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT 16 |
| 2561 | +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR |
| 2562 | +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK 0x00000FFF // MDP_MIN_QUOTA[11..0] |
| 2563 | +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT 0 |
| 2564 | + |
| 2565 | +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP2_GROUP_ADDR |
| 2566 | +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_MASK 0x0FFF0000 // MDP2_MAX_QUOTA[27..16] |
| 2567 | +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_SHFT 16 |
| 2568 | +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP2_GROUP_ADDR |
| 2569 | +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_MASK 0x00000FFF // MDP2_MIN_QUOTA[11..0] |
| 2570 | +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_SHFT 0 |
| 2571 | + |
| 2572 | +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF2_GROUP_ADDR |
| 2573 | +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_MASK 0x0FFF0000 // HIF2_MAX_QUOTA[27..16] |
| 2574 | +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_SHFT 16 |
| 2575 | +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF2_GROUP_ADDR |
| 2576 | +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_MASK 0x00000FFF // HIF2_MIN_QUOTA[11..0] |
| 2577 | +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_SHFT 0 |
| 2578 | + |
| 2579 | +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP3_GROUP_ADDR |
| 2580 | +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_MASK 0x0FFF0000 // MDP3_MAX_QUOTA[27..16] |
| 2581 | +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_SHFT 16 |
| 2582 | +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP3_GROUP_ADDR |
| 2583 | +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_MASK 0x00000FFF // MDP3_MIN_QUOTA[11..0] |
| 2584 | +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_SHFT 0 |
| 2585 | + |
| 2586 | +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR |
| 2587 | +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK 0x0FFF0000 // HIF0_SRC_CNT[27..16] |
| 2588 | +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT 16 |
| 2589 | +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR |
| 2590 | +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK 0x00000FFF // HIF0_RSV_CNT[11..0] |
| 2591 | +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT 0 |
| 2592 | + |
| 2593 | +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR |
| 2594 | +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK 0x0FFF0000 // HIF1_SRC_CNT[27..16] |
| 2595 | +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT 16 |
| 2596 | +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR |
| 2597 | +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK 0x00000FFF // HIF1_RSV_CNT[11..0] |
| 2598 | +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT 0 |
| 2599 | + |
| 2600 | +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR |
| 2601 | +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16] |
| 2602 | +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 |
| 2603 | +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR |
| 2604 | +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0] |
| 2605 | +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 |
| 2606 | + |
| 2607 | +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR |
| 2608 | +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK 0x0FFF0000 // PLE_SRC_CNT[27..16] |
| 2609 | +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT 16 |
| 2610 | +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR |
| 2611 | +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK 0x00000FFF // PLE_RSV_CNT[11..0] |
| 2612 | +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT 0 |
| 2613 | + |
| 2614 | +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR |
| 2615 | +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK 0x0FFF0000 // LMAC0_SRC_CNT[27..16] |
| 2616 | +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT 16 |
| 2617 | +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR |
| 2618 | +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK 0x00000FFF // LMAC0_RSV_CNT[11..0] |
| 2619 | +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT 0 |
| 2620 | + |
| 2621 | +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR |
| 2622 | +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK 0x0FFF0000 // LMAC1_SRC_CNT[27..16] |
| 2623 | +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT 16 |
| 2624 | +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR |
| 2625 | +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK 0x00000FFF // LMAC1_RSV_CNT[11..0] |
| 2626 | +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT 0 |
| 2627 | + |
| 2628 | +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR |
| 2629 | +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK 0x0FFF0000 // LMAC2_SRC_CNT[27..16] |
| 2630 | +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT 16 |
| 2631 | +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR |
| 2632 | +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK 0x00000FFF // LMAC2_RSV_CNT[11..0] |
| 2633 | +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT 0 |
| 2634 | + |
| 2635 | +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR |
| 2636 | +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK 0x0FFF0000 // LMAC3_SRC_CNT[27..16] |
| 2637 | +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT 16 |
| 2638 | +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR |
| 2639 | +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK 0x00000FFF // LMAC3_RSV_CNT[11..0] |
| 2640 | +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT 0 |
| 2641 | + |
| 2642 | +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR |
| 2643 | +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK 0x0FFF0000 // MDP_SRC_CNT[27..16] |
| 2644 | +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT 16 |
| 2645 | +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR |
| 2646 | +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK 0x00000FFF // MDP_RSV_CNT[11..0] |
| 2647 | +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT 0 |
| 2648 | + |
| 2649 | +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_ADDR WF_PSE_TOP_MDP2_PG_INFO_ADDR |
| 2650 | +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_MASK 0x0FFF0000 // MDP2_SRC_CNT[27..16] |
| 2651 | +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_SHFT 16 |
| 2652 | +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_ADDR WF_PSE_TOP_MDP2_PG_INFO_ADDR |
| 2653 | +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_MASK 0x00000FFF // MDP2_RSV_CNT[11..0] |
| 2654 | +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_SHFT 0 |
| 2655 | + |
| 2656 | +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_ADDR WF_PSE_TOP_HIF2_PG_INFO_ADDR |
| 2657 | +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_MASK 0x0FFF0000 // HIF2_SRC_CNT[27..16] |
| 2658 | +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_SHFT 16 |
| 2659 | +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_ADDR WF_PSE_TOP_HIF2_PG_INFO_ADDR |
| 2660 | +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_MASK 0x00000FFF // HIF2_RSV_CNT[11..0] |
| 2661 | +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_SHFT 0 |
| 2662 | + |
| 2663 | +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_ADDR WF_PSE_TOP_MDP3_PG_INFO_ADDR |
| 2664 | +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_MASK 0x0FFF0000 // MDP3_SRC_CNT[27..16] |
| 2665 | +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_SHFT 16 |
| 2666 | +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_ADDR WF_PSE_TOP_MDP3_PG_INFO_ADDR |
| 2667 | +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_MASK 0x00000FFF // MDP3_RSV_CNT[11..0] |
| 2668 | +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_SHFT 0 |
| 2669 | + |
| 2670 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR |
| 2671 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31] |
| 2672 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 |
| 2673 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR |
| 2674 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24] |
| 2675 | +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 |
| 2676 | + |
| 2677 | +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PSE_TOP_FL_QUE_CTRL_1_ADDR |
| 2678 | +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28] |
| 2679 | +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28 |
| 2680 | + |
| 2681 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR |
| 2682 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16] |
| 2683 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 |
| 2684 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR |
| 2685 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0] |
| 2686 | +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 |
| 2687 | + |
| 2688 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR |
| 2689 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_MASK 0x00FFF000 // QUEUE_PAGE_NUM[23..12] |
| 2690 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_SHFT 12 |
| 2691 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR |
| 2692 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0] |
| 2693 | +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 |
| 2694 | + |
| 2695 | +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR |
| 2696 | +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16] |
| 2697 | +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 |
| 2698 | +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR |
| 2699 | +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0] |
| 2700 | +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 |
| 2701 | + |
| 2702 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR |
| 2703 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16] |
| 2704 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 |
| 2705 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR |
| 2706 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0] |
| 2707 | +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 |
| 2708 | + |
| 2709 | +/* AGG */ |
| 2710 | +#define BN0_WF_AGG_TOP_BASE 0x820e2000 |
| 2711 | +#define BN1_WF_AGG_TOP_BASE 0x820f2000 |
| 2712 | +#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000 |
| 2713 | + |
| 2714 | +#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000 |
| 2715 | +#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004 |
| 2716 | +#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008 |
| 2717 | +#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C |
| 2718 | +#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010 |
| 2719 | +#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014 |
| 2720 | +#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018 |
| 2721 | +#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C |
| 2722 | +#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020 |
| 2723 | +#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024 |
| 2724 | +#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028 |
| 2725 | +#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C |
| 2726 | +#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030 |
| 2727 | +#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034 |
| 2728 | +#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038 |
| 2729 | +#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C |
| 2730 | +#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040 |
| 2731 | +#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044 |
| 2732 | +#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C |
| 2733 | +#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050 |
| 2734 | +#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054 |
| 2735 | +#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058 |
| 2736 | +#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C |
| 2737 | +#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060 |
| 2738 | +#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064 |
| 2739 | +#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068 |
| 2740 | +#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C |
| 2741 | +#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070 |
| 2742 | +#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074 |
| 2743 | +#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078 |
| 2744 | +#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C |
| 2745 | +#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080 |
| 2746 | +#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084 |
| 2747 | +#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088 |
| 2748 | +#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C |
| 2749 | +#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090 |
| 2750 | +#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094 |
| 2751 | +#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098 |
| 2752 | +#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C |
| 2753 | +#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0 |
| 2754 | +#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4 |
| 2755 | +#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8 |
| 2756 | +#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC |
| 2757 | +#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0 |
| 2758 | +#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4 |
| 2759 | +#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8 |
| 2760 | +#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC |
| 2761 | +#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0 |
| 2762 | +#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4 |
| 2763 | +#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8 |
| 2764 | +#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC |
| 2765 | +#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0 |
| 2766 | +#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4 |
| 2767 | +#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8 |
| 2768 | +#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC |
| 2769 | +#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0 |
| 2770 | +#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4 |
| 2771 | +#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8 |
| 2772 | +#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC |
| 2773 | +#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0xf0) // 20F0 |
| 2774 | +#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xf4) // 20F4 |
| 2775 | +#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0xf8) // 20F8 |
| 2776 | +#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + 0xfc) // 20FC |
| 2777 | +#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x100) // 2100 |
| 2778 | +#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + 0x104) // 2104 |
| 2779 | +#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108 |
| 2780 | +#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C |
| 2781 | +#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110 |
| 2782 | +#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114 |
| 2783 | +#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118 |
| 2784 | +#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C |
| 2785 | +#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x120) // 2120 |
| 2786 | +#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x124) // 2124 |
| 2787 | +#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x128) // 2128 |
| 2788 | +#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x12c) // 212C |
| 2789 | +#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x130) // 2130 |
| 2790 | +#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178 |
| 2791 | +#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198 |
| 2792 | +#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8 |
| 2793 | +#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC |
| 2794 | +#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0 |
| 2795 | +#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4 |
| 2796 | +#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8 |
| 2797 | +#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4 |
| 2798 | +#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8 |
| 2799 | +#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC |
| 2800 | +#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0 |
| 2801 | +#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4 |
| 2802 | +#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8 |
| 2803 | +#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC |
| 2804 | + |
| 2805 | +#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR |
| 2806 | +#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16] |
| 2807 | +#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16 |
| 2808 | +#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR |
| 2809 | +#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0] |
| 2810 | +#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0 |
| 2811 | + |
| 2812 | +#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR |
| 2813 | +#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16] |
| 2814 | +#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16 |
| 2815 | +#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR |
| 2816 | +#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0] |
| 2817 | +#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0 |
| 2818 | + |
| 2819 | +#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR |
| 2820 | +#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16] |
| 2821 | +#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16 |
| 2822 | +#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR |
| 2823 | +#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0] |
| 2824 | +#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0 |
| 2825 | + |
| 2826 | +#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR |
| 2827 | +#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16] |
| 2828 | +#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16 |
| 2829 | +#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR |
| 2830 | +#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0] |
| 2831 | +#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0 |
| 2832 | + |
| 2833 | +#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR |
| 2834 | +#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16] |
| 2835 | +#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16 |
| 2836 | +#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR |
| 2837 | +#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0] |
| 2838 | +#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0 |
| 2839 | + |
| 2840 | +#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR |
| 2841 | +#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16] |
| 2842 | +#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16 |
| 2843 | +#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR |
| 2844 | +#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0] |
| 2845 | +#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0 |
| 2846 | + |
| 2847 | +#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR |
| 2848 | +#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16] |
| 2849 | +#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16 |
| 2850 | +#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR |
| 2851 | +#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0] |
| 2852 | +#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0 |
| 2853 | +#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR |
| 2854 | +#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16] |
| 2855 | +#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16 |
| 2856 | +#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR |
| 2857 | +#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0] |
| 2858 | +#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0 |
| 2859 | + |
| 2860 | +/* MIB */ |
| 2861 | +#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0 |
| 2862 | +#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4 |
| 2863 | +#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8 |
| 2864 | +#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC |
| 2865 | +#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0 |
| 2866 | +#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4 |
| 2867 | +#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8 |
| 2868 | +#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC |
| 2869 | + |
| 2870 | +#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B4) // D9B4 |
| 2871 | +#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B8) // D9B8 |
| 2872 | +#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9BC) // D9BC |
| 2873 | +#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C0) // D9C0 |
| 2874 | +#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C4) // D9C4 |
| 2875 | +#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C8) // D9C8 |
| 2876 | +#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x9CC) // D9CC |
| 2877 | +#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D0) // D9D0 |
| 2878 | +#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4 |
| 2879 | +#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D8) // D9D8 |
| 2880 | +#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0x9DC) // D9DC |
| 2881 | +#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E0) // D9E0 |
| 2882 | +#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E4) // D9E4 |
| 2883 | +#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E8) // D9E8 |
| 2884 | +#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0x9EC) // D9EC |
| 2885 | +#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F0) // D9F0 |
| 2886 | + |
| 2887 | +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR |
| 2888 | +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16] |
| 2889 | +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16 |
| 2890 | +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR |
| 2891 | +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0] |
| 2892 | +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0 |
| 2893 | + |
| 2894 | +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR |
| 2895 | +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16] |
| 2896 | +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16 |
| 2897 | +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR |
| 2898 | +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0] |
| 2899 | +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0 |
| 2900 | + |
| 2901 | +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR |
| 2902 | +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16] |
| 2903 | +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16 |
| 2904 | +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR |
| 2905 | +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0] |
| 2906 | +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0 |
| 2907 | + |
| 2908 | +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR |
| 2909 | +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16] |
| 2910 | +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16 |
| 2911 | +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR |
| 2912 | +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0] |
| 2913 | +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0 |
| 2914 | + |
| 2915 | +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR |
| 2916 | +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16] |
| 2917 | +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16 |
| 2918 | +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR |
| 2919 | +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0] |
| 2920 | +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0 |
| 2921 | + |
| 2922 | +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR |
| 2923 | +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16] |
| 2924 | +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16 |
| 2925 | +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR |
| 2926 | +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0] |
| 2927 | +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0 |
| 2928 | + |
| 2929 | +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR |
| 2930 | +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16] |
| 2931 | +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16 |
| 2932 | +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR |
| 2933 | +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0] |
| 2934 | +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0 |
| 2935 | + |
| 2936 | +#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR |
| 2937 | +#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0] |
| 2938 | +#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0 |
| 2939 | + |
| 2940 | +/* RXD */ |
| 2941 | +enum { |
| 2942 | + BMAC_GROUP_VLD_1 = 0x01, |
| 2943 | + BMAC_GROUP_VLD_2 = 0x02, |
| 2944 | + BMAC_GROUP_VLD_3 = 0x04, |
| 2945 | + BMAC_GROUP_VLD_4 = 0x08, |
| 2946 | + BMAC_GROUP_VLD_5 = 0x10, |
| 2947 | +}; |
| 2948 | + |
| 2949 | +// DW0 |
| 2950 | +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_DW 0 |
| 2951 | +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_ADDR 0 |
| 2952 | +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_MASK 0x0000ffff // 15- 0 |
| 2953 | +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_SHIFT 0 |
| 2954 | +#define WF_RX_DESCRIPTOR_PACKET_TYPE_DW 0 |
| 2955 | +#define WF_RX_DESCRIPTOR_PACKET_TYPE_ADDR 0 |
| 2956 | +#define WF_RX_DESCRIPTOR_PACKET_TYPE_MASK 0xf8000000 // 31-27 |
| 2957 | +#define WF_RX_DESCRIPTOR_PACKET_TYPE_SHIFT 27 |
| 2958 | +// DW1 |
| 2959 | +#define WF_RX_DESCRIPTOR_MLD_ID_DW 1 |
| 2960 | +#define WF_RX_DESCRIPTOR_MLD_ID_ADDR 4 |
| 2961 | +#define WF_RX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0 |
| 2962 | +#define WF_RX_DESCRIPTOR_MLD_ID_SHIFT 0 |
| 2963 | +#define WF_RX_DESCRIPTOR_GROUP_VLD_DW 1 |
| 2964 | +#define WF_RX_DESCRIPTOR_GROUP_VLD_ADDR 4 |
| 2965 | +#define WF_RX_DESCRIPTOR_GROUP_VLD_MASK 0x001f0000 // 20-16 |
| 2966 | +#define WF_RX_DESCRIPTOR_GROUP_VLD_SHIFT 16 |
| 2967 | +#define WF_RX_DESCRIPTOR_KID_DW 1 |
| 2968 | +#define WF_RX_DESCRIPTOR_KID_ADDR 4 |
| 2969 | +#define WF_RX_DESCRIPTOR_KID_MASK 0x00600000 // 22-21 |
| 2970 | +#define WF_RX_DESCRIPTOR_KID_SHIFT 21 |
| 2971 | +#define WF_RX_DESCRIPTOR_CM_DW 1 |
| 2972 | +#define WF_RX_DESCRIPTOR_CM_ADDR 4 |
| 2973 | +#define WF_RX_DESCRIPTOR_CM_MASK 0x00800000 // 23-23 |
| 2974 | +#define WF_RX_DESCRIPTOR_CM_SHIFT 23 |
| 2975 | +#define WF_RX_DESCRIPTOR_CLM_DW 1 |
| 2976 | +#define WF_RX_DESCRIPTOR_CLM_ADDR 4 |
| 2977 | +#define WF_RX_DESCRIPTOR_CLM_MASK 0x01000000 // 24-24 |
| 2978 | +#define WF_RX_DESCRIPTOR_CLM_SHIFT 24 |
| 2979 | +#define WF_RX_DESCRIPTOR_I_DW 1 |
| 2980 | +#define WF_RX_DESCRIPTOR_I_ADDR 4 |
| 2981 | +#define WF_RX_DESCRIPTOR_I_MASK 0x02000000 // 25-25 |
| 2982 | +#define WF_RX_DESCRIPTOR_I_SHIFT 25 |
| 2983 | +#define WF_RX_DESCRIPTOR_T_DW 1 |
| 2984 | +#define WF_RX_DESCRIPTOR_T_ADDR 4 |
| 2985 | +#define WF_RX_DESCRIPTOR_T_MASK 0x04000000 // 26-26 |
| 2986 | +#define WF_RX_DESCRIPTOR_T_SHIFT 26 |
| 2987 | +#define WF_RX_DESCRIPTOR_BN_DW 1 |
| 2988 | +#define WF_RX_DESCRIPTOR_BN_ADDR 4 |
| 2989 | +#define WF_RX_DESCRIPTOR_BN_MASK 0x18000000 // 28-27 |
| 2990 | +#define WF_RX_DESCRIPTOR_BN_SHIFT 27 |
| 2991 | +#define WF_RX_DESCRIPTOR_BIPN_FAIL_DW 1 |
| 2992 | +#define WF_RX_DESCRIPTOR_BIPN_FAIL_ADDR 4 |
| 2993 | +#define WF_RX_DESCRIPTOR_BIPN_FAIL_MASK 0x20000000 // 29-29 |
| 2994 | +#define WF_RX_DESCRIPTOR_BIPN_FAIL_SHIFT 29 |
| 2995 | +// DW2 |
| 2996 | +#define WF_RX_DESCRIPTOR_BSSID_DW 2 |
| 2997 | +#define WF_RX_DESCRIPTOR_BSSID_ADDR 8 |
| 2998 | +#define WF_RX_DESCRIPTOR_BSSID_MASK 0x0000003f // 5- 0 |
| 2999 | +#define WF_RX_DESCRIPTOR_BSSID_SHIFT 0 |
| 3000 | +#define WF_RX_DESCRIPTOR_H_DW 2 |
| 3001 | +#define WF_RX_DESCRIPTOR_H_ADDR 8 |
| 3002 | +#define WF_RX_DESCRIPTOR_H_MASK 0x00000080 // 7- 7 |
| 3003 | +#define WF_RX_DESCRIPTOR_H_SHIFT 7 |
| 3004 | +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_DW 2 |
| 3005 | +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_ADDR 8 |
| 3006 | +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_MASK 0x00001f00 // 12- 8 |
| 3007 | +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_SHIFT 8 |
| 3008 | +#define WF_RX_DESCRIPTOR_HO_DW 2 |
| 3009 | +#define WF_RX_DESCRIPTOR_HO_ADDR 8 |
| 3010 | +#define WF_RX_DESCRIPTOR_HO_MASK 0x0000e000 // 15-13 |
| 3011 | +#define WF_RX_DESCRIPTOR_HO_SHIFT 13 |
| 3012 | +#define WF_RX_DESCRIPTOR_SEC_MODE_DW 2 |
| 3013 | +#define WF_RX_DESCRIPTOR_SEC_MODE_ADDR 8 |
| 3014 | +#define WF_RX_DESCRIPTOR_SEC_MODE_MASK 0x001f0000 // 20-16 |
| 3015 | +#define WF_RX_DESCRIPTOR_SEC_MODE_SHIFT 16 |
| 3016 | +#define WF_RX_DESCRIPTOR_MUBAR_DW 2 |
| 3017 | +#define WF_RX_DESCRIPTOR_MUBAR_ADDR 8 |
| 3018 | +#define WF_RX_DESCRIPTOR_MUBAR_MASK 0x00200000 // 21-21 |
| 3019 | +#define WF_RX_DESCRIPTOR_MUBAR_SHIFT 21 |
| 3020 | +#define WF_RX_DESCRIPTOR_SWBIT_DW 2 |
| 3021 | +#define WF_RX_DESCRIPTOR_SWBIT_ADDR 8 |
| 3022 | +#define WF_RX_DESCRIPTOR_SWBIT_MASK 0x00400000 // 22-22 |
| 3023 | +#define WF_RX_DESCRIPTOR_SWBIT_SHIFT 22 |
| 3024 | +#define WF_RX_DESCRIPTOR_DAF_DW 2 |
| 3025 | +#define WF_RX_DESCRIPTOR_DAF_ADDR 8 |
| 3026 | +#define WF_RX_DESCRIPTOR_DAF_MASK 0x00800000 // 23-23 |
| 3027 | +#define WF_RX_DESCRIPTOR_DAF_SHIFT 23 |
| 3028 | +#define WF_RX_DESCRIPTOR_EL_DW 2 |
| 3029 | +#define WF_RX_DESCRIPTOR_EL_ADDR 8 |
| 3030 | +#define WF_RX_DESCRIPTOR_EL_MASK 0x01000000 // 24-24 |
| 3031 | +#define WF_RX_DESCRIPTOR_EL_SHIFT 24 |
| 3032 | +#define WF_RX_DESCRIPTOR_HTF_DW 2 |
| 3033 | +#define WF_RX_DESCRIPTOR_HTF_ADDR 8 |
| 3034 | +#define WF_RX_DESCRIPTOR_HTF_MASK 0x02000000 // 25-25 |
| 3035 | +#define WF_RX_DESCRIPTOR_HTF_SHIFT 25 |
| 3036 | +#define WF_RX_DESCRIPTOR_INTF_DW 2 |
| 3037 | +#define WF_RX_DESCRIPTOR_INTF_ADDR 8 |
| 3038 | +#define WF_RX_DESCRIPTOR_INTF_MASK 0x04000000 // 26-26 |
| 3039 | +#define WF_RX_DESCRIPTOR_INTF_SHIFT 26 |
| 3040 | +#define WF_RX_DESCRIPTOR_FRAG_DW 2 |
| 3041 | +#define WF_RX_DESCRIPTOR_FRAG_ADDR 8 |
| 3042 | +#define WF_RX_DESCRIPTOR_FRAG_MASK 0x08000000 // 27-27 |
| 3043 | +#define WF_RX_DESCRIPTOR_FRAG_SHIFT 27 |
| 3044 | +#define WF_RX_DESCRIPTOR_NUL_DW 2 |
| 3045 | +#define WF_RX_DESCRIPTOR_NUL_ADDR 8 |
| 3046 | +#define WF_RX_DESCRIPTOR_NUL_MASK 0x10000000 // 28-28 |
| 3047 | +#define WF_RX_DESCRIPTOR_NUL_SHIFT 28 |
| 3048 | +#define WF_RX_DESCRIPTOR_NDATA_DW 2 |
| 3049 | +#define WF_RX_DESCRIPTOR_NDATA_ADDR 8 |
| 3050 | +#define WF_RX_DESCRIPTOR_NDATA_MASK 0x20000000 // 29-29 |
| 3051 | +#define WF_RX_DESCRIPTOR_NDATA_SHIFT 29 |
| 3052 | +#define WF_RX_DESCRIPTOR_NAMP_DW 2 |
| 3053 | +#define WF_RX_DESCRIPTOR_NAMP_ADDR 8 |
| 3054 | +#define WF_RX_DESCRIPTOR_NAMP_MASK 0x40000000 // 30-30 |
| 3055 | +#define WF_RX_DESCRIPTOR_NAMP_SHIFT 30 |
| 3056 | +#define WF_RX_DESCRIPTOR_BF_RPT_DW 2 |
| 3057 | +#define WF_RX_DESCRIPTOR_BF_RPT_ADDR 8 |
| 3058 | +#define WF_RX_DESCRIPTOR_BF_RPT_MASK 0x80000000 // 31-31 |
| 3059 | +#define WF_RX_DESCRIPTOR_BF_RPT_SHIFT 31 |
| 3060 | +// DW3 |
| 3061 | +#define WF_RX_DESCRIPTOR_RXV_SN_DW 3 |
| 3062 | +#define WF_RX_DESCRIPTOR_RXV_SN_ADDR 12 |
| 3063 | +#define WF_RX_DESCRIPTOR_RXV_SN_MASK 0x000000ff // 7- 0 |
| 3064 | +#define WF_RX_DESCRIPTOR_RXV_SN_SHIFT 0 |
| 3065 | +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_DW 3 |
| 3066 | +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_ADDR 12 |
| 3067 | +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_MASK 0x0000ff00 // 15- 8 |
| 3068 | +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_SHIFT 8 |
| 3069 | +#define WF_RX_DESCRIPTOR_A1_TYPE_DW 3 |
| 3070 | +#define WF_RX_DESCRIPTOR_A1_TYPE_ADDR 12 |
| 3071 | +#define WF_RX_DESCRIPTOR_A1_TYPE_MASK 0x00030000 // 17-16 |
| 3072 | +#define WF_RX_DESCRIPTOR_A1_TYPE_SHIFT 16 |
| 3073 | +#define WF_RX_DESCRIPTOR_HTC_DW 3 |
| 3074 | +#define WF_RX_DESCRIPTOR_HTC_ADDR 12 |
| 3075 | +#define WF_RX_DESCRIPTOR_HTC_MASK 0x00040000 // 18-18 |
| 3076 | +#define WF_RX_DESCRIPTOR_HTC_SHIFT 18 |
| 3077 | +#define WF_RX_DESCRIPTOR_TCL_DW 3 |
| 3078 | +#define WF_RX_DESCRIPTOR_TCL_ADDR 12 |
| 3079 | +#define WF_RX_DESCRIPTOR_TCL_MASK 0x00080000 // 19-19 |
| 3080 | +#define WF_RX_DESCRIPTOR_TCL_SHIFT 19 |
| 3081 | +#define WF_RX_DESCRIPTOR_BBM_DW 3 |
| 3082 | +#define WF_RX_DESCRIPTOR_BBM_ADDR 12 |
| 3083 | +#define WF_RX_DESCRIPTOR_BBM_MASK 0x00100000 // 20-20 |
| 3084 | +#define WF_RX_DESCRIPTOR_BBM_SHIFT 20 |
| 3085 | +#define WF_RX_DESCRIPTOR_BU_DW 3 |
| 3086 | +#define WF_RX_DESCRIPTOR_BU_ADDR 12 |
| 3087 | +#define WF_RX_DESCRIPTOR_BU_MASK 0x00200000 // 21-21 |
| 3088 | +#define WF_RX_DESCRIPTOR_BU_SHIFT 21 |
| 3089 | +#define WF_RX_DESCRIPTOR_CO_ANT_DW 3 |
| 3090 | +#define WF_RX_DESCRIPTOR_CO_ANT_ADDR 12 |
| 3091 | +#define WF_RX_DESCRIPTOR_CO_ANT_MASK 0x00400000 // 22-22 |
| 3092 | +#define WF_RX_DESCRIPTOR_CO_ANT_SHIFT 22 |
| 3093 | +#define WF_RX_DESCRIPTOR_BF_CQI_DW 3 |
| 3094 | +#define WF_RX_DESCRIPTOR_BF_CQI_ADDR 12 |
| 3095 | +#define WF_RX_DESCRIPTOR_BF_CQI_MASK 0x00800000 // 23-23 |
| 3096 | +#define WF_RX_DESCRIPTOR_BF_CQI_SHIFT 23 |
| 3097 | +#define WF_RX_DESCRIPTOR_FC_DW 3 |
| 3098 | +#define WF_RX_DESCRIPTOR_FC_ADDR 12 |
| 3099 | +#define WF_RX_DESCRIPTOR_FC_MASK 0x01000000 // 24-24 |
| 3100 | +#define WF_RX_DESCRIPTOR_FC_SHIFT 24 |
| 3101 | +#define WF_RX_DESCRIPTOR_VLAN_DW 3 |
| 3102 | +#define WF_RX_DESCRIPTOR_VLAN_ADDR 12 |
| 3103 | +#define WF_RX_DESCRIPTOR_VLAN_MASK 0x80000000 // 31-31 |
| 3104 | +#define WF_RX_DESCRIPTOR_VLAN_SHIFT 31 |
| 3105 | +// DW4 |
| 3106 | +#define WF_RX_DESCRIPTOR_PF_DW 4 |
| 3107 | +#define WF_RX_DESCRIPTOR_PF_ADDR 16 |
| 3108 | +#define WF_RX_DESCRIPTOR_PF_MASK 0x00000003 // 1- 0 |
| 3109 | +#define WF_RX_DESCRIPTOR_PF_SHIFT 0 |
| 3110 | +#define WF_RX_DESCRIPTOR_MAC_DW 4 |
| 3111 | +#define WF_RX_DESCRIPTOR_MAC_ADDR 16 |
| 3112 | +#define WF_RX_DESCRIPTOR_MAC_MASK 0x00000004 // 2- 2 |
| 3113 | +#define WF_RX_DESCRIPTOR_MAC_SHIFT 2 |
| 3114 | +#define WF_RX_DESCRIPTOR_TID_DW 4 |
| 3115 | +#define WF_RX_DESCRIPTOR_TID_ADDR 16 |
| 3116 | +#define WF_RX_DESCRIPTOR_TID_MASK 0x00000078 // 6- 3 |
| 3117 | +#define WF_RX_DESCRIPTOR_TID_SHIFT 3 |
| 3118 | +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 4 |
| 3119 | +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 16 |
| 3120 | +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x00003f80 // 13- 7 |
| 3121 | +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 7 |
| 3122 | +#define WF_RX_DESCRIPTOR_IP_DW 4 |
| 3123 | +#define WF_RX_DESCRIPTOR_IP_ADDR 16 |
| 3124 | +#define WF_RX_DESCRIPTOR_IP_MASK 0x00004000 // 14-14 |
| 3125 | +#define WF_RX_DESCRIPTOR_IP_SHIFT 14 |
| 3126 | +#define WF_RX_DESCRIPTOR_UT_DW 4 |
| 3127 | +#define WF_RX_DESCRIPTOR_UT_ADDR 16 |
| 3128 | +#define WF_RX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15 |
| 3129 | +#define WF_RX_DESCRIPTOR_UT_SHIFT 15 |
| 3130 | +#define WF_RX_DESCRIPTOR_PSE_FID_DW 4 |
| 3131 | +#define WF_RX_DESCRIPTOR_PSE_FID_ADDR 16 |
| 3132 | +#define WF_RX_DESCRIPTOR_PSE_FID_MASK 0x0fff0000 // 27-16 |
| 3133 | +#define WF_RX_DESCRIPTOR_PSE_FID_SHIFT 16 |
| 3134 | +// DW5 |
| 3135 | +// DW6 |
| 3136 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__DW 6 |
| 3137 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__ADDR 24 |
| 3138 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__MASK 0xffffffff // 31- 0 |
| 3139 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__SHIFT 0 |
| 3140 | +// DW7 |
| 3141 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__DW 7 |
| 3142 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__ADDR 28 |
| 3143 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__MASK 0x00000003 // 1- 0 |
| 3144 | +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__SHIFT 0 |
| 3145 | +#define WF_RX_DESCRIPTOR_DP_DW 7 |
| 3146 | +#define WF_RX_DESCRIPTOR_DP_ADDR 28 |
| 3147 | +#define WF_RX_DESCRIPTOR_DP_MASK 0x00080000 // 19-19 |
| 3148 | +#define WF_RX_DESCRIPTOR_DP_SHIFT 19 |
| 3149 | +#define WF_RX_DESCRIPTOR_CLS_DW 7 |
| 3150 | +#define WF_RX_DESCRIPTOR_CLS_ADDR 28 |
| 3151 | +#define WF_RX_DESCRIPTOR_CLS_MASK 0x00100000 // 20-20 |
| 3152 | +#define WF_RX_DESCRIPTOR_CLS_SHIFT 20 |
| 3153 | +#define WF_RX_DESCRIPTOR_OFLD_DW 7 |
| 3154 | +#define WF_RX_DESCRIPTOR_OFLD_ADDR 28 |
| 3155 | +#define WF_RX_DESCRIPTOR_OFLD_MASK 0x00600000 // 22-21 |
| 3156 | +#define WF_RX_DESCRIPTOR_OFLD_SHIFT 21 |
| 3157 | +#define WF_RX_DESCRIPTOR_MGC_DW 7 |
| 3158 | +#define WF_RX_DESCRIPTOR_MGC_ADDR 28 |
| 3159 | +#define WF_RX_DESCRIPTOR_MGC_MASK 0x00800000 // 23-23 |
| 3160 | +#define WF_RX_DESCRIPTOR_MGC_SHIFT 23 |
| 3161 | +#define WF_RX_DESCRIPTOR_WOL_DW 7 |
| 3162 | +#define WF_RX_DESCRIPTOR_WOL_ADDR 28 |
| 3163 | +#define WF_RX_DESCRIPTOR_WOL_MASK 0x1f000000 // 28-24 |
| 3164 | +#define WF_RX_DESCRIPTOR_WOL_SHIFT 24 |
| 3165 | +#define WF_RX_DESCRIPTOR_PF_MODE_DW 7 |
| 3166 | +#define WF_RX_DESCRIPTOR_PF_MODE_ADDR 28 |
| 3167 | +#define WF_RX_DESCRIPTOR_PF_MODE_MASK 0x20000000 // 29-29 |
| 3168 | +#define WF_RX_DESCRIPTOR_PF_MODE_SHIFT 29 |
| 3169 | +#define WF_RX_DESCRIPTOR_PF_STS_DW 7 |
| 3170 | +#define WF_RX_DESCRIPTOR_PF_STS_ADDR 28 |
| 3171 | +#define WF_RX_DESCRIPTOR_PF_STS_MASK 0xc0000000 // 31-30 |
| 3172 | +#define WF_RX_DESCRIPTOR_PF_STS_SHIFT 30 |
| 3173 | +// DW8 |
| 3174 | +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_DW 8 |
| 3175 | +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_ADDR 32 |
| 3176 | +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_MASK 0x0000ffff // 15- 0 |
| 3177 | +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_SHIFT 0 |
| 3178 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__DW 8 |
| 3179 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__ADDR 32 |
| 3180 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__MASK 0xffff0000 // 31-16 |
| 3181 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__SHIFT 16 |
| 3182 | +// DW9 |
| 3183 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__DW 9 |
| 3184 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__ADDR 36 |
| 3185 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__MASK 0xffffffff // 31- 0 |
| 3186 | +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__SHIFT 0 |
| 3187 | +// DW10 |
| 3188 | +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_DW 10 |
| 3189 | +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_ADDR 40 |
| 3190 | +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_MASK 0x0000000f // 3- 0 |
| 3191 | +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_SHIFT 0 |
| 3192 | +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_DW 10 |
| 3193 | +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_ADDR 40 |
| 3194 | +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0x0000fff0 // 15- 4 |
| 3195 | +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_SHIFT 4 |
| 3196 | +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_DW 10 |
| 3197 | +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_ADDR 40 |
| 3198 | +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_MASK 0xffff0000 // 31-16 |
| 3199 | +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_SHIFT 16 |
| 3200 | +// DW11 |
| 3201 | +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_DW 11 |
| 3202 | +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_ADDR 44 |
| 3203 | +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_MASK 0xffffffff // 31- 0 |
| 3204 | +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_SHIFT 0 |
| 3205 | +// DW12 |
| 3206 | +#define WF_RX_DESCRIPTOR_PN_31_0__DW 12 |
| 3207 | +#define WF_RX_DESCRIPTOR_PN_31_0__ADDR 48 |
| 3208 | +#define WF_RX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0 |
| 3209 | +#define WF_RX_DESCRIPTOR_PN_31_0__SHIFT 0 |
| 3210 | +// DW13 |
| 3211 | +#define WF_RX_DESCRIPTOR_PN_63_32__DW 13 |
| 3212 | +#define WF_RX_DESCRIPTOR_PN_63_32__ADDR 52 |
| 3213 | +#define WF_RX_DESCRIPTOR_PN_63_32__MASK 0xffffffff // 31- 0 |
| 3214 | +#define WF_RX_DESCRIPTOR_PN_63_32__SHIFT 0 |
| 3215 | +// DW14 |
| 3216 | +#define WF_RX_DESCRIPTOR_PN_95_64__DW 14 |
| 3217 | +#define WF_RX_DESCRIPTOR_PN_95_64__ADDR 56 |
| 3218 | +#define WF_RX_DESCRIPTOR_PN_95_64__MASK 0xffffffff // 31- 0 |
| 3219 | +#define WF_RX_DESCRIPTOR_PN_95_64__SHIFT 0 |
| 3220 | +// DW15 |
| 3221 | +#define WF_RX_DESCRIPTOR_PN_127_96__DW 15 |
| 3222 | +#define WF_RX_DESCRIPTOR_PN_127_96__ADDR 60 |
| 3223 | +#define WF_RX_DESCRIPTOR_PN_127_96__MASK 0xffffffff // 31- 0 |
| 3224 | +#define WF_RX_DESCRIPTOR_PN_127_96__SHIFT 0 |
| 3225 | +// DW16 |
| 3226 | +#define WF_RX_DESCRIPTOR_TIMESTAMP_DW 16 |
| 3227 | +#define WF_RX_DESCRIPTOR_TIMESTAMP_ADDR 64 |
| 3228 | +#define WF_RX_DESCRIPTOR_TIMESTAMP_MASK 0xffffffff // 31- 0 |
| 3229 | +#define WF_RX_DESCRIPTOR_TIMESTAMP_SHIFT 0 |
| 3230 | +// DW17 |
| 3231 | +#define WF_RX_DESCRIPTOR_CRC_DW 17 |
| 3232 | +#define WF_RX_DESCRIPTOR_CRC_ADDR 68 |
| 3233 | +#define WF_RX_DESCRIPTOR_CRC_MASK 0xffffffff // 31- 0 |
| 3234 | +#define WF_RX_DESCRIPTOR_CRC_SHIFT 0 |
| 3235 | +// DW18 |
| 3236 | +// DW19 |
| 3237 | +// DW20 |
| 3238 | +#define WF_RX_DESCRIPTOR_P_RXV_DW 20 |
| 3239 | +#define WF_RX_DESCRIPTOR_P_RXV_ADDR 80 |
| 3240 | +#define WF_RX_DESCRIPTOR_P_RXV_MASK 0xffffffff // 31- 0 |
| 3241 | +#define WF_RX_DESCRIPTOR_P_RXV_SHIFT 0 |
| 3242 | +// DW21 |
| 3243 | +// DO NOT process repeat field(p_rxv) |
| 3244 | +// DW22 |
| 3245 | +#define WF_RX_DESCRIPTOR_DBW_DW 22 |
| 3246 | +#define WF_RX_DESCRIPTOR_DBW_ADDR 88 |
| 3247 | +#define WF_RX_DESCRIPTOR_DBW_MASK 0x00000007 // 2- 0 |
| 3248 | +#define WF_RX_DESCRIPTOR_DBW_SHIFT 0 |
| 3249 | +#define WF_RX_DESCRIPTOR_GI_DW 22 |
| 3250 | +#define WF_RX_DESCRIPTOR_GI_ADDR 88 |
| 3251 | +#define WF_RX_DESCRIPTOR_GI_MASK 0x00000018 // 4- 3 |
| 3252 | +#define WF_RX_DESCRIPTOR_GI_SHIFT 3 |
| 3253 | +#define WF_RX_DESCRIPTOR_DCM_DW 22 |
| 3254 | +#define WF_RX_DESCRIPTOR_DCM_ADDR 88 |
| 3255 | +#define WF_RX_DESCRIPTOR_DCM_MASK 0x00000020 // 5- 5 |
| 3256 | +#define WF_RX_DESCRIPTOR_DCM_SHIFT 5 |
| 3257 | +#define WF_RX_DESCRIPTOR_NUM_RX_DW 22 |
| 3258 | +#define WF_RX_DESCRIPTOR_NUM_RX_ADDR 88 |
| 3259 | +#define WF_RX_DESCRIPTOR_NUM_RX_MASK 0x000001c0 // 8- 6 |
| 3260 | +#define WF_RX_DESCRIPTOR_NUM_RX_SHIFT 6 |
| 3261 | +#define WF_RX_DESCRIPTOR_STBC_DW 22 |
| 3262 | +#define WF_RX_DESCRIPTOR_STBC_ADDR 88 |
| 3263 | +#define WF_RX_DESCRIPTOR_STBC_MASK 0x00000600 // 10- 9 |
| 3264 | +#define WF_RX_DESCRIPTOR_STBC_SHIFT 9 |
| 3265 | +#define WF_RX_DESCRIPTOR_TX_MODE_DW 22 |
| 3266 | +#define WF_RX_DESCRIPTOR_TX_MODE_ADDR 88 |
| 3267 | +#define WF_RX_DESCRIPTOR_TX_MODE_MASK 0x00007800 // 14-11 |
| 3268 | +#define WF_RX_DESCRIPTOR_TX_MODE_SHIFT 11 |
| 3269 | +// DW23 |
| 3270 | +#define WF_RX_DESCRIPTOR_RCPI_DW 23 |
| 3271 | +#define WF_RX_DESCRIPTOR_RCPI_ADDR 92 |
| 3272 | +#define WF_RX_DESCRIPTOR_RCPI_MASK 0xffffffff // 31- 0 |
| 3273 | +#define WF_RX_DESCRIPTOR_RCPI_SHIFT 0 |
| 3274 | +// DW24 |
| 3275 | +#define WF_RX_DESCRIPTOR_C_RXV_DW 24 |
| 3276 | +#define WF_RX_DESCRIPTOR_C_RXV_ADDR 96 |
| 3277 | +#define WF_RX_DESCRIPTOR_C_RXV_MASK 0xffffffff // 31- 0 |
| 3278 | +#define WF_RX_DESCRIPTOR_C_RXV_SHIFT 0 |
| 3279 | +// DW25 |
| 3280 | +// DO NOT process repeat field(c_rxv) |
| 3281 | +// DW26 |
| 3282 | +// DO NOT process repeat field(c_rxv) |
| 3283 | +// DW27 |
| 3284 | +// DO NOT process repeat field(c_rxv) |
| 3285 | +// DW28 |
| 3286 | +// DO NOT process repeat field(c_rxv) |
| 3287 | +// DW29 |
| 3288 | +// DO NOT process repeat field(c_rxv) |
| 3289 | +// DW30 |
| 3290 | +// DO NOT process repeat field(c_rxv) |
| 3291 | +// DW31 |
| 3292 | +// DO NOT process repeat field(c_rxv) |
| 3293 | +// DW32 |
| 3294 | +// DO NOT process repeat field(c_rxv) |
| 3295 | +// DW33 |
| 3296 | +// DO NOT process repeat field(c_rxv) |
| 3297 | +// DW34 |
| 3298 | +// DO NOT process repeat field(c_rxv) |
| 3299 | +// DW35 |
| 3300 | +// DO NOT process repeat field(c_rxv) |
| 3301 | +// DW36 |
| 3302 | +// DO NOT process repeat field(c_rxv) |
| 3303 | +// DW37 |
| 3304 | +// DO NOT process repeat field(c_rxv) |
| 3305 | +// DW38 |
| 3306 | +// DO NOT process repeat field(c_rxv) |
| 3307 | +// DW39 |
| 3308 | +// DO NOT process repeat field(c_rxv) |
| 3309 | +// DW40 |
| 3310 | +// DO NOT process repeat field(c_rxv) |
| 3311 | +// DW41 |
| 3312 | +// DO NOT process repeat field(c_rxv) |
| 3313 | +// DW42 |
| 3314 | +// DO NOT process repeat field(c_rxv) |
| 3315 | +// DW43 |
| 3316 | +// DO NOT process repeat field(c_rxv) |
| 3317 | +// DW44 |
| 3318 | +// DO NOT process repeat field(c_rxv) |
| 3319 | +// DW45 |
| 3320 | +// DO NOT process repeat field(c_rxv) |
| 3321 | +// DW46 |
| 3322 | +// DW47 |
| 3323 | + |
| 3324 | +/* TXD */ |
| 3325 | +// DW0 |
| 3326 | +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_DW 0 |
| 3327 | +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_ADDR 0 |
| 3328 | +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_MASK 0x0000ffff // 15- 0 |
| 3329 | +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_SHIFT 0 |
| 3330 | +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 0 |
| 3331 | +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 0 |
| 3332 | +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x007f0000 // 22-16 |
| 3333 | +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 16 |
| 3334 | +#define WF_TX_DESCRIPTOR_PKT_FT_DW 0 |
| 3335 | +#define WF_TX_DESCRIPTOR_PKT_FT_ADDR 0 |
| 3336 | +#define WF_TX_DESCRIPTOR_PKT_FT_MASK 0x01800000 // 24-23 |
| 3337 | +#define WF_TX_DESCRIPTOR_PKT_FT_SHIFT 23 |
| 3338 | +#define WF_TX_DESCRIPTOR_Q_IDX_DW 0 |
| 3339 | +#define WF_TX_DESCRIPTOR_Q_IDX_ADDR 0 |
| 3340 | +#define WF_TX_DESCRIPTOR_Q_IDX_MASK 0xfe000000 // 31-25 |
| 3341 | +#define WF_TX_DESCRIPTOR_Q_IDX_SHIFT 25 |
| 3342 | +// DW1 |
| 3343 | +#define WF_TX_DESCRIPTOR_MLD_ID_DW 1 |
| 3344 | +#define WF_TX_DESCRIPTOR_MLD_ID_ADDR 4 |
| 3345 | +#define WF_TX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0 |
| 3346 | +#define WF_TX_DESCRIPTOR_MLD_ID_SHIFT 0 |
| 3347 | +#define WF_TX_DESCRIPTOR_TGID_DW 1 |
| 3348 | +#define WF_TX_DESCRIPTOR_TGID_ADDR 4 |
| 3349 | +#define WF_TX_DESCRIPTOR_TGID_MASK 0x00003000 // 13-12 |
| 3350 | +#define WF_TX_DESCRIPTOR_TGID_SHIFT 12 |
| 3351 | +#define WF_TX_DESCRIPTOR_HF_DW 1 |
| 3352 | +#define WF_TX_DESCRIPTOR_HF_ADDR 4 |
| 3353 | +#define WF_TX_DESCRIPTOR_HF_MASK 0x0000c000 // 15-14 |
| 3354 | +#define WF_TX_DESCRIPTOR_HF_SHIFT 14 |
| 3355 | +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_DW 1 |
| 3356 | +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_ADDR 4 |
| 3357 | +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_MASK 0x001f0000 // 20-16 |
| 3358 | +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_SHIFT 16 |
| 3359 | +#define WF_TX_DESCRIPTOR_MRD_DW 1 |
| 3360 | +#define WF_TX_DESCRIPTOR_MRD_ADDR 4 |
| 3361 | +#define WF_TX_DESCRIPTOR_MRD_MASK 0x00010000 // 16-16 |
| 3362 | +#define WF_TX_DESCRIPTOR_MRD_SHIFT 16 |
| 3363 | +#define WF_TX_DESCRIPTOR_EOSP_DW 1 |
| 3364 | +#define WF_TX_DESCRIPTOR_EOSP_ADDR 4 |
| 3365 | +#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17 |
| 3366 | +#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17 |
| 3367 | +#define WF_TX_DESCRIPTOR_EOSP_DW 1 |
| 3368 | +#define WF_TX_DESCRIPTOR_EOSP_ADDR 4 |
| 3369 | +#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17 |
| 3370 | +#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17 |
| 3371 | +#define WF_TX_DESCRIPTOR_AMS_DW 1 |
| 3372 | +#define WF_TX_DESCRIPTOR_AMS_ADDR 4 |
| 3373 | +#define WF_TX_DESCRIPTOR_AMS_MASK 0x00040000 // 18-18 |
| 3374 | +#define WF_TX_DESCRIPTOR_AMS_SHIFT 18 |
| 3375 | +#define WF_TX_DESCRIPTOR_RMVL_DW 1 |
| 3376 | +#define WF_TX_DESCRIPTOR_RMVL_ADDR 4 |
| 3377 | +#define WF_TX_DESCRIPTOR_RMVL_MASK 0x00040000 // 18-18 |
| 3378 | +#define WF_TX_DESCRIPTOR_RMVL_SHIFT 18 |
| 3379 | +#define WF_TX_DESCRIPTOR_VLAN_DW 1 |
| 3380 | +#define WF_TX_DESCRIPTOR_VLAN_ADDR 4 |
| 3381 | +#define WF_TX_DESCRIPTOR_VLAN_MASK 0x00080000 // 19-19 |
| 3382 | +#define WF_TX_DESCRIPTOR_VLAN_SHIFT 19 |
| 3383 | +#define WF_TX_DESCRIPTOR_ETYP_DW 1 |
| 3384 | +#define WF_TX_DESCRIPTOR_ETYP_ADDR 4 |
| 3385 | +#define WF_TX_DESCRIPTOR_ETYP_MASK 0x00100000 // 20-20 |
| 3386 | +#define WF_TX_DESCRIPTOR_ETYP_SHIFT 20 |
| 3387 | +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_DW 1 |
| 3388 | +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_ADDR 4 |
| 3389 | +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_MASK 0x01e00000 // 24-21 |
| 3390 | +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_SHIFT 21 |
| 3391 | +#define WF_TX_DESCRIPTOR_OM_DW 1 |
| 3392 | +#define WF_TX_DESCRIPTOR_OM_ADDR 4 |
| 3393 | +#define WF_TX_DESCRIPTOR_OM_MASK 0x7e000000 // 30-25 |
| 3394 | +#define WF_TX_DESCRIPTOR_OM_SHIFT 25 |
| 3395 | +#define WF_TX_DESCRIPTOR_FR_DW 1 |
| 3396 | +#define WF_TX_DESCRIPTOR_FR_ADDR 4 |
| 3397 | +#define WF_TX_DESCRIPTOR_FR_MASK 0x80000000 // 31-31 |
| 3398 | +#define WF_TX_DESCRIPTOR_FR_SHIFT 31 |
| 3399 | +// DW2 |
| 3400 | +#define WF_TX_DESCRIPTOR_SUBTYPE_DW 2 |
| 3401 | +#define WF_TX_DESCRIPTOR_SUBTYPE_ADDR 8 |
| 3402 | +#define WF_TX_DESCRIPTOR_SUBTYPE_MASK 0x0000000f // 3- 0 |
| 3403 | +#define WF_TX_DESCRIPTOR_SUBTYPE_SHIFT 0 |
| 3404 | +#define WF_TX_DESCRIPTOR_FTYPE_DW 2 |
| 3405 | +#define WF_TX_DESCRIPTOR_FTYPE_ADDR 8 |
| 3406 | +#define WF_TX_DESCRIPTOR_FTYPE_MASK 0x00000030 // 5- 4 |
| 3407 | +#define WF_TX_DESCRIPTOR_FTYPE_SHIFT 4 |
| 3408 | +#define WF_TX_DESCRIPTOR_BF_TYPE_DW 2 |
| 3409 | +#define WF_TX_DESCRIPTOR_BF_TYPE_ADDR 8 |
| 3410 | +#define WF_TX_DESCRIPTOR_BF_TYPE_MASK 0x000000c0 // 7- 6 |
| 3411 | +#define WF_TX_DESCRIPTOR_BF_TYPE_SHIFT 6 |
| 3412 | +#define WF_TX_DESCRIPTOR_OM_MAP_DW 2 |
| 3413 | +#define WF_TX_DESCRIPTOR_OM_MAP_ADDR 8 |
| 3414 | +#define WF_TX_DESCRIPTOR_OM_MAP_MASK 0x00000100 // 8- 8 |
| 3415 | +#define WF_TX_DESCRIPTOR_OM_MAP_SHIFT 8 |
| 3416 | +#define WF_TX_DESCRIPTOR_RTS_DW 2 |
| 3417 | +#define WF_TX_DESCRIPTOR_RTS_ADDR 8 |
| 3418 | +#define WF_TX_DESCRIPTOR_RTS_MASK 0x00000200 // 9- 9 |
| 3419 | +#define WF_TX_DESCRIPTOR_RTS_SHIFT 9 |
| 3420 | +#define WF_TX_DESCRIPTOR_HEADER_PADDING_DW 2 |
| 3421 | +#define WF_TX_DESCRIPTOR_HEADER_PADDING_ADDR 8 |
| 3422 | +#define WF_TX_DESCRIPTOR_HEADER_PADDING_MASK 0x00000c00 // 11-10 |
| 3423 | +#define WF_TX_DESCRIPTOR_HEADER_PADDING_SHIFT 10 |
| 3424 | +#define WF_TX_DESCRIPTOR_DU_DW 2 |
| 3425 | +#define WF_TX_DESCRIPTOR_DU_ADDR 8 |
| 3426 | +#define WF_TX_DESCRIPTOR_DU_MASK 0x00001000 // 12-12 |
| 3427 | +#define WF_TX_DESCRIPTOR_DU_SHIFT 12 |
| 3428 | +#define WF_TX_DESCRIPTOR_HE_DW 2 |
| 3429 | +#define WF_TX_DESCRIPTOR_HE_ADDR 8 |
| 3430 | +#define WF_TX_DESCRIPTOR_HE_MASK 0x00002000 // 13-13 |
| 3431 | +#define WF_TX_DESCRIPTOR_HE_SHIFT 13 |
| 3432 | +#define WF_TX_DESCRIPTOR_FRAG_DW 2 |
| 3433 | +#define WF_TX_DESCRIPTOR_FRAG_ADDR 8 |
| 3434 | +#define WF_TX_DESCRIPTOR_FRAG_MASK 0x0000c000 // 15-14 |
| 3435 | +#define WF_TX_DESCRIPTOR_FRAG_SHIFT 14 |
| 3436 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_DW 2 |
| 3437 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_ADDR 8 |
| 3438 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_MASK 0x03ff0000 // 25-16 |
| 3439 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_SHIFT 16 |
| 3440 | +#define WF_TX_DESCRIPTOR_POWER_OFFSET_DW 2 |
| 3441 | +#define WF_TX_DESCRIPTOR_POWER_OFFSET_ADDR 8 |
| 3442 | +#define WF_TX_DESCRIPTOR_POWER_OFFSET_MASK 0xfc000000 // 31-26 |
| 3443 | +#define WF_TX_DESCRIPTOR_POWER_OFFSET_SHIFT 26 |
| 3444 | +// DW3 |
| 3445 | +#define WF_TX_DESCRIPTOR_NA_DW 3 |
| 3446 | +#define WF_TX_DESCRIPTOR_NA_ADDR 12 |
| 3447 | +#define WF_TX_DESCRIPTOR_NA_MASK 0x00000001 // 0- 0 |
| 3448 | +#define WF_TX_DESCRIPTOR_NA_SHIFT 0 |
| 3449 | +#define WF_TX_DESCRIPTOR_PF_DW 3 |
| 3450 | +#define WF_TX_DESCRIPTOR_PF_ADDR 12 |
| 3451 | +#define WF_TX_DESCRIPTOR_PF_MASK 0x00000002 // 1- 1 |
| 3452 | +#define WF_TX_DESCRIPTOR_PF_SHIFT 1 |
| 3453 | +#define WF_TX_DESCRIPTOR_EMRD_DW 3 |
| 3454 | +#define WF_TX_DESCRIPTOR_EMRD_ADDR 12 |
| 3455 | +#define WF_TX_DESCRIPTOR_EMRD_MASK 0x00000004 // 2- 2 |
| 3456 | +#define WF_TX_DESCRIPTOR_EMRD_SHIFT 2 |
| 3457 | +#define WF_TX_DESCRIPTOR_EEOSP_DW 3 |
| 3458 | +#define WF_TX_DESCRIPTOR_EEOSP_ADDR 12 |
| 3459 | +#define WF_TX_DESCRIPTOR_EEOSP_MASK 0x00000008 // 3- 3 |
| 3460 | +#define WF_TX_DESCRIPTOR_EEOSP_SHIFT 3 |
| 3461 | +#define WF_TX_DESCRIPTOR_BM_DW 3 |
| 3462 | +#define WF_TX_DESCRIPTOR_BM_ADDR 12 |
| 3463 | +#define WF_TX_DESCRIPTOR_BM_MASK 0x00000010 // 4- 4 |
| 3464 | +#define WF_TX_DESCRIPTOR_BM_SHIFT 4 |
| 3465 | +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_DW 3 |
| 3466 | +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_ADDR 12 |
| 3467 | +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_MASK 0x00000020 // 5- 5 |
| 3468 | +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_SHIFT 5 |
| 3469 | +#define WF_TX_DESCRIPTOR_TX_COUNT_DW 3 |
| 3470 | +#define WF_TX_DESCRIPTOR_TX_COUNT_ADDR 12 |
| 3471 | +#define WF_TX_DESCRIPTOR_TX_COUNT_MASK 0x000007c0 // 10- 6 |
| 3472 | +#define WF_TX_DESCRIPTOR_TX_COUNT_SHIFT 6 |
| 3473 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_DW 3 |
| 3474 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_ADDR 12 |
| 3475 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_MASK 0x0000f800 // 15-11 |
| 3476 | +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_SHIFT 11 |
| 3477 | +#define WF_TX_DESCRIPTOR_SN_DW 3 |
| 3478 | +#define WF_TX_DESCRIPTOR_SN_ADDR 12 |
| 3479 | +#define WF_TX_DESCRIPTOR_SN_MASK 0x0fff0000 // 27-16 |
| 3480 | +#define WF_TX_DESCRIPTOR_SN_SHIFT 16 |
| 3481 | +#define WF_TX_DESCRIPTOR_BA_DIS_DW 3 |
| 3482 | +#define WF_TX_DESCRIPTOR_BA_DIS_ADDR 12 |
| 3483 | +#define WF_TX_DESCRIPTOR_BA_DIS_MASK 0x10000000 // 28-28 |
| 3484 | +#define WF_TX_DESCRIPTOR_BA_DIS_SHIFT 28 |
| 3485 | +#define WF_TX_DESCRIPTOR_PM_DW 3 |
| 3486 | +#define WF_TX_DESCRIPTOR_PM_ADDR 12 |
| 3487 | +#define WF_TX_DESCRIPTOR_PM_MASK 0x20000000 // 29-29 |
| 3488 | +#define WF_TX_DESCRIPTOR_PM_SHIFT 29 |
| 3489 | +#define WF_TX_DESCRIPTOR_PN_VLD_DW 3 |
| 3490 | +#define WF_TX_DESCRIPTOR_PN_VLD_ADDR 12 |
| 3491 | +#define WF_TX_DESCRIPTOR_PN_VLD_MASK 0x40000000 // 30-30 |
| 3492 | +#define WF_TX_DESCRIPTOR_PN_VLD_SHIFT 30 |
| 3493 | +#define WF_TX_DESCRIPTOR_SN_VLD_DW 3 |
| 3494 | +#define WF_TX_DESCRIPTOR_SN_VLD_ADDR 12 |
| 3495 | +#define WF_TX_DESCRIPTOR_SN_VLD_MASK 0x80000000 // 31-31 |
| 3496 | +#define WF_TX_DESCRIPTOR_SN_VLD_SHIFT 31 |
| 3497 | +// DW4 |
| 3498 | +#define WF_TX_DESCRIPTOR_PN_31_0__DW 4 |
| 3499 | +#define WF_TX_DESCRIPTOR_PN_31_0__ADDR 16 |
| 3500 | +#define WF_TX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0 |
| 3501 | +#define WF_TX_DESCRIPTOR_PN_31_0__SHIFT 0 |
| 3502 | +// DW5 |
| 3503 | +#define WF_TX_DESCRIPTOR_PID_DW 5 |
| 3504 | +#define WF_TX_DESCRIPTOR_PID_ADDR 20 |
| 3505 | +#define WF_TX_DESCRIPTOR_PID_MASK 0x000000ff // 7- 0 |
| 3506 | +#define WF_TX_DESCRIPTOR_PID_SHIFT 0 |
| 3507 | +#define WF_TX_DESCRIPTOR_TXSFM_DW 5 |
| 3508 | +#define WF_TX_DESCRIPTOR_TXSFM_ADDR 20 |
| 3509 | +#define WF_TX_DESCRIPTOR_TXSFM_MASK 0x00000100 // 8- 8 |
| 3510 | +#define WF_TX_DESCRIPTOR_TXSFM_SHIFT 8 |
| 3511 | +#define WF_TX_DESCRIPTOR_TXS2M_DW 5 |
| 3512 | +#define WF_TX_DESCRIPTOR_TXS2M_ADDR 20 |
| 3513 | +#define WF_TX_DESCRIPTOR_TXS2M_MASK 0x00000200 // 9- 9 |
| 3514 | +#define WF_TX_DESCRIPTOR_TXS2M_SHIFT 9 |
| 3515 | +#define WF_TX_DESCRIPTOR_TXS2H_DW 5 |
| 3516 | +#define WF_TX_DESCRIPTOR_TXS2H_ADDR 20 |
| 3517 | +#define WF_TX_DESCRIPTOR_TXS2H_MASK 0x00000400 // 10-10 |
| 3518 | +#define WF_TX_DESCRIPTOR_TXS2H_SHIFT 10 |
| 3519 | +#define WF_TX_DESCRIPTOR_FBCZ_DW 5 |
| 3520 | +#define WF_TX_DESCRIPTOR_FBCZ_ADDR 20 |
| 3521 | +#define WF_TX_DESCRIPTOR_FBCZ_MASK 0x00001000 // 12-12 |
| 3522 | +#define WF_TX_DESCRIPTOR_FBCZ_SHIFT 12 |
| 3523 | +#define WF_TX_DESCRIPTOR_BYPASS_RBB_DW 5 |
| 3524 | +#define WF_TX_DESCRIPTOR_BYPASS_RBB_ADDR 20 |
| 3525 | +#define WF_TX_DESCRIPTOR_BYPASS_RBB_MASK 0x00002000 // 13-13 |
| 3526 | +#define WF_TX_DESCRIPTOR_BYPASS_RBB_SHIFT 13 |
| 3527 | +#define WF_TX_DESCRIPTOR_BYPASS_TBB_DW 5 |
| 3528 | +#define WF_TX_DESCRIPTOR_BYPASS_TBB_ADDR 20 |
| 3529 | +#define WF_TX_DESCRIPTOR_BYPASS_TBB_MASK 0x00004000 // 14-14 |
| 3530 | +#define WF_TX_DESCRIPTOR_BYPASS_TBB_SHIFT 14 |
| 3531 | +#define WF_TX_DESCRIPTOR_FL_DW 5 |
| 3532 | +#define WF_TX_DESCRIPTOR_FL_ADDR 20 |
| 3533 | +#define WF_TX_DESCRIPTOR_FL_MASK 0x00008000 // 15-15 |
| 3534 | +#define WF_TX_DESCRIPTOR_FL_SHIFT 15 |
| 3535 | +#define WF_TX_DESCRIPTOR_PN_47_32__DW 5 |
| 3536 | +#define WF_TX_DESCRIPTOR_PN_47_32__ADDR 20 |
| 3537 | +#define WF_TX_DESCRIPTOR_PN_47_32__MASK 0xffff0000 // 31-16 |
| 3538 | +#define WF_TX_DESCRIPTOR_PN_47_32__SHIFT 16 |
| 3539 | +// DW6 |
| 3540 | +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_DW 6 |
| 3541 | +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_ADDR 24 |
| 3542 | +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_MASK 0x00000002 // 1- 1 |
| 3543 | +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_SHIFT 1 |
| 3544 | +#define WF_TX_DESCRIPTOR_DAS_DW 6 |
| 3545 | +#define WF_TX_DESCRIPTOR_DAS_ADDR 24 |
| 3546 | +#define WF_TX_DESCRIPTOR_DAS_MASK 0x00000004 // 2- 2 |
| 3547 | +#define WF_TX_DESCRIPTOR_DAS_SHIFT 2 |
| 3548 | +#define WF_TX_DESCRIPTOR_DIS_MAT_DW 6 |
| 3549 | +#define WF_TX_DESCRIPTOR_DIS_MAT_ADDR 24 |
| 3550 | +#define WF_TX_DESCRIPTOR_DIS_MAT_MASK 0x00000008 // 3- 3 |
| 3551 | +#define WF_TX_DESCRIPTOR_DIS_MAT_SHIFT 3 |
| 3552 | +#define WF_TX_DESCRIPTOR_MSDU_COUNT_DW 6 |
| 3553 | +#define WF_TX_DESCRIPTOR_MSDU_COUNT_ADDR 24 |
| 3554 | +#define WF_TX_DESCRIPTOR_MSDU_COUNT_MASK 0x000003f0 // 9- 4 |
| 3555 | +#define WF_TX_DESCRIPTOR_MSDU_COUNT_SHIFT 4 |
| 3556 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_DW 6 |
| 3557 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_ADDR 24 |
| 3558 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_MASK 0x00007c00 // 14-10 |
| 3559 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_SHIFT 10 |
| 3560 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_DW 6 |
| 3561 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_ADDR 24 |
| 3562 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_MASK 0x00008000 // 15-15 |
| 3563 | +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_SHIFT 15 |
| 3564 | +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_DW 6 |
| 3565 | +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_ADDR 24 |
| 3566 | +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_MASK 0x003f0000 // 21-16 |
| 3567 | +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_SHIFT 16 |
| 3568 | +#define WF_TX_DESCRIPTOR_BW_DW 6 |
| 3569 | +#define WF_TX_DESCRIPTOR_BW_ADDR 24 |
| 3570 | +#define WF_TX_DESCRIPTOR_BW_MASK 0x03c00000 // 25-22 |
| 3571 | +#define WF_TX_DESCRIPTOR_BW_SHIFT 22 |
| 3572 | +#define WF_TX_DESCRIPTOR_VTA_DW 6 |
| 3573 | +#define WF_TX_DESCRIPTOR_VTA_ADDR 24 |
| 3574 | +#define WF_TX_DESCRIPTOR_VTA_MASK 0x10000000 // 28-28 |
| 3575 | +#define WF_TX_DESCRIPTOR_VTA_SHIFT 28 |
| 3576 | +#define WF_TX_DESCRIPTOR_SRC_DW 6 |
| 3577 | +#define WF_TX_DESCRIPTOR_SRC_ADDR 24 |
| 3578 | +#define WF_TX_DESCRIPTOR_SRC_MASK 0xc0000000 // 31-30 |
| 3579 | +#define WF_TX_DESCRIPTOR_SRC_SHIFT 30 |
| 3580 | +// DW7 |
| 3581 | +#define WF_TX_DESCRIPTOR_SW_TX_TIME_DW 7 |
| 3582 | +#define WF_TX_DESCRIPTOR_SW_TX_TIME_ADDR 28 |
| 3583 | +#define WF_TX_DESCRIPTOR_SW_TX_TIME_MASK 0x000003ff // 9- 0 |
| 3584 | +#define WF_TX_DESCRIPTOR_SW_TX_TIME_SHIFT 0 |
| 3585 | +#define WF_TX_DESCRIPTOR_UT_DW 7 |
| 3586 | +#define WF_TX_DESCRIPTOR_UT_ADDR 28 |
| 3587 | +#define WF_TX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15 |
| 3588 | +#define WF_TX_DESCRIPTOR_UT_SHIFT 15 |
| 3589 | +#define WF_TX_DESCRIPTOR_CTXD_CNT_DW 7 |
| 3590 | +#define WF_TX_DESCRIPTOR_CTXD_CNT_ADDR 28 |
| 3591 | +#define WF_TX_DESCRIPTOR_CTXD_CNT_MASK 0x03c00000 // 25-22 |
| 3592 | +#define WF_TX_DESCRIPTOR_CTXD_CNT_SHIFT 22 |
| 3593 | +#define WF_TX_DESCRIPTOR_CTXD_DW 7 |
| 3594 | +#define WF_TX_DESCRIPTOR_CTXD_ADDR 28 |
| 3595 | +#define WF_TX_DESCRIPTOR_CTXD_MASK 0x04000000 // 26-26 |
| 3596 | +#define WF_TX_DESCRIPTOR_CTXD_SHIFT 26 |
| 3597 | +#define WF_TX_DESCRIPTOR_HM_DW 7 |
| 3598 | +#define WF_TX_DESCRIPTOR_HM_ADDR 28 |
| 3599 | +#define WF_TX_DESCRIPTOR_HM_MASK 0x08000000 // 27-27 |
| 3600 | +#define WF_TX_DESCRIPTOR_HM_SHIFT 27 |
| 3601 | +#define WF_TX_DESCRIPTOR_DP_DW 7 |
| 3602 | +#define WF_TX_DESCRIPTOR_DP_ADDR 28 |
| 3603 | +#define WF_TX_DESCRIPTOR_DP_MASK 0x10000000 // 28-28 |
| 3604 | +#define WF_TX_DESCRIPTOR_DP_SHIFT 28 |
| 3605 | +#define WF_TX_DESCRIPTOR_IP_DW 7 |
| 3606 | +#define WF_TX_DESCRIPTOR_IP_ADDR 28 |
| 3607 | +#define WF_TX_DESCRIPTOR_IP_MASK 0x20000000 // 29-29 |
| 3608 | +#define WF_TX_DESCRIPTOR_IP_SHIFT 29 |
| 3609 | +#define WF_TX_DESCRIPTOR_TXD_LEN_DW 7 |
| 3610 | +#define WF_TX_DESCRIPTOR_TXD_LEN_ADDR 28 |
| 3611 | +#define WF_TX_DESCRIPTOR_TXD_LEN_MASK 0xc0000000 // 31-30 |
| 3612 | +#define WF_TX_DESCRIPTOR_TXD_LEN_SHIFT 30 |
| 3613 | +// DW8 |
| 3614 | +#define WF_TX_DESCRIPTOR_MSDU0_DW 8 |
| 3615 | +#define WF_TX_DESCRIPTOR_MSDU0_ADDR 32 |
| 3616 | +#define WF_TX_DESCRIPTOR_MSDU0_MASK 0x0000ffff // 15- 0 |
| 3617 | +#define WF_TX_DESCRIPTOR_MSDU0_SHIFT 0 |
| 3618 | +#define WF_TX_DESCRIPTOR_MSDU1_DW 8 |
| 3619 | +#define WF_TX_DESCRIPTOR_MSDU1_ADDR 32 |
| 3620 | +#define WF_TX_DESCRIPTOR_MSDU1_MASK 0xffff0000 // 31-16 |
| 3621 | +#define WF_TX_DESCRIPTOR_MSDU1_SHIFT 16 |
| 3622 | +// DW9 |
| 3623 | +#define WF_TX_DESCRIPTOR_MSDU2_DW 9 |
| 3624 | +#define WF_TX_DESCRIPTOR_MSDU2_ADDR 36 |
| 3625 | +#define WF_TX_DESCRIPTOR_MSDU2_MASK 0x0000ffff // 15- 0 |
| 3626 | +#define WF_TX_DESCRIPTOR_MSDU2_SHIFT 0 |
| 3627 | +#define WF_TX_DESCRIPTOR_MSDU3_DW 9 |
| 3628 | +#define WF_TX_DESCRIPTOR_MSDU3_ADDR 36 |
| 3629 | +#define WF_TX_DESCRIPTOR_MSDU3_MASK 0xffff0000 // 31-16 |
| 3630 | +#define WF_TX_DESCRIPTOR_MSDU3_SHIFT 16 |
| 3631 | +// DW10 |
| 3632 | +#define WF_TX_DESCRIPTOR_TXP0_DW 10 |
| 3633 | +#define WF_TX_DESCRIPTOR_TXP0_ADDR 40 |
| 3634 | +#define WF_TX_DESCRIPTOR_TXP0_MASK 0xffffffff // 31- 0 |
| 3635 | +#define WF_TX_DESCRIPTOR_TXP0_SHIFT 0 |
| 3636 | +// DW11 |
| 3637 | +// DO NOT process repeat field(txp[0]) |
| 3638 | +#define WF_TX_DESCRIPTOR_TXP1_DW 11 |
| 3639 | +#define WF_TX_DESCRIPTOR_TXP1_ADDR 44 |
| 3640 | +#define WF_TX_DESCRIPTOR_TXP1_MASK 0xffff0000 // 31-16 |
| 3641 | +#define WF_TX_DESCRIPTOR_TXP1_SHIFT 16 |
| 3642 | +// DW12 |
| 3643 | +// DO NOT process repeat field(txp[1]) |
| 3644 | +// DW13 |
| 3645 | +#define WF_TX_DESCRIPTOR_TXP2_DW 13 |
| 3646 | +#define WF_TX_DESCRIPTOR_TXP2_ADDR 52 |
| 3647 | +#define WF_TX_DESCRIPTOR_TXP2_MASK 0xffffffff // 31- 0 |
| 3648 | +#define WF_TX_DESCRIPTOR_TXP2_SHIFT 0 |
| 3649 | +// DW14 |
| 3650 | +// DO NOT process repeat field(txp[2]) |
| 3651 | +#define WF_TX_DESCRIPTOR_TXP3_DW 14 |
| 3652 | +#define WF_TX_DESCRIPTOR_TXP3_ADDR 56 |
| 3653 | +#define WF_TX_DESCRIPTOR_TXP3_MASK 0xffff0000 // 31-16 |
| 3654 | +#define WF_TX_DESCRIPTOR_TXP3_SHIFT 16 |
| 3655 | +// DW15 |
| 3656 | +// DO NOT process repeat field(txp[3]) |
| 3657 | +// DW16 |
| 3658 | +#define WF_TX_DESCRIPTOR_MSDU4_DW 16 |
| 3659 | +#define WF_TX_DESCRIPTOR_MSDU4_ADDR 64 |
| 3660 | +#define WF_TX_DESCRIPTOR_MSDU4_MASK 0x0000ffff // 15- 0 |
| 3661 | +#define WF_TX_DESCRIPTOR_MSDU4_SHIFT 0 |
| 3662 | +#define WF_TX_DESCRIPTOR_MSDU5_DW 16 |
| 3663 | +#define WF_TX_DESCRIPTOR_MSDU5_ADDR 64 |
| 3664 | +#define WF_TX_DESCRIPTOR_MSDU5_MASK 0xffff0000 // 31-16 |
| 3665 | +#define WF_TX_DESCRIPTOR_MSDU5_SHIFT 16 |
| 3666 | +// DW17 |
| 3667 | +#define WF_TX_DESCRIPTOR_MSDU6_DW 17 |
| 3668 | +#define WF_TX_DESCRIPTOR_MSDU6_ADDR 68 |
| 3669 | +#define WF_TX_DESCRIPTOR_MSDU6_MASK 0x0000ffff // 15- 0 |
| 3670 | +#define WF_TX_DESCRIPTOR_MSDU6_SHIFT 0 |
| 3671 | +#define WF_TX_DESCRIPTOR_MSDU7_DW 17 |
| 3672 | +#define WF_TX_DESCRIPTOR_MSDU7_ADDR 68 |
| 3673 | +#define WF_TX_DESCRIPTOR_MSDU7_MASK 0xffff0000 // 31-16 |
| 3674 | +#define WF_TX_DESCRIPTOR_MSDU7_SHIFT 16 |
| 3675 | +// DW18 |
| 3676 | +#define WF_TX_DESCRIPTOR_TXP4_DW 18 |
| 3677 | +#define WF_TX_DESCRIPTOR_TXP4_ADDR 72 |
| 3678 | +#define WF_TX_DESCRIPTOR_TXP4_MASK 0xffffffff // 31- 0 |
| 3679 | +#define WF_TX_DESCRIPTOR_TXP4_SHIFT 0 |
| 3680 | +// DW19 |
| 3681 | +// DO NOT process repeat field(txp[4]) |
| 3682 | +#define WF_TX_DESCRIPTOR_TXP5_DW 19 |
| 3683 | +#define WF_TX_DESCRIPTOR_TXP5_ADDR 76 |
| 3684 | +#define WF_TX_DESCRIPTOR_TXP5_MASK 0xffff0000 // 31-16 |
| 3685 | +#define WF_TX_DESCRIPTOR_TXP5_SHIFT 16 |
| 3686 | +// DW20 |
| 3687 | +// DO NOT process repeat field(txp[5]) |
| 3688 | +// DW21 |
| 3689 | +#define WF_TX_DESCRIPTOR_TXP6_DW 21 |
| 3690 | +#define WF_TX_DESCRIPTOR_TXP6_ADDR 84 |
| 3691 | +#define WF_TX_DESCRIPTOR_TXP6_MASK 0xffffffff // 31- 0 |
| 3692 | +#define WF_TX_DESCRIPTOR_TXP6_SHIFT 0 |
| 3693 | +// DW22 |
| 3694 | +// DO NOT process repeat field(txp[6]) |
| 3695 | +#define WF_TX_DESCRIPTOR_TXP7_DW 22 |
| 3696 | +#define WF_TX_DESCRIPTOR_TXP7_ADDR 88 |
| 3697 | +#define WF_TX_DESCRIPTOR_TXP7_MASK 0xffff0000 // 31-16 |
| 3698 | +#define WF_TX_DESCRIPTOR_TXP7_SHIFT 16 |
| 3699 | +// DW23 |
| 3700 | +// DO NOT process repeat field(txp[7]) |
| 3701 | +// DW24 |
| 3702 | +#define WF_TX_DESCRIPTOR_TXP8_DW 24 |
| 3703 | +#define WF_TX_DESCRIPTOR_TXP8_ADDR 96 |
| 3704 | +#define WF_TX_DESCRIPTOR_TXP8_MASK 0xffffffff // 31- 0 |
| 3705 | +#define WF_TX_DESCRIPTOR_TXP8_SHIFT 0 |
| 3706 | +// DW25 |
| 3707 | +// DO NOT process repeat field(txp[8]) |
| 3708 | +#define WF_TX_DESCRIPTOR_TXP9_DW 25 |
| 3709 | +#define WF_TX_DESCRIPTOR_TXP9_ADDR 100 |
| 3710 | +#define WF_TX_DESCRIPTOR_TXP9_MASK 0xffff0000 // 31-16 |
| 3711 | +#define WF_TX_DESCRIPTOR_TXP9_SHIFT 16 |
| 3712 | +// DW26 |
| 3713 | +// DO NOT process repeat field(txp[9]) |
| 3714 | +// DW27 |
| 3715 | +#define WF_TX_DESCRIPTOR_TXP10_DW 27 |
| 3716 | +#define WF_TX_DESCRIPTOR_TXP10_ADDR 108 |
| 3717 | +#define WF_TX_DESCRIPTOR_TXP10_MASK 0xffffffff // 31- 0 |
| 3718 | +#define WF_TX_DESCRIPTOR_TXP10_SHIFT 0 |
| 3719 | +// DW28 |
| 3720 | +// DO NOT process repeat field(txp[10]) |
| 3721 | +#define WF_TX_DESCRIPTOR_TXP11_DW 28 |
| 3722 | +#define WF_TX_DESCRIPTOR_TXP11_ADDR 112 |
| 3723 | +#define WF_TX_DESCRIPTOR_TXP11_MASK 0xffff0000 // 31-16 |
| 3724 | +#define WF_TX_DESCRIPTOR_TXP11_SHIFT 16 |
| 3725 | +// DW29 |
| 3726 | +// DO NOT process repeat field(txp[11]) |
| 3727 | +// DW30 |
| 3728 | +#define WF_TX_DESCRIPTOR_TXP12_DW 30 |
| 3729 | +#define WF_TX_DESCRIPTOR_TXP12_ADDR 120 |
| 3730 | +#define WF_TX_DESCRIPTOR_TXP12_MASK 0xffffffff // 31- 0 |
| 3731 | +#define WF_TX_DESCRIPTOR_TXP12_SHIFT 0 |
| 3732 | +// DW31 |
| 3733 | +// DO NOT process repeat field(txp[12]) |
| 3734 | +#define WF_TX_DESCRIPTOR_TXP13_DW 31 |
| 3735 | +#define WF_TX_DESCRIPTOR_TXP13_ADDR 124 |
| 3736 | +#define WF_TX_DESCRIPTOR_TXP13_MASK 0xffff0000 // 31-16 |
| 3737 | +#define WF_TX_DESCRIPTOR_TXP13_SHIFT 16 |
| 3738 | +// DW32 |
| 3739 | +// DO NOT process repeat field(txp[13]) |
| 3740 | +// DW33 |
| 3741 | +#define WF_TX_DESCRIPTOR_TXP14_DW 33 |
| 3742 | +#define WF_TX_DESCRIPTOR_TXP14_ADDR 132 |
| 3743 | +#define WF_TX_DESCRIPTOR_TXP14_MASK 0xffffffff // 31- 0 |
| 3744 | +#define WF_TX_DESCRIPTOR_TXP14_SHIFT 0 |
| 3745 | +// DW34 |
| 3746 | +// DO NOT process repeat field(txp[14]) |
| 3747 | +#define WF_TX_DESCRIPTOR_TXP15_DW 34 |
| 3748 | +#define WF_TX_DESCRIPTOR_TXP15_ADDR 136 |
| 3749 | +#define WF_TX_DESCRIPTOR_TXP15_MASK 0xffff0000 // 31-16 |
| 3750 | +#define WF_TX_DESCRIPTOR_TXP15_SHIFT 16 |
| 3751 | +// DW35 |
| 3752 | +// DO NOT process repeat field(txp[15]) |
| 3753 | +// DW36 |
| 3754 | +#define WF_TX_DESCRIPTOR_TXP16_DW 36 |
| 3755 | +#define WF_TX_DESCRIPTOR_TXP16_ADDR 144 |
| 3756 | +#define WF_TX_DESCRIPTOR_TXP16_MASK 0xffffffff // 31- 0 |
| 3757 | +#define WF_TX_DESCRIPTOR_TXP16_SHIFT 0 |
| 3758 | +// DW37 |
| 3759 | +// DO NOT process repeat field(txp[16]) |
| 3760 | +#define WF_TX_DESCRIPTOR_TXP17_DW 37 |
| 3761 | +#define WF_TX_DESCRIPTOR_TXP17_ADDR 148 |
| 3762 | +#define WF_TX_DESCRIPTOR_TXP17_MASK 0xffff0000 // 31-16 |
| 3763 | +#define WF_TX_DESCRIPTOR_TXP17_SHIFT 16 |
| 3764 | +// DW38 |
| 3765 | +// DO NOT process repeat field(txp[17]) |
| 3766 | +// DW39 |
| 3767 | +#define WF_TX_DESCRIPTOR_TXP18_DW 39 |
| 3768 | +#define WF_TX_DESCRIPTOR_TXP18_ADDR 156 |
| 3769 | +#define WF_TX_DESCRIPTOR_TXP18_MASK 0xffffffff // 31- 0 |
| 3770 | +#define WF_TX_DESCRIPTOR_TXP18_SHIFT 0 |
| 3771 | +// DW40 |
| 3772 | +// DO NOT process repeat field(txp[18]) |
| 3773 | +#define WF_TX_DESCRIPTOR_TXP19_DW 40 |
| 3774 | +#define WF_TX_DESCRIPTOR_TXP19_ADDR 160 |
| 3775 | +#define WF_TX_DESCRIPTOR_TXP19_MASK 0xffff0000 // 31-16 |
| 3776 | +#define WF_TX_DESCRIPTOR_TXP19_SHIFT 16 |
| 3777 | +// DW41 |
| 3778 | +// DO NOT process repeat field(txp[19]) |
| 3779 | +// DW42 |
| 3780 | +#define WF_TX_DESCRIPTOR_TXP20_DW 42 |
| 3781 | +#define WF_TX_DESCRIPTOR_TXP20_ADDR 168 |
| 3782 | +#define WF_TX_DESCRIPTOR_TXP20_MASK 0xffffffff // 31- 0 |
| 3783 | +#define WF_TX_DESCRIPTOR_TXP20_SHIFT 0 |
| 3784 | +// DW43 |
| 3785 | +// DO NOT process repeat field(txp[20]) |
| 3786 | +#define WF_TX_DESCRIPTOR_TXP21_DW 43 |
| 3787 | +#define WF_TX_DESCRIPTOR_TXP21_ADDR 172 |
| 3788 | +#define WF_TX_DESCRIPTOR_TXP21_MASK 0xffff0000 // 31-16 |
| 3789 | +#define WF_TX_DESCRIPTOR_TXP21_SHIFT 16 |
| 3790 | +// DW44 |
| 3791 | +// DO NOT process repeat field(txp[21]) |
| 3792 | +// DW45 |
| 3793 | +#define WF_TX_DESCRIPTOR_TXP22_DW 45 |
| 3794 | +#define WF_TX_DESCRIPTOR_TXP22_ADDR 180 |
| 3795 | +#define WF_TX_DESCRIPTOR_TXP22_MASK 0xffffffff // 31- 0 |
| 3796 | +#define WF_TX_DESCRIPTOR_TXP22_SHIFT 0 |
| 3797 | +// DW46 |
| 3798 | +// DO NOT process repeat field(txp[22]) |
| 3799 | +#define WF_TX_DESCRIPTOR_TXP23_DW 46 |
| 3800 | +#define WF_TX_DESCRIPTOR_TXP23_ADDR 184 |
| 3801 | +#define WF_TX_DESCRIPTOR_TXP23_MASK 0xffff0000 // 31-16 |
| 3802 | +#define WF_TX_DESCRIPTOR_TXP23_SHIFT 16 |
| 3803 | +// DW47 |
| 3804 | +// DO NOT process repeat field(txp[23]) |
| 3805 | +// DW48 |
| 3806 | +#define WF_TX_DESCRIPTOR_TXP24_DW 48 |
| 3807 | +#define WF_TX_DESCRIPTOR_TXP24_ADDR 192 |
| 3808 | +#define WF_TX_DESCRIPTOR_TXP24_MASK 0xffffffff // 31- 0 |
| 3809 | +#define WF_TX_DESCRIPTOR_TXP24_SHIFT 0 |
| 3810 | +// DW49 |
| 3811 | +// DO NOT process repeat field(txp[24]) |
| 3812 | +#define WF_TX_DESCRIPTOR_TXP25_DW 49 |
| 3813 | +#define WF_TX_DESCRIPTOR_TXP25_ADDR 196 |
| 3814 | +#define WF_TX_DESCRIPTOR_TXP25_MASK 0xffff0000 // 31-16 |
| 3815 | +#define WF_TX_DESCRIPTOR_TXP25_SHIFT 16 |
| 3816 | +// DW50 |
| 3817 | +// DO NOT process repeat field(txp[25]) |
| 3818 | +// DW51 |
| 3819 | +#define WF_TX_DESCRIPTOR_TXP26_DW 51 |
| 3820 | +#define WF_TX_DESCRIPTOR_TXP26_ADDR 204 |
| 3821 | +#define WF_TX_DESCRIPTOR_TXP26_MASK 0xffffffff // 31- 0 |
| 3822 | +#define WF_TX_DESCRIPTOR_TXP26_SHIFT 0 |
| 3823 | +// DW52 |
| 3824 | +// DO NOT process repeat field(txp[26]) |
| 3825 | +#define WF_TX_DESCRIPTOR_TXP27_DW 52 |
| 3826 | +#define WF_TX_DESCRIPTOR_TXP27_ADDR 208 |
| 3827 | +#define WF_TX_DESCRIPTOR_TXP27_MASK 0xffff0000 // 31-16 |
| 3828 | +#define WF_TX_DESCRIPTOR_TXP27_SHIFT 16 |
| 3829 | +// DW53 |
| 3830 | +// DO NOT process repeat field(txp[27]) |
| 3831 | +// DW54 |
| 3832 | +#define WF_TX_DESCRIPTOR_TXP28_DW 54 |
| 3833 | +#define WF_TX_DESCRIPTOR_TXP28_ADDR 216 |
| 3834 | +#define WF_TX_DESCRIPTOR_TXP28_MASK 0xffffffff // 31- 0 |
| 3835 | +#define WF_TX_DESCRIPTOR_TXP28_SHIFT 0 |
| 3836 | +// DW55 |
| 3837 | +// DO NOT process repeat field(txp[28]) |
| 3838 | +#define WF_TX_DESCRIPTOR_TXP29_DW 55 |
| 3839 | +#define WF_TX_DESCRIPTOR_TXP29_ADDR 220 |
| 3840 | +#define WF_TX_DESCRIPTOR_TXP29_MASK 0xffff0000 // 31-16 |
| 3841 | +#define WF_TX_DESCRIPTOR_TXP29_SHIFT 16 |
| 3842 | +// DW56 |
| 3843 | +// DO NOT process repeat field(txp[29]) |
| 3844 | +// DW57 |
| 3845 | +#define WF_TX_DESCRIPTOR_TXP30_DW 57 |
| 3846 | +#define WF_TX_DESCRIPTOR_TXP30_ADDR 228 |
| 3847 | +#define WF_TX_DESCRIPTOR_TXP30_MASK 0xffffffff // 31- 0 |
| 3848 | +#define WF_TX_DESCRIPTOR_TXP30_SHIFT 0 |
| 3849 | +// DW58 |
| 3850 | +// DO NOT process repeat field(txp[30]) |
| 3851 | +#define WF_TX_DESCRIPTOR_TXP31_DW 58 |
| 3852 | +#define WF_TX_DESCRIPTOR_TXP31_ADDR 232 |
| 3853 | +#define WF_TX_DESCRIPTOR_TXP31_MASK 0xffff0000 // 31-16 |
| 3854 | +#define WF_TX_DESCRIPTOR_TXP31_SHIFT 16 |
| 3855 | +// DW59 |
| 3856 | +// DO NOT process repeat field(txp[31]) |
| 3857 | + |
| 3858 | +/* TXP PAO */ |
| 3859 | +#define HIF_TXP_V2_SIZE (24 * 4) |
| 3860 | +/* DW0 */ |
| 3861 | +#define HIF_TXD_VERSION_SHIFT 19 |
| 3862 | +#define HIF_TXD_VERSION_MASK 0x00780000 |
| 3863 | + |
| 3864 | +/* DW8 */ |
| 3865 | +#define HIF_TXP_PRIORITY_SHIFT 0 |
| 3866 | +#define HIF_TXP_PRIORITY_MASK 0x00000001 |
| 3867 | +#define HIF_TXP_FIXED_RATE_SHIFT 1 |
| 3868 | +#define HIF_TXP_FIXED_RATE_MASK 0x00000002 |
| 3869 | +#define HIF_TXP_TCP_SHIFT 2 |
| 3870 | +#define HIF_TXP_TCP_MASK 0x00000004 |
| 3871 | +#define HIF_TXP_NON_CIPHER_SHIFT 3 |
| 3872 | +#define HIF_TXP_NON_CIPHER_MASK 0x00000008 |
| 3873 | +#define HIF_TXP_VLAN_SHIFT 4 |
| 3874 | +#define HIF_TXP_VLAN_MASK 0x00000010 |
| 3875 | +#define HIF_TXP_BC_MC_FLAG_SHIFT 5 |
| 3876 | +#define HIF_TXP_BC_MC_FLAG_MASK 0x00000060 |
| 3877 | +#define HIF_TXP_FR_HOST_SHIFT 7 |
| 3878 | +#define HIF_TXP_FR_HOST_MASK 0x00000080 |
| 3879 | +#define HIF_TXP_ETYPE_SHIFT 8 |
| 3880 | +#define HIF_TXP_ETYPE_MASK 0x00000100 |
| 3881 | +#define HIF_TXP_TXP_AMSDU_SHIFT 9 |
| 3882 | +#define HIF_TXP_TXP_AMSDU_MASK 0x00000200 |
| 3883 | +#define HIF_TXP_TXP_MC_CLONE_SHIFT 10 |
| 3884 | +#define HIF_TXP_TXP_MC_CLONE_MASK 0x00000400 |
| 3885 | +#define HIF_TXP_TOKEN_ID_SHIFT 16 |
| 3886 | +#define HIF_TXP_TOKEN_ID_MASK 0xffff0000 |
| 3887 | + |
| 3888 | +/* DW9 */ |
| 3889 | +#define HIF_TXP_BSS_IDX_SHIFT 0 |
| 3890 | +#define HIF_TXP_BSS_IDX_MASK 0x000000ff |
| 3891 | +#define HIF_TXP_USER_PRIORITY_SHIFT 8 |
| 3892 | +#define HIF_TXP_USER_PRIORITY_MASK 0x0000ff00 |
| 3893 | +#define HIF_TXP_BUF_NUM_SHIFT 16 |
| 3894 | +#define HIF_TXP_BUF_NUM_MASK 0x001f0000 |
| 3895 | +#define HIF_TXP_MSDU_CNT_SHIFT 21 |
| 3896 | +#define HIF_TXP_MSDU_CNT_MASK 0x03e00000 |
| 3897 | +#define HIF_TXP_SRC_SHIFT 26 |
| 3898 | +#define HIF_TXP_SRC_MASK 0x0c000000 |
| 3899 | + |
| 3900 | +/* DW10 */ |
| 3901 | +#define HIF_TXP_ETH_TYPE_SHIFT 0 |
| 3902 | +#define HIF_TXP_ETH_TYPE_MASK 0x0000ffff |
| 3903 | +#define HIF_TXP_WLAN_IDX_SHIFT 16 |
| 3904 | +#define HIF_TXP_WLAN_IDX_MASK 0x0fff0000 |
| 3905 | + |
| 3906 | +/* DW11 */ |
| 3907 | +#define HIF_TXP_PPE_INFO_SHIFT 0 |
| 3908 | +#define HIF_TXP_PPE_INFO_MASK 0xffffffff |
| 3909 | + |
| 3910 | +/* DW12 - DW31 */ |
| 3911 | +#define HIF_TXP_BUF_PTR0_L_SHIFT 0 |
| 3912 | +#define HIF_TXP_BUF_PTR0_L_MASK 0xffffffff |
| 3913 | +#define HIF_TXP_BUF_LEN0_SHIFT 0 |
| 3914 | +#define HIF_TXP_BUF_LEN0_MASK 0x00000fff |
| 3915 | +#define HIF_TXP_BUF_PTR0_H_SHIFT 12 |
| 3916 | +#define HIF_TXP_BUF_PTR0_H_MASK 0x0000f000 |
| 3917 | +#define HIF_TXP_BUF_LEN1_SHIFT 16 |
| 3918 | +#define HIF_TXP_BUF_LEN1_MASK 0x0fff0000 |
| 3919 | +#define HIF_TXP_BUF_PTR1_H_SHIFT 28 |
| 3920 | +#define HIF_TXP_BUF_PTR1_H_MASK 0xf0000000 |
| 3921 | +#define HIF_TXP_BUF_PTR1_L_SHIFT 0 |
| 3922 | +#define HIF_TXP_BUF_PTR1_L_MASK 0xffffffff |
| 3923 | + |
| 3924 | +/* DW31 */ |
| 3925 | +#define HIF_TXP_ML_SHIFT 16 |
| 3926 | +#define HIF_TXP_ML_MASK 0xffff0000 |
| 3927 | + |
| 3928 | +#endif |
| 3929 | +#endif |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3930 | diff --git a/besra/mtk_debugfs.c b/besra/mtk_debugfs.c |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3931 | new file mode 100644 |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 3932 | index 00000000..ea6a2620 |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3933 | --- /dev/null |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3934 | +++ b/besra/mtk_debugfs.c |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3935 | @@ -0,0 +1,3576 @@ |
| 3936 | +#include<linux/inet.h> |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3937 | +#include "besra.h" |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3938 | +#include "mtk_debug.h" |
| 3939 | +#include "../mt76.h" |
| 3940 | +#include "mcu.h" |
| 3941 | +#include "mac.h" |
| 3942 | + |
| 3943 | +#ifdef CONFIG_MTK_DEBUG |
| 3944 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3945 | +void besra_packet_log_to_host(struct besra_dev *dev, const void *data, int len, int type, int des_len) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3946 | +{ |
| 3947 | + struct bin_debug_hdr *hdr; |
| 3948 | + char *buf; |
| 3949 | + |
| 3950 | + if (len > 1500 - sizeof(*hdr)) |
| 3951 | + len = 1500 - sizeof(*hdr); |
| 3952 | + |
| 3953 | + buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL); |
| 3954 | + if (!buf) |
| 3955 | + return; |
| 3956 | + |
| 3957 | + hdr = (struct bin_debug_hdr *)buf; |
| 3958 | + hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC); |
| 3959 | + hdr->serial_id = cpu_to_le16(dev->fw_debug_seq++); |
| 3960 | + hdr->msg_type = cpu_to_le16(type); |
| 3961 | + hdr->len = cpu_to_le16(len); |
| 3962 | + hdr->des_len = cpu_to_le16(des_len); |
| 3963 | + |
| 3964 | + memcpy(buf + sizeof(*hdr), data, len); |
| 3965 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3966 | + besra_debugfs_rx_log(dev, buf, sizeof(*hdr) + len); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3967 | +} |
| 3968 | + |
| 3969 | +/* DBG MODLE */ |
| 3970 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3971 | +besra_fw_debug_module_set(void *data, u64 module) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3972 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3973 | + struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3974 | + |
| 3975 | + dev->dbg.fw_dbg_module = module; |
| 3976 | + return 0; |
| 3977 | +} |
| 3978 | + |
| 3979 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3980 | +besra_fw_debug_module_get(void *data, u64 *module) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3981 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3982 | + struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3983 | + |
| 3984 | + *module = dev->dbg.fw_dbg_module; |
| 3985 | + return 0; |
| 3986 | +} |
| 3987 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3988 | +DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, besra_fw_debug_module_get, |
| 3989 | + besra_fw_debug_module_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3990 | + |
| 3991 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3992 | +besra_fw_debug_level_set(void *data, u64 level) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3993 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3994 | + struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3995 | + |
| 3996 | + dev->dbg.fw_dbg_lv = level; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 3997 | + besra_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 3998 | + return 0; |
| 3999 | +} |
| 4000 | + |
| 4001 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4002 | +besra_fw_debug_level_get(void *data, u64 *level) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 4003 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4004 | + struct besra_dev *dev = data; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 4005 | + |
| 4006 | + *level = dev->dbg.fw_dbg_lv; |
| 4007 | + return 0; |
| 4008 | +} |
| 4009 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4010 | +DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, besra_fw_debug_level_get, |
| 4011 | + besra_fw_debug_level_set, "%lld\n"); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 4012 | + |
| 4013 | +/* WTBL INFO */ |
| 4014 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4015 | +besra_wtbl_read_raw(struct besra_dev *dev, u16 idx, |
| 4016 | + enum besra_wtbl_type type, u16 start_dw, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 4017 | + u16 len, void *buf) |
| 4018 | +{ |
| 4019 | + u32 *dest_cpy = (u32 *)buf; |
| 4020 | + u32 size_dw = len; |
| 4021 | + u32 src = 0; |
| 4022 | + |
| 4023 | + if (!buf) |
| 4024 | + return 0xFF; |
| 4025 | + |
| 4026 | + if (type == WTBL_TYPE_LMAC) { |
| 4027 | + mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR, |
| 4028 | + FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7))); |
| 4029 | + src = LWTBL_IDX2BASE(idx, start_dw); |
| 4030 | + } else if (type == WTBL_TYPE_UMAC) { |
| 4031 | + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 4032 | + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| 4033 | + src = UWTBL_IDX2BASE(idx, start_dw); |
| 4034 | + } else if (type == WTBL_TYPE_KEY) { |
| 4035 | + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 4036 | + MT_DBG_UWTBL_TOP_WDUCR_TARGET | |
| 4037 | + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| 4038 | + src = KEYTBL_IDX2BASE(idx, start_dw); |
| 4039 | + } |
| 4040 | + |
| 4041 | + while (size_dw--) { |
| 4042 | + *dest_cpy++ = mt76_rr(dev, src); |
| 4043 | + src += 4; |
| 4044 | + }; |
| 4045 | + |
| 4046 | + return 0; |
| 4047 | +} |
| 4048 | + |
| 4049 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 4050 | +besra_wtbl_write_raw(struct besra_dev *dev, u16 idx, |
| 4051 | + enum besra_wtbl_type type, u16 start_dw, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 4052 | + u32 val) |
| 4053 | +{ |
| 4054 | + u32 addr = 0; |
| 4055 | + |
| 4056 | + if (type == WTBL_TYPE_LMAC) { |
| 4057 | + mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR, |
| 4058 | + FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7))); |
| 4059 | + addr = LWTBL_IDX2BASE(idx, start_dw); |
| 4060 | + } else if (type == WTBL_TYPE_UMAC) { |
| 4061 | + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 4062 | + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| 4063 | + addr = UWTBL_IDX2BASE(idx, start_dw); |
| 4064 | + } else if (type == WTBL_TYPE_KEY) { |
| 4065 | + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 4066 | + MT_DBG_UWTBL_TOP_WDUCR_TARGET | |
| 4067 | + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| 4068 | + addr = KEYTBL_IDX2BASE(idx, start_dw); |
| 4069 | + } |
| 4070 | + |
| 4071 | + mt76_wr(dev, addr, val); |
| 4072 | + |
| 4073 | + return 0; |
| 4074 | +} |
| 4075 | + |
| 4076 | +static const struct berse_wtbl_parse WTBL_LMAC_DW0[] = { |
| 4077 | + {"MUAR_IDX", WF_LWTBL_MUAR_MASK, WF_LWTBL_MUAR_SHIFT,false}, |
| 4078 | + {"RCA1", WF_LWTBL_RCA1_MASK, NO_SHIFT_DEFINE, false}, |
| 4079 | + {"KID", WF_LWTBL_KID_MASK, WF_LWTBL_KID_SHIFT, false}, |
| 4080 | + {"RCID", WF_LWTBL_RCID_MASK, NO_SHIFT_DEFINE, false}, |
| 4081 | + {"BAND", WF_LWTBL_BAND_MASK, WF_LWTBL_BAND_SHIFT,false}, |
| 4082 | + {"RV", WF_LWTBL_RV_MASK, NO_SHIFT_DEFINE, false}, |
| 4083 | + {"RCA2", WF_LWTBL_RCA2_MASK, NO_SHIFT_DEFINE, false}, |
| 4084 | + {"WPI_FLAG", WF_LWTBL_WPI_FLAG_MASK, NO_SHIFT_DEFINE,true}, |
| 4085 | + {NULL,} |
| 4086 | +}; |
| 4087 | + |
| 4088 | +static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl) |
| 4089 | +{ |
| 4090 | + u32 *addr = 0; |
| 4091 | + u32 dw_value = 0; |
| 4092 | + u16 i = 0; |
| 4093 | + |
| 4094 | + seq_printf(s, "\t\n"); |
| 4095 | + seq_printf(s, "LinkAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n", |
| 4096 | + lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]); |
| 4097 | + |
| 4098 | + /* LMAC WTBL DW 0 */ |
| 4099 | + seq_printf(s, "\t\n"); |
| 4100 | + seq_printf(s, "LWTBL DW 0/1\n"); |
| 4101 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_PEER_INFO_DW_0*4]); |
| 4102 | + dw_value = *addr; |
| 4103 | + |
| 4104 | + while (WTBL_LMAC_DW0[i].name) { |
| 4105 | + |
| 4106 | + if (WTBL_LMAC_DW0[i].shift == NO_SHIFT_DEFINE) |
| 4107 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW0[i].name, |
| 4108 | + (dw_value & WTBL_LMAC_DW0[i].mask) ? 1 : 0); |
| 4109 | + else |
| 4110 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW0[i].name, |
| 4111 | + (dw_value & WTBL_LMAC_DW0[i].mask) >> WTBL_LMAC_DW0[i].shift); |
| 4112 | + i++; |
| 4113 | + } |
| 4114 | +} |
| 4115 | + |
| 4116 | +static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = { |
| 4117 | + {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false}, |
| 4118 | + {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false}, |
| 4119 | + {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false}, |
| 4120 | + {"WPI_EVEN", WF_LWTBL_WPI_EVEN_MASK, NO_SHIFT_DEFINE, false}, |
| 4121 | + {"AAD_OM", WF_LWTBL_AAD_OM_MASK, NO_SHIFT_DEFINE, false}, |
| 4122 | + {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true}, |
| 4123 | + {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false}, |
| 4124 | + {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false}, |
| 4125 | + {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false}, |
| 4126 | + {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false}, |
| 4127 | + {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true}, |
| 4128 | + {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false}, |
| 4129 | + {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false}, |
| 4130 | + {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| 4131 | + {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false}, |
| 4132 | + {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false}, |
| 4133 | + {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true}, |
| 4134 | + {NULL,} |
| 4135 | +}; |
| 4136 | + |
| 4137 | +static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl) |
| 4138 | +{ |
| 4139 | + u32 *addr = 0; |
| 4140 | + u32 dw_value = 0; |
| 4141 | + u16 i = 0; |
| 4142 | + |
| 4143 | + /* LMAC WTBL DW 2 */ |
| 4144 | + seq_printf(s, "\t\n"); |
| 4145 | + seq_printf(s, "LWTBL DW 2\n"); |
| 4146 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]); |
| 4147 | + dw_value = *addr; |
| 4148 | + |
| 4149 | + while (WTBL_LMAC_DW2[i].name) { |
| 4150 | + |
| 4151 | + if (WTBL_LMAC_DW2[i].shift == NO_SHIFT_DEFINE) |
| 4152 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW2[i].name, |
| 4153 | + (dw_value & WTBL_LMAC_DW2[i].mask) ? 1 : 0); |
| 4154 | + else |
| 4155 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[i].name, |
| 4156 | + (dw_value & WTBL_LMAC_DW2[i].mask) >> WTBL_LMAC_DW2[i].shift); |
| 4157 | + i++; |
| 4158 | + } |
| 4159 | +} |
| 4160 | + |
| 4161 | +static const struct berse_wtbl_parse WTBL_LMAC_DW3[] = { |
| 4162 | + {"WMM_Q", WF_LWTBL_WMM_Q_MASK, WF_LWTBL_WMM_Q_SHIFT, false}, |
| 4163 | + {"EHT_SIG_MCS", WF_LWTBL_EHT_SIG_MCS_MASK, WF_LWTBL_EHT_SIG_MCS_SHIFT, false}, |
| 4164 | + {"HDRT_MODE", WF_LWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, false}, |
| 4165 | + {"BEAM_CHG", WF_LWTBL_BEAM_CHG_MASK, NO_SHIFT_DEFINE, false}, |
| 4166 | + {"EHT_LTF_SYM_NUM", WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK, WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT, true}, |
| 4167 | + {"PFMU_IDX", WF_LWTBL_PFMU_IDX_MASK, WF_LWTBL_PFMU_IDX_SHIFT, false}, |
| 4168 | + {"ULPF_IDX", WF_LWTBL_ULPF_IDX_MASK, WF_LWTBL_ULPF_IDX_SHIFT, false}, |
| 4169 | + {"RIBF", WF_LWTBL_RIBF_MASK, NO_SHIFT_DEFINE, false}, |
| 4170 | + {"ULPF", WF_LWTBL_ULPF_MASK, NO_SHIFT_DEFINE, true}, |
| 4171 | + {"TBF_HT", WF_LWTBL_TBF_HT_MASK, NO_SHIFT_DEFINE, false}, |
| 4172 | + {"TBF_VHT", WF_LWTBL_TBF_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| 4173 | + {"TBF_HE", WF_LWTBL_TBF_HE_MASK, NO_SHIFT_DEFINE, false}, |
| 4174 | + {"TBF_EHT", WF_LWTBL_TBF_EHT_MASK, NO_SHIFT_DEFINE, false}, |
| 4175 | + {"IGN_FBK", WF_LWTBL_IGN_FBK_MASK, NO_SHIFT_DEFINE, true}, |
| 4176 | + {NULL,} |
| 4177 | +}; |
| 4178 | + |
| 4179 | +static void parse_fmac_lwtbl_dw3(struct seq_file *s, u8 *lwtbl) |
| 4180 | +{ |
| 4181 | + u32 *addr = 0; |
| 4182 | + u32 dw_value = 0; |
| 4183 | + u16 i = 0; |
| 4184 | + |
| 4185 | + /* LMAC WTBL DW 3 */ |
| 4186 | + seq_printf(s, "\t\n"); |
| 4187 | + seq_printf(s, "LWTBL DW 3\n"); |
| 4188 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_3*4]); |
| 4189 | + dw_value = *addr; |
| 4190 | + |
| 4191 | + while (WTBL_LMAC_DW3[i].name) { |
| 4192 | + |
| 4193 | + if (WTBL_LMAC_DW3[i].shift == NO_SHIFT_DEFINE) |
| 4194 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW3[i].name, |
| 4195 | + (dw_value & WTBL_LMAC_DW3[i].mask) ? 1 : 0); |
| 4196 | + else |
| 4197 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW3[i].name, |
| 4198 | + (dw_value & WTBL_LMAC_DW3[i].mask) >> WTBL_LMAC_DW3[i].shift); |
| 4199 | + i++; |
| 4200 | + } |
| 4201 | +} |
| 4202 | + |
| 4203 | +static const struct berse_wtbl_parse WTBL_LMAC_DW4[] = { |
| 4204 | + {"ANT_ID_STS0", WF_LWTBL_ANT_ID0_MASK, WF_LWTBL_ANT_ID0_SHIFT, false}, |
| 4205 | + {"STS1", WF_LWTBL_ANT_ID1_MASK, WF_LWTBL_ANT_ID1_SHIFT, false}, |
| 4206 | + {"STS2", WF_LWTBL_ANT_ID2_MASK, WF_LWTBL_ANT_ID2_SHIFT, false}, |
| 4207 | + {"STS3", WF_LWTBL_ANT_ID3_MASK, WF_LWTBL_ANT_ID3_SHIFT, true}, |
| 4208 | + {"ANT_ID_STS4", WF_LWTBL_ANT_ID4_MASK, WF_LWTBL_ANT_ID4_SHIFT, false}, |
| 4209 | + {"STS5", WF_LWTBL_ANT_ID5_MASK, WF_LWTBL_ANT_ID5_SHIFT, false}, |
| 4210 | + {"STS6", WF_LWTBL_ANT_ID6_MASK, WF_LWTBL_ANT_ID6_SHIFT, false}, |
| 4211 | + {"STS7", WF_LWTBL_ANT_ID7_MASK, WF_LWTBL_ANT_ID7_SHIFT, true}, |
| 4212 | + {"PE", WF_LWTBL_PE_MASK, WF_LWTBL_PE_SHIFT, false}, |
| 4213 | + {"DIS_RHTR", WF_LWTBL_DIS_RHTR_MASK, NO_SHIFT_DEFINE, false}, |
| 4214 | + {"LDPC_HT", WF_LWTBL_LDPC_HT_MASK, NO_SHIFT_DEFINE, false}, |
| 4215 | + {"LDPC_VHT", WF_LWTBL_LDPC_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| 4216 | + {"LDPC_HE", WF_LWTBL_LDPC_HE_MASK, NO_SHIFT_DEFINE, false}, |
| 4217 | + {"LDPC_EHT", WF_LWTBL_LDPC_EHT_MASK, NO_SHIFT_DEFINE, true}, |
| 4218 | + {NULL,} |
| 4219 | +}; |
| 4220 | + |
| 4221 | +static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl) |
| 4222 | +{ |
| 4223 | + u32 *addr = 0; |
| 4224 | + u32 dw_value = 0; |
| 4225 | + u16 i = 0; |
| 4226 | + |
| 4227 | + /* LMAC WTBL DW 4 */ |
| 4228 | + seq_printf(s, "\t\n"); |
| 4229 | + seq_printf(s, "LWTBL DW 4\n"); |
| 4230 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_4*4]); |
| 4231 | + dw_value = *addr; |
| 4232 | + |
| 4233 | + while (WTBL_LMAC_DW4[i].name) { |
| 4234 | + if (WTBL_LMAC_DW4[i].shift == NO_SHIFT_DEFINE) |
| 4235 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW4[i].name, |
| 4236 | + (dw_value & WTBL_LMAC_DW4[i].mask) ? 1 : 0); |
| 4237 | + else |
| 4238 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW4[i].name, |
| 4239 | + (dw_value & WTBL_LMAC_DW4[i].mask) >> WTBL_LMAC_DW4[i].shift); |
| 4240 | + i++; |
| 4241 | + } |
| 4242 | +} |
| 4243 | + |
| 4244 | +static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = { |
| 4245 | + {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false}, |
| 4246 | + {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false}, |
| 4247 | + {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false}, |
| 4248 | + {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false}, |
| 4249 | + {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true}, |
| 4250 | + {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false}, |
| 4251 | + {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false}, |
| 4252 | + {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false}, |
| 4253 | + {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true}, |
| 4254 | + {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false}, |
| 4255 | + {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false}, |
| 4256 | + {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false}, |
| 4257 | + {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false}, |
| 4258 | + {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false}, |
| 4259 | + {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true}, |
| 4260 | + {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false}, |
| 4261 | + {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false}, |
| 4262 | + {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true}, |
| 4263 | + {NULL,} |
| 4264 | +}; |
| 4265 | + |
| 4266 | +static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl) |
| 4267 | +{ |
| 4268 | + u32 *addr = 0; |
| 4269 | + u32 dw_value = 0; |
| 4270 | + u16 i = 0; |
| 4271 | + |
| 4272 | + /* LMAC WTBL DW 5 */ |
| 4273 | + seq_printf(s, "\t\n"); |
| 4274 | + seq_printf(s, "LWTBL DW 5\n"); |
| 4275 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]); |
| 4276 | + dw_value = *addr; |
| 4277 | + |
| 4278 | + while (WTBL_LMAC_DW5[i].name) { |
| 4279 | + if (WTBL_LMAC_DW5[i].shift == NO_SHIFT_DEFINE) |
| 4280 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW5[i].name, |
| 4281 | + (dw_value & WTBL_LMAC_DW5[i].mask) ? 1 : 0); |
| 4282 | + else |
| 4283 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW5[i].name, |
| 4284 | + (dw_value & WTBL_LMAC_DW5[i].mask) >> WTBL_LMAC_DW5[i].shift); |
| 4285 | + i++; |
| 4286 | + } |
| 4287 | +} |
| 4288 | + |
| 4289 | +static const struct berse_wtbl_parse WTBL_LMAC_DW6[] = { |
| 4290 | + {"CBRN", WF_LWTBL_CBRN_MASK, WF_LWTBL_CBRN_SHIFT, false}, |
| 4291 | + {"DBNSS_EN", WF_LWTBL_DBNSS_EN_MASK, NO_SHIFT_DEFINE, false}, |
| 4292 | + {"BAF_EN", WF_LWTBL_BAF_EN_MASK, NO_SHIFT_DEFINE, false}, |
| 4293 | + {"RDGBA", WF_LWTBL_RDGBA_MASK, NO_SHIFT_DEFINE, false}, |
| 4294 | + {"RDG", WF_LWTBL_R_MASK, NO_SHIFT_DEFINE, false}, |
| 4295 | + {"SPE_IDX", WF_LWTBL_SPE_IDX_MASK, WF_LWTBL_SPE_IDX_SHIFT, true}, |
| 4296 | + {"G2", WF_LWTBL_G2_MASK, NO_SHIFT_DEFINE, false}, |
| 4297 | + {"G4", WF_LWTBL_G4_MASK, NO_SHIFT_DEFINE, false}, |
| 4298 | + {"G8", WF_LWTBL_G8_MASK, NO_SHIFT_DEFINE, false}, |
| 4299 | + {"G16", WF_LWTBL_G16_MASK, NO_SHIFT_DEFINE, true}, |
| 4300 | + {"G2_LTF", WF_LWTBL_G2_LTF_MASK, WF_LWTBL_G2_LTF_SHIFT, false}, |
| 4301 | + {"G4_LTF", WF_LWTBL_G4_LTF_MASK, WF_LWTBL_G4_LTF_SHIFT, false}, |
| 4302 | + {"G8_LTF", WF_LWTBL_G8_LTF_MASK, WF_LWTBL_G8_LTF_SHIFT, false}, |
| 4303 | + {"G16_LTF", WF_LWTBL_G16_LTF_MASK, WF_LWTBL_G16_LTF_SHIFT, true}, |
| 4304 | + {"G2_HE", WF_LWTBL_G2_HE_MASK, WF_LWTBL_G2_HE_SHIFT, false}, |
| 4305 | + {"G4_HE", WF_LWTBL_G4_HE_MASK, WF_LWTBL_G4_HE_SHIFT, false}, |
| 4306 | + {"G8_HE", WF_LWTBL_G8_HE_MASK, WF_LWTBL_G8_HE_SHIFT, false}, |
| 4307 | + {"G16_HE", WF_LWTBL_G16_HE_MASK, WF_LWTBL_G16_HE_SHIFT, true}, |
| 4308 | + {NULL,} |
| 4309 | +}; |
| 4310 | + |
| 4311 | +static void parse_fmac_lwtbl_dw6(struct seq_file *s, u8 *lwtbl) |
| 4312 | +{ |
| 4313 | + u32 *addr = 0; |
| 4314 | + u32 dw_value = 0; |
| 4315 | + u16 i = 0; |
| 4316 | + |
| 4317 | + /* LMAC WTBL DW 6 */ |
| 4318 | + seq_printf(s, "\t\n"); |
| 4319 | + seq_printf(s, "LWTBL DW 6\n"); |
| 4320 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_6*4]); |
| 4321 | + dw_value = *addr; |
| 4322 | + |
| 4323 | + while (WTBL_LMAC_DW6[i].name) { |
| 4324 | + if (WTBL_LMAC_DW6[i].shift == NO_SHIFT_DEFINE) |
| 4325 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW6[i].name, |
| 4326 | + (dw_value & WTBL_LMAC_DW6[i].mask) ? 1 : 0); |
| 4327 | + else |
| 4328 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW6[i].name, |
| 4329 | + (dw_value & WTBL_LMAC_DW6[i].mask) >> WTBL_LMAC_DW6[i].shift); |
| 4330 | + i++; |
| 4331 | + } |
| 4332 | +} |
| 4333 | + |
| 4334 | +static void parse_fmac_lwtbl_dw7(struct seq_file *s, u8 *lwtbl) |
| 4335 | +{ |
| 4336 | + u32 *addr = 0; |
| 4337 | + u32 dw_value = 0; |
| 4338 | + int i = 0; |
| 4339 | + |
| 4340 | + /* LMAC WTBL DW 7 */ |
| 4341 | + seq_printf(s, "\t\n"); |
| 4342 | + seq_printf(s, "LWTBL DW 7\n"); |
| 4343 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_7*4]); |
| 4344 | + dw_value = *addr; |
| 4345 | + |
| 4346 | + for (i = 0; i < 8; i++) { |
| 4347 | + seq_printf(s, "\tBA_WIN_SIZE%u:%lu\n", i, ((dw_value & BITS(i*4, i*4+3)) >> i*4)); |
| 4348 | + } |
| 4349 | +} |
| 4350 | + |
| 4351 | +static const struct berse_wtbl_parse WTBL_LMAC_DW8[] = { |
| 4352 | + {"RTS_FAIL_CNT_AC0", WF_LWTBL_AC0_RTS_FAIL_CNT_MASK, WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT, false}, |
| 4353 | + {"AC1", WF_LWTBL_AC1_RTS_FAIL_CNT_MASK, WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT, false}, |
| 4354 | + {"AC2", WF_LWTBL_AC2_RTS_FAIL_CNT_MASK, WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT, false}, |
| 4355 | + {"AC3", WF_LWTBL_AC3_RTS_FAIL_CNT_MASK, WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT, true}, |
| 4356 | + {"PARTIAL_AID", WF_LWTBL_PARTIAL_AID_MASK, WF_LWTBL_PARTIAL_AID_SHIFT, false}, |
| 4357 | + {"CHK_PER", WF_LWTBL_CHK_PER_MASK, NO_SHIFT_DEFINE, true}, |
| 4358 | + {NULL,} |
| 4359 | +}; |
| 4360 | + |
| 4361 | +static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl) |
| 4362 | +{ |
| 4363 | + u32 *addr = 0; |
| 4364 | + u32 dw_value = 0; |
| 4365 | + u16 i = 0; |
| 4366 | + |
| 4367 | + /* LMAC WTBL DW 8 */ |
| 4368 | + seq_printf(s, "\t\n"); |
| 4369 | + seq_printf(s, "LWTBL DW 8\n"); |
| 4370 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_8*4]); |
| 4371 | + dw_value = *addr; |
| 4372 | + |
| 4373 | + while (WTBL_LMAC_DW8[i].name) { |
| 4374 | + if (WTBL_LMAC_DW8[i].shift == NO_SHIFT_DEFINE) |
| 4375 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW8[i].name, |
| 4376 | + (dw_value & WTBL_LMAC_DW8[i].mask) ? 1 : 0); |
| 4377 | + else |
| 4378 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW8[i].name, |
| 4379 | + (dw_value & WTBL_LMAC_DW8[i].mask) >> WTBL_LMAC_DW8[i].shift); |
| 4380 | + i++; |
| 4381 | + } |
| 4382 | +} |
| 4383 | + |
| 4384 | +static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = { |
| 4385 | + {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false}, |
| 4386 | + {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false}, |
| 4387 | + {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false}, |
| 4388 | + {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK, NO_SHIFT_DEFINE, true}, |
| 4389 | + {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false}, |
| 4390 | + {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true}, |
| 4391 | + /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */ |
| 4392 | + {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false}, |
| 4393 | + {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false}, |
| 4394 | + {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true}, |
| 4395 | + {NULL,} |
| 4396 | +}; |
| 4397 | + |
| 4398 | +char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"}; |
| 4399 | + |
| 4400 | +static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl) |
| 4401 | +{ |
| 4402 | + u32 *addr = 0; |
| 4403 | + u32 dw_value = 0; |
| 4404 | + u16 i = 0; |
| 4405 | + |
| 4406 | + /* LMAC WTBL DW 9 */ |
| 4407 | + seq_printf(s, "\t\n"); |
| 4408 | + seq_printf(s, "LWTBL DW 9\n"); |
| 4409 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_9*4]); |
| 4410 | + dw_value = *addr; |
| 4411 | + |
| 4412 | + while (WTBL_LMAC_DW9[i].name) { |
| 4413 | + if (WTBL_LMAC_DW9[i].shift == NO_SHIFT_DEFINE) |
| 4414 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW9[i].name, |
| 4415 | + (dw_value & WTBL_LMAC_DW9[i].mask) ? 1 : 0); |
| 4416 | + else |
| 4417 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW9[i].name, |
| 4418 | + (dw_value & WTBL_LMAC_DW9[i].mask) >> WTBL_LMAC_DW9[i].shift); |
| 4419 | + i++; |
| 4420 | + } |
| 4421 | + |
| 4422 | + /* FCAP parser */ |
| 4423 | + seq_printf(s, "\t\n"); |
| 4424 | + seq_printf(s, "FCAP:%s\n", fcap_name[(dw_value & WF_LWTBL_FCAP_MASK) >> WF_LWTBL_FCAP_SHIFT]); |
| 4425 | +} |
| 4426 | + |
| 4427 | +#define HW_TX_RATE_TO_MODE(_x) (((_x) & WTBL_RATE_TX_MODE_MASK) >> WTBL_RATE_TX_MODE_OFFSET) |
| 4428 | +#define HW_TX_RATE_TO_MCS(_x, _mode) ((_x) & WTBL_RATE_TX_RATE_MASK >> WTBL_RATE_TX_RATE_OFFSET) |
| 4429 | +#define HW_TX_RATE_TO_NSS(_x) (((_x) & WTBL_RATE_NSTS_MASK) >> WTBL_RATE_NSTS_OFFSET) |
| 4430 | +#define HW_TX_RATE_TO_STBC(_x) (((_x) & WTBL_RATE_STBC_MASK) >> WTBL_RATE_STBC_OFFSET) |
| 4431 | + |
| 4432 | +#define MAX_TX_MODE 16 |
| 4433 | +static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT", |
| 4434 | + "N/A", "N/A", "N/A", |
| 4435 | + "HE_SU", "HE_EXT_SU", "HE_TRIG", "HE_MU", |
| 4436 | + "N/A", |
| 4437 | + "EHT_EXT_SU", "EHT_TRIG", "EHT_MU", |
| 4438 | + "N/A"}; |
| 4439 | +static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong", "N/A", "2Mshort", "5.5Mshort", "11Mshort", "N/A"}; |
| 4440 | +static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", "N/A"}; |
| 4441 | + |
| 4442 | +static char *hw_rate_ofdm_str(uint16_t ofdm_idx) |
| 4443 | +{ |
| 4444 | + switch (ofdm_idx) { |
| 4445 | + case 11: /* 6M */ |
| 4446 | + return HW_TX_RATE_OFDM_STR[0]; |
| 4447 | + |
| 4448 | + case 15: /* 9M */ |
| 4449 | + return HW_TX_RATE_OFDM_STR[1]; |
| 4450 | + |
| 4451 | + case 10: /* 12M */ |
| 4452 | + return HW_TX_RATE_OFDM_STR[2]; |
| 4453 | + |
| 4454 | + case 14: /* 18M */ |
| 4455 | + return HW_TX_RATE_OFDM_STR[3]; |
| 4456 | + |
| 4457 | + case 9: /* 24M */ |
| 4458 | + return HW_TX_RATE_OFDM_STR[4]; |
| 4459 | + |
| 4460 | + case 13: /* 36M */ |
| 4461 | + return HW_TX_RATE_OFDM_STR[5]; |
| 4462 | + |
| 4463 | + case 8: /* 48M */ |
| 4464 | + return HW_TX_RATE_OFDM_STR[6]; |
| 4465 | + |
| 4466 | + case 12: /* 54M */ |
| 4467 | + return HW_TX_RATE_OFDM_STR[7]; |
| 4468 | + |
| 4469 | + default: |
| 4470 | + return HW_TX_RATE_OFDM_STR[8]; |
| 4471 | + } |
| 4472 | +} |
| 4473 | + |
| 4474 | +static char *hw_rate_str(u8 mode, uint16_t rate_idx) |
| 4475 | +{ |
| 4476 | + if (mode == 0) |
| 4477 | + return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8]; |
| 4478 | + else if (mode == 1) |
| 4479 | + return hw_rate_ofdm_str(rate_idx); |
| 4480 | + else |
| 4481 | + return "MCS"; |
| 4482 | +} |
| 4483 | + |
| 4484 | +static void |
| 4485 | +parse_rate(struct seq_file *s, uint16_t rate_idx, uint16_t txrate) |
| 4486 | +{ |
| 4487 | + uint16_t txmode, mcs, nss, stbc; |
| 4488 | + |
| 4489 | + txmode = HW_TX_RATE_TO_MODE(txrate); |
| 4490 | + mcs = HW_TX_RATE_TO_MCS(txrate, txmode); |
| 4491 | + nss = HW_TX_RATE_TO_NSS(txrate); |
| 4492 | + stbc = HW_TX_RATE_TO_STBC(txrate); |
| 4493 | + |
| 4494 | + seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n", |
| 4495 | + rate_idx + 1, txrate, |
| 4496 | + txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]), |
| 4497 | + mcs, hw_rate_str(txmode, mcs), nss, stbc); |
| 4498 | +} |
| 4499 | + |
| 4500 | + |
| 4501 | +static const struct berse_wtbl_parse WTBL_LMAC_DW10[] = { |
| 4502 | + {"RATE1", WF_LWTBL_RATE1_MASK, WF_LWTBL_RATE1_SHIFT}, |
| 4503 | + {"RATE2", WF_LWTBL_RATE2_MASK, WF_LWTBL_RATE2_SHIFT}, |
| 4504 | + {NULL,} |
| 4505 | +}; |
| 4506 | + |
| 4507 | +static void parse_fmac_lwtbl_dw10(struct seq_file *s, u8 *lwtbl) |
| 4508 | +{ |
| 4509 | + u32 *addr = 0; |
| 4510 | + u32 dw_value = 0; |
| 4511 | + u16 i = 0; |
| 4512 | + |
| 4513 | + /* LMAC WTBL DW 10 */ |
| 4514 | + seq_printf(s, "\t\n"); |
| 4515 | + seq_printf(s, "LWTBL DW 10\n"); |
| 4516 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_1_2*4]); |
| 4517 | + dw_value = *addr; |
| 4518 | + |
| 4519 | + while (WTBL_LMAC_DW10[i].name) { |
| 4520 | + parse_rate(s, i, (dw_value & WTBL_LMAC_DW10[i].mask) >> WTBL_LMAC_DW10[i].shift); |
| 4521 | + i++; |
| 4522 | + } |
| 4523 | +} |
| 4524 | + |
| 4525 | +static const struct berse_wtbl_parse WTBL_LMAC_DW11[] = { |
| 4526 | + {"RATE3", WF_LWTBL_RATE3_MASK, WF_LWTBL_RATE3_SHIFT}, |
| 4527 | + {"RATE4", WF_LWTBL_RATE4_MASK, WF_LWTBL_RATE4_SHIFT}, |
| 4528 | + {NULL,} |
| 4529 | +}; |
| 4530 | + |
| 4531 | +static void parse_fmac_lwtbl_dw11(struct seq_file *s, u8 *lwtbl) |
| 4532 | +{ |
| 4533 | + u32 *addr = 0; |
| 4534 | + u32 dw_value = 0; |
| 4535 | + u16 i = 0; |
| 4536 | + |
| 4537 | + /* LMAC WTBL DW 11 */ |
| 4538 | + seq_printf(s, "\t\n"); |
| 4539 | + seq_printf(s, "LWTBL DW 11\n"); |
| 4540 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_3_4*4]); |
| 4541 | + dw_value = *addr; |
| 4542 | + |
| 4543 | + while (WTBL_LMAC_DW11[i].name) { |
| 4544 | + parse_rate(s, i+2, (dw_value & WTBL_LMAC_DW11[i].mask) >> WTBL_LMAC_DW11[i].shift); |
| 4545 | + i++; |
| 4546 | + } |
| 4547 | +} |
| 4548 | + |
| 4549 | +static const struct berse_wtbl_parse WTBL_LMAC_DW12[] = { |
| 4550 | + {"RATE5", WF_LWTBL_RATE5_MASK, WF_LWTBL_RATE5_SHIFT}, |
| 4551 | + {"RATE6", WF_LWTBL_RATE6_MASK, WF_LWTBL_RATE6_SHIFT}, |
| 4552 | + {NULL,} |
| 4553 | +}; |
| 4554 | + |
| 4555 | +static void parse_fmac_lwtbl_dw12(struct seq_file *s, u8 *lwtbl) |
| 4556 | +{ |
| 4557 | + u32 *addr = 0; |
| 4558 | + u32 dw_value = 0; |
| 4559 | + u16 i = 0; |
| 4560 | + |
| 4561 | + /* LMAC WTBL DW 12 */ |
| 4562 | + seq_printf(s, "\t\n"); |
| 4563 | + seq_printf(s, "LWTBL DW 12\n"); |
| 4564 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_5_6*4]); |
| 4565 | + dw_value = *addr; |
| 4566 | + |
| 4567 | + while (WTBL_LMAC_DW12[i].name) { |
| 4568 | + parse_rate(s, i+4, (dw_value & WTBL_LMAC_DW12[i].mask) >> WTBL_LMAC_DW12[i].shift); |
| 4569 | + i++; |
| 4570 | + } |
| 4571 | +} |
| 4572 | + |
| 4573 | +static const struct berse_wtbl_parse WTBL_LMAC_DW13[] = { |
| 4574 | + {"RATE7", WF_LWTBL_RATE7_MASK, WF_LWTBL_RATE7_SHIFT}, |
| 4575 | + {"RATE8", WF_LWTBL_RATE8_MASK, WF_LWTBL_RATE8_SHIFT}, |
| 4576 | + {NULL,} |
| 4577 | +}; |
| 4578 | + |
| 4579 | +static void parse_fmac_lwtbl_dw13(struct seq_file *s, u8 *lwtbl) |
| 4580 | +{ |
| 4581 | + u32 *addr = 0; |
| 4582 | + u32 dw_value = 0; |
| 4583 | + u16 i = 0; |
| 4584 | + |
| 4585 | + /* LMAC WTBL DW 13 */ |
| 4586 | + seq_printf(s, "\t\n"); |
| 4587 | + seq_printf(s, "LWTBL DW 13\n"); |
| 4588 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_7_8*4]); |
| 4589 | + dw_value = *addr; |
| 4590 | + |
| 4591 | + while (WTBL_LMAC_DW13[i].name) { |
| 4592 | + parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW13[i].mask) >> WTBL_LMAC_DW13[i].shift); |
| 4593 | + i++; |
| 4594 | + } |
| 4595 | +} |
| 4596 | + |
| 4597 | +static const struct berse_wtbl_parse WTBL_LMAC_DW14_BMC[] = { |
| 4598 | + {"CIPHER_IGTK", WF_LWTBL_CIPHER_SUIT_IGTK_MASK, WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT, false}, |
| 4599 | + {"CIPHER_BIGTK", WF_LWTBL_CIPHER_SUIT_BIGTK_MASK, WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT, true}, |
| 4600 | + {NULL,} |
| 4601 | +}; |
| 4602 | + |
| 4603 | +static void parse_fmac_lwtbl_dw14(struct seq_file *s, u8 *lwtbl) |
| 4604 | +{ |
| 4605 | + u32 *addr, *muar_addr = 0; |
| 4606 | + u32 dw_value, muar_dw_value = 0; |
| 4607 | + u16 i = 0; |
| 4608 | + |
| 4609 | + /* DUMP DW14 for BMC entry only */ |
| 4610 | + muar_addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]); |
| 4611 | + muar_dw_value = *muar_addr; |
| 4612 | + if (((muar_dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) |
| 4613 | + == MUAR_INDEX_OWN_MAC_ADDR_BC_MC) { |
| 4614 | + /* LMAC WTBL DW 14 */ |
| 4615 | + seq_printf(s, "\t\n"); |
| 4616 | + seq_printf(s, "LWTBL DW 14\n"); |
| 4617 | + addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]); |
| 4618 | + dw_value = *addr; |
| 4619 | + |
| 4620 | + while (WTBL_LMAC_DW14_BMC[i].name) { |
| 4621 | + parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW14_BMC[i].mask) >> WTBL_LMAC_DW14_BMC[i].shift); |
| 4622 | + i++; |
| 4623 | + } |
| 4624 | + } |
| 4625 | +} |
| 4626 | + |
| 4627 | +static const struct berse_wtbl_parse WTBL_LMAC_DW28[] = { |
| 4628 | + {"RELATED_IDX0", WF_LWTBL_RELATED_IDX0_MASK, WF_LWTBL_RELATED_IDX0_SHIFT, false}, |
| 4629 | + {"RELATED_BAND0", WF_LWTBL_RELATED_BAND0_MASK, WF_LWTBL_RELATED_BAND0_SHIFT, false}, |
| 4630 | + {"PRI_MLD_BAND", WF_LWTBL_PRIMARY_MLD_BAND_MASK, WF_LWTBL_PRIMARY_MLD_BAND_SHIFT, true}, |
| 4631 | + {"RELATED_IDX0", WF_LWTBL_RELATED_IDX1_MASK, WF_LWTBL_RELATED_IDX1_SHIFT, false}, |
| 4632 | + {"RELATED_BAND1", WF_LWTBL_RELATED_BAND1_MASK, WF_LWTBL_RELATED_BAND1_SHIFT, false}, |
| 4633 | + {"SEC_MLD_BAND", WF_LWTBL_SECONDARY_MLD_BAND_MASK, WF_LWTBL_SECONDARY_MLD_BAND_SHIFT, true}, |
| 4634 | + {NULL,} |
| 4635 | +}; |
| 4636 | + |
| 4637 | +static void parse_fmac_lwtbl_dw28(struct seq_file *s, u8 *lwtbl) |
| 4638 | +{ |
| 4639 | + u32 *addr = 0; |
| 4640 | + u32 dw_value = 0; |
| 4641 | + u16 i = 0; |
| 4642 | + |
| 4643 | + /* LMAC WTBL DW 28 */ |
| 4644 | + seq_printf(s, "\t\n"); |
| 4645 | + seq_printf(s, "LWTBL DW 28\n"); |
| 4646 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_1*4]); |
| 4647 | + dw_value = *addr; |
| 4648 | + |
| 4649 | + while (WTBL_LMAC_DW28[i].name) { |
| 4650 | + if (WTBL_LMAC_DW28[i].shift == NO_SHIFT_DEFINE) |
| 4651 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW28[i].name, |
| 4652 | + (dw_value & WTBL_LMAC_DW28[i].mask) ? 1 : 0); |
| 4653 | + else |
| 4654 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW28[i].name, |
| 4655 | + (dw_value & WTBL_LMAC_DW28[i].mask) >> |
| 4656 | + WTBL_LMAC_DW28[i].shift); |
| 4657 | + i++; |
| 4658 | + } |
| 4659 | +} |
| 4660 | + |
| 4661 | +static const struct berse_wtbl_parse WTBL_LMAC_DW29[] = { |
| 4662 | + {"DISPATCH_POLICY_MLD_TID0", WF_LWTBL_DISPATCH_POLICY0_MASK, WF_LWTBL_DISPATCH_POLICY0_SHIFT, false}, |
| 4663 | + {"MLD_TID1", WF_LWTBL_DISPATCH_POLICY1_MASK, WF_LWTBL_DISPATCH_POLICY1_SHIFT, false}, |
| 4664 | + {"MLD_TID2", WF_LWTBL_DISPATCH_POLICY2_MASK, WF_LWTBL_DISPATCH_POLICY2_SHIFT, false}, |
| 4665 | + {"MLD_TID3", WF_LWTBL_DISPATCH_POLICY3_MASK, WF_LWTBL_DISPATCH_POLICY3_SHIFT, true}, |
| 4666 | + {"MLD_TID4", WF_LWTBL_DISPATCH_POLICY4_MASK, WF_LWTBL_DISPATCH_POLICY4_SHIFT, false}, |
| 4667 | + {"MLD_TID5", WF_LWTBL_DISPATCH_POLICY5_MASK, WF_LWTBL_DISPATCH_POLICY5_SHIFT, false}, |
| 4668 | + {"MLD_TID6", WF_LWTBL_DISPATCH_POLICY6_MASK, WF_LWTBL_DISPATCH_POLICY6_SHIFT, false}, |
| 4669 | + {"MLD_TID7", WF_LWTBL_DISPATCH_POLICY7_MASK, WF_LWTBL_DISPATCH_POLICY7_SHIFT, true}, |
| 4670 | + {"OMLD_ID", WF_LWTBL_OWN_MLD_ID_MASK, WF_LWTBL_OWN_MLD_ID_SHIFT, false}, |
| 4671 | + {"EMLSR0", WF_LWTBL_EMLSR0_MASK, NO_SHIFT_DEFINE, false}, |
| 4672 | + {"EMLMR0", WF_LWTBL_EMLMR0_MASK, NO_SHIFT_DEFINE, false}, |
| 4673 | + {"EMLSR1", WF_LWTBL_EMLSR1_MASK, NO_SHIFT_DEFINE, false}, |
| 4674 | + {"EMLMR1", WF_LWTBL_EMLMR1_MASK, NO_SHIFT_DEFINE, true}, |
| 4675 | + {"EMLSR2", WF_LWTBL_EMLSR2_MASK, NO_SHIFT_DEFINE, false}, |
| 4676 | + {"EMLMR2", WF_LWTBL_EMLMR2_MASK, NO_SHIFT_DEFINE, false}, |
| 4677 | + {"STR_BITMAP", WF_LWTBL_STR_BITMAP_MASK, WF_LWTBL_STR_BITMAP_SHIFT, true}, |
| 4678 | + {NULL,} |
| 4679 | +}; |
| 4680 | + |
| 4681 | +static void parse_fmac_lwtbl_dw29(struct seq_file *s, u8 *lwtbl) |
| 4682 | +{ |
| 4683 | + u32 *addr = 0; |
| 4684 | + u32 dw_value = 0; |
| 4685 | + u16 i = 0; |
| 4686 | + |
| 4687 | + /* LMAC WTBL DW 29 */ |
| 4688 | + seq_printf(s, "\t\n"); |
| 4689 | + seq_printf(s, "LWTBL DW 29\n"); |
| 4690 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_2*4]); |
| 4691 | + dw_value = *addr; |
| 4692 | + |
| 4693 | + while (WTBL_LMAC_DW29[i].name) { |
| 4694 | + if (WTBL_LMAC_DW29[i].shift == NO_SHIFT_DEFINE) |
| 4695 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW29[i].name, |
| 4696 | + (dw_value & WTBL_LMAC_DW29[i].mask) ? 1 : 0); |
| 4697 | + else |
| 4698 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW29[i].name, |
| 4699 | + (dw_value & WTBL_LMAC_DW29[i].mask) >> |
| 4700 | + WTBL_LMAC_DW29[i].shift); |
| 4701 | + i++; |
| 4702 | + } |
| 4703 | +} |
| 4704 | + |
| 4705 | +static const struct berse_wtbl_parse WTBL_LMAC_DW30[] = { |
| 4706 | + {"DISPATCH_ORDER", WF_LWTBL_DISPATCH_ORDER_MASK, WF_LWTBL_DISPATCH_ORDER_SHIFT, false}, |
| 4707 | + {"DISPATCH_RATIO", WF_LWTBL_DISPATCH_RATIO_MASK, WF_LWTBL_DISPATCH_RATIO_SHIFT, false}, |
| 4708 | + {"LINK_MGF", WF_LWTBL_LINK_MGF_MASK, WF_LWTBL_LINK_MGF_SHIFT, true}, |
| 4709 | + {NULL,} |
| 4710 | +}; |
| 4711 | + |
| 4712 | +static void parse_fmac_lwtbl_dw30(struct seq_file *s, u8 *lwtbl) |
| 4713 | +{ |
| 4714 | + u32 *addr = 0; |
| 4715 | + u32 dw_value = 0; |
| 4716 | + u16 i = 0; |
| 4717 | + |
| 4718 | + /* LMAC WTBL DW 30 */ |
| 4719 | + seq_printf(s, "\t\n"); |
| 4720 | + seq_printf(s, "LWTBL DW 30\n"); |
| 4721 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_3*4]); |
| 4722 | + dw_value = *addr; |
| 4723 | + |
| 4724 | + |
| 4725 | + while (WTBL_LMAC_DW30[i].name) { |
| 4726 | + if (WTBL_LMAC_DW30[i].shift == NO_SHIFT_DEFINE) |
| 4727 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW30[i].name, |
| 4728 | + (dw_value & WTBL_LMAC_DW30[i].mask) ? 1 : 0); |
| 4729 | + else |
| 4730 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW30[i].name, |
| 4731 | + (dw_value & WTBL_LMAC_DW30[i].mask) >> WTBL_LMAC_DW30[i].shift); |
| 4732 | + i++; |
| 4733 | + } |
| 4734 | +} |
| 4735 | + |
| 4736 | +static const struct berse_wtbl_parse WTBL_LMAC_DW31[] = { |
| 4737 | + {"NEGO_WINSIZE0", WF_LWTBL_NEGOTIATED_WINSIZE0_MASK, WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT, false}, |
| 4738 | + {"WINSIZE1", WF_LWTBL_NEGOTIATED_WINSIZE1_MASK, WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT, false}, |
| 4739 | + {"WINSIZE2", WF_LWTBL_NEGOTIATED_WINSIZE2_MASK, WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT, false}, |
| 4740 | + {"WINSIZE3", WF_LWTBL_NEGOTIATED_WINSIZE3_MASK, WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT, true}, |
| 4741 | + {"WINSIZE4", WF_LWTBL_NEGOTIATED_WINSIZE4_MASK, WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT, false}, |
| 4742 | + {"WINSIZE5", WF_LWTBL_NEGOTIATED_WINSIZE5_MASK, WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT, false}, |
| 4743 | + {"WINSIZE6", WF_LWTBL_NEGOTIATED_WINSIZE6_MASK, WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT, false}, |
| 4744 | + {"WINSIZE7", WF_LWTBL_NEGOTIATED_WINSIZE7_MASK, WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT, true}, |
| 4745 | + {"CASCAD", WF_LWTBL_CASCAD_MASK, NO_SHIFT_DEFINE, false}, |
| 4746 | + {"ALL_ACK", WF_LWTBL_ALL_ACK_MASK, NO_SHIFT_DEFINE, false}, |
| 4747 | + {"MPDU_SIZE", WF_LWTBL_MPDU_SIZE_MASK, WF_LWTBL_MPDU_SIZE_SHIFT, false}, |
| 4748 | + {"BA_MODE", WF_LWTBL_BA_MODE_MASK, WF_LWTBL_BA_MODE_SHIFT, true}, |
| 4749 | + {NULL,} |
| 4750 | +}; |
| 4751 | + |
| 4752 | +static void parse_fmac_lwtbl_dw31(struct seq_file *s, u8 *lwtbl) |
| 4753 | +{ |
| 4754 | + u32 *addr = 0; |
| 4755 | + u32 dw_value = 0; |
| 4756 | + u16 i = 0; |
| 4757 | + |
| 4758 | + /* LMAC WTBL DW 31 */ |
| 4759 | + seq_printf(s, "\t\n"); |
| 4760 | + seq_printf(s, "LWTBL DW 31\n"); |
| 4761 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_RESP_INFO_DW_31*4]); |
| 4762 | + dw_value = *addr; |
| 4763 | + |
| 4764 | + while (WTBL_LMAC_DW31[i].name) { |
| 4765 | + if (WTBL_LMAC_DW31[i].shift == NO_SHIFT_DEFINE) |
| 4766 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW31[i].name, |
| 4767 | + (dw_value & WTBL_LMAC_DW31[i].mask) ? 1 : 0); |
| 4768 | + else |
| 4769 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW31[i].name, |
| 4770 | + (dw_value & WTBL_LMAC_DW31[i].mask) >> |
| 4771 | + WTBL_LMAC_DW31[i].shift); |
| 4772 | + i++; |
| 4773 | + } |
| 4774 | +} |
| 4775 | + |
| 4776 | +static const struct berse_wtbl_parse WTBL_LMAC_DW32[] = { |
| 4777 | + {"OM_INFO", WF_LWTBL_OM_INFO_MASK, WF_LWTBL_OM_INFO_SHIFT, false}, |
| 4778 | + {"OM_RXD_DUP_MODE", WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK, NO_SHIFT_DEFINE, false}, |
| 4779 | + {"RXD_DUP_WHITE_LIST", WF_LWTBL_RXD_DUP_WHITE_LIST_MASK, WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT, false}, |
| 4780 | + {"RXD_DUP_MODE", WF_LWTBL_RXD_DUP_MODE_MASK, WF_LWTBL_RXD_DUP_MODE_SHIFT, false}, |
| 4781 | + {"DROP", WF_LWTBL_DROP_MASK, NO_SHIFT_DEFINE, false}, |
| 4782 | + {"ACK_EN", WF_LWTBL_ACK_EN_MASK, NO_SHIFT_DEFINE, true}, |
| 4783 | + {NULL,} |
| 4784 | +}; |
| 4785 | + |
| 4786 | +static void parse_fmac_lwtbl_dw32(struct seq_file *s, u8 *lwtbl) |
| 4787 | +{ |
| 4788 | + u32 *addr = 0; |
| 4789 | + u32 dw_value = 0; |
| 4790 | + u16 i = 0; |
| 4791 | + |
| 4792 | + /* LMAC WTBL DW 32 */ |
| 4793 | + seq_printf(s, "\t\n"); |
| 4794 | + seq_printf(s, "LWTBL DW 32\n"); |
| 4795 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_DUP_INFO_DW_32*4]); |
| 4796 | + dw_value = *addr; |
| 4797 | + |
| 4798 | + while (WTBL_LMAC_DW32[i].name) { |
| 4799 | + if (WTBL_LMAC_DW32[i].shift == NO_SHIFT_DEFINE) |
| 4800 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW32[i].name, |
| 4801 | + (dw_value & WTBL_LMAC_DW32[i].mask) ? 1 : 0); |
| 4802 | + else |
| 4803 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW32[i].name, |
| 4804 | + (dw_value & WTBL_LMAC_DW32[i].mask) >> |
| 4805 | + WTBL_LMAC_DW32[i].shift); |
| 4806 | + i++; |
| 4807 | + } |
| 4808 | +} |
| 4809 | + |
| 4810 | +static const struct berse_wtbl_parse WTBL_LMAC_DW33[] = { |
| 4811 | + {"USER_RSSI", WF_LWTBL_USER_RSSI_MASK, WF_LWTBL_USER_RSSI_SHIFT, false}, |
| 4812 | + {"USER_SNR", WF_LWTBL_USER_SNR_MASK, WF_LWTBL_USER_SNR_SHIFT, false}, |
| 4813 | + {"RAPID_REACTION_RATE", WF_LWTBL_RAPID_REACTION_RATE_MASK, WF_LWTBL_RAPID_REACTION_RATE_SHIFT, true}, |
| 4814 | + {"HT_AMSDU(Read Only)", WF_LWTBL_HT_AMSDU_MASK, NO_SHIFT_DEFINE, false}, |
| 4815 | + {"AMSDU_CROSS_LG(Read Only)", WF_LWTBL_AMSDU_CROSS_LG_MASK, NO_SHIFT_DEFINE, true}, |
| 4816 | + {NULL,} |
| 4817 | +}; |
| 4818 | + |
| 4819 | +static void parse_fmac_lwtbl_dw33(struct seq_file *s, u8 *lwtbl) |
| 4820 | +{ |
| 4821 | + u32 *addr = 0; |
| 4822 | + u32 dw_value = 0; |
| 4823 | + u16 i = 0; |
| 4824 | + |
| 4825 | + /* LMAC WTBL DW 33 */ |
| 4826 | + seq_printf(s, "\t\n"); |
| 4827 | + seq_printf(s, "LWTBL DW 33\n"); |
| 4828 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_1*4]); |
| 4829 | + dw_value = *addr; |
| 4830 | + |
| 4831 | + while (WTBL_LMAC_DW33[i].name) { |
| 4832 | + if (WTBL_LMAC_DW33[i].shift == NO_SHIFT_DEFINE) |
| 4833 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW33[i].name, |
| 4834 | + (dw_value & WTBL_LMAC_DW33[i].mask) ? 1 : 0); |
| 4835 | + else |
| 4836 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW33[i].name, |
| 4837 | + (dw_value & WTBL_LMAC_DW33[i].mask) >> |
| 4838 | + WTBL_LMAC_DW33[i].shift); |
| 4839 | + i++; |
| 4840 | + } |
| 4841 | +} |
| 4842 | + |
| 4843 | +static const struct berse_wtbl_parse WTBL_LMAC_DW34[] = { |
| 4844 | + {"RESP_RCPI0", WF_LWTBL_RESP_RCPI0_MASK, WF_LWTBL_RESP_RCPI0_SHIFT, false}, |
| 4845 | + {"RCPI1", WF_LWTBL_RESP_RCPI1_MASK, WF_LWTBL_RESP_RCPI1_SHIFT, false}, |
| 4846 | + {"RCPI2", WF_LWTBL_RESP_RCPI2_MASK, WF_LWTBL_RESP_RCPI2_SHIFT, false}, |
| 4847 | + {"RCPI3", WF_LWTBL_RESP_RCPI3_MASK, WF_LWTBL_RESP_RCPI3_SHIFT, true}, |
| 4848 | + {NULL,} |
| 4849 | +}; |
| 4850 | + |
| 4851 | +static void parse_fmac_lwtbl_dw34(struct seq_file *s, u8 *lwtbl) |
| 4852 | +{ |
| 4853 | + u32 *addr = 0; |
| 4854 | + u32 dw_value = 0; |
| 4855 | + u16 i = 0; |
| 4856 | + |
| 4857 | + /* LMAC WTBL DW 34 */ |
| 4858 | + seq_printf(s, "\t\n"); |
| 4859 | + seq_printf(s, "LWTBL DW 34\n"); |
| 4860 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_2*4]); |
| 4861 | + dw_value = *addr; |
| 4862 | + |
| 4863 | + |
| 4864 | + while (WTBL_LMAC_DW34[i].name) { |
| 4865 | + if (WTBL_LMAC_DW34[i].shift == NO_SHIFT_DEFINE) |
| 4866 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW34[i].name, |
| 4867 | + (dw_value & WTBL_LMAC_DW34[i].mask) ? 1 : 0); |
| 4868 | + else |
| 4869 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW34[i].name, |
| 4870 | + (dw_value & WTBL_LMAC_DW34[i].mask) >> |
| 4871 | + WTBL_LMAC_DW34[i].shift); |
| 4872 | + i++; |
| 4873 | + } |
| 4874 | +} |
| 4875 | + |
| 4876 | +static const struct berse_wtbl_parse WTBL_LMAC_DW35[] = { |
| 4877 | + {"SNR 0", WF_LWTBL_SNR_RX0_MASK, WF_LWTBL_SNR_RX0_SHIFT, false}, |
| 4878 | + {"SNR 1", WF_LWTBL_SNR_RX1_MASK, WF_LWTBL_SNR_RX1_SHIFT, false}, |
| 4879 | + {"SNR 2", WF_LWTBL_SNR_RX2_MASK, WF_LWTBL_SNR_RX2_SHIFT, false}, |
| 4880 | + {"SNR 3", WF_LWTBL_SNR_RX3_MASK, WF_LWTBL_SNR_RX3_SHIFT, true}, |
| 4881 | + {NULL,} |
| 4882 | +}; |
| 4883 | + |
| 4884 | +static void parse_fmac_lwtbl_dw35(struct seq_file *s, u8 *lwtbl) |
| 4885 | +{ |
| 4886 | + u32 *addr = 0; |
| 4887 | + u32 dw_value = 0; |
| 4888 | + u16 i = 0; |
| 4889 | + |
| 4890 | + /* LMAC WTBL DW 35 */ |
| 4891 | + seq_printf(s, "\t\n"); |
| 4892 | + seq_printf(s, "LWTBL DW 35\n"); |
| 4893 | + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_3*4]); |
| 4894 | + dw_value = *addr; |
| 4895 | + |
| 4896 | + |
| 4897 | + while (WTBL_LMAC_DW35[i].name) { |
| 4898 | + if (WTBL_LMAC_DW35[i].shift == NO_SHIFT_DEFINE) |
| 4899 | + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW35[i].name, |
| 4900 | + (dw_value & WTBL_LMAC_DW35[i].mask) ? 1 : 0); |
| 4901 | + else |
| 4902 | + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW35[i].name, |
| 4903 | + (dw_value & WTBL_LMAC_DW35[i].mask) >> |
| 4904 | + WTBL_LMAC_DW35[i].shift); |
| 4905 | + i++; |
| 4906 | + } |
| 4907 | +} |
| 4908 | + |
| 4909 | +static void parse_fmac_lwtbl_rx_stats(struct seq_file *s, u8 *lwtbl) |
| 4910 | +{ |
| 4911 | + parse_fmac_lwtbl_dw33(s, lwtbl); |
| 4912 | + parse_fmac_lwtbl_dw34(s, lwtbl); |
| 4913 | + parse_fmac_lwtbl_dw35(s, lwtbl); |
| 4914 | +} |
| 4915 | + |
| 4916 | +static void parse_fmac_lwtbl_mlo_info(struct seq_file *s, u8 *lwtbl) |
| 4917 | +{ |
| 4918 | + parse_fmac_lwtbl_dw28(s, lwtbl); |
| 4919 | + parse_fmac_lwtbl_dw29(s, lwtbl); |
| 4920 | + parse_fmac_lwtbl_dw30(s, lwtbl); |
| 4921 | +} |
| 4922 | + |
| 4923 | +static const struct berse_wtbl_parse WTBL_UMAC_DW9[] = { |
| 4924 | + {"RELATED_IDX0", WF_UWTBL_RELATED_IDX0_MASK, WF_UWTBL_RELATED_IDX0_SHIFT, false}, |
| 4925 | + {"RELATED_BAND0", WF_UWTBL_RELATED_BAND0_MASK, WF_UWTBL_RELATED_BAND0_SHIFT, false}, |
| 4926 | + {"PRI_MLD_BAND", WF_UWTBL_PRIMARY_MLD_BAND_MASK, WF_UWTBL_PRIMARY_MLD_BAND_SHIFT, true}, |
| 4927 | + {"RELATED_IDX0", WF_UWTBL_RELATED_IDX1_MASK, WF_UWTBL_RELATED_IDX1_SHIFT, false}, |
| 4928 | + {"RELATED_BAND1", WF_UWTBL_RELATED_BAND1_MASK, WF_UWTBL_RELATED_BAND1_SHIFT, false}, |
| 4929 | + {"SEC_MLD_BAND", WF_UWTBL_SECONDARY_MLD_BAND_MASK, WF_UWTBL_SECONDARY_MLD_BAND_SHIFT, true}, |
| 4930 | + {NULL,} |
| 4931 | +}; |
| 4932 | + |
| 4933 | +static void parse_fmac_uwtbl_mlo_info(struct seq_file *s, u8 *uwtbl) |
| 4934 | +{ |
| 4935 | + u32 *addr = 0; |
| 4936 | + u32 dw_value = 0; |
| 4937 | + u16 i = 0; |
| 4938 | + |
| 4939 | + seq_printf(s, "\t\n"); |
| 4940 | + seq_printf(s, "MldAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n", |
| 4941 | + uwtbl[4], uwtbl[5], uwtbl[6], uwtbl[7], uwtbl[0], uwtbl[1]); |
| 4942 | + |
| 4943 | + /* UMAC WTBL DW 0 */ |
| 4944 | + seq_printf(s, "\t\n"); |
| 4945 | + seq_printf(s, "UWTBL DW 0\n"); |
| 4946 | + addr = (u32 *)&(uwtbl[WF_UWTBL_OWN_MLD_ID_DW*4]); |
| 4947 | + dw_value = *addr; |
| 4948 | + |
| 4949 | + seq_printf(s, "\t%s:%u\n", "OMLD_ID", |
| 4950 | + (dw_value & WF_UWTBL_OWN_MLD_ID_MASK) >> WF_UWTBL_OWN_MLD_ID_SHIFT); |
| 4951 | + |
| 4952 | + /* UMAC WTBL DW 9 */ |
| 4953 | + seq_printf(s, "\t\n"); |
| 4954 | + seq_printf(s, "UWTBL DW 9\n"); |
| 4955 | + addr = (u32 *)&(uwtbl[WF_UWTBL_RELATED_IDX0_DW*4]); |
| 4956 | + dw_value = *addr; |
| 4957 | + |
| 4958 | + while (WTBL_UMAC_DW9[i].name) { |
| 4959 | + |
| 4960 | + if (WTBL_UMAC_DW9[i].shift == NO_SHIFT_DEFINE) |
| 4961 | + seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW9[i].name, |
| 4962 | + (dw_value & WTBL_UMAC_DW9[i].mask) ? 1 : 0); |
| 4963 | + else |
| 4964 | + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW9[i].name, |
| 4965 | + (dw_value & WTBL_UMAC_DW9[i].mask) >> |
| 4966 | + WTBL_UMAC_DW9[i].shift); |
| 4967 | + i++; |
| 4968 | + } |
| 4969 | +} |
| 4970 | + |
| 4971 | +static bool |
| 4972 | +is_wtbl_bigtk_exist(u8 *lwtbl) |
| 4973 | +{ |
| 4974 | + u32 *addr = 0; |
| 4975 | + u32 dw_value = 0; |
| 4976 | + |
| 4977 | + addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]); |
| 4978 | + dw_value = *addr; |
| 4979 | + if (((dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) == |
| 4980 | + MUAR_INDEX_OWN_MAC_ADDR_BC_MC) { |
| 4981 | + addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_BIGTK_DW*4]); |
| 4982 | + dw_value = *addr; |
| 4983 | + if (((dw_value & WF_LWTBL_CIPHER_SUIT_BIGTK_MASK) >> |
| 4984 | + WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT) != IGTK_CIPHER_SUIT_NONE) |
| 4985 | + return true; |
| 4986 | + } |
| 4987 | + |
| 4988 | + return false; |
| 4989 | +} |
| 4990 | + |
| 4991 | +static const struct berse_wtbl_parse WTBL_UMAC_DW2[] = { |
| 4992 | + {"PN0", WTBL_PN0_MASK, WTBL_PN0_OFFSET, false}, |
| 4993 | + {"PN1", WTBL_PN1_MASK, WTBL_PN1_OFFSET, false}, |
| 4994 | + {"PN2", WTBL_PN2_MASK, WTBL_PN2_OFFSET, true}, |
| 4995 | + {"PN3", WTBL_PN3_MASK, WTBL_PN3_OFFSET, false}, |
| 4996 | + {NULL,} |
| 4997 | +}; |
| 4998 | + |
| 4999 | +static const struct berse_wtbl_parse WTBL_UMAC_DW3[] = { |
| 5000 | + {"PN4", WTBL_PN4_MASK, WTBL_PN4_OFFSET, false}, |
| 5001 | + {"PN5", WTBL_PN5_MASK, WTBL_PN5_OFFSET, true}, |
| 5002 | + {NULL,} |
| 5003 | +}; |
| 5004 | + |
| 5005 | +static const struct berse_wtbl_parse WTBL_UMAC_DW4_BIPN[] = { |
| 5006 | + {"BIPN0", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false}, |
| 5007 | + {"BIPN1", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, false}, |
| 5008 | + {"BIPN2", WTBL_BIPN2_MASK, WTBL_BIPN2_OFFSET, true}, |
| 5009 | + {"BIPN3", WTBL_BIPN3_MASK, WTBL_BIPN3_OFFSET, false}, |
| 5010 | + {NULL,} |
| 5011 | +}; |
| 5012 | + |
| 5013 | +static const struct berse_wtbl_parse WTBL_UMAC_DW5_BIPN[] = { |
| 5014 | + {"BIPN4", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false}, |
| 5015 | + {"BIPN5", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, true}, |
| 5016 | + {NULL,} |
| 5017 | +}; |
| 5018 | + |
| 5019 | +static void parse_fmac_uwtbl_pn(struct seq_file *s, u8 *uwtbl, u8 *lwtbl) |
| 5020 | +{ |
| 5021 | + u32 *addr = 0; |
| 5022 | + u32 dw_value = 0; |
| 5023 | + u16 i = 0; |
| 5024 | + |
| 5025 | + seq_printf(s, "\t\n"); |
| 5026 | + seq_printf(s, "UWTBL PN\n"); |
| 5027 | + |
| 5028 | + /* UMAC WTBL DW 2/3 */ |
| 5029 | + addr = (u32 *)&(uwtbl[WF_UWTBL_PN_31_0__DW*4]); |
| 5030 | + dw_value = *addr; |
| 5031 | + |
| 5032 | + while (WTBL_UMAC_DW2[i].name) { |
| 5033 | + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW2[i].name, |
| 5034 | + (dw_value & WTBL_UMAC_DW2[i].mask) >> |
| 5035 | + WTBL_UMAC_DW2[i].shift); |
| 5036 | + i++; |
| 5037 | + } |
| 5038 | + |
| 5039 | + i = 0; |
| 5040 | + addr = (u32 *)&(uwtbl[WF_UWTBL_PN_47_32__DW*4]); |
| 5041 | + dw_value = *addr; |
| 5042 | + |
| 5043 | + while (WTBL_UMAC_DW3[i].name) { |
| 5044 | + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW3[i].name, |
| 5045 | + (dw_value & WTBL_UMAC_DW3[i].mask) >> |
| 5046 | + WTBL_UMAC_DW3[i].shift); |
| 5047 | + i++; |
| 5048 | + } |
| 5049 | + |
| 5050 | + |
| 5051 | + /* UMAC WTBL DW 4/5 for BIGTK */ |
| 5052 | + if (is_wtbl_bigtk_exist(lwtbl) == true) { |
| 5053 | + i = 0; |
| 5054 | + addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_31_0__DW*4]); |
| 5055 | + dw_value = *addr; |
| 5056 | + |
| 5057 | + while (WTBL_UMAC_DW4_BIPN[i].name) { |
| 5058 | + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW4_BIPN[i].name, |
| 5059 | + (dw_value & WTBL_UMAC_DW4_BIPN[i].mask) >> |
| 5060 | + WTBL_UMAC_DW4_BIPN[i].shift); |
| 5061 | + i++; |
| 5062 | + } |
| 5063 | + |
| 5064 | + i = 0; |
| 5065 | + addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_47_32__DW*4]); |
| 5066 | + dw_value = *addr; |
| 5067 | + |
| 5068 | + while (WTBL_UMAC_DW5_BIPN[i].name) { |
| 5069 | + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW5_BIPN[i].name, |
| 5070 | + (dw_value & WTBL_UMAC_DW5_BIPN[i].mask) >> |
| 5071 | + WTBL_UMAC_DW5_BIPN[i].shift); |
| 5072 | + i++; |
| 5073 | + } |
| 5074 | + } |
| 5075 | +} |
| 5076 | + |
| 5077 | +static void parse_fmac_uwtbl_sn(struct seq_file *s, u8 *uwtbl) |
| 5078 | +{ |
| 5079 | + u32 *addr = 0; |
| 5080 | + u32 u2SN = 0; |
| 5081 | + |
| 5082 | + /* UMAC WTBL DW SN part */ |
| 5083 | + seq_printf(s, "\t\n"); |
| 5084 | + seq_printf(s, "UWTBL SN\n"); |
| 5085 | + |
| 5086 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID0_SN_DW*4]); |
| 5087 | + u2SN = ((*addr) & WF_UWTBL_TID0_SN_MASK) >> WF_UWTBL_TID0_SN_SHIFT; |
| 5088 | + seq_printf(s, "\t%s:%u\n", "TID0_AC0_SN", u2SN); |
| 5089 | + |
| 5090 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID1_SN_DW*4]); |
| 5091 | + u2SN = ((*addr) & WF_UWTBL_TID1_SN_MASK) >> WF_UWTBL_TID1_SN_SHIFT; |
| 5092 | + seq_printf(s, "\t%s:%u\n", "TID1_AC1_SN", u2SN); |
| 5093 | + |
| 5094 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_7_0__DW*4]); |
| 5095 | + u2SN = ((*addr) & WF_UWTBL_TID2_SN_7_0__MASK) >> |
| 5096 | + WF_UWTBL_TID2_SN_7_0__SHIFT; |
| 5097 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_11_8__DW*4]); |
| 5098 | + u2SN |= (((*addr) & WF_UWTBL_TID2_SN_11_8__MASK) >> |
| 5099 | + WF_UWTBL_TID2_SN_11_8__SHIFT) << 8; |
| 5100 | + seq_printf(s, "\t%s:%u\n", "TID2_AC2_SN", u2SN); |
| 5101 | + |
| 5102 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID3_SN_DW*4]); |
| 5103 | + u2SN = ((*addr) & WF_UWTBL_TID3_SN_MASK) >> WF_UWTBL_TID3_SN_SHIFT; |
| 5104 | + seq_printf(s, "\t%s:%u\n", "TID3_AC3_SN", u2SN); |
| 5105 | + |
| 5106 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID4_SN_DW*4]); |
| 5107 | + u2SN = ((*addr) & WF_UWTBL_TID4_SN_MASK) >> WF_UWTBL_TID4_SN_SHIFT; |
| 5108 | + seq_printf(s, "\t%s:%u\n", "TID4_SN", u2SN); |
| 5109 | + |
| 5110 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_3_0__DW*4]); |
| 5111 | + u2SN = ((*addr) & WF_UWTBL_TID5_SN_3_0__MASK) >> |
| 5112 | + WF_UWTBL_TID5_SN_3_0__SHIFT; |
| 5113 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_11_4__DW*4]); |
| 5114 | + u2SN |= (((*addr) & WF_UWTBL_TID5_SN_11_4__MASK) >> |
| 5115 | + WF_UWTBL_TID5_SN_11_4__SHIFT) << 4; |
| 5116 | + seq_printf(s, "\t%s:%u\n", "TID5_SN", u2SN); |
| 5117 | + |
| 5118 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID6_SN_DW*4]); |
| 5119 | + u2SN = ((*addr) & WF_UWTBL_TID6_SN_MASK) >> WF_UWTBL_TID6_SN_SHIFT; |
| 5120 | + seq_printf(s, "\t%s:%u\n", "TID6_SN", u2SN); |
| 5121 | + |
| 5122 | + addr = (u32 *)&(uwtbl[WF_UWTBL_TID7_SN_DW*4]); |
| 5123 | + u2SN = ((*addr) & WF_UWTBL_TID7_SN_MASK) >> WF_UWTBL_TID7_SN_SHIFT; |
| 5124 | + seq_printf(s, "\t%s:%u\n", "TID7_SN", u2SN); |
| 5125 | + |
| 5126 | + addr = (u32 *)&(uwtbl[WF_UWTBL_COM_SN_DW*4]); |
| 5127 | + u2SN = ((*addr) & WF_UWTBL_COM_SN_MASK) >> WF_UWTBL_COM_SN_SHIFT; |
| 5128 | + seq_printf(s, "\t%s:%u\n", "COM_SN", u2SN); |
| 5129 | +} |
| 5130 | + |
| 5131 | +static void dump_key_table( |
| 5132 | + struct seq_file *s, |
| 5133 | + uint16_t keyloc0, |
| 5134 | + uint16_t keyloc1, |
| 5135 | + uint16_t keyloc2 |
| 5136 | +) |
| 5137 | +{ |
| 5138 | +#define ONE_KEY_ENTRY_LEN_IN_DW 8 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5139 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5140 | + u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0}; |
| 5141 | + uint16_t x; |
| 5142 | + |
| 5143 | + seq_printf(s, "\t\n"); |
| 5144 | + seq_printf(s, "\t%s:%d\n", "keyloc0", keyloc0); |
| 5145 | + if (keyloc0 != INVALID_KEY_ENTRY) { |
| 5146 | + |
| 5147 | + /* Don't swap below two lines, halWtblReadRaw will |
| 5148 | + * write new value WF_WTBLON_TOP_WDUCR_ADDR |
| 5149 | + */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5150 | + besra_wtbl_read_raw(dev, keyloc0, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5151 | + WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl); |
| 5152 | + seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%x\n", |
| 5153 | + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 5154 | + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| 5155 | + KEYTBL_IDX2BASE(keyloc0, 0)); |
| 5156 | + for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) { |
| 5157 | + seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n", |
| 5158 | + x, |
| 5159 | + keytbl[x * 4 + 3], |
| 5160 | + keytbl[x * 4 + 2], |
| 5161 | + keytbl[x * 4 + 1], |
| 5162 | + keytbl[x * 4]); |
| 5163 | + } |
| 5164 | + } |
| 5165 | + |
| 5166 | + seq_printf(s, "\t%s:%d\n", "keyloc1", keyloc1); |
| 5167 | + if (keyloc1 != INVALID_KEY_ENTRY) { |
| 5168 | + /* Don't swap below two lines, halWtblReadRaw will |
| 5169 | + * write new value WF_WTBLON_TOP_WDUCR_ADDR |
| 5170 | + */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5171 | + besra_wtbl_read_raw(dev, keyloc1, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5172 | + WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl); |
| 5173 | + seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%x\n", |
| 5174 | + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 5175 | + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| 5176 | + KEYTBL_IDX2BASE(keyloc1, 0)); |
| 5177 | + for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) { |
| 5178 | + seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n", |
| 5179 | + x, |
| 5180 | + keytbl[x * 4 + 3], |
| 5181 | + keytbl[x * 4 + 2], |
| 5182 | + keytbl[x * 4 + 1], |
| 5183 | + keytbl[x * 4]); |
| 5184 | + } |
| 5185 | + } |
| 5186 | + |
| 5187 | + seq_printf(s, "\t%s:%d\n", "keyloc2", keyloc2); |
| 5188 | + if (keyloc2 != INVALID_KEY_ENTRY) { |
| 5189 | + /* Don't swap below two lines, halWtblReadRaw will |
| 5190 | + * write new value WF_WTBLON_TOP_WDUCR_ADDR |
| 5191 | + */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5192 | + besra_wtbl_read_raw(dev, keyloc2, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5193 | + WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl); |
| 5194 | + seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%x\n", |
| 5195 | + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 5196 | + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| 5197 | + KEYTBL_IDX2BASE(keyloc2, 0)); |
| 5198 | + for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) { |
| 5199 | + seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n", |
| 5200 | + x, |
| 5201 | + keytbl[x * 4 + 3], |
| 5202 | + keytbl[x * 4 + 2], |
| 5203 | + keytbl[x * 4 + 1], |
| 5204 | + keytbl[x * 4]); |
| 5205 | + } |
| 5206 | + } |
| 5207 | +} |
| 5208 | + |
| 5209 | +static void parse_fmac_uwtbl_key_info(struct seq_file *s, u8 *uwtbl, u8 *lwtbl) |
| 5210 | +{ |
| 5211 | + u32 *addr = 0; |
| 5212 | + u32 dw_value = 0; |
| 5213 | + uint16_t keyloc0 = INVALID_KEY_ENTRY; |
| 5214 | + uint16_t keyloc1 = INVALID_KEY_ENTRY; |
| 5215 | + uint16_t keyloc2 = INVALID_KEY_ENTRY; |
| 5216 | + |
| 5217 | + /* UMAC WTBL DW 7 */ |
| 5218 | + seq_printf(s, "\t\n"); |
| 5219 | + seq_printf(s, "UWTBL key info\n"); |
| 5220 | + |
| 5221 | + addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC0_DW*4]); |
| 5222 | + dw_value = *addr; |
| 5223 | + keyloc0 = (dw_value & WF_UWTBL_KEY_LOC0_MASK) >> WF_UWTBL_KEY_LOC0_SHIFT; |
| 5224 | + keyloc1 = (dw_value & WF_UWTBL_KEY_LOC1_MASK) >> WF_UWTBL_KEY_LOC1_SHIFT; |
| 5225 | + |
| 5226 | + seq_printf(s, "\t%s:%u/%u\n", "Key Loc 0/1", keyloc0, keyloc1); |
| 5227 | + |
| 5228 | + /* UMAC WTBL DW 6 for BIGTK */ |
| 5229 | + if (is_wtbl_bigtk_exist(lwtbl) == true) { |
| 5230 | + keyloc2 = (dw_value & WF_UWTBL_KEY_LOC2_MASK) >> |
| 5231 | + WF_UWTBL_KEY_LOC2_SHIFT; |
| 5232 | + seq_printf(s, "\t%s:%u\n", "Key Loc 2", keyloc2); |
| 5233 | + } |
| 5234 | + |
| 5235 | + /* Parse KEY link */ |
| 5236 | + dump_key_table(s, keyloc0, keyloc1, keyloc2); |
| 5237 | +} |
| 5238 | + |
| 5239 | +static const struct berse_wtbl_parse WTBL_UMAC_DW8[] = { |
| 5240 | + {"UWTBL_WMM_Q", WF_UWTBL_WMM_Q_MASK, WF_UWTBL_WMM_Q_SHIFT, false}, |
| 5241 | + {"UWTBL_QOS", WF_UWTBL_QOS_MASK, NO_SHIFT_DEFINE, false}, |
| 5242 | + {"UWTBL_HT_VHT_HE", WF_UWTBL_HT_MASK, NO_SHIFT_DEFINE, false}, |
| 5243 | + {"UWTBL_HDRT_MODE", WF_UWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, true}, |
| 5244 | + {NULL,} |
| 5245 | +}; |
| 5246 | + |
| 5247 | +static void parse_fmac_uwtbl_msdu_info(struct seq_file *s, u8 *uwtbl) |
| 5248 | +{ |
| 5249 | + u32 *addr = 0; |
| 5250 | + u32 dw_value = 0; |
| 5251 | + u32 amsdu_len = 0; |
| 5252 | + u16 i = 0; |
| 5253 | + |
| 5254 | + /* UMAC WTBL DW 8 */ |
| 5255 | + seq_printf(s, "\t\n"); |
| 5256 | + seq_printf(s, "UWTBL DW8\n"); |
| 5257 | + |
| 5258 | + addr = (u32 *)&(uwtbl[WF_UWTBL_AMSDU_CFG_DW*4]); |
| 5259 | + dw_value = *addr; |
| 5260 | + |
| 5261 | + while (WTBL_UMAC_DW8[i].name) { |
| 5262 | + |
| 5263 | + if (WTBL_UMAC_DW8[i].shift == NO_SHIFT_DEFINE) |
| 5264 | + seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW8[i].name, |
| 5265 | + (dw_value & WTBL_UMAC_DW8[i].mask) ? 1 : 0); |
| 5266 | + else |
| 5267 | + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW8[i].name, |
| 5268 | + (dw_value & WTBL_UMAC_DW8[i].mask) >> |
| 5269 | + WTBL_UMAC_DW8[i].shift); |
| 5270 | + i++; |
| 5271 | + } |
| 5272 | + |
| 5273 | + /* UMAC WTBL DW 8 - AMSDU_CFG */ |
| 5274 | + seq_printf(s, "\t%s:%d\n", "HW AMSDU Enable", |
| 5275 | + (dw_value & WTBL_AMSDU_EN_MASK) ? 1 : 0); |
| 5276 | + |
| 5277 | + amsdu_len = (dw_value & WTBL_AMSDU_LEN_MASK) >> WTBL_AMSDU_LEN_OFFSET; |
| 5278 | + if (amsdu_len == 0) |
| 5279 | + seq_printf(s, "\t%s:invalid (WTBL value=0x%x)\n", "HW AMSDU Len", |
| 5280 | + amsdu_len); |
| 5281 | + else if (amsdu_len == 1) |
| 5282 | + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| 5283 | + 1, |
| 5284 | + 255, |
| 5285 | + amsdu_len); |
| 5286 | + else if (amsdu_len == 2) |
| 5287 | + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| 5288 | + 256, |
| 5289 | + 511, |
| 5290 | + amsdu_len); |
| 5291 | + else if (amsdu_len == 3) |
| 5292 | + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| 5293 | + 512, |
| 5294 | + 767, |
| 5295 | + amsdu_len); |
| 5296 | + else |
| 5297 | + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| 5298 | + 256 * (amsdu_len - 1), |
| 5299 | + 256 * (amsdu_len - 1) + 255, |
| 5300 | + amsdu_len); |
| 5301 | + |
| 5302 | + seq_printf(s, "\t%s:%lu (WTBL value=0x%lx)\n", "HW AMSDU Num", |
| 5303 | + ((dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET) + 1, |
| 5304 | + (dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET); |
| 5305 | +} |
| 5306 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5307 | +static int besra_wtbl_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5308 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5309 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5310 | + u8 lwtbl[LWTBL_LEN_IN_DW * 4] = {0}; |
| 5311 | + u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0}; |
| 5312 | + int x; |
| 5313 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5314 | + besra_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5315 | + LWTBL_LEN_IN_DW, lwtbl); |
| 5316 | + seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx); |
| 5317 | + seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n", |
| 5318 | + MT_DBG_WTBLON_TOP_WDUCR_ADDR, |
| 5319 | + mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR), |
| 5320 | + LWTBL_IDX2BASE(dev->wlan_idx, 0)); |
| 5321 | + for (x = 0; x < LWTBL_LEN_IN_DW; x++) { |
| 5322 | + seq_printf(s, "DW%02d: %02x %02x %02x %02x\n", |
| 5323 | + x, |
| 5324 | + lwtbl[x * 4 + 3], |
| 5325 | + lwtbl[x * 4 + 2], |
| 5326 | + lwtbl[x * 4 + 1], |
| 5327 | + lwtbl[x * 4]); |
| 5328 | + } |
| 5329 | + |
| 5330 | + /* Parse LWTBL */ |
| 5331 | + parse_fmac_lwtbl_dw0_1(s, lwtbl); |
| 5332 | + parse_fmac_lwtbl_dw2(s, lwtbl); |
| 5333 | + parse_fmac_lwtbl_dw3(s, lwtbl); |
| 5334 | + parse_fmac_lwtbl_dw4(s, lwtbl); |
| 5335 | + parse_fmac_lwtbl_dw5(s, lwtbl); |
| 5336 | + parse_fmac_lwtbl_dw6(s, lwtbl); |
| 5337 | + parse_fmac_lwtbl_dw7(s, lwtbl); |
| 5338 | + parse_fmac_lwtbl_dw8(s, lwtbl); |
| 5339 | + parse_fmac_lwtbl_dw9(s, lwtbl); |
| 5340 | + parse_fmac_lwtbl_dw10(s, lwtbl); |
| 5341 | + parse_fmac_lwtbl_dw11(s, lwtbl); |
| 5342 | + parse_fmac_lwtbl_dw12(s, lwtbl); |
| 5343 | + parse_fmac_lwtbl_dw13(s, lwtbl); |
| 5344 | + parse_fmac_lwtbl_dw14(s, lwtbl); |
| 5345 | + parse_fmac_lwtbl_mlo_info(s, lwtbl); |
| 5346 | + parse_fmac_lwtbl_dw31(s, lwtbl); |
| 5347 | + parse_fmac_lwtbl_dw32(s, lwtbl); |
| 5348 | + parse_fmac_lwtbl_rx_stats(s, lwtbl); |
| 5349 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5350 | + besra_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5351 | + UWTBL_LEN_IN_DW, uwtbl); |
| 5352 | + seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx); |
| 5353 | + seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n", |
| 5354 | + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| 5355 | + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| 5356 | + UWTBL_IDX2BASE(dev->wlan_idx, 0)); |
| 5357 | + for (x = 0; x < UWTBL_LEN_IN_DW; x++) { |
| 5358 | + seq_printf(s, "DW%02d: %02x %02x %02x %02x\n", |
| 5359 | + x, |
| 5360 | + uwtbl[x * 4 + 3], |
| 5361 | + uwtbl[x * 4 + 2], |
| 5362 | + uwtbl[x * 4 + 1], |
| 5363 | + uwtbl[x * 4]); |
| 5364 | + } |
| 5365 | + |
| 5366 | + /* Parse UWTBL */ |
| 5367 | + parse_fmac_uwtbl_mlo_info(s, uwtbl); |
| 5368 | + parse_fmac_uwtbl_pn(s, uwtbl, lwtbl); |
| 5369 | + parse_fmac_uwtbl_sn(s, uwtbl); |
| 5370 | + parse_fmac_uwtbl_key_info(s, uwtbl, lwtbl); |
| 5371 | + parse_fmac_uwtbl_msdu_info(s, uwtbl); |
| 5372 | + |
| 5373 | + return 0; |
| 5374 | +} |
| 5375 | + |
| 5376 | +/* dma info dump */ |
| 5377 | +const struct queue_desc mt7902_tx_ring_layout[] = { |
| 5378 | + { |
| 5379 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR, |
| 5380 | + .ring_size = 2048, |
| 5381 | + .ring_info = "band0 TXD" |
| 5382 | + }, |
| 5383 | + { |
| 5384 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR, |
| 5385 | + .ring_size = 2048, |
| 5386 | + .ring_info = "band1 TXD" |
| 5387 | + }, |
| 5388 | + { |
| 5389 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR, |
| 5390 | + .ring_size = 2048, |
| 5391 | + .ring_info = "band2 TXD" |
| 5392 | + }, |
| 5393 | + { |
| 5394 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR, |
| 5395 | + .ring_size = 128, |
| 5396 | + .ring_info = "FWDL" |
| 5397 | + }, |
| 5398 | + { |
| 5399 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR, |
| 5400 | + .ring_size = 256, |
| 5401 | + .ring_info = "cmd to WM" |
| 5402 | + }, |
| 5403 | + { |
| 5404 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR, |
| 5405 | + .ring_size = 256, |
| 5406 | + .ring_info = "cmd to WA" |
| 5407 | + } |
| 5408 | +}; |
| 5409 | + |
| 5410 | +const struct queue_desc mt7902_rx_ring_layout[] = { |
| 5411 | + { |
| 5412 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR, |
| 5413 | + .ring_size = 1536, |
| 5414 | + .ring_info = "band0 RX data" |
| 5415 | + }, |
| 5416 | + { |
| 5417 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR, |
| 5418 | + .ring_size = 1536, |
| 5419 | + .ring_info = "band1 RX data" |
| 5420 | + }, |
| 5421 | + { |
| 5422 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR, |
| 5423 | + .ring_size = 1536, |
| 5424 | + .ring_info = "band2 RX data" |
| 5425 | + }, |
| 5426 | + { |
| 5427 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR, |
| 5428 | + .ring_size = 512, |
| 5429 | + .ring_info = "event from WM" |
| 5430 | + }, |
| 5431 | + { |
| 5432 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR, |
| 5433 | + .ring_size = 1024, |
| 5434 | + .ring_info = "event from WA" |
| 5435 | + }, |
| 5436 | + { |
| 5437 | + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR, |
| 5438 | + .ring_size = 1024, |
| 5439 | + .ring_info = "band0/1/2 tx free done" |
| 5440 | + }, |
| 5441 | +}; |
| 5442 | + |
| 5443 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5444 | +dump_dma_tx_ring_info(struct seq_file *s, struct besra_dev *dev, char *str1, char *str2, u32 ring_base) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5445 | +{ |
| 5446 | + u32 base, cnt, cidx, didx, queue_cnt; |
| 5447 | + |
| 5448 | + base= mt76_rr(dev, ring_base); |
| 5449 | + cnt = mt76_rr(dev, ring_base + 4); |
| 5450 | + cidx = mt76_rr(dev, ring_base + 8); |
| 5451 | + didx = mt76_rr(dev, ring_base + 12); |
| 5452 | + queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt); |
| 5453 | + |
| 5454 | + seq_printf(s, "%20s %6s %10x %10x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt); |
| 5455 | +} |
| 5456 | + |
| 5457 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5458 | +dump_dma_rx_ring_info(struct seq_file *s, struct besra_dev *dev, char *str1, char *str2, u32 ring_base) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5459 | +{ |
| 5460 | + u32 base, cnt, cidx, didx, queue_cnt; |
| 5461 | + |
| 5462 | + base= mt76_rr(dev, ring_base); |
| 5463 | + cnt = mt76_rr(dev, ring_base + 4); |
| 5464 | + cidx = mt76_rr(dev, ring_base + 8); |
| 5465 | + didx = mt76_rr(dev, ring_base + 12); |
| 5466 | + queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1); |
| 5467 | + |
| 5468 | + seq_printf(s, "%20s %6s %10x %10x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt); |
| 5469 | +} |
| 5470 | + |
| 5471 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5472 | +besra_show_dma_info(struct seq_file *s, struct besra_dev *dev) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5473 | +{ |
| 5474 | + u32 sys_ctrl[10]; |
| 5475 | + |
| 5476 | + /* HOST DMA information */ |
| 5477 | + sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR); |
| 5478 | + sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR); |
| 5479 | + sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR); |
| 5480 | + |
| 5481 | + seq_printf(s, "HOST_DMA Configuration\n"); |
| 5482 | + seq_printf(s, "%10s %10s %10s %10s %10s %10s\n", |
| 5483 | + "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy"); |
| 5484 | + seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n", |
| 5485 | + "DMA0", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2], |
| 5486 | + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) |
| 5487 | + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT, |
| 5488 | + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) |
| 5489 | + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT, |
| 5490 | + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) |
| 5491 | + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT, |
| 5492 | + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) |
| 5493 | + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT); |
| 5494 | + |
| 5495 | + seq_printf(s, "HOST_DMA0 Ring Configuration\n"); |
| 5496 | + seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n", |
| 5497 | + "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| 5498 | + dump_dma_tx_ring_info(s, dev, "T0:TXD0(H2MAC)", "STA", |
| 5499 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR); |
| 5500 | + dump_dma_tx_ring_info(s, dev, "T1:TXD1(H2MAC)", "STA", |
| 5501 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR); |
| 5502 | + dump_dma_tx_ring_info(s, dev, "T2:TXD2(H2MAC)", "STA", |
| 5503 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR); |
| 5504 | + dump_dma_tx_ring_info(s, dev, "T3:", "STA", |
| 5505 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR); |
| 5506 | + dump_dma_tx_ring_info(s, dev, "T4:", "STA", |
| 5507 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR); |
| 5508 | + dump_dma_tx_ring_info(s, dev, "T5:", "STA", |
| 5509 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR); |
| 5510 | + dump_dma_tx_ring_info(s, dev, "T6:", "STA", |
| 5511 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR); |
| 5512 | + dump_dma_tx_ring_info(s, dev, "T16:FWDL", "Both", |
| 5513 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR); |
| 5514 | + dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", "Both", |
| 5515 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR); |
| 5516 | + dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", "AP", |
| 5517 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR); |
| 5518 | + dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", "AP", |
| 5519 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR); |
| 5520 | + dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", "AP", |
| 5521 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR); |
| 5522 | + dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP", |
| 5523 | + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR); |
| 5524 | + dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", "Both", |
| 5525 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR); |
| 5526 | + dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", "AP", |
| 5527 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR); |
| 5528 | + dump_dma_rx_ring_info(s, dev, "R2:TxDone0(WA2H)", "AP", |
| 5529 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR); |
| 5530 | + dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP", |
| 5531 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR); |
| 5532 | + dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", "Both", |
| 5533 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR); |
| 5534 | + dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both", |
| 5535 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR); |
| 5536 | + dump_dma_rx_ring_info(s, dev, "R6:TxDone0(MAC2H)", "STA", |
| 5537 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR); |
| 5538 | + dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "STA", |
| 5539 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR); |
| 5540 | + dump_dma_rx_ring_info(s, dev, "R8:Data2(MAC2H)", "Both", |
| 5541 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR); |
| 5542 | + dump_dma_rx_ring_info(s, dev, "R9:TxDone2(MAC2H)", "STA", |
| 5543 | + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR); |
| 5544 | + |
| 5545 | + /* MCU DMA information */ |
| 5546 | + sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR); |
| 5547 | + sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR); |
| 5548 | + sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR); |
| 5549 | + |
| 5550 | + seq_printf(s, "MCU_DMA Configuration\n"); |
| 5551 | + seq_printf(s, "%10s %10s %10s %10s %10s %10s\n", |
| 5552 | + "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy"); |
| 5553 | + seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n", |
| 5554 | + "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0], |
| 5555 | + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) |
| 5556 | + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT, |
| 5557 | + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) |
| 5558 | + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT, |
| 5559 | + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) |
| 5560 | + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT, |
| 5561 | + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) |
| 5562 | + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT); |
| 5563 | + |
| 5564 | + seq_printf(s, "MCU_DMA0 Ring Configuration\n"); |
| 5565 | + seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n", |
| 5566 | + "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| 5567 | + dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", "Both", |
| 5568 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR); |
| 5569 | + dump_dma_tx_ring_info(s, dev, "T1:Event(WA2H)", "AP", |
| 5570 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR); |
| 5571 | + dump_dma_tx_ring_info(s, dev, "T2:TxDone0(WA2H)", "AP", |
| 5572 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR); |
| 5573 | + dump_dma_tx_ring_info(s, dev, "T3:TxDone1(WA2H)", "AP", |
| 5574 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR); |
| 5575 | + dump_dma_tx_ring_info(s, dev, "T4:TXD(WM2MAC)", "Both", |
| 5576 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR); |
| 5577 | + dump_dma_tx_ring_info(s, dev, "T5:TXCMD(WM2MAC)", "Both", |
| 5578 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR); |
| 5579 | + dump_dma_tx_ring_info(s, dev, "T6:TXD(WA2MAC)", "AP", |
| 5580 | + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR); |
| 5581 | + dump_dma_rx_ring_info(s, dev, "R0:FWDL", "Both", |
| 5582 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR); |
| 5583 | + dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", "Both", |
| 5584 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR); |
| 5585 | + dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", "AP", |
| 5586 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR); |
| 5587 | + dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", "AP", |
| 5588 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR); |
| 5589 | + dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", "AP", |
| 5590 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR); |
| 5591 | + dump_dma_rx_ring_info(s, dev, "R5:Data0(MAC2WM)", "Both", |
| 5592 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR); |
| 5593 | + dump_dma_rx_ring_info(s, dev, "R6:TxDone(MAC2WM)", "Both", |
| 5594 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR); |
| 5595 | + dump_dma_rx_ring_info(s, dev, "R7:SPL/RPT(MAC2WM)", "Both", |
| 5596 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR); |
| 5597 | + dump_dma_rx_ring_info(s, dev, "R8:TxDone(MAC2WA)", "AP", |
| 5598 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR); |
| 5599 | + dump_dma_rx_ring_info(s, dev, "R9:Data1(MAC2WM)", "Both", |
| 5600 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR); |
| 5601 | + dump_dma_rx_ring_info(s, dev, "R10:TXD2(H2WA)", "AP", |
| 5602 | + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR); |
| 5603 | + |
| 5604 | + /* MEM DMA information */ |
| 5605 | + sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR); |
| 5606 | + sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR); |
| 5607 | + sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR); |
| 5608 | + |
| 5609 | + seq_printf(s, "MEM_DMA Configuration\n"); |
| 5610 | + seq_printf(s, "%10s %10s %10s %10s %10s %10s\n", |
| 5611 | + "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy"); |
| 5612 | + seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n", |
| 5613 | + "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0], |
| 5614 | + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) |
| 5615 | + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT, |
| 5616 | + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) |
| 5617 | + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT, |
| 5618 | + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) |
| 5619 | + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT, |
| 5620 | + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) |
| 5621 | + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT); |
| 5622 | + |
| 5623 | + seq_printf(s, "MEM_DMA Ring Configuration\n"); |
| 5624 | + seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n", |
| 5625 | + "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| 5626 | + dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", "AP", |
| 5627 | + WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR); |
| 5628 | + dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", "AP", |
| 5629 | + WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR); |
| 5630 | + dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", "AP", |
| 5631 | + WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR); |
| 5632 | + dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", "AP", |
| 5633 | + WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR); |
| 5634 | +} |
| 5635 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5636 | +static int besra_trinfo_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5637 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5638 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5639 | + const struct queue_desc *tx_ring_layout; |
| 5640 | + const struct queue_desc *rx_ring_layout; |
| 5641 | + u32 tx_ring_num, rx_ring_num; |
| 5642 | + u32 tbase[10], tcnt[10]; |
| 5643 | + u32 tcidx[10], tdidx[10]; |
| 5644 | + u32 rbase[10], rcnt[10]; |
| 5645 | + u32 rcidx[10], rdidx[10]; |
| 5646 | + int idx; |
| 5647 | + |
| 5648 | + tx_ring_layout = &mt7902_tx_ring_layout[0]; |
| 5649 | + rx_ring_layout = &mt7902_rx_ring_layout[0]; |
| 5650 | + tx_ring_num = ARRAY_SIZE(mt7902_tx_ring_layout); |
| 5651 | + rx_ring_num = ARRAY_SIZE(mt7902_rx_ring_layout); |
| 5652 | + |
| 5653 | + for (idx = 0; idx < tx_ring_num; idx++) { |
| 5654 | + tbase[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base); |
| 5655 | + tcnt[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x04); |
| 5656 | + tcidx[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x08); |
| 5657 | + tdidx[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x0c); |
| 5658 | + } |
| 5659 | + |
| 5660 | + for (idx = 0; idx < rx_ring_num; idx++) { |
| 5661 | + rbase[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base); |
| 5662 | + rcnt[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x04); |
| 5663 | + rcidx[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x08); |
| 5664 | + rdidx[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x0c); |
| 5665 | + } |
| 5666 | + |
| 5667 | + seq_printf(s, "=================================================\n"); |
| 5668 | + seq_printf(s, "TxRing Configuration\n"); |
| 5669 | + seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n", |
| 5670 | + "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX", |
| 5671 | + "QCnt"); |
| 5672 | + for (idx = 0; idx < tx_ring_num; idx++) { |
| 5673 | + u32 queue_cnt; |
| 5674 | + |
| 5675 | + queue_cnt = (tcidx[idx] >= tdidx[idx]) ? |
| 5676 | + (tcidx[idx] - tdidx[idx]) : |
| 5677 | + (tcidx[idx] - tdidx[idx] + tcnt[idx]); |
| 5678 | + seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n", |
| 5679 | + idx, tx_ring_layout[idx].ring_info, |
| 5680 | + tx_ring_layout[idx].hw_desc_base, tbase[idx], |
| 5681 | + tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt); |
| 5682 | + } |
| 5683 | + |
| 5684 | + seq_printf(s, "RxRing Configuration\n"); |
| 5685 | + seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n", |
| 5686 | + "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX", |
| 5687 | + "QCnt"); |
| 5688 | + |
| 5689 | + for (idx = 0; idx < rx_ring_num; idx++) { |
| 5690 | + u32 queue_cnt; |
| 5691 | + |
| 5692 | + queue_cnt = (rdidx[idx] > rcidx[idx]) ? |
| 5693 | + (rdidx[idx] - rcidx[idx] - 1) : |
| 5694 | + (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1); |
| 5695 | + seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n", |
| 5696 | + idx, rx_ring_layout[idx].ring_info, |
| 5697 | + rx_ring_layout[idx].hw_desc_base, |
| 5698 | + rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt); |
| 5699 | + } |
| 5700 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5701 | + besra_show_dma_info(s, dev); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5702 | + return 0; |
| 5703 | +} |
| 5704 | + |
| 5705 | +/* MIB INFO */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5706 | +static int besra_mibinfo_read_per_band(struct seq_file *s, int band_idx) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5707 | +{ |
| 5708 | +#define BSS_NUM 4 |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5709 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5710 | + u8 bss_nums = BSS_NUM; |
| 5711 | + u32 idx; |
| 5712 | + u32 mac_val, band_offset = 0, band_offset_umib = 0; |
| 5713 | + u32 msdr6, msdr9, msdr18; |
| 5714 | + u32 rvsr0, rscr26, rscr35, mctr5, mctr6, msr0, msr1, msr2; |
| 5715 | + u32 tbcr0, tbcr1, tbcr2, tbcr3, tbcr4; |
| 5716 | + u32 btscr[7]; |
| 5717 | + u32 tdrcr[5]; |
| 5718 | + u32 mbtocr[16], mbtbcr[16], mbrocr[16], mbrbcr[16]; |
| 5719 | + u32 btcr, btbcr, brocr, brbcr, btdcr, brdcr; |
| 5720 | + u32 mu_cnt[5]; |
| 5721 | + u32 ampdu_cnt[3]; |
| 5722 | + u64 per; |
| 5723 | + |
| 5724 | + switch (band_idx) { |
| 5725 | + case 0: |
| 5726 | + band_offset = 0; |
| 5727 | + band_offset_umib = 0; |
| 5728 | + break; |
| 5729 | + case 1: |
| 5730 | + band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| 5731 | + band_offset_umib = WF_UMIB_TOP_B1BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR; |
| 5732 | + break; |
| 5733 | + case 2: |
| 5734 | + band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| 5735 | + band_offset_umib = WF_UMIB_TOP_B2BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR; |
| 5736 | + break; |
| 5737 | + default: |
| 5738 | + return true; |
| 5739 | + } |
| 5740 | + |
| 5741 | + seq_printf(s, "Band %d MIB Status\n", band_idx); |
| 5742 | + seq_printf(s, "===============================\n"); |
| 5743 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset); |
| 5744 | + seq_printf(s, "MIB Status Control=0x%x\n", mac_val); |
| 5745 | + |
| 5746 | + msdr6 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset); |
| 5747 | + rvsr0 = mt76_rr(dev, BN0_WF_MIB_TOP_RVSR0_ADDR + band_offset); |
| 5748 | + rscr35 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR35_ADDR + band_offset); |
| 5749 | + msdr9 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset); |
| 5750 | + rscr26 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR26_ADDR + band_offset); |
| 5751 | + mctr5 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR5_ADDR + band_offset); |
| 5752 | + mctr6 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR6_ADDR + band_offset); |
| 5753 | + msdr18 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset); |
| 5754 | + msr0 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR0_ADDR + band_offset); |
| 5755 | + msr1 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR1_ADDR + band_offset); |
| 5756 | + msr2 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR2_ADDR + band_offset); |
| 5757 | + ampdu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR0_ADDR + band_offset); |
| 5758 | + ampdu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR3_ADDR + band_offset); |
| 5759 | + ampdu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR4_ADDR + band_offset); |
| 5760 | + ampdu_cnt[1] &= BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK; |
| 5761 | + ampdu_cnt[2] &= BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK; |
| 5762 | + |
| 5763 | + seq_printf(s, "===Phy/Timing Related Counters===\n"); |
| 5764 | + seq_printf(s, "\tChannelIdleCnt=0x%x\n", |
| 5765 | + msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK); |
| 5766 | + seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", |
| 5767 | + msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK); |
| 5768 | + seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n", |
| 5769 | + rscr26 & BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK); |
| 5770 | + seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x", |
| 5771 | + msr0 & BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK, |
| 5772 | + msr1 & BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK); |
| 5773 | + seq_printf(s, ", OFDM_GREEN_MDRDY_TIME=0x%x\n", |
| 5774 | + msr2 & BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK); |
| 5775 | + seq_printf(s, "\tPrim CCA Time=0x%x\n", |
| 5776 | + mctr5 & BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK); |
| 5777 | + seq_printf(s, "\tSec CCA Time=0x%x\n", |
| 5778 | + mctr6 & BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK); |
| 5779 | + seq_printf(s, "\tPrim ED Time=0x%x\n", |
| 5780 | + msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK); |
| 5781 | + |
| 5782 | + seq_printf(s, "===Tx Related Counters(Generic)===\n"); |
| 5783 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR18_ADDR + band_offset); |
| 5784 | + dev->dbg.bcn_total_cnt[band_idx] += |
| 5785 | + (mac_val & BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK); |
| 5786 | + seq_printf(s, "\tBeaconTxCnt=0x%x\n", dev->dbg.bcn_total_cnt[band_idx]); |
| 5787 | + dev->dbg.bcn_total_cnt[band_idx] = 0; |
| 5788 | + |
| 5789 | + tbcr0 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR0_ADDR + band_offset); |
| 5790 | + seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", |
| 5791 | + tbcr0 & BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK); |
| 5792 | + tbcr1 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR1_ADDR + band_offset); |
| 5793 | + seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", |
| 5794 | + tbcr1 & BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK); |
| 5795 | + tbcr2 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR2_ADDR + band_offset); |
| 5796 | + seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", |
| 5797 | + tbcr2 & BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK); |
| 5798 | + tbcr3 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR3_ADDR + band_offset); |
| 5799 | + seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", |
| 5800 | + tbcr3 & BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK); |
| 5801 | + tbcr4 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR4_ADDR + band_offset); |
| 5802 | + seq_printf(s, "\tTx 320MHz Cnt=0x%x\n", |
| 5803 | + tbcr4 & BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK); |
| 5804 | + seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]); |
| 5805 | + seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]); |
| 5806 | + seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]); |
| 5807 | + per = (ampdu_cnt[2] == 0 ? |
| 5808 | + 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]); |
| 5809 | + seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10); |
| 5810 | + |
| 5811 | + seq_printf(s, "===MU Related Counters===\n"); |
| 5812 | + mu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSCR2_ADDR + band_offset); |
| 5813 | + mu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR5_ADDR + band_offset); |
| 5814 | + mu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR6_ADDR + band_offset); |
| 5815 | + mu_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR8_ADDR + band_offset); |
| 5816 | + mu_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR7_ADDR + band_offset); |
| 5817 | + |
| 5818 | + seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", |
| 5819 | + mu_cnt[0] & BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK); |
| 5820 | + seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]); |
| 5821 | + seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]); |
| 5822 | + seq_printf(s, "\tMU_TO_MU_FAIL_PPDU_COUNT=0x%x\n", mu_cnt[3]); |
| 5823 | + seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]); |
| 5824 | + |
| 5825 | + seq_printf(s, "===Rx Related Counters(Generic)===\n"); |
| 5826 | + seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", |
| 5827 | + rvsr0 & BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK); |
| 5828 | + seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", |
| 5829 | + rscr35 & BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK); |
| 5830 | + |
| 5831 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR1_ADDR + band_offset); |
| 5832 | + seq_printf(s, "\tRxFCSErrCnt=0x%x\n", |
| 5833 | + (mac_val & BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK)); |
| 5834 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR33_ADDR + band_offset); |
| 5835 | + seq_printf(s, "\tRxFifoFullCnt=0x%x\n", |
| 5836 | + (mac_val & BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK)); |
| 5837 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR36_ADDR + band_offset); |
| 5838 | + seq_printf(s, "\tRxLenMismatch=0x%x\n", |
| 5839 | + (mac_val & BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK)); |
| 5840 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR31_ADDR + band_offset); |
| 5841 | + seq_printf(s, "\tRxMPDUCnt=0x%x\n", |
| 5842 | + (mac_val & BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK)); |
| 5843 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR27_ADDR + band_offset); |
| 5844 | + seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val); |
| 5845 | + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR28_ADDR + band_offset); |
| 5846 | + seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val); |
| 5847 | + |
| 5848 | + |
| 5849 | + /* Per-BSS T/RX Counters */ |
| 5850 | + seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n"); |
| 5851 | + seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxOkCnt/DataCnt RxByteCnt\n"); |
| 5852 | + for (idx = 0; idx < bss_nums; idx++) { |
| 5853 | + btcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTCR_ADDR + band_offset + idx * 4); |
| 5854 | + btdcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + idx * 4); |
| 5855 | + btbcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + idx * 4); |
| 5856 | + |
| 5857 | + brocr = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + idx * 4); |
| 5858 | + brdcr = mt76_rr(dev, WF_UMIB_TOP_B0BRDCR_ADDR + band_offset_umib + idx * 4); |
| 5859 | + brbcr = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + idx * 4); |
| 5860 | + |
| 5861 | + seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n", |
| 5862 | + idx, btcr, btdcr, btbcr, brocr, brdcr, brbcr); |
| 5863 | + } |
| 5864 | + |
| 5865 | + seq_printf(s, "===Per-BSS Related MIB Counters===\n"); |
| 5866 | + seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n"); |
| 5867 | + |
| 5868 | + /* Per-BSS TX Status */ |
| 5869 | + for (idx = 0; idx < bss_nums; idx++) { |
| 5870 | + btscr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR5_ADDR + band_offset + idx * 4); |
| 5871 | + btscr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR6_ADDR + band_offset + idx * 4); |
| 5872 | + btscr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR0_ADDR + band_offset + idx * 4); |
| 5873 | + btscr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR1_ADDR + band_offset + idx * 4); |
| 5874 | + btscr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR2_ADDR + band_offset + idx * 4); |
| 5875 | + btscr[5] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR3_ADDR + band_offset + idx * 4); |
| 5876 | + btscr[6] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR4_ADDR + band_offset + idx * 4); |
| 5877 | + |
| 5878 | + seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n", |
| 5879 | + idx, (btscr[0] & BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK), |
| 5880 | + (btscr[1] & BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK), |
| 5881 | + (btscr[2] & BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK), |
| 5882 | + (btscr[3] & BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK), |
| 5883 | + (btscr[4] & BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK), |
| 5884 | + (btscr[5] & BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK), |
| 5885 | + (btscr[6] & BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK)); |
| 5886 | + } |
| 5887 | + |
| 5888 | + /* Dummy delimiter insertion result */ |
| 5889 | + seq_printf(s, "===Dummy delimiter insertion result===\n"); |
| 5890 | + tdrcr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR0_ADDR + band_offset); |
| 5891 | + tdrcr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR1_ADDR + band_offset); |
| 5892 | + tdrcr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR2_ADDR + band_offset); |
| 5893 | + tdrcr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR3_ADDR + band_offset); |
| 5894 | + tdrcr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR4_ADDR + band_offset); |
| 5895 | + |
| 5896 | + seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n", |
| 5897 | + tdrcr[0], |
| 5898 | + tdrcr[1], |
| 5899 | + tdrcr[2], |
| 5900 | + tdrcr[3], |
| 5901 | + tdrcr[4]); |
| 5902 | + |
| 5903 | + /* Per-MBSS T/RX Counters */ |
| 5904 | + seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n"); |
| 5905 | + seq_printf(s, "MBSSIdx TxOkCnt TxByteCnt RxOkCnt RxByteCnt\n"); |
| 5906 | + |
| 5907 | + for (idx = 0; idx < 16; idx++) { |
| 5908 | + mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (bss_nums + idx) * 4); |
| 5909 | + mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (bss_nums + idx) * 4); |
| 5910 | + |
| 5911 | + mbrocr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + (bss_nums + idx) * 4); |
| 5912 | + mbrbcr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + (bss_nums + idx) * 4); |
| 5913 | + } |
| 5914 | + |
| 5915 | + for (idx = 0; idx < 16; idx++) { |
| 5916 | + seq_printf(s, "%d\t 0x%x\t 0x%x \t 0x%x \t 0x%x\n", |
| 5917 | + idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]); |
| 5918 | + } |
| 5919 | + |
| 5920 | + return 0; |
| 5921 | +} |
| 5922 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5923 | +static int besra_mibinfo_band0(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5924 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5925 | + besra_mibinfo_read_per_band(s, MT_BAND0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5926 | + return 0; |
| 5927 | +} |
| 5928 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5929 | +static int besra_mibinfo_band1(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5930 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5931 | + besra_mibinfo_read_per_band(s, MT_BAND1); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5932 | + return 0; |
| 5933 | +} |
| 5934 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5935 | +static int besra_mibinfo_band2(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5936 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5937 | + besra_mibinfo_read_per_band(s, MT_BAND2); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5938 | + return 0; |
| 5939 | +} |
| 5940 | + |
| 5941 | +//bmac dump txp |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 5942 | +void besra_dump_bmac_txp_info(struct besra_dev *dev, __le32 *txp) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 5943 | +{ |
| 5944 | + int i, j = 0; |
| 5945 | + u32 dw; |
| 5946 | + |
| 5947 | + printk("txp raw data: size=%d\n", HIF_TXP_V2_SIZE); |
| 5948 | + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txp, HIF_TXP_V2_SIZE, false); |
| 5949 | + |
| 5950 | + printk("BMAC_TXP Fields:\n"); |
| 5951 | + |
| 5952 | + /* dw0 */ |
| 5953 | + dw = le32_to_cpu(txp[0]); |
| 5954 | + printk("HIF_TXP_PRIORITY = %d\n", |
| 5955 | + GET_FIELD(HIF_TXP_PRIORITY, dw)); |
| 5956 | + printk("HIF_TXP_FIXED_RATE = %d\n", |
| 5957 | + GET_FIELD(HIF_TXP_FIXED_RATE, dw)); |
| 5958 | + printk("HIF_TXP_TCP = %d\n", |
| 5959 | + GET_FIELD(HIF_TXP_TCP, dw)); |
| 5960 | + printk("HIF_TXP_NON_CIPHER = %d\n", |
| 5961 | + GET_FIELD(HIF_TXP_NON_CIPHER, dw)); |
| 5962 | + printk("HIF_TXP_VLAN = %d\n", |
| 5963 | + GET_FIELD(HIF_TXP_VLAN, dw)); |
| 5964 | + printk("HIF_TXP_BC_MC_FLAG = %d\n", |
| 5965 | + GET_FIELD(HIF_TXP_BC_MC_FLAG, dw)); |
| 5966 | + printk("HIF_TXP_FR_HOST = %d\n", |
| 5967 | + GET_FIELD(HIF_TXP_FR_HOST, dw)); |
| 5968 | + printk("HIF_TXP_ETYPE = %d\n", |
| 5969 | + GET_FIELD(HIF_TXP_ETYPE, dw)); |
| 5970 | + printk("HIF_TXP_TXP_AMSDU = %d\n", |
| 5971 | + GET_FIELD(HIF_TXP_TXP_AMSDU, dw)); |
| 5972 | + printk("HIF_TXP_TXP_MC_CLONE = %d\n", |
| 5973 | + GET_FIELD(HIF_TXP_TXP_MC_CLONE, dw)); |
| 5974 | + printk("HIF_TXP_TOKEN_ID = %d\n", |
| 5975 | + GET_FIELD(HIF_TXP_TOKEN_ID, dw)); |
| 5976 | + |
| 5977 | + /* dw1 */ |
| 5978 | + dw = le32_to_cpu(txp[1]); |
| 5979 | + printk("HIF_TXP_BSS_IDX = %d\n", |
| 5980 | + GET_FIELD(HIF_TXP_BSS_IDX, dw)); |
| 5981 | + printk("HIF_TXP_USER_PRIORITY = %d\n", |
| 5982 | + GET_FIELD(HIF_TXP_USER_PRIORITY, dw)); |
| 5983 | + printk("HIF_TXP_BUF_NUM = %d\n", |
| 5984 | + GET_FIELD(HIF_TXP_BUF_NUM, dw)); |
| 5985 | + printk("HIF_TXP_MSDU_CNT = %d\n", |
| 5986 | + GET_FIELD(HIF_TXP_MSDU_CNT, dw)); |
| 5987 | + printk("HIF_TXP_SRC = %d\n", |
| 5988 | + GET_FIELD(HIF_TXP_SRC, dw)); |
| 5989 | + |
| 5990 | + /* dw2 */ |
| 5991 | + dw = le32_to_cpu(txp[2]); |
| 5992 | + printk("HIF_TXP_ETH_TYPE(network-endian) = 0x%x\n", |
| 5993 | + GET_FIELD(HIF_TXP_ETH_TYPE, dw)); |
| 5994 | + printk("HIF_TXP_WLAN_IDX = %d\n", |
| 5995 | + GET_FIELD(HIF_TXP_WLAN_IDX, dw)); |
| 5996 | + |
| 5997 | + /* dw3 */ |
| 5998 | + dw = le32_to_cpu(txp[3]); |
| 5999 | + printk("HIF_TXP_PPE_INFO = 0x%x\n", |
| 6000 | + GET_FIELD(HIF_TXP_PPE_INFO, dw)); |
| 6001 | + |
| 6002 | + for (i = 0; i < 13; i++) { |
| 6003 | + if (i % 2 == 0) { |
| 6004 | + printk("HIF_TXP_BUF_PTR%d_L = 0x%x\n", |
| 6005 | + i, GET_FIELD(HIF_TXP_BUF_PTR0_L, |
| 6006 | + le32_to_cpu(txp[4 + j]))); |
| 6007 | + j++; |
| 6008 | + printk("HIF_TXP_BUF_LEN%d = %d\n", |
| 6009 | + i, GET_FIELD(HIF_TXP_BUF_LEN0, le32_to_cpu(txp[4 + j]))); |
| 6010 | + printk("HIF_TXP_BUF_PTR%d_H = 0x%x\n", |
| 6011 | + i, GET_FIELD(HIF_TXP_BUF_PTR0_H, le32_to_cpu(txp[4 + j]))); |
| 6012 | + if (i <= 10) { |
| 6013 | + printk("HIF_TXP_BUF_LEN%d = %d\n", |
| 6014 | + i + 1, GET_FIELD(HIF_TXP_BUF_LEN1, le32_to_cpu(txp[4 + j]))); |
| 6015 | + printk("HIF_TXP_BUF_PTR%d_H = 0x%x\n", |
| 6016 | + i + 1, GET_FIELD(HIF_TXP_BUF_PTR1_H, le32_to_cpu(txp[4 + j]))); |
| 6017 | + } |
| 6018 | + j++; |
| 6019 | + } else { |
| 6020 | + printk("HIF_TXP_BUF_PTR%d_L = 0x%x\n", |
| 6021 | + i, GET_FIELD(HIF_TXP_BUF_PTR1_L, |
| 6022 | + le32_to_cpu(txp[4 + j]))); |
| 6023 | + j++; |
| 6024 | + } |
| 6025 | + } |
| 6026 | + |
| 6027 | + printk("ml = 0x%x\n", |
| 6028 | + GET_FIELD(HIF_TXP_ML, le32_to_cpu(txp[23]))); |
| 6029 | +} |
| 6030 | + |
| 6031 | +/* bmac txd dump */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6032 | +void besra_dump_bmac_txd_info(struct besra_dev *dev, __le32 *txd, bool dump_txp) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6033 | +{ |
| 6034 | + /* dump stop */ |
| 6035 | + if (!dev->dbg.txd_read_cnt) |
| 6036 | + return; |
| 6037 | + |
| 6038 | + /* force dump */ |
| 6039 | + if (dev->dbg.txd_read_cnt > 8) |
| 6040 | + dev->dbg.txd_read_cnt = 8; |
| 6041 | + |
| 6042 | + /* dump txd_read_cnt times */ |
| 6043 | + if (dev->dbg.txd_read_cnt != 8) |
| 6044 | + dev->dbg.txd_read_cnt--; |
| 6045 | + |
| 6046 | + printk("txd raw data: size=%d\n", MT_TXD_SIZE); |
| 6047 | + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txd, MT_TXD_SIZE, false); |
| 6048 | + |
| 6049 | + printk("BMAC_TXD Fields:\n"); |
| 6050 | + /* dw0 */ |
| 6051 | + printk("TX_BYTE_COUNT = %d\n", |
| 6052 | + GET_FIELD(WF_TX_DESCRIPTOR_TX_BYTE_COUNT, txd[0])); |
| 6053 | + printk("ETHER_TYPE_OFFSET(word) = %d\n", |
| 6054 | + GET_FIELD(WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET, txd[0])); |
| 6055 | + printk("PKT_FT = %d%s%s%s%s\n", |
| 6056 | + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]), |
| 6057 | + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 0 ? "(ct)" : "", |
| 6058 | + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 1 ? "(s&f)" : "", |
| 6059 | + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 2 ? "(cmd)" : "", |
| 6060 | + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 3 ? "(redirect)" : ""); |
| 6061 | + printk("Q_IDX = %d%s%s%s\n", |
| 6062 | + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]), |
| 6063 | + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x10 ? "(ALTX)" : "", |
| 6064 | + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x11 ? "(BMC)" : "", |
| 6065 | + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x12 ? "(BCN)" : ""); |
| 6066 | + |
| 6067 | + /* dw1 */ |
| 6068 | + printk("MLD_ID = %d\n", |
| 6069 | + GET_FIELD(WF_TX_DESCRIPTOR_MLD_ID, txd[1])); |
| 6070 | + printk("TGID = %d\n", |
| 6071 | + GET_FIELD(WF_TX_DESCRIPTOR_TGID, txd[1])); |
| 6072 | + printk("HF = %d%s%s%s%s\n", |
| 6073 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]), |
| 6074 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? "(eth/802.3)" : "", |
| 6075 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 1 ? "(cmd)" : "", |
| 6076 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? "(802.11)" : "", |
| 6077 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? "(802.11 enhanced" : ""); |
| 6078 | + printk("802.11 HEADER_LENGTH = %d\n", |
| 6079 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? |
| 6080 | + GET_FIELD(WF_TX_DESCRIPTOR_HEADER_LENGTH, txd[1]) : 0); |
| 6081 | + printk("MRD = %d\n", |
| 6082 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| 6083 | + GET_FIELD(WF_TX_DESCRIPTOR_MRD, txd[1]) : 0); |
| 6084 | + printk("EOSP = %d\n", |
| 6085 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| 6086 | + GET_FIELD(WF_TX_DESCRIPTOR_EOSP, txd[1]) : 0); |
| 6087 | + printk("AMS = %d\n", |
| 6088 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? |
| 6089 | + GET_FIELD(WF_TX_DESCRIPTOR_AMS, txd[1]) : 0); |
| 6090 | + printk("RMVL = %d\n", |
| 6091 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| 6092 | + GET_FIELD(WF_TX_DESCRIPTOR_RMVL, txd[1]): 0); |
| 6093 | + printk("VLAN = %d\n", |
| 6094 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| 6095 | + GET_FIELD(WF_TX_DESCRIPTOR_VLAN, txd[1]) : 0); |
| 6096 | + printk("ETYP = %d\n", |
| 6097 | + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| 6098 | + GET_FIELD(WF_TX_DESCRIPTOR_ETYP, txd[1]) : 0); |
| 6099 | + printk("TID_MGMT_TYPE = %d\n", |
| 6100 | + GET_FIELD(WF_TX_DESCRIPTOR_TID_MGMT_TYPE, txd[1])); |
| 6101 | + printk("OM = %d\n", |
| 6102 | + GET_FIELD(WF_TX_DESCRIPTOR_OM, txd[1])); |
| 6103 | + printk("FR = %d\n", |
| 6104 | + GET_FIELD(WF_TX_DESCRIPTOR_FR, txd[1])); |
| 6105 | + |
| 6106 | + /* dw2 */ |
| 6107 | + printk("SUBTYPE = %d%s%s%s%s\n", |
| 6108 | + GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]), |
| 6109 | + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0) && |
| 6110 | + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 13) ? |
| 6111 | + "(action)" : "", |
| 6112 | + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1) && |
| 6113 | + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 8) ? |
| 6114 | + "(bar)" : "", |
| 6115 | + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) && |
| 6116 | + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 4) ? |
| 6117 | + "(null)" : "", |
| 6118 | + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) && |
| 6119 | + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 12) ? |
| 6120 | + "(qos null)" : ""); |
| 6121 | + |
| 6122 | + printk("FTYPE = %d%s\n", |
| 6123 | + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]), |
| 6124 | + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0 ? "(mgmt)" : "", |
| 6125 | + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1 ? "(ctl)" : "", |
| 6126 | + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2 ? "(data)" : ""); |
| 6127 | + printk("BF_TYPE = %d\n", |
| 6128 | + GET_FIELD(WF_TX_DESCRIPTOR_BF_TYPE, txd[2])); |
| 6129 | + printk("OM_MAP = %d\n", |
| 6130 | + GET_FIELD(WF_TX_DESCRIPTOR_OM_MAP, txd[2])); |
| 6131 | + printk("RTS = %d\n", |
| 6132 | + GET_FIELD(WF_TX_DESCRIPTOR_RTS, txd[2])); |
| 6133 | + printk("HEADER_PADDING = %d\n", |
| 6134 | + GET_FIELD(WF_TX_DESCRIPTOR_HEADER_PADDING, txd[2])); |
| 6135 | + printk("DU = %d\n", |
| 6136 | + GET_FIELD(WF_TX_DESCRIPTOR_DU, txd[2])); |
| 6137 | + printk("HE = %d\n", |
| 6138 | + GET_FIELD(WF_TX_DESCRIPTOR_HE, txd[2])); |
| 6139 | + printk("FRAG = %d\n", |
| 6140 | + GET_FIELD(WF_TX_DESCRIPTOR_FRAG, txd[2])); |
| 6141 | + printk("REMAINING_TX_TIME = %d\n", |
| 6142 | + GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_TIME, txd[2])); |
| 6143 | + printk("POWER_OFFSET = %d\n", |
| 6144 | + GET_FIELD(WF_TX_DESCRIPTOR_POWER_OFFSET, txd[2])); |
| 6145 | + |
| 6146 | + /* dw3 */ |
| 6147 | + printk("NA = %d\n", |
| 6148 | + GET_FIELD(WF_TX_DESCRIPTOR_NA, txd[3])); |
| 6149 | + printk("PF = %d\n", |
| 6150 | + GET_FIELD(WF_TX_DESCRIPTOR_PF, txd[3])); |
| 6151 | + printk("EMRD = %d\n", |
| 6152 | + GET_FIELD(WF_TX_DESCRIPTOR_EMRD, txd[3])); |
| 6153 | + printk("EEOSP = %d\n", |
| 6154 | + GET_FIELD(WF_TX_DESCRIPTOR_EEOSP, txd[3])); |
| 6155 | + printk("BM = %d\n", |
| 6156 | + GET_FIELD(WF_TX_DESCRIPTOR_BM, txd[3])); |
| 6157 | + printk("HW_AMSDU_CAP = %d\n", |
| 6158 | + GET_FIELD(WF_TX_DESCRIPTOR_HW_AMSDU_CAP, txd[3])); |
| 6159 | + printk("TX_COUNT = %d\n", |
| 6160 | + GET_FIELD(WF_TX_DESCRIPTOR_TX_COUNT, txd[3])); |
| 6161 | + printk("REMAINING_TX_COUNT = %d\n", |
| 6162 | + GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_COUNT, txd[3])); |
| 6163 | + printk("SN = %d\n", |
| 6164 | + GET_FIELD(WF_TX_DESCRIPTOR_SN, txd[3])); |
| 6165 | + printk("BA_DIS = %d\n", |
| 6166 | + GET_FIELD(WF_TX_DESCRIPTOR_BA_DIS, txd[3])); |
| 6167 | + printk("PM = %d\n", |
| 6168 | + GET_FIELD(WF_TX_DESCRIPTOR_PM, txd[3])); |
| 6169 | + printk("PN_VLD = %d\n", |
| 6170 | + GET_FIELD(WF_TX_DESCRIPTOR_PN_VLD, txd[3])); |
| 6171 | + printk("SN_VLD = %d\n", |
| 6172 | + GET_FIELD(WF_TX_DESCRIPTOR_SN_VLD, txd[3])); |
| 6173 | + |
| 6174 | + /* dw4 */ |
| 6175 | + printk("PN_31_0 = 0x%x\n", |
| 6176 | + GET_FIELD(WF_TX_DESCRIPTOR_PN_31_0_, txd[4])); |
| 6177 | + |
| 6178 | + /* dw5 */ |
| 6179 | + printk("PID = %d\n", |
| 6180 | + GET_FIELD(WF_TX_DESCRIPTOR_PID, txd[5])); |
| 6181 | + printk("TXSFM = %d\n", |
| 6182 | + GET_FIELD(WF_TX_DESCRIPTOR_TXSFM, txd[5])); |
| 6183 | + printk("TXS2M = %d\n", |
| 6184 | + GET_FIELD(WF_TX_DESCRIPTOR_TXS2M, txd[5])); |
| 6185 | + printk("TXS2H = %d\n", |
| 6186 | + GET_FIELD(WF_TX_DESCRIPTOR_TXS2H, txd[5])); |
| 6187 | + printk("FBCZ = %d\n", |
| 6188 | + GET_FIELD(WF_TX_DESCRIPTOR_FBCZ, txd[5])); |
| 6189 | + printk("BYPASS_RBB = %d\n", |
| 6190 | + GET_FIELD(WF_TX_DESCRIPTOR_BYPASS_RBB, txd[5])); |
| 6191 | + |
| 6192 | + printk("FL = %d\n", |
| 6193 | + GET_FIELD(WF_TX_DESCRIPTOR_FL, txd[5])); |
| 6194 | + printk("PN_47_32 = 0x%x\n", |
| 6195 | + GET_FIELD(WF_TX_DESCRIPTOR_PN_47_32_, txd[5])); |
| 6196 | + |
| 6197 | + /* dw6 */ |
| 6198 | + printk("AMSDU_CAP_UTXB = %d\n", |
| 6199 | + GET_FIELD(WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB, txd[6])); |
| 6200 | + printk("DAS = %d\n", |
| 6201 | + GET_FIELD(WF_TX_DESCRIPTOR_DAS, txd[6])); |
| 6202 | + printk("DIS_MAT = %d\n", |
| 6203 | + GET_FIELD(WF_TX_DESCRIPTOR_DIS_MAT, txd[6])); |
| 6204 | + printk("MSDU_COUNT = %d\n", |
| 6205 | + GET_FIELD(WF_TX_DESCRIPTOR_MSDU_COUNT, txd[6])); |
| 6206 | + printk("TIMESTAMP_OFFSET = %d\n", |
| 6207 | + GET_FIELD(WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX, txd[6])); |
| 6208 | + printk("FIXED_RATE_IDX = %d\n", |
| 6209 | + GET_FIELD(WF_TX_DESCRIPTOR_FIXED_RATE_IDX, txd[6])); |
| 6210 | + printk("BW = %d\n", |
| 6211 | + GET_FIELD(WF_TX_DESCRIPTOR_BW, txd[6])); |
| 6212 | + printk("VTA = %d\n", |
| 6213 | + GET_FIELD(WF_TX_DESCRIPTOR_VTA, txd[6])); |
| 6214 | + printk("SRC = %d\n", |
| 6215 | + GET_FIELD(WF_TX_DESCRIPTOR_SRC, txd[6])); |
| 6216 | + |
| 6217 | + /* dw7 */ |
| 6218 | + printk("SW_TX_TIME(unit:65536ns) = d%\n", |
| 6219 | + GET_FIELD(WF_TX_DESCRIPTOR_SW_TX_TIME , txd[7])); |
| 6220 | + printk("UT = %d\n", |
| 6221 | + GET_FIELD(WF_TX_DESCRIPTOR_UT, txd[7])); |
| 6222 | + printk("CTXD_CNT = %d\n", |
| 6223 | + GET_FIELD(WF_TX_DESCRIPTOR_CTXD_CNT, txd[7])); |
| 6224 | + printk("HM = %d\n", |
| 6225 | + GET_FIELD(WF_TX_DESCRIPTOR_HM, txd[7])); |
| 6226 | + printk("DP = %d\n", |
| 6227 | + GET_FIELD(WF_TX_DESCRIPTOR_DP, txd[7])); |
| 6228 | + printk("IP = %d\n", |
| 6229 | + GET_FIELD(WF_TX_DESCRIPTOR_IP, txd[7])); |
| 6230 | + printk("TXD_LEN = %d\n", |
| 6231 | + GET_FIELD(WF_TX_DESCRIPTOR_TXD_LEN, txd[7])); |
| 6232 | + |
| 6233 | + if (dump_txp) { |
| 6234 | + __le32 *txp = txd + 8; |
| 6235 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6236 | + besra_dump_bmac_txp_info(dev, txp); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6237 | + } |
| 6238 | +} |
| 6239 | + |
| 6240 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6241 | +besra_dump_bmac_txd_by_fid(u32 fid) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6242 | +{ |
| 6243 | + //TDO |
| 6244 | +} |
| 6245 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6246 | +void besra_dump_bmac_rxd_info(struct besra_dev *dev, __le32 *rxd) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6247 | +{ |
| 6248 | + /* dump stop */ |
| 6249 | + if (!dev->dbg.rxd_read_cnt) |
| 6250 | + return; |
| 6251 | + |
| 6252 | + /* force dump */ |
| 6253 | + if (dev->dbg.rxd_read_cnt > 8) |
| 6254 | + dev->dbg.rxd_read_cnt = 8; |
| 6255 | + |
| 6256 | + /* dump txd_read_cnt times */ |
| 6257 | + if (dev->dbg.rxd_read_cnt != 8) |
| 6258 | + dev->dbg.rxd_read_cnt--; |
| 6259 | + |
| 6260 | + printk("rxd raw data: size=%d\n", MT_TXD_SIZE); |
| 6261 | + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)rxd, 96, false); |
| 6262 | + |
| 6263 | + printk("BMAC_RXD Fields:\n"); |
| 6264 | + |
| 6265 | + /* group0 */ |
| 6266 | + /* dw0 */ |
| 6267 | + printk("RX_BYTE_COUNT = %d\n", |
| 6268 | + GET_FIELD(WF_RX_DESCRIPTOR_RX_BYTE_COUNT, le32_to_cpu(rxd[0]))); |
| 6269 | + printk("PACKET_TYPE = %d\n", |
| 6270 | + GET_FIELD(WF_RX_DESCRIPTOR_PACKET_TYPE, le32_to_cpu(rxd[0]))); |
| 6271 | + |
| 6272 | + /* dw1 */ |
| 6273 | + printk("MLD_ID = %d\n", |
| 6274 | + GET_FIELD(WF_RX_DESCRIPTOR_MLD_ID, le32_to_cpu(rxd[1]))); |
| 6275 | + printk("GROUP_VLD = 0x%x%s%s%s%s%s\n", |
| 6276 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])), |
| 6277 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6278 | + & BMAC_GROUP_VLD_1 ? "[group1]" : "", |
| 6279 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6280 | + & BMAC_GROUP_VLD_2 ? "[group2]" : "", |
| 6281 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6282 | + & BMAC_GROUP_VLD_3 ? "[group3]" : "", |
| 6283 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6284 | + & BMAC_GROUP_VLD_4 ? "[group4]" : "", |
| 6285 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6286 | + & BMAC_GROUP_VLD_5 ? "[group5]" : ""); |
| 6287 | + printk("KID = %d\n", |
| 6288 | + GET_FIELD(WF_RX_DESCRIPTOR_KID, le32_to_cpu(rxd[1]))); |
| 6289 | + printk("CM = %d\n", |
| 6290 | + GET_FIELD(WF_RX_DESCRIPTOR_CM, le32_to_cpu(rxd[1]))); |
| 6291 | + printk("CLM = %d\n", |
| 6292 | + GET_FIELD(WF_RX_DESCRIPTOR_CLM, le32_to_cpu(rxd[1]))); |
| 6293 | + printk("I = %d\n", |
| 6294 | + GET_FIELD(WF_RX_DESCRIPTOR_I, le32_to_cpu(rxd[1]))); |
| 6295 | + printk("T = %d\n", |
| 6296 | + GET_FIELD(WF_RX_DESCRIPTOR_T, le32_to_cpu(rxd[1]))); |
| 6297 | + printk("BN = %d\n", |
| 6298 | + GET_FIELD(WF_RX_DESCRIPTOR_BN, le32_to_cpu(rxd[1]))); |
| 6299 | + printk("BIPN_FAIL = %d\n", |
| 6300 | + GET_FIELD(WF_RX_DESCRIPTOR_BIPN_FAIL, le32_to_cpu(rxd[1]))); |
| 6301 | + |
| 6302 | + /* dw2 */ |
| 6303 | + printk("BSSID = %d\n", |
| 6304 | + GET_FIELD(WF_RX_DESCRIPTOR_BSSID, le32_to_cpu(rxd[2]))); |
| 6305 | + printk("H = %d%s\n", |
| 6306 | + GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])), |
| 6307 | + GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])) == 0 ? |
| 6308 | + "802.11 frame" : "eth/802.3 frame"); |
| 6309 | + printk("HEADER_LENGTH(word) = %d\n", |
| 6310 | + GET_FIELD(WF_RX_DESCRIPTOR_HEADER_LENGTH, le32_to_cpu(rxd[2]))); |
| 6311 | + printk("HO(word) = %d\n", |
| 6312 | + GET_FIELD(WF_RX_DESCRIPTOR_HO, le32_to_cpu(rxd[2]))); |
| 6313 | + printk("SEC_MODE = %d\n", |
| 6314 | + GET_FIELD(WF_RX_DESCRIPTOR_SEC_MODE, le32_to_cpu(rxd[2]))); |
| 6315 | + printk("MUBAR = %d\n", |
| 6316 | + GET_FIELD(WF_RX_DESCRIPTOR_MUBAR, le32_to_cpu(rxd[2]))); |
| 6317 | + printk("SWBIT = %d\n", |
| 6318 | + GET_FIELD(WF_RX_DESCRIPTOR_SWBIT, le32_to_cpu(rxd[2]))); |
| 6319 | + printk("DAF = %d\n", |
| 6320 | + GET_FIELD(WF_RX_DESCRIPTOR_DAF, le32_to_cpu(rxd[2]))); |
| 6321 | + printk("EL = %d\n", |
| 6322 | + GET_FIELD(WF_RX_DESCRIPTOR_EL, le32_to_cpu(rxd[2]))); |
| 6323 | + printk("HTF = %d\n", |
| 6324 | + GET_FIELD(WF_RX_DESCRIPTOR_HTF, le32_to_cpu(rxd[2]))); |
| 6325 | + printk("INTF = %d\n", |
| 6326 | + GET_FIELD(WF_RX_DESCRIPTOR_INTF, le32_to_cpu(rxd[2]))); |
| 6327 | + printk("FRAG = %d\n", |
| 6328 | + GET_FIELD(WF_RX_DESCRIPTOR_FRAG, le32_to_cpu(rxd[2]))); |
| 6329 | + printk("NUL = %d\n", |
| 6330 | + GET_FIELD(WF_RX_DESCRIPTOR_NUL, le32_to_cpu(rxd[2]))); |
| 6331 | + printk("NDATA = %d%s\n", |
| 6332 | + GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])), |
| 6333 | + GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])) == 0 ? |
| 6334 | + "[data frame]" : "[mgmt/ctl frame]"); |
| 6335 | + printk("NAMP = %d%s\n", |
| 6336 | + GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])), |
| 6337 | + GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])) == 0 ? |
| 6338 | + "[ampdu frame]" : "[mpdu frame]"); |
| 6339 | + printk("BF_RPT = %d\n", |
| 6340 | + GET_FIELD(WF_RX_DESCRIPTOR_BF_RPT, le32_to_cpu(rxd[2]))); |
| 6341 | + |
| 6342 | + /* dw3 */ |
| 6343 | + printk("RXV_SN = %d\n", |
| 6344 | + GET_FIELD(WF_RX_DESCRIPTOR_RXV_SN, le32_to_cpu(rxd[3]))); |
| 6345 | + printk("CH_FREQUENCY = %d\n", |
| 6346 | + GET_FIELD(WF_RX_DESCRIPTOR_CH_FREQUENCY, le32_to_cpu(rxd[3]))); |
| 6347 | + printk("A1_TYPE = %d%s%s%s%s\n", |
| 6348 | + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])), |
| 6349 | + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 0 ? |
| 6350 | + "[reserved]" : "", |
| 6351 | + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 1 ? |
| 6352 | + "[uc2me]" : "", |
| 6353 | + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 2 ? |
| 6354 | + "[mc]" : "", |
| 6355 | + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 3 ? |
| 6356 | + "[bc]" : ""); |
| 6357 | + printk("HTC = %d\n", |
| 6358 | + GET_FIELD(WF_RX_DESCRIPTOR_HTC, le32_to_cpu(rxd[3]))); |
| 6359 | + printk("TCL = %d\n", |
| 6360 | + GET_FIELD(WF_RX_DESCRIPTOR_TCL, le32_to_cpu(rxd[3]))); |
| 6361 | + printk("BBM = %d\n", |
| 6362 | + GET_FIELD(WF_RX_DESCRIPTOR_BBM, le32_to_cpu(rxd[3]))); |
| 6363 | + printk("BU = %d\n", |
| 6364 | + GET_FIELD(WF_RX_DESCRIPTOR_BU, le32_to_cpu(rxd[3]))); |
| 6365 | + printk("CO_ANT = %d\n", |
| 6366 | + GET_FIELD(WF_RX_DESCRIPTOR_CO_ANT, le32_to_cpu(rxd[3]))); |
| 6367 | + printk("BF_CQI = %d\n", |
| 6368 | + GET_FIELD(WF_RX_DESCRIPTOR_BF_CQI, le32_to_cpu(rxd[3]))); |
| 6369 | + printk("FC = %d\n", |
| 6370 | + GET_FIELD(WF_RX_DESCRIPTOR_FC, le32_to_cpu(rxd[3]))); |
| 6371 | + printk("VLAN = %d\n", |
| 6372 | + GET_FIELD(WF_RX_DESCRIPTOR_VLAN, le32_to_cpu(rxd[3]))); |
| 6373 | + |
| 6374 | + /* dw4 */ |
| 6375 | + printk("PF = %d%s%s%s%s\n", |
| 6376 | + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])), |
| 6377 | + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 0 ? |
| 6378 | + "[msdu]" : "", |
| 6379 | + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 1 ? |
| 6380 | + "[final amsdu]" : "", |
| 6381 | + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 2 ? |
| 6382 | + "[middle amsdu]" : "", |
| 6383 | + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 3 ? |
| 6384 | + "[first amsdu]" : ""); |
| 6385 | + printk("MAC = %d\n", |
| 6386 | + GET_FIELD(WF_RX_DESCRIPTOR_MAC, le32_to_cpu(rxd[4]))); |
| 6387 | + printk("TID = %d\n", |
| 6388 | + GET_FIELD(WF_RX_DESCRIPTOR_TID, le32_to_cpu(rxd[4]))); |
| 6389 | + printk("ETHER_TYPE_OFFSET = %d\n", |
| 6390 | + GET_FIELD(WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET, le32_to_cpu(rxd[4]))); |
| 6391 | + printk("IP = %d\n", |
| 6392 | + GET_FIELD(WF_RX_DESCRIPTOR_IP, le32_to_cpu(rxd[4]))); |
| 6393 | + printk("UT = %d\n", |
| 6394 | + GET_FIELD(WF_RX_DESCRIPTOR_UT, le32_to_cpu(rxd[4]))); |
| 6395 | + printk("PSE_FID = %d\n", |
| 6396 | + GET_FIELD(WF_RX_DESCRIPTOR_PSE_FID, le32_to_cpu(rxd[4]))); |
| 6397 | + |
| 6398 | + /* group4 */ |
| 6399 | + /* dw0 */ |
| 6400 | + printk("FRAME_CONTROL_FIELD = 0x%x\n", |
| 6401 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6402 | + & BMAC_GROUP_VLD_4 ? |
| 6403 | + GET_FIELD(WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD, le32_to_cpu(rxd[8])) : 0); |
| 6404 | + printk("PEER_MLD_ADDRESS_15_0 = 0x%x\n", |
| 6405 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6406 | + & BMAC_GROUP_VLD_4 ? |
| 6407 | + GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0_, |
| 6408 | + le32_to_cpu(rxd[8])) : 0); |
| 6409 | + |
| 6410 | + /* dw1 */ |
| 6411 | + printk("PEER_MLD_ADDRESS_47_16 = 0x%x\n", |
| 6412 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6413 | + & BMAC_GROUP_VLD_4 ? |
| 6414 | + GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16_, |
| 6415 | + le32_to_cpu(rxd[9])) : 0); |
| 6416 | + |
| 6417 | + /* dw2 */ |
| 6418 | + printk("FRAGMENT_NUMBER = %d\n", |
| 6419 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6420 | + & BMAC_GROUP_VLD_4 ? |
| 6421 | + GET_FIELD(WF_RX_DESCRIPTOR_FRAGMENT_NUMBER, |
| 6422 | + le32_to_cpu(rxd[10])) : 0); |
| 6423 | + printk("SEQUENCE_NUMBER = %d\n", |
| 6424 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6425 | + & BMAC_GROUP_VLD_4 ? |
| 6426 | + GET_FIELD(WF_RX_DESCRIPTOR_SEQUENCE_NUMBER, |
| 6427 | + le32_to_cpu(rxd[10])) : 0); |
| 6428 | + printk("QOS_CONTROL_FIELD = 0x%x\n", |
| 6429 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6430 | + & BMAC_GROUP_VLD_4 ? |
| 6431 | + GET_FIELD(WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD, |
| 6432 | + le32_to_cpu(rxd[10])) : 0); |
| 6433 | + |
| 6434 | + /* dw3 */ |
| 6435 | + printk("HT_CONTROL_FIELD = 0x%x\n", |
| 6436 | + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| 6437 | + & BMAC_GROUP_VLD_4 ? |
| 6438 | + GET_FIELD(WF_RX_DESCRIPTOR_HT_CONTROL_FIELD, |
| 6439 | + le32_to_cpu(rxd[11])) : 0); |
| 6440 | +} |
| 6441 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6442 | +static int besra_token_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6443 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6444 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6445 | + int id, count = 0; |
| 6446 | + struct mt76_txwi_cache *txwi; |
| 6447 | + |
| 6448 | + seq_printf(s, "Cut through token:\n"); |
| 6449 | + spin_lock_bh(&dev->mt76.token_lock); |
| 6450 | + idr_for_each_entry(&dev->mt76.token, txwi, id) { |
| 6451 | + seq_printf(s, "%4d ", id); |
| 6452 | + count++; |
| 6453 | + if (count % 8 == 0) |
| 6454 | + seq_printf(s, "\n"); |
| 6455 | + } |
| 6456 | + spin_unlock_bh(&dev->mt76.token_lock); |
| 6457 | + seq_printf(s, "\n"); |
| 6458 | + |
| 6459 | + return 0; |
| 6460 | +} |
| 6461 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6462 | +static int besra_token_txd_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6463 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6464 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6465 | + struct mt76_txwi_cache *t; |
| 6466 | + u8* txwi; |
| 6467 | + |
| 6468 | + printk("\n"); |
| 6469 | + spin_lock_bh(&dev->mt76.token_lock); |
| 6470 | + |
| 6471 | + t = idr_find(&dev->mt76.token, dev->dbg.token_idx); |
| 6472 | + |
| 6473 | + spin_unlock_bh(&dev->mt76.token_lock); |
| 6474 | + if (t != NULL) { |
| 6475 | + struct mt76_dev *mdev = &dev->mt76; |
| 6476 | + txwi = ((u8*)(t)) - (mdev->drv->txwi_size); |
| 6477 | + /* dump one txd info */ |
| 6478 | + dev->dbg.txd_read_cnt = 1; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6479 | + besra_dump_bmac_txd_info(dev, (__le32 *)txwi, false); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6480 | + printk("\n"); |
| 6481 | + printk("[SKB]\n"); |
| 6482 | + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false); |
| 6483 | + printk("\n"); |
| 6484 | + } |
| 6485 | + return 0; |
| 6486 | +} |
| 6487 | + |
| 6488 | +/* AMSDU INFO */ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6489 | +static int besra_amsdu_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6490 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6491 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6492 | + u32 ple_stat[8] = {0}, total_amsdu = 0; |
| 6493 | + u8 i; |
| 6494 | + |
| 6495 | + for (i = 0; i < 8; i++) |
| 6496 | + ple_stat[i] = mt76_rr(dev, WF_PLE_TOP_AMSDU_PACK_1_MSDU_CNT_ADDR + i * 0x04); |
| 6497 | + |
| 6498 | + seq_printf(s, "TXD counter status of MSDU:\n"); |
| 6499 | + |
| 6500 | + for (i = 0; i < 8; i++) |
| 6501 | + total_amsdu += ple_stat[i]; |
| 6502 | + |
| 6503 | + for (i = 0; i < 8; i++) { |
| 6504 | + seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i+1, ple_stat[i]); |
| 6505 | + if (total_amsdu != 0) |
| 6506 | + seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu); |
| 6507 | + else |
| 6508 | + seq_printf(s, "\n"); |
| 6509 | + } |
| 6510 | + |
| 6511 | + return 0; |
| 6512 | +} |
| 6513 | + |
| 6514 | +/* AGG INFO */ |
| 6515 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6516 | +besra_agginfo_read_per_band(struct seq_file *s, int band_idx) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6517 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6518 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6519 | + u64 total_burst, total_ampdu, ampdu_cnt[16]; |
| 6520 | + u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0; |
| 6521 | + u8 readFW = 0, partial_str[16] = {}, full_str[64] = {}; |
| 6522 | + |
| 6523 | + switch (band_idx) { |
| 6524 | + case 0: |
| 6525 | + band_offset = 0; |
| 6526 | + break; |
| 6527 | + case 1: |
| 6528 | + band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE; |
| 6529 | + break; |
| 6530 | + case 2: |
| 6531 | + band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE; |
| 6532 | + break; |
| 6533 | + default: |
| 6534 | + return 0; |
| 6535 | + } |
| 6536 | + |
| 6537 | + seq_printf(s, "Band %d AGG Status\n", band_idx); |
| 6538 | + seq_printf(s, "===============================\n"); |
| 6539 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset); |
| 6540 | + seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT); |
| 6541 | + seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT); |
| 6542 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset); |
| 6543 | + seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT); |
| 6544 | + seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT); |
| 6545 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset); |
| 6546 | + seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT); |
| 6547 | + seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT); |
| 6548 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset); |
| 6549 | + seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT); |
| 6550 | + seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT); |
| 6551 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset); |
| 6552 | + seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT); |
| 6553 | + seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT); |
| 6554 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset); |
| 6555 | + seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT); |
| 6556 | + seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT); |
| 6557 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset); |
| 6558 | + seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT); |
| 6559 | + seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT); |
| 6560 | + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset); |
| 6561 | + seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT); |
| 6562 | + seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT); |
| 6563 | + |
| 6564 | + switch (band_idx) { |
| 6565 | + case 0: |
| 6566 | + band_offset = 0; |
| 6567 | + break; |
| 6568 | + case 1: |
| 6569 | + band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| 6570 | + break; |
| 6571 | + case 2: |
| 6572 | + band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| 6573 | + break; |
| 6574 | + default: |
| 6575 | + return 0; |
| 6576 | + } |
| 6577 | + |
| 6578 | + seq_printf(s, "===AMPDU Related Counters===\n"); |
| 6579 | + |
| 6580 | + if (readFW) { |
| 6581 | + /* BELLWETHER TODO: Wait MIB counter API implement complete */ |
| 6582 | + } else { |
| 6583 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset); |
| 6584 | + agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT; |
| 6585 | + agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT; |
| 6586 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset); |
| 6587 | + agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT; |
| 6588 | + agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT; |
| 6589 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset); |
| 6590 | + agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT; |
| 6591 | + agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT; |
| 6592 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset); |
| 6593 | + agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT; |
| 6594 | + agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT; |
| 6595 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset); |
| 6596 | + agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT; |
| 6597 | + agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT; |
| 6598 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset); |
| 6599 | + agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT; |
| 6600 | + agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT; |
| 6601 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset); |
| 6602 | + agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT; |
| 6603 | + agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT; |
| 6604 | + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset); |
| 6605 | + agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT; |
| 6606 | + |
| 6607 | + burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset); |
| 6608 | + burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset); |
| 6609 | + burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset); |
| 6610 | + burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset); |
| 6611 | + burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset); |
| 6612 | + burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset); |
| 6613 | + burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset); |
| 6614 | + burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset); |
| 6615 | + burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset); |
| 6616 | + burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset); |
| 6617 | + burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset); |
| 6618 | + burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset); |
| 6619 | + burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset); |
| 6620 | + burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset); |
| 6621 | + burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset); |
| 6622 | + burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset); |
| 6623 | + } |
| 6624 | + |
| 6625 | + start_range = 1; |
| 6626 | + total_burst = 0; |
| 6627 | + total_ampdu = 0; |
| 6628 | + agg_rang_sel[15] = 1023; |
| 6629 | + |
| 6630 | + /* Need to add 1 after read from AGG_RANG_SEL CR */ |
| 6631 | + for (idx = 0; idx < 16; idx++) { |
| 6632 | + agg_rang_sel[idx]++; |
| 6633 | + total_burst += burst_cnt[idx]; |
| 6634 | + |
| 6635 | + if (start_range == agg_rang_sel[idx]) |
| 6636 | + ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx]; |
| 6637 | + else |
| 6638 | + ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx]; |
| 6639 | + |
| 6640 | + start_range = agg_rang_sel[idx] + 1; |
| 6641 | + total_ampdu += ampdu_cnt[idx]; |
| 6642 | + } |
| 6643 | + |
| 6644 | + start_range = 1; |
| 6645 | + sprintf(full_str, "%13s ", "Tx Agg Range:"); |
| 6646 | + |
| 6647 | + for (row_idx = 0; row_idx < 4; row_idx++) { |
| 6648 | + for (col_idx = 0; col_idx < 4; col_idx++, idx++) { |
| 6649 | + idx = 4 * row_idx + col_idx; |
| 6650 | + |
| 6651 | + if (start_range == agg_rang_sel[idx]) |
| 6652 | + sprintf(partial_str, "%d", agg_rang_sel[idx]); |
| 6653 | + else |
| 6654 | + sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]); |
| 6655 | + |
| 6656 | + start_range = agg_rang_sel[idx] + 1; |
| 6657 | + sprintf(full_str + strlen(full_str), "%-11s ", partial_str); |
| 6658 | + } |
| 6659 | + |
| 6660 | + idx = 4 * row_idx; |
| 6661 | + |
| 6662 | + seq_printf(s, "%s\n", full_str); |
| 6663 | + seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n", |
| 6664 | + row_idx ? "" : "Burst count:", |
| 6665 | + burst_cnt[idx], burst_cnt[idx + 1], |
| 6666 | + burst_cnt[idx + 2], burst_cnt[idx + 3]); |
| 6667 | + |
| 6668 | + if (total_burst != 0) { |
| 6669 | + if (row_idx == 0) |
| 6670 | + sprintf(full_str, "%13s ", |
| 6671 | + "Burst ratio:"); |
| 6672 | + else |
| 6673 | + sprintf(full_str, "%13s ", ""); |
| 6674 | + |
| 6675 | + for (col_idx = 0; col_idx < 4; col_idx++) { |
| 6676 | + u64 count = (u64) burst_cnt[idx + col_idx] * 100; |
| 6677 | + |
| 6678 | + sprintf(partial_str, "(%llu%%)", |
| 6679 | + div64_u64(count, total_burst)); |
| 6680 | + sprintf(full_str + strlen(full_str), |
| 6681 | + "%-11s ", partial_str); |
| 6682 | + } |
| 6683 | + |
| 6684 | + seq_printf(s, "%s\n", full_str); |
| 6685 | + |
| 6686 | + if (row_idx == 0) |
| 6687 | + sprintf(full_str, "%13s ", |
| 6688 | + "MDPU ratio:"); |
| 6689 | + else |
| 6690 | + sprintf(full_str, "%13s ", ""); |
| 6691 | + |
| 6692 | + for (col_idx = 0; col_idx < 4; col_idx++) { |
| 6693 | + u64 count = ampdu_cnt[idx + col_idx] * 100; |
| 6694 | + |
| 6695 | + sprintf(partial_str, "(%llu%%)", |
| 6696 | + div64_u64(count, total_ampdu)); |
| 6697 | + sprintf(full_str + strlen(full_str), |
| 6698 | + "%-11s ", partial_str); |
| 6699 | + } |
| 6700 | + |
| 6701 | + seq_printf(s, "%s\n", full_str); |
| 6702 | + } |
| 6703 | + |
| 6704 | + sprintf(full_str, "%13s ", ""); |
| 6705 | + } |
| 6706 | + |
| 6707 | + return 0; |
| 6708 | +} |
| 6709 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6710 | +static int besra_agginfo_read_band0(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6711 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6712 | + besra_agginfo_read_per_band(s, MT_BAND0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6713 | + return 0; |
| 6714 | +} |
| 6715 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6716 | +static int besra_agginfo_read_band1(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6717 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6718 | + besra_agginfo_read_per_band(s, MT_BAND1); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6719 | + return 0; |
| 6720 | +} |
| 6721 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6722 | +static int besra_agginfo_read_band2(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6723 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6724 | + besra_agginfo_read_per_band(s, MT_BAND2); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6725 | + return 0; |
| 6726 | +} |
| 6727 | + |
| 6728 | +/* PSE INFO */ |
| 6729 | +static struct bmac_queue_info_t pse_queue_empty_info[] = { |
| 6730 | + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0}, |
| 6731 | + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1}, |
| 6732 | + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2}, |
| 6733 | + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3}, |
| 6734 | + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */ |
| 6735 | + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| 6736 | + {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */ |
| 6737 | + {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0}, |
| 6738 | + {"MDP TX Q0", ENUM_UMAC_LMAC_PORT_2, 1}, |
| 6739 | + {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2}, |
| 6740 | + {"SEC TX Q0", ENUM_UMAC_LMAC_PORT_2, 3}, |
| 6741 | + {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4}, |
| 6742 | + {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5}, |
| 6743 | + {"MDP_TXIOC Q0", ENUM_UMAC_LMAC_PORT_2, 6}, |
| 6744 | + {"MDP_RXIOC Q0", ENUM_UMAC_LMAC_PORT_2, 7}, |
| 6745 | + {"MDP TX Q1", ENUM_UMAC_LMAC_PORT_2, 0x11}, |
| 6746 | + {"SEC TX Q1", ENUM_UMAC_LMAC_PORT_2, 0x13}, |
| 6747 | + {"MDP_TXIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x16}, |
| 6748 | + {"MDP_RXIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x17}, |
| 6749 | + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, 4}, |
| 6750 | + {NULL, 0, 0}, {NULL, 0, 0}, |
| 6751 | + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F} |
| 6752 | +}; |
| 6753 | + |
| 6754 | +static struct bmac_queue_info_t pse_queue_empty2_info[] = { |
| 6755 | + {"MDP_TDPIOC Q0", ENUM_UMAC_LMAC_PORT_2, 0x8}, |
| 6756 | + {"MDP_RDPIOC Q0", ENUM_UMAC_LMAC_PORT_2, 0x9}, |
| 6757 | + {"MDP_TDPIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x18}, |
| 6758 | + {"MDP_RDPIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x19}, |
| 6759 | + {"MDP_TDPIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x28}, |
| 6760 | + {"MDP_RDPIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x29}, |
| 6761 | + {NULL, 0, 0}, |
| 6762 | + {"MDP_RDPIOC Q3", ENUM_UMAC_LMAC_PORT_2, 0x39}, |
| 6763 | + {"MDP TX Q2", ENUM_UMAC_LMAC_PORT_2, 0x21}, |
| 6764 | + {"SEC TX Q2", ENUM_UMAC_LMAC_PORT_2, 0x23}, |
| 6765 | + {"MDP_TXIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x26}, |
| 6766 | + {"MDP_RXIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x27}, |
| 6767 | + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| 6768 | + {"MDP_RXIOC Q3", ENUM_UMAC_LMAC_PORT_2, 0x37}, |
| 6769 | + {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, |
| 6770 | + {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1}, |
| 6771 | + {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2}, |
| 6772 | + {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3}, |
| 6773 | + {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4}, |
| 6774 | + {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5}, |
| 6775 | + {"HIF Q6", ENUM_UMAC_HIF_PORT_0, 6}, |
| 6776 | + {"HIF Q7", ENUM_UMAC_HIF_PORT_0, 7}, |
| 6777 | + {"HIF Q8", ENUM_UMAC_HIF_PORT_0, 8}, |
| 6778 | + {"HIF Q9", ENUM_UMAC_HIF_PORT_0, 9}, |
| 6779 | + {"HIF Q10", ENUM_UMAC_HIF_PORT_0, 10}, |
| 6780 | + {"HIF Q11", ENUM_UMAC_HIF_PORT_0, 11}, |
| 6781 | + {"HIF Q12", ENUM_UMAC_HIF_PORT_0, 12}, |
| 6782 | + {"HIF Q13", ENUM_UMAC_HIF_PORT_0, 13}, |
| 6783 | + {NULL, 0, 0}, {NULL, 0, 0} |
| 6784 | +}; |
| 6785 | + |
| 6786 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6787 | +besra_pseinfo_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6788 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 6789 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 6790 | + u32 pse_buf_ctrl, pg_sz, pg_num; |
| 6791 | + u32 pse_stat[2], pg_flow_ctrl[28] = {0}; |
| 6792 | + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail; |
| 6793 | + u32 max_q, min_q, rsv_pg, used_pg; |
| 6794 | + int i; |
| 6795 | + |
| 6796 | + pse_buf_ctrl = mt76_rr(dev, WF_PSE_TOP_PBUF_CTRL_ADDR); |
| 6797 | + pse_stat[0] = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR); |
| 6798 | + pse_stat[1] = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_1_ADDR); |
| 6799 | + pg_flow_ctrl[0] = mt76_rr(dev, WF_PSE_TOP_FREEPG_CNT_ADDR); |
| 6800 | + pg_flow_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR); |
| 6801 | + pg_flow_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_PG_HIF0_GROUP_ADDR); |
| 6802 | + pg_flow_ctrl[3] = mt76_rr(dev, WF_PSE_TOP_HIF0_PG_INFO_ADDR); |
| 6803 | + pg_flow_ctrl[4] = mt76_rr(dev, WF_PSE_TOP_PG_HIF1_GROUP_ADDR); |
| 6804 | + pg_flow_ctrl[5] = mt76_rr(dev, WF_PSE_TOP_HIF1_PG_INFO_ADDR); |
| 6805 | + pg_flow_ctrl[6] = mt76_rr(dev, WF_PSE_TOP_PG_CPU_GROUP_ADDR); |
| 6806 | + pg_flow_ctrl[7] = mt76_rr(dev, WF_PSE_TOP_CPU_PG_INFO_ADDR); |
| 6807 | + pg_flow_ctrl[8] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC0_GROUP_ADDR); |
| 6808 | + pg_flow_ctrl[9] = mt76_rr(dev, WF_PSE_TOP_LMAC0_PG_INFO_ADDR); |
| 6809 | + pg_flow_ctrl[10] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC1_GROUP_ADDR); |
| 6810 | + pg_flow_ctrl[11] = mt76_rr(dev, WF_PSE_TOP_LMAC1_PG_INFO_ADDR); |
| 6811 | + pg_flow_ctrl[12] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC2_GROUP_ADDR); |
| 6812 | + pg_flow_ctrl[13] = mt76_rr(dev, WF_PSE_TOP_LMAC2_PG_INFO_ADDR); |
| 6813 | + pg_flow_ctrl[14] = mt76_rr(dev, WF_PSE_TOP_PG_PLE_GROUP_ADDR); |
| 6814 | + pg_flow_ctrl[15] = mt76_rr(dev, WF_PSE_TOP_PLE_PG_INFO_ADDR); |
| 6815 | + pg_flow_ctrl[16] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC3_GROUP_ADDR); |
| 6816 | + pg_flow_ctrl[17] = mt76_rr(dev, WF_PSE_TOP_LMAC3_PG_INFO_ADDR); |
| 6817 | + pg_flow_ctrl[18] = mt76_rr(dev, WF_PSE_TOP_PG_MDP_GROUP_ADDR); |
| 6818 | + pg_flow_ctrl[19] = mt76_rr(dev, WF_PSE_TOP_MDP_PG_INFO_ADDR); |
| 6819 | + pg_flow_ctrl[20] = mt76_rr(dev, WF_PSE_TOP_PG_PLE1_GROUP_ADDR); |
| 6820 | + pg_flow_ctrl[21] = mt76_rr(dev, WF_PSE_TOP_PLE1_PG_INFO_ADDR); |
| 6821 | + pg_flow_ctrl[22] = mt76_rr(dev, WF_PSE_TOP_PG_MDP2_GROUP_ADDR); |
| 6822 | + pg_flow_ctrl[23] = mt76_rr(dev, WF_PSE_TOP_MDP2_PG_INFO_ADDR); |
| 6823 | + pg_flow_ctrl[24] = mt76_rr(dev, WF_PSE_TOP_PG_MDP3_GROUP_ADDR); |
| 6824 | + pg_flow_ctrl[25] = mt76_rr(dev, WF_PSE_TOP_MDP3_PG_INFO_ADDR); |
| 6825 | + pg_flow_ctrl[26] = mt76_rr(dev, WF_PSE_TOP_PG_HIF2_GROUP_ADDR); |
| 6826 | + pg_flow_ctrl[27] = mt76_rr(dev, WF_PSE_TOP_HIF2_PG_INFO_ADDR); |
| 6827 | + /* Configuration Info */ |
| 6828 | + printk("PSE Configuration Info:\n"); |
| 6829 | + printk("\tPacket Buffer Control: 0x%08x\n", pse_buf_ctrl); |
| 6830 | + pg_sz = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; |
| 6831 | + printk("\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128)); |
| 6832 | + printk("\t\tPage Offset=%d(in unit of 64KB)\n", |
| 6833 | + (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); |
| 6834 | + pg_num = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; |
| 6835 | + printk("\t\tTotal page numbers=%d pages\n", pg_num); |
| 6836 | + /* Page Flow Control */ |
| 6837 | + printk("PSE Page Flow Control:\n"); |
| 6838 | + printk("\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); |
| 6839 | + fpg_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; |
| 6840 | + printk("\t\tThe toal page number of free=0x%03x\n", fpg_cnt); |
| 6841 | + ffa_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT; |
| 6842 | + printk("\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt); |
| 6843 | + printk("\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); |
| 6844 | + fpg_head = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; |
| 6845 | + fpg_tail = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; |
| 6846 | + printk("\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head); |
| 6847 | + printk("\tReserved page counter of HIF0 group: 0x%08x\n", pg_flow_ctrl[2]); |
| 6848 | + printk("\tHIF0 group page status: 0x%08x\n", pg_flow_ctrl[3]); |
| 6849 | + min_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT; |
| 6850 | + max_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT; |
| 6851 | + printk("\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6852 | + rsv_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT; |
| 6853 | + used_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT; |
| 6854 | + printk("\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6855 | + printk("\tReserved page counter of HIF1 group: 0x%08x\n", pg_flow_ctrl[4]); |
| 6856 | + printk("\tHIF1 group page status: 0x%08x\n", pg_flow_ctrl[5]); |
| 6857 | + min_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT; |
| 6858 | + max_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT; |
| 6859 | + printk("\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6860 | + rsv_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT; |
| 6861 | + used_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT; |
| 6862 | + printk("\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6863 | + printk("\tReserved page counter of HIF2 group: 0x%08x\n", pg_flow_ctrl[26]); |
| 6864 | + printk("\tHIF2 group page status: 0x%08x\n", pg_flow_ctrl[27]); |
| 6865 | + min_q = (pg_flow_ctrl[26] & WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_SHFT; |
| 6866 | + max_q = (pg_flow_ctrl[26] & WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_SHFT; |
| 6867 | + printk("\t\tThe max/min quota pages of HIF2 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6868 | + rsv_pg = (pg_flow_ctrl[27] & WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_MASK) >> WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_SHFT; |
| 6869 | + used_pg = (pg_flow_ctrl[27] & WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_MASK) >> WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_SHFT; |
| 6870 | + printk("\t\tThe used/reserved pages of HIF2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6871 | + printk("\tReserved page counter of CPU group: 0x%08x\n", pg_flow_ctrl[6]); |
| 6872 | + printk("\tCPU group page status: 0x%08x\n", pg_flow_ctrl[7]); |
| 6873 | + min_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT; |
| 6874 | + max_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT; |
| 6875 | + printk("\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q); |
| 6876 | + rsv_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT; |
| 6877 | + used_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT; |
| 6878 | + printk("\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6879 | + printk("\tReserved page counter of LMAC0 group: 0x%08x\n", pg_flow_ctrl[8]); |
| 6880 | + printk("\tLMAC0 group page status: 0x%08x\n", pg_flow_ctrl[9]); |
| 6881 | + min_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT; |
| 6882 | + max_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT; |
| 6883 | + printk("\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6884 | + rsv_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT; |
| 6885 | + used_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT; |
| 6886 | + printk("\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6887 | + printk("\tReserved page counter of LMAC1 group: 0x%08x\n", pg_flow_ctrl[10]); |
| 6888 | + printk("\tLMAC1 group page status: 0x%08x\n", pg_flow_ctrl[11]); |
| 6889 | + min_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT; |
| 6890 | + max_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT; |
| 6891 | + printk("\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6892 | + rsv_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT; |
| 6893 | + used_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT; |
| 6894 | + printk("\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6895 | + printk("\tReserved page counter of LMAC2 group: 0x%08x\n", pg_flow_ctrl[11]); |
| 6896 | + printk("\tLMAC2 group page status: 0x%08x\n", pg_flow_ctrl[12]); |
| 6897 | + min_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT; |
| 6898 | + max_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT; |
| 6899 | + printk("\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6900 | + rsv_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT; |
| 6901 | + used_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT; |
| 6902 | + printk("\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6903 | + |
| 6904 | + printk("\tReserved page counter of LMAC3 group: 0x%08x\n", pg_flow_ctrl[16]); |
| 6905 | + printk("\tLMAC3 group page status: 0x%08x\n", pg_flow_ctrl[17]); |
| 6906 | + min_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT; |
| 6907 | + max_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT; |
| 6908 | + printk("\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6909 | + rsv_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT; |
| 6910 | + used_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT; |
| 6911 | + printk("\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6912 | + |
| 6913 | + printk("\tReserved page counter of PLE group: 0x%08x\n", pg_flow_ctrl[14]); |
| 6914 | + printk("\tPLE group page status: 0x%08x\n", pg_flow_ctrl[15]); |
| 6915 | + min_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT; |
| 6916 | + max_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT; |
| 6917 | + printk("\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q); |
| 6918 | + rsv_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT; |
| 6919 | + used_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT; |
| 6920 | + printk("\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6921 | + |
| 6922 | + printk("\tReserved page counter of PLE1 group: 0x%08x\n", pg_flow_ctrl[14]); |
| 6923 | + printk("\tPLE1 group page status: 0x%08x\n", pg_flow_ctrl[15]); |
| 6924 | + min_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT; |
| 6925 | + max_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT; |
| 6926 | + printk("\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6927 | + rsv_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT; |
| 6928 | + used_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT; |
| 6929 | + printk("\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6930 | + |
| 6931 | + printk("\tReserved page counter of MDP group: 0x%08x\n", pg_flow_ctrl[18]); |
| 6932 | + printk("\tMDP group page status: 0x%08x\n", pg_flow_ctrl[19]); |
| 6933 | + min_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT; |
| 6934 | + max_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT; |
| 6935 | + printk("\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q); |
| 6936 | + rsv_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT; |
| 6937 | + used_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT; |
| 6938 | + printk("\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6939 | + printk("\tReserved page counter of MDP2 group: 0x%08x\n", pg_flow_ctrl[22]); |
| 6940 | + printk("\tMDP2 group page status: 0x%08x\n", pg_flow_ctrl[23]); |
| 6941 | + min_q = (pg_flow_ctrl[22] & WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_SHFT; |
| 6942 | + max_q = (pg_flow_ctrl[22] & WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_SHFT; |
| 6943 | + printk("\t\tThe max/min quota pages of MDP2 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6944 | + rsv_pg = (pg_flow_ctrl[23] & WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_MASK) >> WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_SHFT; |
| 6945 | + used_pg = (pg_flow_ctrl[23] & WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_MASK) >> WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_SHFT; |
| 6946 | + printk("\t\tThe used/reserved pages of MDP2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6947 | + printk("\tReserved page counter of MDP3 group: 0x%08x\n", pg_flow_ctrl[24]); |
| 6948 | + printk("\tMDP3 group page status: 0x%08x\n", pg_flow_ctrl[25]); |
| 6949 | + min_q = (pg_flow_ctrl[24] & WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_SHFT; |
| 6950 | + max_q = (pg_flow_ctrl[24] & WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_SHFT; |
| 6951 | + printk("\t\tThe max/min quota pages of MDP3 group=0x%03x/0x%03x\n", max_q, min_q); |
| 6952 | + rsv_pg = (pg_flow_ctrl[25] & WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_MASK) >> WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_SHFT; |
| 6953 | + used_pg = (pg_flow_ctrl[25] & WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_MASK) >> WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_SHFT; |
| 6954 | + printk("\t\tThe used/reserved pages of MDP3 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| 6955 | + /* Queue Empty Status */ |
| 6956 | + printk("PSE Queue Empty Status:\n"); |
| 6957 | + printk("\tQUEUE_EMPTY: 0x%08x, QUEUE_EMPTY2: 0x%08x\n", pse_stat[0], pse_stat[1]); |
| 6958 | + printk("\t\tCPU Q0/1/2/3/4 empty=%d/%d/%d/%d/%d\n", |
| 6959 | + (pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT, |
| 6960 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT), |
| 6961 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT), |
| 6962 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT), |
| 6963 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT)); |
| 6964 | + printk("\t\tHIF Q0/1/2/3/4/5/6/7/8/9/10/11/12/13 empty=%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d\n", |
| 6965 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT), |
| 6966 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT), |
| 6967 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT), |
| 6968 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT), |
| 6969 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT), |
| 6970 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT), |
| 6971 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT), |
| 6972 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT), |
| 6973 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT), |
| 6974 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT), |
| 6975 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT), |
| 6976 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT), |
| 6977 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT), |
| 6978 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT)); |
| 6979 | + printk("\t\tLMAC TX Q empty=%d\n", |
| 6980 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT)); |
| 6981 | + printk("\t\tMDP TX Q0/Q1/Q2/RX Q empty=%d/%d/%d/%d\n", |
| 6982 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT), |
| 6983 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT), |
| 6984 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT), |
| 6985 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT)); |
| 6986 | + printk("\t\tSEC TX Q0/Q1/Q2/RX Q empty=%d/%d/%d/%d\n", |
| 6987 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT), |
| 6988 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT), |
| 6989 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT), |
| 6990 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT)); |
| 6991 | + printk("\t\tSFD PARK Q empty=%d\n", |
| 6992 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT)); |
| 6993 | + printk("\t\tMDP TXIOC Q0/Q1/Q2 empty=%d/%d/%d\n", |
| 6994 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT), |
| 6995 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT), |
| 6996 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT)); |
| 6997 | + printk("\t\tMDP RXIOC Q0/Q1/Q2/Q3 empty=%d/%d/%d/%d\n", |
| 6998 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT), |
| 6999 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT), |
| 7000 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT), |
| 7001 | + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT)); |
| 7002 | + printk("\t\tRLS Q empty=%d\n", |
| 7003 | + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT)); |
| 7004 | + printk("Nonempty Q info:\n"); |
| 7005 | + |
| 7006 | + for (i = 0; i < 31; i++) { |
| 7007 | + if (((pse_stat[0] & (0x1 << i)) >> i) == 0) { |
| 7008 | + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| 7009 | + |
| 7010 | + if (pse_queue_empty_info[i].QueueName != NULL) { |
| 7011 | + printk("\t%s: ", pse_queue_empty_info[i].QueueName); |
| 7012 | + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| 7013 | + fl_que_ctrl[1] |= (pse_queue_empty_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| 7014 | + fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| 7015 | + } else |
| 7016 | + continue; |
| 7017 | + |
| 7018 | + fl_que_ctrl[0] |= (0x1 << 31); |
| 7019 | + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| 7020 | + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| 7021 | + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); |
| 7022 | + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); |
| 7023 | + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| 7024 | + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| 7025 | + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| 7026 | + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| 7027 | + tfid, hfid, pktcnt); |
| 7028 | + } |
| 7029 | + } |
| 7030 | + |
| 7031 | + for (i = 0; i < 31; i++) { |
| 7032 | + if (((pse_stat[1] & (0x1 << i)) >> i) == 0) { |
| 7033 | + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| 7034 | + |
| 7035 | + if (pse_queue_empty2_info[i].QueueName != NULL) { |
| 7036 | + printk("\t%s: ", pse_queue_empty2_info[i].QueueName); |
| 7037 | + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| 7038 | + fl_que_ctrl[1] |= (pse_queue_empty2_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| 7039 | + fl_que_ctrl[0] |= (pse_queue_empty2_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| 7040 | + } else |
| 7041 | + continue; |
| 7042 | + |
| 7043 | + fl_que_ctrl[0] |= (0x1 << 31); |
| 7044 | + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| 7045 | + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| 7046 | + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); |
| 7047 | + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); |
| 7048 | + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| 7049 | + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| 7050 | + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| 7051 | + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| 7052 | + tfid, hfid, pktcnt); |
| 7053 | + } |
| 7054 | + } |
| 7055 | + |
| 7056 | + return true; |
| 7057 | +} |
| 7058 | + |
| 7059 | +/* PLE INFO */ |
| 7060 | +static char *sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"}; |
| 7061 | +static struct bmac_queue_info ple_queue_empty_info[] = { |
| 7062 | + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0, 0}, |
| 7063 | + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1, 0}, |
| 7064 | + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2, 0}, |
| 7065 | + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3, 0}, |
| 7066 | + {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x10, 0}, |
| 7067 | + {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, 0x11, 0}, |
| 7068 | + {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, 0x12, 0}, |
| 7069 | + {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, 0x13, 0}, |
| 7070 | + {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x10, 1}, |
| 7071 | + {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, 0x11, 1}, |
| 7072 | + {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, 0x12, 1}, |
| 7073 | + {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, 0x13, 1}, |
| 7074 | + {"ALTX Q2", ENUM_UMAC_LMAC_PORT_2, 0x10, 2}, |
| 7075 | + {"BMC Q2", ENUM_UMAC_LMAC_PORT_2, 0x11, 2}, |
| 7076 | + {"BCN Q2", ENUM_UMAC_LMAC_PORT_2, 0x12, 2}, |
| 7077 | + {"PSMP Q2", ENUM_UMAC_LMAC_PORT_2, 0x13, 2}, |
| 7078 | + {"NAF Q", ENUM_UMAC_LMAC_PORT_2, 0x18, 0}, |
| 7079 | + {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, 0x19, 0}, |
| 7080 | + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, /* 18, 19 not defined */ |
| 7081 | + {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a, 0}, |
| 7082 | + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, |
| 7083 | + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, |
| 7084 | + {"RLS4 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7c, 0}, |
| 7085 | + {"RLS3 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7d, 0}, |
| 7086 | + {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e, 0}, |
| 7087 | + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f, 0} |
| 7088 | +}; |
| 7089 | + |
| 7090 | +static struct bmac_queue_info_t ple_txcmd_queue_empty_info[] = { |
| 7091 | + {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40}, |
| 7092 | + {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41}, |
| 7093 | + {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42}, |
| 7094 | + {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43}, |
| 7095 | + {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44}, |
| 7096 | + {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45}, |
| 7097 | + {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46}, |
| 7098 | + {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47}, |
| 7099 | + {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48}, |
| 7100 | + {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49}, |
| 7101 | + {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a}, |
| 7102 | + {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b}, |
| 7103 | + {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c}, |
| 7104 | + {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d}, |
| 7105 | + {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e}, |
| 7106 | + {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f}, |
| 7107 | + {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50}, |
| 7108 | + {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51}, |
| 7109 | + {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52}, |
| 7110 | + {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53}, |
| 7111 | + {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54}, |
| 7112 | + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| 7113 | + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| 7114 | +}; |
| 7115 | + |
| 7116 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7117 | +besra_get_ple_acq_stat(struct besra_dev *dev, u32 *ple_stat) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7118 | +{ |
| 7119 | + ple_stat[0] = mt76_rr(dev, WF_PLE_TOP_QUEUE_EMPTY_ADDR); |
| 7120 | + |
| 7121 | + ple_stat[1] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR); |
| 7122 | + ple_stat[2] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR); |
| 7123 | + ple_stat[3] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR); |
| 7124 | + ple_stat[4] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR); |
| 7125 | + ple_stat[5] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR); |
| 7126 | + ple_stat[6] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR); |
| 7127 | + ple_stat[7] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR); |
| 7128 | + ple_stat[8] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR); |
| 7129 | + ple_stat[9] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR); |
| 7130 | + |
| 7131 | + ple_stat[10] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR); |
| 7132 | + ple_stat[11] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR); |
| 7133 | + ple_stat[12] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR); |
| 7134 | + ple_stat[13] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR); |
| 7135 | + ple_stat[14] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR); |
| 7136 | + ple_stat[15] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR); |
| 7137 | + ple_stat[16] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR); |
| 7138 | + ple_stat[17] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR); |
| 7139 | + ple_stat[18] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR); |
| 7140 | + |
| 7141 | + ple_stat[19] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR); |
| 7142 | + ple_stat[20] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR); |
| 7143 | + ple_stat[21] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR); |
| 7144 | + ple_stat[22] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR); |
| 7145 | + ple_stat[23] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR); |
| 7146 | + ple_stat[24] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR); |
| 7147 | + ple_stat[25] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR); |
| 7148 | + ple_stat[26] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR); |
| 7149 | + ple_stat[27] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR); |
| 7150 | + |
| 7151 | + ple_stat[28] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR); |
| 7152 | + ple_stat[29] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR); |
| 7153 | + ple_stat[30] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR); |
| 7154 | + ple_stat[31] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR); |
| 7155 | + ple_stat[32] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR); |
| 7156 | + ple_stat[33] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR); |
| 7157 | + ple_stat[34] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR); |
| 7158 | + ple_stat[35] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR); |
| 7159 | + ple_stat[36] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR); |
| 7160 | +} |
| 7161 | + |
| 7162 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7163 | +besra_get_ple_txcmd_stat(struct besra_dev *dev, u32 *ple_txcmd_stat) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7164 | +{ |
| 7165 | + *ple_txcmd_stat = mt76_rr(dev, WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR); |
| 7166 | +} |
| 7167 | + |
| 7168 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7169 | +besra_get_dis_sta_map(struct besra_dev *dev, u32 *dis_sta_map) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7170 | +{ |
| 7171 | + dis_sta_map[0] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP0_ADDR); |
| 7172 | + dis_sta_map[1] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP1_ADDR); |
| 7173 | + dis_sta_map[2] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP2_ADDR); |
| 7174 | + dis_sta_map[3] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP3_ADDR); |
| 7175 | + dis_sta_map[4] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP4_ADDR); |
| 7176 | + dis_sta_map[5] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP5_ADDR); |
| 7177 | + dis_sta_map[6] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP6_ADDR); |
| 7178 | + dis_sta_map[7] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP7_ADDR); |
| 7179 | + dis_sta_map[8] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP8_ADDR); |
| 7180 | +} |
| 7181 | + |
| 7182 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7183 | +besra_get_sta_pause(struct besra_dev *dev, u32 *sta_pause) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7184 | +{ |
| 7185 | + /* BELLWETHER TODO: Wait MIB counter API implement complete */ |
| 7186 | +} |
| 7187 | + |
| 7188 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7189 | +besra_show_sta_acq_info(struct seq_file *s, u32 *ple_stat, |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7190 | + u32 *sta_pause, u32 *dis_sta_map, |
| 7191 | + u32 dumptxd) |
| 7192 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7193 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7194 | + int i, j; |
| 7195 | + u32 total_nonempty_cnt = 0; |
| 7196 | + |
| 7197 | + for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { /* show AC Q info */ |
| 7198 | + for (i = 0; i < 32; i++) { |
| 7199 | + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { |
| 7200 | + u32 hfid, tfid, pktcnt, ac_num = j / CR_NUM_OF_AC, ctrl = 0; |
| 7201 | + u32 sta_num = i + (j % CR_NUM_OF_AC) * 32, fl_que_ctrl[3] = {0}; |
| 7202 | + u32 wmmidx = 0; |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7203 | + struct besra_sta *msta; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7204 | + struct mt76_wcid *wcid; |
| 7205 | + struct ieee80211_sta *sta = NULL; |
| 7206 | + |
| 7207 | + wcid = rcu_dereference(dev->mt76.wcid[sta_num]); |
| 7208 | + sta = wcid_to_sta(wcid); |
| 7209 | + if (!sta) { |
| 7210 | + printk("ERROR!! no found STA wcid=%d\n", sta_num); |
| 7211 | + return 0; |
| 7212 | + } |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7213 | + msta = container_of(wcid, struct besra_sta, wcid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7214 | + wmmidx = msta->vif->mt76.wmm_idx; |
| 7215 | + |
| 7216 | + printk("\tSTA%d AC%d: ", sta_num, ac_num); |
| 7217 | + |
| 7218 | + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| 7219 | + fl_que_ctrl[1] |= (ENUM_UMAC_LMAC_PORT_2 << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| 7220 | + fl_que_ctrl[0] |= (ac_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| 7221 | + fl_que_ctrl[0] |= (sta_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT); |
| 7222 | + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| 7223 | + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| 7224 | + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); |
| 7225 | + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); |
| 7226 | + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> |
| 7227 | + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| 7228 | + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> |
| 7229 | + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| 7230 | + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> |
| 7231 | + WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| 7232 | + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x", |
| 7233 | + tfid, hfid, pktcnt); |
| 7234 | + |
| 7235 | + if (((sta_pause[j % CR_NUM_OF_AC] & 0x1 << i) >> i) == 1) |
| 7236 | + ctrl = 2; |
| 7237 | + |
| 7238 | + if (((dis_sta_map[j % CR_NUM_OF_AC] & 0x1 << i) >> i) == 1) |
| 7239 | + ctrl = 1; |
| 7240 | + |
| 7241 | + printk(" ctrl = %s", sta_ctrl_reg[ctrl]); |
| 7242 | + printk(" (wmmidx=%d)\n", wmmidx); |
| 7243 | + |
| 7244 | + total_nonempty_cnt++; |
| 7245 | + |
| 7246 | + if (pktcnt > 0 && dumptxd > 0) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7247 | + besra_dump_bmac_txd_by_fid(hfid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7248 | + } |
| 7249 | + } |
| 7250 | + } |
| 7251 | + |
| 7252 | + return total_nonempty_cnt; |
| 7253 | +} |
| 7254 | + |
| 7255 | +static void |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7256 | +besra_show_txcmdq_info(struct seq_file *s, u32 ple_txcmd_stat) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7257 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7258 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7259 | + int i; |
| 7260 | + |
| 7261 | + printk("Nonempty TXCMD Q info:\n"); |
| 7262 | + for (i = 0; i < 32 ; i++) { |
| 7263 | + if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) { |
| 7264 | + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| 7265 | + |
| 7266 | + if (ple_txcmd_queue_empty_info[i].QueueName != NULL) { |
| 7267 | + printk("\t%s: ", ple_txcmd_queue_empty_info[i].QueueName); |
| 7268 | + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| 7269 | + fl_que_ctrl[1] |= (ple_txcmd_queue_empty_info[i].Portid << |
| 7270 | + WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| 7271 | + fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid << |
| 7272 | + WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| 7273 | + } else |
| 7274 | + continue; |
| 7275 | + |
| 7276 | + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| 7277 | + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| 7278 | + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); |
| 7279 | + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); |
| 7280 | + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> |
| 7281 | + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| 7282 | + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> |
| 7283 | + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| 7284 | + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> |
| 7285 | + WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| 7286 | + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| 7287 | + tfid, hfid, pktcnt); |
| 7288 | + } |
| 7289 | + } |
| 7290 | +} |
| 7291 | + |
| 7292 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7293 | +besra_pleinfo_read(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7294 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7295 | + struct besra_dev *dev = dev_get_drvdata(s->private); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7296 | + u32 ple_buf_ctrl, pg_sz, pg_num; |
| 7297 | + u32 ple_stat[ALL_CR_NUM_OF_ALL_AC + 1] = {0}, pg_flow_ctrl[10] = {0}; |
| 7298 | + u32 ple_native_txcmd_stat; |
| 7299 | + u32 ple_txcmd_stat; |
| 7300 | + u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0}; |
| 7301 | + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q; |
| 7302 | + u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu; |
| 7303 | + int i, j; |
| 7304 | + u32 dumptxd = 1; |
| 7305 | + |
| 7306 | + ple_buf_ctrl = mt76_rr(dev, WF_PLE_TOP_PBUF_CTRL_ADDR); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7307 | + besra_get_ple_acq_stat(dev, ple_stat); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7308 | + ple_txcmd_stat = mt76_rr(dev, WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7309 | + besra_get_ple_txcmd_stat(dev, &ple_native_txcmd_stat); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7310 | + pg_flow_ctrl[0] = mt76_rr(dev, WF_PLE_TOP_FREEPG_CNT_ADDR); |
| 7311 | + pg_flow_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR); |
| 7312 | + pg_flow_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_GROUP_ADDR); |
| 7313 | + pg_flow_ctrl[3] = mt76_rr(dev, WF_PLE_TOP_HIF_PG_INFO_ADDR); |
| 7314 | + pg_flow_ctrl[4] = mt76_rr(dev, WF_PLE_TOP_PG_CPU_GROUP_ADDR); |
| 7315 | + pg_flow_ctrl[5] = mt76_rr(dev, WF_PLE_TOP_CPU_PG_INFO_ADDR); |
| 7316 | + pg_flow_ctrl[6] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR); |
| 7317 | + pg_flow_ctrl[7] = mt76_rr(dev, WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR); |
| 7318 | + pg_flow_ctrl[8] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR); |
| 7319 | + pg_flow_ctrl[9] = mt76_rr(dev, WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR); |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7320 | + besra_get_dis_sta_map(dev, dis_sta_map); |
| 7321 | + besra_get_sta_pause(dev, sta_pause); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7322 | + |
| 7323 | + /* Configuration Info */ |
| 7324 | + printk("PLE Configuration Info:\n"); |
| 7325 | + printk("\tPacket Buffer Control(0x82060014): 0x%08x\n", ple_buf_ctrl); |
| 7326 | + pg_sz = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; |
| 7327 | + printk("\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 128 : 64)); |
| 7328 | + printk("\t\tPage Offset=%d(in unit of 2KB)\n", |
| 7329 | + (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); |
| 7330 | + pg_num = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; |
| 7331 | + printk("\t\tTotal Page=%d pages\n", pg_num); |
| 7332 | + |
| 7333 | + /* Page Flow Control */ |
| 7334 | + printk("PLE Page Flow Control:\n"); |
| 7335 | + printk("\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); |
| 7336 | + fpg_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; |
| 7337 | + printk("\t\tThe toal page number of free=0x%03x\n", fpg_cnt); |
| 7338 | + ffa_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT; |
| 7339 | + printk("\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt); |
| 7340 | + printk("\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); |
| 7341 | + fpg_head = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; |
| 7342 | + fpg_tail = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; |
| 7343 | + printk("\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head); |
| 7344 | + printk("\tReserved page counter of HIF group: 0x%08x\n", pg_flow_ctrl[2]); |
| 7345 | + printk("\tHIF group page status: 0x%08x\n", pg_flow_ctrl[3]); |
| 7346 | + hif_min_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT; |
| 7347 | + hif_max_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT; |
| 7348 | + printk("\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q); |
| 7349 | + rpg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT; |
| 7350 | + upg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT; |
| 7351 | + printk("\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif); |
| 7352 | + |
| 7353 | + printk("\tReserved page counter of WMTXD group: 0x%08x\n", pg_flow_ctrl[8]); |
| 7354 | + printk("\tWMTXD group page status: 0x%08x\n", pg_flow_ctrl[9]); |
| 7355 | + cpu_min_q = (pg_flow_ctrl[8] & WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT; |
| 7356 | + cpu_max_q = (pg_flow_ctrl[8] & WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT; |
| 7357 | + printk("\t\tThe max/min quota pages of WMTXD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); |
| 7358 | + rpg_cpu = (pg_flow_ctrl[9] & WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT; |
| 7359 | + upg_cpu = (pg_flow_ctrl[9] & WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT; |
| 7360 | + printk("\t\tThe used/reserved pages of WMTXD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); |
| 7361 | + |
| 7362 | + printk("\tReserved page counter of HIF_TXCMD group: 0x%08x\n", pg_flow_ctrl[6]); |
| 7363 | + printk("\tHIF_TXCMD group page status: 0x%08x\n", pg_flow_ctrl[7]); |
| 7364 | + cpu_min_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT; |
| 7365 | + cpu_max_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT; |
| 7366 | + printk("\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); |
| 7367 | + rpg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT; |
| 7368 | + upg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT; |
| 7369 | + printk("\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); |
| 7370 | + |
| 7371 | + printk("\tReserved page counter of CPU group(0x820c0150): 0x%08x\n", pg_flow_ctrl[4]); |
| 7372 | + printk("\tCPU group page status(0x820c0154): 0x%08x\n", pg_flow_ctrl[5]); |
| 7373 | + cpu_min_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT; |
| 7374 | + cpu_max_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT; |
| 7375 | + printk("\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); |
| 7376 | + rpg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT; |
| 7377 | + upg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT; |
| 7378 | + printk("\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); |
| 7379 | + |
| 7380 | + if ((ple_stat[0] & WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK) == 0) { |
| 7381 | + for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { |
| 7382 | + if (j % CR_NUM_OF_AC == 0) { |
| 7383 | + printk("\n\tNonempty AC%d Q of STA#: ", j / CR_NUM_OF_AC); |
| 7384 | + } |
| 7385 | + |
| 7386 | + for (i = 0; i < 32; i++) { |
| 7387 | + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { |
| 7388 | + printk("%d ", i + (j % CR_NUM_OF_AC) * 32); |
| 7389 | + } |
| 7390 | + } |
| 7391 | + } |
| 7392 | + |
| 7393 | + printk("\n"); |
| 7394 | + } |
| 7395 | + |
| 7396 | + printk("non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat); |
| 7397 | + |
| 7398 | + printk("Nonempty Q info:\n"); |
| 7399 | + |
| 7400 | + for (i = 0; i < 32; i++) { |
| 7401 | + if (((ple_stat[0] & (0x1 << i)) >> i) == 0) { |
| 7402 | + u32 hfid, tfid, pktcnt, waitcnt = 3, fl_que_ctrl[3] = {0}; |
| 7403 | + |
| 7404 | + if (ple_queue_empty_info[i].QueueName != NULL) { |
| 7405 | + printk("\t%s: ", ple_queue_empty_info[i].QueueName); |
| 7406 | + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| 7407 | + fl_que_ctrl[1] |= (ple_queue_empty_info[i].Portid << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| 7408 | + fl_que_ctrl[1] |= (ple_queue_empty_info[i].tgid << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT); |
| 7409 | + /* Bellwether HW issue, Queueid need + (4 * band_idx) */ |
| 7410 | + fl_que_ctrl[0] |= ((ple_queue_empty_info[i].Queueid + 4 * ple_queue_empty_info[i].tgid) |
| 7411 | + << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| 7412 | + } else |
| 7413 | + continue; |
| 7414 | + |
| 7415 | + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| 7416 | + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| 7417 | + |
| 7418 | + do { |
| 7419 | + /* Polling if HW done (0 = Done, 1 = Not done) */ |
| 7420 | + fl_que_ctrl[0] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR); |
| 7421 | + fl_que_ctrl[0] &= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| 7422 | + waitcnt -= 1; |
| 7423 | + } while (fl_que_ctrl[0] && waitcnt); |
| 7424 | + |
| 7425 | + if (fl_que_ctrl[0] && waitcnt == 0) { |
| 7426 | + printk("Polling HW too many times, drop information\n"); |
| 7427 | + continue; |
| 7428 | + } |
| 7429 | + |
| 7430 | + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); |
| 7431 | + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); |
| 7432 | + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| 7433 | + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| 7434 | + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| 7435 | + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| 7436 | + tfid, hfid, pktcnt); |
| 7437 | + |
| 7438 | + if (pktcnt > 0 && dumptxd > 0) |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7439 | + besra_dump_bmac_txd_by_fid(hfid); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7440 | + } |
| 7441 | + } |
| 7442 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7443 | + besra_show_sta_acq_info(s, ple_stat, sta_pause, dis_sta_map, dumptxd); |
| 7444 | + besra_show_txcmdq_info(s, ple_native_txcmd_stat); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7445 | + |
| 7446 | + return true; |
| 7447 | +} |
| 7448 | + |
| 7449 | +/* DRR */ |
| 7450 | +static int |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7451 | +besra_drr_info(struct seq_file *s, void *data) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7452 | +{ |
| 7453 | + /* BELLWETHER TODO: Wait MIB counter API implement complete */ |
| 7454 | + return 0; |
| 7455 | +} |
| 7456 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7457 | +int besra_mtk_init_debugfs(struct besra_phy *phy, struct dentry *dir) |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7458 | +{ |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7459 | + struct besra_dev *dev = phy->dev; |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7460 | + |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7461 | + besra_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7462 | + |
| 7463 | + debugfs_create_file("fw_debug_module", 0600, dir, dev, |
| 7464 | + &fops_fw_debug_module); |
| 7465 | + debugfs_create_file("fw_debug_level", 0600, dir, dev, |
| 7466 | + &fops_fw_debug_level); |
| 7467 | + |
| 7468 | + debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7469 | + besra_wtbl_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7470 | + |
| 7471 | + debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7472 | + besra_trinfo_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7473 | + |
| 7474 | + debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7475 | + besra_drr_info); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7476 | + |
| 7477 | + debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7478 | + besra_pleinfo_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7479 | + |
| 7480 | + debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7481 | + besra_pseinfo_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7482 | + |
| 7483 | + debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7484 | + besra_mibinfo_band0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7485 | + debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7486 | + besra_mibinfo_band1); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7487 | + debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info2", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7488 | + besra_mibinfo_band2); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7489 | + |
| 7490 | + debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx); |
| 7491 | + debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7492 | + besra_token_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7493 | + debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7494 | + besra_token_txd_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7495 | + debugfs_create_u32("txd_dump", 0600, dir, &dev->dbg.txd_read_cnt); |
| 7496 | + debugfs_create_u32("rxd_dump", 0600, dir, &dev->dbg.rxd_read_cnt); |
| 7497 | + |
| 7498 | + debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7499 | + besra_amsdu_read); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7500 | + |
| 7501 | + debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7502 | + besra_agginfo_read_band0); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7503 | + debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7504 | + besra_agginfo_read_band1); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7505 | + debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info2", dir, |
developer | 7800b8d | 2022-06-23 22:15:56 +0800 | [diff] [blame] | 7506 | + besra_agginfo_read_band2); |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7507 | + |
| 7508 | + return 0; |
| 7509 | +} |
| 7510 | + |
| 7511 | +#endif |
| 7512 | diff --git a/tools/fwlog.c b/tools/fwlog.c |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 7513 | index e5d4a105..3c6a61d7 100644 |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7514 | --- a/tools/fwlog.c |
| 7515 | +++ b/tools/fwlog.c |
| 7516 | @@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file) |
| 7517 | return path; |
| 7518 | } |
| 7519 | |
| 7520 | -static int mt76_set_fwlog_en(const char *phyname, bool en) |
| 7521 | +static int mt76_set_fwlog_en(const char *phyname, bool en, char *val) |
| 7522 | { |
| 7523 | FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w"); |
| 7524 | |
| 7525 | @@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en) |
| 7526 | return 1; |
| 7527 | } |
| 7528 | |
| 7529 | - fprintf(f, "7"); |
| 7530 | + if (en && val) |
| 7531 | + fprintf(f, "%s", val); |
| 7532 | + else if (en) |
| 7533 | + fprintf(f, "7"); |
| 7534 | + else |
| 7535 | + fprintf(f, "0"); |
| 7536 | + |
| 7537 | fclose(f); |
| 7538 | |
| 7539 | return 0; |
| 7540 | @@ -76,6 +82,7 @@ static void handle_signal(int sig) |
| 7541 | |
| 7542 | int mt76_fwlog(const char *phyname, int argc, char **argv) |
| 7543 | { |
| 7544 | +#define BUF_SIZE 1504 |
| 7545 | struct sockaddr_in local = { |
| 7546 | .sin_family = AF_INET, |
| 7547 | .sin_addr.s_addr = INADDR_ANY, |
| 7548 | @@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| 7549 | .sin_family = AF_INET, |
| 7550 | .sin_port = htons(55688), |
| 7551 | }; |
| 7552 | - char buf[1504]; |
| 7553 | + char *buf = calloc(BUF_SIZE, sizeof(char)); |
| 7554 | int ret = 0; |
| 7555 | - int yes = 1; |
| 7556 | + /* int yes = 1; */ |
| 7557 | int s, fd; |
| 7558 | |
| 7559 | if (argc < 1) { |
| 7560 | @@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| 7561 | return 1; |
| 7562 | } |
| 7563 | |
| 7564 | - setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); |
| 7565 | + /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */ |
| 7566 | if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) { |
| 7567 | perror("bind"); |
| 7568 | return 1; |
| 7569 | } |
| 7570 | |
| 7571 | - if (mt76_set_fwlog_en(phyname, true)) |
| 7572 | + if (mt76_set_fwlog_en(phyname, true, argv[1])) |
| 7573 | return 1; |
| 7574 | |
| 7575 | fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY); |
| 7576 | @@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| 7577 | if (!r) |
| 7578 | continue; |
| 7579 | |
| 7580 | - if (len > sizeof(buf)) { |
| 7581 | - fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf)); |
| 7582 | + if (len > BUF_SIZE) { |
| 7583 | + fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE); |
| 7584 | ret = 1; |
| 7585 | break; |
| 7586 | } |
| 7587 | @@ -171,7 +178,7 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| 7588 | close(fd); |
| 7589 | |
| 7590 | out: |
| 7591 | - mt76_set_fwlog_en(phyname, false); |
| 7592 | + mt76_set_fwlog_en(phyname, false, NULL); |
| 7593 | |
| 7594 | return ret; |
| 7595 | } |
| 7596 | -- |
developer | 5909dd5 | 2022-05-09 15:44:17 +0800 | [diff] [blame] | 7597 | 2.18.0 |
developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 7598 | |