developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986b.dtsi" |
| 3 | #include "mt7986b-pinctrl.dtsi" |
| 4 | #include "mt7986-spim-nand-partition.dtsi" |
| 5 | / { |
| 6 | model = "MediaTek MT7986b gsw RFB"; |
developer | bd0dd0e | 2022-04-18 18:28:19 +0800 | [diff] [blame] | 7 | compatible = "mediatek,mt7986b-2500wan-gsw-spim-snand-rfb"; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 8 | chosen { |
| 9 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 10 | earlycon=uart8250,mmio32,0x11002000"; |
| 11 | }; |
| 12 | |
| 13 | gsw: gsw@0 { |
| 14 | compatible = "mediatek,mt753x"; |
| 15 | mediatek,ethsys = <ðsys>; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | }; |
| 19 | |
| 20 | memory { |
| 21 | reg = <0 0x40000000 0 0x10000000>; |
| 22 | }; |
| 23 | }; |
| 24 | |
| 25 | &uart0 { |
| 26 | status = "okay"; |
| 27 | }; |
| 28 | |
| 29 | /* Warning: pins shared with &snand */ |
| 30 | &uart1 { |
| 31 | pinctrl-names = "default"; |
| 32 | pinctrl-0 = <&uart1_pins>; |
| 33 | status = "disabled"; |
| 34 | }; |
| 35 | |
| 36 | /* Warning: pins shared with &spi1 */ |
| 37 | &uart2 { |
| 38 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&uart2_pins>; |
| 40 | status = "disabled"; |
| 41 | }; |
| 42 | |
| 43 | &i2c0 { |
| 44 | pinctrl-names = "default"; |
| 45 | pinctrl-0 = <&i2c_pins>; |
| 46 | status = "okay"; |
| 47 | }; |
| 48 | |
| 49 | &watchdog { |
| 50 | status = "okay"; |
| 51 | }; |
| 52 | |
| 53 | ð { |
| 54 | status = "okay"; |
| 55 | |
| 56 | gmac0: mac@0 { |
| 57 | compatible = "mediatek,eth-mac"; |
| 58 | reg = <0>; |
| 59 | phy-mode = "2500base-x"; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 60 | |
| 61 | fixed-link { |
| 62 | speed = <2500>; |
| 63 | full-duplex; |
| 64 | pause; |
| 65 | link-gpio = <&pio 47 0>; |
| 66 | phy-handle = <&phy5>; |
| 67 | label = "lan5"; |
| 68 | }; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 69 | }; |
| 70 | |
| 71 | gmac1: mac@1 { |
| 72 | compatible = "mediatek,eth-mac"; |
| 73 | reg = <1>; |
| 74 | phy-mode = "2500base-x"; |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 75 | phy-handle = <&phy6>; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | mdio: mdio-bus { |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <0>; |
| 81 | |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 82 | reset-gpios = <&pio 6 1>; |
| 83 | reset-delay-us = <600>; |
| 84 | |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 85 | phy5: phy@5 { |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 86 | compatible = "ethernet-phy-id67c9.de0a"; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 87 | reg = <5>; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | phy6: phy@6 { |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 91 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 92 | reg = <6>; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 93 | }; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 94 | }; |
| 95 | }; |
| 96 | |
| 97 | &gsw { |
| 98 | mediatek,mdio = <&mdio>; |
| 99 | mediatek,portmap = "lllll"; |
| 100 | mediatek,mdio_master_pinmux = <1>; |
| 101 | reset-gpios = <&pio 5 0>; |
| 102 | interrupt-parent = <&pio>; |
| 103 | interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; |
| 104 | status = "okay"; |
| 105 | |
| 106 | port5: port@5 { |
| 107 | compatible = "mediatek,mt753x-port"; |
| 108 | reg = <5>; |
| 109 | phy-mode = "sgmii"; |
| 110 | |
| 111 | fixed-link { |
| 112 | speed = <2500>; |
| 113 | full-duplex; |
| 114 | }; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 115 | }; |
| 116 | |
| 117 | port6: port@6 { |
| 118 | compatible = "mediatek,mt753x-port"; |
developer | 3c21f19 | 2022-03-14 20:37:51 +0800 | [diff] [blame] | 119 | /* mediatek,ssc-on; */ |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 120 | reg = <6>; |
| 121 | phy-mode = "sgmii"; |
| 122 | fixed-link { |
| 123 | speed = <2500>; |
| 124 | full-duplex; |
| 125 | }; |
| 126 | }; |
| 127 | }; |
| 128 | |
| 129 | &hnat { |
| 130 | mtketh-wan = "eth1"; |
developer | 3c21f19 | 2022-03-14 20:37:51 +0800 | [diff] [blame] | 131 | mtketh-lan = "eth0"; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 132 | mtketh-max-gmac = <2>; |
| 133 | status = "okay"; |
| 134 | }; |
| 135 | |
| 136 | &spi0 { |
| 137 | pinctrl-names = "default"; |
| 138 | pinctrl-0 = <&spi_flash_pins>; |
| 139 | cs-gpios = <0>, <0>; |
| 140 | status = "okay"; |
| 141 | |
| 142 | spi_nor@0 { |
| 143 | #address-cells = <1>; |
| 144 | #size-cells = <1>; |
| 145 | compatible = "jedec,spi-nor"; |
| 146 | reg = <0>; |
| 147 | spi-max-frequency = <20000000>; |
| 148 | spi-tx-buswidth = <4>; |
| 149 | spi-rx-buswidth = <4>; |
| 150 | }; |
| 151 | |
| 152 | spi_nand: spi_nand@1 { |
| 153 | #address-cells = <1>; |
| 154 | #size-cells = <1>; |
| 155 | compatible = "spi-nand"; |
| 156 | reg = <1>; |
| 157 | spi-max-frequency = <20000000>; |
| 158 | spi-tx-buswidth = <4>; |
| 159 | spi-rx-buswidth = <4>; |
| 160 | }; |
| 161 | }; |
| 162 | |
| 163 | /* Warning: pins shared with &uart2 */ |
| 164 | &spi1 { |
| 165 | pinctrl-names = "default"; |
| 166 | pinctrl-0 = <&spic_pins>; |
| 167 | status = "okay"; |
| 168 | }; |
| 169 | |
| 170 | &wbsys { |
| 171 | mediatek,mtd-eeprom = <&factory 0x0000>; |
| 172 | status = "okay"; |
| 173 | }; |
| 174 | |
| 175 | &pio { |
| 176 | spi_flash_pins: spi-flash-pins-33-to-38 { |
| 177 | mux { |
| 178 | function = "flash"; |
| 179 | groups = "spi0", "spi0_wp_hold"; |
| 180 | }; |
| 181 | conf-pu { |
| 182 | pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| 183 | drive-strength = <MTK_DRIVE_8mA>; |
developer | b5a819c | 2022-05-16 19:16:07 +0800 | [diff] [blame] | 184 | bias-pull-up = <MTK_PUPD_SET_R1R0_11>; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 185 | }; |
| 186 | conf-pd { |
| 187 | pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| 188 | drive-strength = <MTK_DRIVE_8mA>; |
developer | b5a819c | 2022-05-16 19:16:07 +0800 | [diff] [blame] | 189 | bias-pull-down = <MTK_PUPD_SET_R1R0_11>; |
developer | 1b76b3f | 2021-12-22 19:53:19 +0800 | [diff] [blame] | 190 | }; |
| 191 | |
| 192 | }; |
| 193 | }; |