developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 1 | From fba2423026ba723423ab2bab81e60eba4448ba57 Mon Sep 17 00:00:00 2001 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 2 | From: Sujuan Chen <sujuan.chen@mediatek.com> |
| 3 | Date: Tue, 12 Apr 2022 15:58:28 +0800 |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 4 | Subject: [PATCH 5/5] mt76:remove WED support patch for build err |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 5 | |
| 6 | Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com> |
| 7 | --- |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 8 | drivers/net/wireless/mediatek/mt76/dma.c | 160 ++++-------------- |
| 9 | drivers/net/wireless/mediatek/mt76/mac80211.c | 4 +- |
| 10 | drivers/net/wireless/mediatek/mt76/mmio.c | 9 +- |
| 11 | drivers/net/wireless/mediatek/mt76/mt76.h | 25 +-- |
| 12 | .../net/wireless/mediatek/mt76/mt7603/dma.c | 8 +- |
| 13 | .../net/wireless/mediatek/mt76/mt7615/dma.c | 6 +- |
| 14 | .../net/wireless/mediatek/mt76/mt76x02_mmio.c | 4 +- |
| 15 | .../net/wireless/mediatek/mt76/mt7915/dma.c | 43 +---- |
| 16 | .../net/wireless/mediatek/mt76/mt7915/mac.c | 129 +++----------- |
| 17 | .../net/wireless/mediatek/mt76/mt7915/mac.h | 2 - |
| 18 | .../net/wireless/mediatek/mt76/mt7915/main.c | 36 ---- |
| 19 | .../net/wireless/mediatek/mt76/mt7915/mcu.c | 3 - |
| 20 | .../net/wireless/mediatek/mt76/mt7915/mmio.c | 29 +--- |
| 21 | .../wireless/mediatek/mt76/mt7915/mt7915.h | 2 - |
| 22 | .../net/wireless/mediatek/mt76/mt7915/pci.c | 96 +---------- |
| 23 | .../net/wireless/mediatek/mt76/mt7915/regs.h | 17 +- |
| 24 | .../net/wireless/mediatek/mt76/mt7921/dma.c | 2 +- |
| 25 | drivers/net/wireless/mediatek/mt76/tx.c | 16 +- |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 26 | 18 files changed, 94 insertions(+), 497 deletions(-) |
| 27 | |
| 28 | diff --git a/dma.c b/dma.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 29 | index f6f5f129..3f7456b1 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 30 | --- a/dma.c |
| 31 | +++ b/dma.c |
| 32 | @@ -7,36 +7,9 @@ |
| 33 | #include "mt76.h" |
| 34 | #include "dma.h" |
| 35 | |
| 36 | -#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) |
| 37 | - |
| 38 | -#define Q_READ(_dev, _q, _field) ({ \ |
| 39 | - u32 _offset = offsetof(struct mt76_queue_regs, _field); \ |
| 40 | - u32 _val; \ |
| 41 | - if ((_q)->flags & MT_QFLAG_WED) \ |
| 42 | - _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \ |
| 43 | - ((_q)->wed_regs + \ |
| 44 | - _offset)); \ |
| 45 | - else \ |
| 46 | - _val = readl(&(_q)->regs->_field); \ |
| 47 | - _val; \ |
| 48 | -}) |
| 49 | - |
| 50 | -#define Q_WRITE(_dev, _q, _field, _val) do { \ |
| 51 | - u32 _offset = offsetof(struct mt76_queue_regs, _field); \ |
| 52 | - if ((_q)->flags & MT_QFLAG_WED) \ |
| 53 | - mtk_wed_device_reg_write(&(_dev)->mmio.wed, \ |
| 54 | - ((_q)->wed_regs + _offset), \ |
| 55 | - _val); \ |
| 56 | - else \ |
| 57 | - writel(_val, &(_q)->regs->_field); \ |
| 58 | -} while (0) |
| 59 | - |
| 60 | -#else |
| 61 | - |
| 62 | -#define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field) |
| 63 | -#define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field) |
| 64 | +#define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field) |
| 65 | +#define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field) |
| 66 | |
| 67 | -#endif |
| 68 | |
| 69 | static struct mt76_txwi_cache * |
| 70 | mt76_alloc_txwi(struct mt76_dev *dev) |
| 71 | @@ -138,6 +111,36 @@ mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) |
| 72 | mt76_dma_sync_idx(dev, q); |
| 73 | } |
| 74 | |
| 75 | +static int |
| 76 | +mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, |
| 77 | + int idx, int n_desc, int bufsize, |
| 78 | + u32 ring_base) |
| 79 | +{ |
| 80 | + int size; |
| 81 | + |
| 82 | + spin_lock_init(&q->lock); |
| 83 | + spin_lock_init(&q->cleanup_lock); |
| 84 | + |
| 85 | + q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; |
| 86 | + q->ndesc = n_desc; |
| 87 | + q->buf_size = bufsize; |
| 88 | + q->hw_idx = idx; |
| 89 | + |
| 90 | + size = q->ndesc * sizeof(struct mt76_desc); |
| 91 | + q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL); |
| 92 | + if (!q->desc) |
| 93 | + return -ENOMEM; |
| 94 | + |
| 95 | + size = q->ndesc * sizeof(*q->entry); |
| 96 | + q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); |
| 97 | + if (!q->entry) |
| 98 | + return -ENOMEM; |
| 99 | + |
| 100 | + mt76_dma_queue_reset(dev, q); |
| 101 | + |
| 102 | + return 0; |
| 103 | +} |
| 104 | + |
| 105 | static int |
| 106 | mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, |
| 107 | struct mt76_queue_buf *buf, int nbufs, u32 info, |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 108 | @@ -482,85 +485,6 @@ mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 109 | return frames; |
| 110 | } |
| 111 | |
| 112 | -static int |
| 113 | -mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q) |
| 114 | -{ |
| 115 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 116 | - struct mtk_wed_device *wed = &dev->mmio.wed; |
| 117 | - int ret, type, ring; |
| 118 | - u8 flags = q->flags; |
| 119 | - |
| 120 | - if (!mtk_wed_device_active(wed)) |
| 121 | - q->flags &= ~MT_QFLAG_WED; |
| 122 | - |
| 123 | - if (!(q->flags & MT_QFLAG_WED)) |
| 124 | - return 0; |
| 125 | - |
| 126 | - type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags); |
| 127 | - ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags); |
| 128 | - |
| 129 | - switch (type) { |
| 130 | - case MT76_WED_Q_TX: |
| 131 | - ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs); |
| 132 | - if (!ret) |
| 133 | - q->wed_regs = wed->tx_ring[ring].reg_base; |
| 134 | - break; |
| 135 | - case MT76_WED_Q_TXFREE: |
| 136 | - /* WED txfree queue needs ring to be initialized before setup */ |
| 137 | - q->flags = 0; |
| 138 | - mt76_dma_queue_reset(dev, q); |
| 139 | - mt76_dma_rx_fill(dev, q); |
| 140 | - q->flags = flags; |
| 141 | - |
| 142 | - ret = mtk_wed_device_txfree_ring_setup(wed, q->regs); |
| 143 | - if (!ret) |
| 144 | - q->wed_regs = wed->txfree_ring.reg_base; |
| 145 | - break; |
| 146 | - default: |
| 147 | - ret = -EINVAL; |
| 148 | - } |
| 149 | - |
| 150 | - return ret; |
| 151 | -#else |
| 152 | - return 0; |
| 153 | -#endif |
| 154 | -} |
| 155 | - |
| 156 | -static int |
| 157 | -mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, |
| 158 | - int idx, int n_desc, int bufsize, |
| 159 | - u32 ring_base) |
| 160 | -{ |
| 161 | - int ret, size; |
| 162 | - |
| 163 | - spin_lock_init(&q->lock); |
| 164 | - spin_lock_init(&q->cleanup_lock); |
| 165 | - |
| 166 | - q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; |
| 167 | - q->ndesc = n_desc; |
| 168 | - q->buf_size = bufsize; |
| 169 | - q->hw_idx = idx; |
| 170 | - |
| 171 | - size = q->ndesc * sizeof(struct mt76_desc); |
| 172 | - q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL); |
| 173 | - if (!q->desc) |
| 174 | - return -ENOMEM; |
| 175 | - |
| 176 | - size = q->ndesc * sizeof(*q->entry); |
| 177 | - q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); |
| 178 | - if (!q->entry) |
| 179 | - return -ENOMEM; |
| 180 | - |
| 181 | - ret = mt76_dma_wed_setup(dev, q); |
| 182 | - if (ret) |
| 183 | - return ret; |
| 184 | - |
| 185 | - if (q->flags != MT_WED_Q_TXFREE) |
| 186 | - mt76_dma_queue_reset(dev, q); |
| 187 | - |
| 188 | - return 0; |
| 189 | -} |
| 190 | - |
| 191 | static void |
| 192 | mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) |
| 193 | { |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 194 | @@ -642,29 +566,14 @@ mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 195 | static int |
| 196 | mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) |
| 197 | { |
| 198 | - int len, data_len, done = 0, dma_idx; |
| 199 | + int len, data_len, done = 0; |
| 200 | struct sk_buff *skb; |
| 201 | unsigned char *data; |
| 202 | - bool check_ddone = false; |
| 203 | bool more; |
| 204 | |
| 205 | - if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && |
| 206 | - q->flags == MT_WED_Q_TXFREE) { |
| 207 | - dma_idx = Q_READ(dev, q, dma_idx); |
| 208 | - check_ddone = true; |
| 209 | - } |
| 210 | - |
| 211 | while (done < budget) { |
| 212 | u32 info; |
| 213 | |
| 214 | - if (check_ddone) { |
| 215 | - if (q->tail == dma_idx) |
| 216 | - dma_idx = Q_READ(dev, q, dma_idx); |
| 217 | - |
| 218 | - if (q->tail == dma_idx) |
| 219 | - break; |
| 220 | - } |
| 221 | - |
| 222 | data = mt76_dma_dequeue(dev, q, false, &len, &info, &more); |
| 223 | if (!data) |
| 224 | break; |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 225 | @@ -805,8 +714,5 @@ void mt76_dma_cleanup(struct mt76_dev *dev) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | mt76_free_pending_txwi(dev); |
| 229 | - |
| 230 | - if (mtk_wed_device_active(&dev->mmio.wed)) |
| 231 | - mtk_wed_device_detach(&dev->mmio.wed); |
| 232 | } |
| 233 | EXPORT_SYMBOL_GPL(mt76_dma_cleanup); |
| 234 | diff --git a/mac80211.c b/mac80211.c |
developer | beb7437 | 2022-05-06 16:53:33 +0800 | [diff] [blame] | 235 | index e17b04b1..1b9a400b 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 236 | --- a/mac80211.c |
| 237 | +++ b/mac80211.c |
developer | beb7437 | 2022-05-06 16:53:33 +0800 | [diff] [blame] | 238 | @@ -1594,7 +1594,7 @@ EXPORT_SYMBOL_GPL(mt76_get_antenna); |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 239 | |
| 240 | struct mt76_queue * |
| 241 | mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, |
| 242 | - int ring_base, u32 flags) |
| 243 | + int ring_base) |
| 244 | { |
| 245 | struct mt76_queue *hwq; |
| 246 | int err; |
developer | beb7437 | 2022-05-06 16:53:33 +0800 | [diff] [blame] | 247 | @@ -1603,8 +1603,6 @@ mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 248 | if (!hwq) |
| 249 | return ERR_PTR(-ENOMEM); |
| 250 | |
| 251 | - hwq->flags = flags; |
| 252 | - |
| 253 | err = dev->queue_ops->alloc(dev, hwq, idx, n_desc, 0, ring_base); |
| 254 | if (err < 0) |
| 255 | return ERR_PTR(err); |
| 256 | diff --git a/mmio.c b/mmio.c |
| 257 | index 86e3d2ac..26353b6b 100644 |
| 258 | --- a/mmio.c |
| 259 | +++ b/mmio.c |
| 260 | @@ -73,13 +73,8 @@ void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, |
| 261 | spin_lock_irqsave(&dev->mmio.irq_lock, flags); |
| 262 | dev->mmio.irqmask &= ~clear; |
| 263 | dev->mmio.irqmask |= set; |
| 264 | - if (addr) { |
| 265 | - if (mtk_wed_device_active(&dev->mmio.wed)) |
| 266 | - mtk_wed_device_irq_set_mask(&dev->mmio.wed, |
| 267 | - dev->mmio.irqmask); |
| 268 | - else |
| 269 | - mt76_mmio_wr(dev, addr, dev->mmio.irqmask); |
| 270 | - } |
| 271 | + if (addr) |
| 272 | + mt76_mmio_wr(dev, addr, dev->mmio.irqmask); |
| 273 | spin_unlock_irqrestore(&dev->mmio.irq_lock, flags); |
| 274 | } |
| 275 | EXPORT_SYMBOL_GPL(mt76_set_irq_mask); |
| 276 | diff --git a/mt76.h b/mt76.h |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 277 | index 3d1e893d..3e299bd4 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 278 | --- a/mt76.h |
| 279 | +++ b/mt76.h |
| 280 | @@ -13,7 +13,6 @@ |
| 281 | #include <linux/leds.h> |
| 282 | #include <linux/usb.h> |
| 283 | #include <linux/average.h> |
| 284 | -#include <linux/soc/mediatek/mtk_wed.h> |
| 285 | #include <net/mac80211.h> |
| 286 | #include "util.h" |
| 287 | #include "testmode.h" |
| 288 | @@ -27,16 +26,6 @@ |
| 289 | |
| 290 | #define MT76_TOKEN_FREE_THR 64 |
| 291 | |
| 292 | -#define MT_QFLAG_WED_RING GENMASK(1, 0) |
| 293 | -#define MT_QFLAG_WED_TYPE GENMASK(3, 2) |
| 294 | -#define MT_QFLAG_WED BIT(4) |
| 295 | - |
| 296 | -#define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ |
| 297 | - FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ |
| 298 | - FIELD_PREP(MT_QFLAG_WED_RING, _n)) |
| 299 | -#define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) |
| 300 | -#define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) |
| 301 | - |
| 302 | struct mt76_dev; |
| 303 | struct mt76_phy; |
| 304 | struct mt76_wcid; |
| 305 | @@ -186,9 +175,6 @@ struct mt76_queue { |
| 306 | u8 buf_offset; |
| 307 | u8 hw_idx; |
| 308 | u8 qid; |
| 309 | - u8 flags; |
| 310 | - |
| 311 | - u32 wed_regs; |
| 312 | |
| 313 | dma_addr_t desc_dma; |
| 314 | struct sk_buff *rx_head; |
| 315 | @@ -556,8 +542,6 @@ struct mt76_mmio { |
| 316 | void __iomem *regs; |
| 317 | spinlock_t irq_lock; |
| 318 | u32 irqmask; |
| 319 | - |
| 320 | - struct mtk_wed_device wed; |
| 321 | }; |
| 322 | |
| 323 | struct mt76_rx_status { |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 324 | @@ -782,7 +766,6 @@ struct mt76_dev { |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 325 | |
| 326 | spinlock_t token_lock; |
| 327 | struct idr token; |
| 328 | - u16 wed_token_count; |
| 329 | u16 token_count; |
| 330 | u16 token_size; |
| 331 | |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 332 | @@ -1008,14 +991,14 @@ int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 333 | |
| 334 | struct mt76_queue * |
| 335 | mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, |
| 336 | - int ring_base, u32 flags); |
| 337 | + int ring_base); |
| 338 | u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); |
| 339 | static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, |
| 340 | - int n_desc, int ring_base, u32 flags) |
| 341 | + int n_desc, int ring_base) |
| 342 | { |
| 343 | struct mt76_queue *q; |
| 344 | |
| 345 | - q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); |
| 346 | + q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); |
| 347 | if (IS_ERR(q)) |
| 348 | return PTR_ERR(q); |
| 349 | |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 350 | @@ -1030,7 +1013,7 @@ static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 351 | { |
| 352 | struct mt76_queue *q; |
| 353 | |
| 354 | - q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); |
| 355 | + q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); |
| 356 | if (IS_ERR(q)) |
| 357 | return PTR_ERR(q); |
| 358 | |
| 359 | diff --git a/mt7603/dma.c b/mt7603/dma.c |
| 360 | index 590cff9d..37b092e3 100644 |
| 361 | --- a/mt7603/dma.c |
| 362 | +++ b/mt7603/dma.c |
| 363 | @@ -173,13 +173,13 @@ int mt7603_dma_init(struct mt7603_dev *dev) |
| 364 | |
| 365 | for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { |
| 366 | ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], |
| 367 | - MT7603_TX_RING_SIZE, MT_TX_RING_BASE, 0); |
| 368 | + MT7603_TX_RING_SIZE, MT_TX_RING_BASE); |
| 369 | if (ret) |
| 370 | return ret; |
| 371 | } |
| 372 | |
| 373 | ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT, |
| 374 | - MT7603_PSD_RING_SIZE, MT_TX_RING_BASE, 0); |
| 375 | + MT7603_PSD_RING_SIZE, MT_TX_RING_BASE); |
| 376 | if (ret) |
| 377 | return ret; |
| 378 | |
| 379 | @@ -189,12 +189,12 @@ int mt7603_dma_init(struct mt7603_dev *dev) |
| 380 | return ret; |
| 381 | |
| 382 | ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_BEACON, MT_TX_HW_QUEUE_BCN, |
| 383 | - MT_MCU_RING_SIZE, MT_TX_RING_BASE, 0); |
| 384 | + MT_MCU_RING_SIZE, MT_TX_RING_BASE); |
| 385 | if (ret) |
| 386 | return ret; |
| 387 | |
| 388 | ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_CAB, MT_TX_HW_QUEUE_BMC, |
| 389 | - MT_MCU_RING_SIZE, MT_TX_RING_BASE, 0); |
| 390 | + MT_MCU_RING_SIZE, MT_TX_RING_BASE); |
| 391 | if (ret) |
| 392 | return ret; |
| 393 | |
| 394 | diff --git a/mt7615/dma.c b/mt7615/dma.c |
| 395 | index 3a79a2d4..00aefea1 100644 |
| 396 | --- a/mt7615/dma.c |
| 397 | +++ b/mt7615/dma.c |
| 398 | @@ -26,14 +26,14 @@ mt7622_init_tx_queues_multi(struct mt7615_dev *dev) |
| 399 | for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { |
| 400 | ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], |
| 401 | MT7615_TX_RING_SIZE / 2, |
| 402 | - MT_TX_RING_BASE, 0); |
| 403 | + MT_TX_RING_BASE); |
| 404 | if (ret) |
| 405 | return ret; |
| 406 | } |
| 407 | |
| 408 | ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT, |
| 409 | MT7615_TX_MGMT_RING_SIZE, |
| 410 | - MT_TX_RING_BASE, 0); |
| 411 | + MT_TX_RING_BASE); |
| 412 | if (ret) |
| 413 | return ret; |
| 414 | |
| 415 | @@ -55,7 +55,7 @@ mt7615_init_tx_queues(struct mt7615_dev *dev) |
| 416 | return mt7622_init_tx_queues_multi(dev); |
| 417 | |
| 418 | ret = mt76_init_tx_queue(&dev->mphy, 0, 0, MT7615_TX_RING_SIZE, |
| 419 | - MT_TX_RING_BASE, 0); |
| 420 | + MT_TX_RING_BASE); |
| 421 | if (ret) |
| 422 | return ret; |
| 423 | |
| 424 | diff --git a/mt76x02_mmio.c b/mt76x02_mmio.c |
| 425 | index 0fa3c7c3..8bcd8afa 100644 |
| 426 | --- a/mt76x02_mmio.c |
| 427 | +++ b/mt76x02_mmio.c |
| 428 | @@ -191,13 +191,13 @@ int mt76x02_dma_init(struct mt76x02_dev *dev) |
| 429 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
| 430 | ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i), |
| 431 | MT76x02_TX_RING_SIZE, |
| 432 | - MT_TX_RING_BASE, 0); |
| 433 | + MT_TX_RING_BASE); |
| 434 | if (ret) |
| 435 | return ret; |
| 436 | } |
| 437 | |
| 438 | ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT, |
| 439 | - MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE, 0); |
| 440 | + MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE); |
| 441 | if (ret) |
| 442 | return ret; |
| 443 | |
| 444 | diff --git a/mt7915/dma.c b/mt7915/dma.c |
developer | 68e1eb2 | 2022-05-09 17:02:12 +0800 | [diff] [blame] | 445 | index 9e3d14db..4358e9bf 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 446 | --- a/mt7915/dma.c |
| 447 | +++ b/mt7915/dma.c |
| 448 | @@ -8,16 +8,9 @@ |
| 449 | static int |
| 450 | mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base) |
| 451 | { |
| 452 | - struct mt7915_dev *dev = phy->dev; |
| 453 | int i, err; |
| 454 | |
| 455 | - if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { |
| 456 | - ring_base = MT_WED_TX_RING_BASE; |
| 457 | - idx -= MT_TXQ_ID(0); |
| 458 | - } |
| 459 | - |
| 460 | - err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base, |
| 461 | - MT_WED_Q_TX(idx)); |
| 462 | + err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, ring_base); |
| 463 | if (err < 0) |
| 464 | return err; |
| 465 | |
| 466 | @@ -326,14 +319,6 @@ static int mt7915_dma_enable(struct mt7915_dev *dev) |
| 467 | if (dev->dbdc_support || dev->phy.band_idx) |
| 468 | irq_mask |= MT_INT_BAND1_RX_DONE; |
| 469 | |
| 470 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 471 | - u32 wed_irq_mask = irq_mask; |
| 472 | - |
| 473 | - wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1; |
| 474 | - mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask); |
| 475 | - mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask); |
| 476 | - } |
| 477 | - |
| 478 | mt7915_irq_enable(dev, irq_mask); |
| 479 | |
| 480 | return 0; |
| 481 | @@ -342,7 +327,6 @@ static int mt7915_dma_enable(struct mt7915_dev *dev) |
| 482 | int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
| 483 | { |
| 484 | struct mt76_dev *mdev = &dev->mt76; |
| 485 | - u32 wa_rx_base, wa_rx_idx; |
| 486 | u32 hif1_ofs = 0; |
| 487 | int ret; |
| 488 | |
| 489 | @@ -355,17 +339,6 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
| 490 | |
| 491 | mt7915_dma_disable(dev, true); |
| 492 | |
| 493 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 494 | - mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); |
| 495 | - |
| 496 | - mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL, |
| 497 | - FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) | |
| 498 | - FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) | |
| 499 | - FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1)); |
| 500 | - } else { |
| 501 | - mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); |
| 502 | - } |
| 503 | - |
| 504 | /* init tx queue */ |
| 505 | ret = mt7915_init_tx_queues(&dev->phy, |
| 506 | MT_TXQ_ID(dev->phy.band_idx), |
| 507 | @@ -417,17 +390,11 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
| 508 | return ret; |
| 509 | |
| 510 | /* event from WA */ |
| 511 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 512 | - wa_rx_base = MT_WED_RX_RING_BASE; |
| 513 | - wa_rx_idx = MT7915_RXQ_MCU_WA; |
| 514 | - dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE; |
| 515 | - } else { |
| 516 | - wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA); |
| 517 | - wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA); |
| 518 | - } |
| 519 | ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], |
| 520 | - wa_rx_idx, MT7915_RX_MCU_RING_SIZE, |
| 521 | - MT_RX_BUF_SIZE, wa_rx_base); |
| 522 | + MT_RXQ_ID(MT_RXQ_MCU_WA), |
| 523 | + MT7915_RX_MCU_RING_SIZE, |
| 524 | + MT_RX_BUF_SIZE, |
| 525 | + MT_RXQ_RING_BASE(MT_RXQ_MCU_WA)); |
| 526 | if (ret) |
| 527 | return ret; |
| 528 | |
| 529 | diff --git a/mt7915/mac.c b/mt7915/mac.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 530 | index d80ef1b3..9e6ac1f0 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 531 | --- a/mt7915/mac.c |
| 532 | +++ b/mt7915/mac.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 533 | @@ -1407,29 +1407,6 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 534 | return 0; |
| 535 | } |
| 536 | |
| 537 | -u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) |
| 538 | -{ |
| 539 | - struct mt7915_txp *txp = ptr + MT_TXD_SIZE; |
| 540 | - __le32 *txwi = ptr; |
| 541 | - u32 val; |
| 542 | - |
| 543 | - memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); |
| 544 | - |
| 545 | - val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | |
| 546 | - FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); |
| 547 | - txwi[0] = cpu_to_le32(val); |
| 548 | - |
| 549 | - val = MT_TXD1_LONG_FORMAT | |
| 550 | - FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); |
| 551 | - txwi[1] = cpu_to_le32(val); |
| 552 | - |
| 553 | - txp->token = cpu_to_le16(token_id); |
| 554 | - txp->nbuf = 1; |
| 555 | - txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); |
| 556 | - |
| 557 | - return MT_TXD_SIZE + sizeof(*txp); |
| 558 | -} |
| 559 | - |
| 560 | static void |
| 561 | mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) |
| 562 | { |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 563 | @@ -1463,7 +1440,7 @@ mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 564 | |
| 565 | txp = mt7915_txwi_to_txp(dev, t); |
| 566 | for (i = 0; i < txp->nbuf; i++) |
| 567 | - dma_unmap_single(dev->dma_dev, le32_to_cpu(txp->buf[i]), |
| 568 | + dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), |
| 569 | le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); |
| 570 | } |
| 571 | |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 572 | @@ -1472,7 +1449,6 @@ mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 573 | struct ieee80211_sta *sta, struct list_head *free_list) |
| 574 | { |
| 575 | struct mt76_dev *mdev = &dev->mt76; |
| 576 | - struct mt7915_sta *msta; |
| 577 | struct mt76_wcid *wcid; |
| 578 | __le32 *txwi; |
| 579 | u16 wcid_idx; |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 580 | @@ -1485,24 +1461,13 @@ mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 581 | if (sta) { |
| 582 | wcid = (struct mt76_wcid *)sta->drv_priv; |
| 583 | wcid_idx = wcid->idx; |
| 584 | + |
| 585 | + if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) |
| 586 | + mt7915_tx_check_aggr(sta, txwi); |
| 587 | } else { |
| 588 | wcid_idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX); |
| 589 | - wcid = rcu_dereference(dev->mt76.wcid[wcid_idx]); |
| 590 | - |
| 591 | - if (wcid && wcid->sta) { |
| 592 | - msta = container_of(wcid, struct mt7915_sta, wcid); |
| 593 | - sta = container_of((void *)msta, struct ieee80211_sta, |
| 594 | - drv_priv); |
| 595 | - spin_lock_bh(&dev->sta_poll_lock); |
| 596 | - if (list_empty(&msta->poll_list)) |
| 597 | - list_add_tail(&msta->poll_list, &dev->sta_poll_list); |
| 598 | - spin_unlock_bh(&dev->sta_poll_lock); |
| 599 | - } |
| 600 | } |
| 601 | |
| 602 | - if (sta && likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE))) |
| 603 | - mt7915_tx_check_aggr(sta, txwi); |
| 604 | - |
| 605 | __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list); |
| 606 | |
| 607 | out: |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 608 | @@ -1510,56 +1475,30 @@ out: |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 609 | mt76_put_txwi(mdev, t); |
| 610 | } |
| 611 | |
| 612 | -static void |
| 613 | -mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) |
| 614 | -{ |
| 615 | - struct mt76_dev *mdev = &dev->mt76; |
| 616 | - struct mt76_phy *mphy_ext = mdev->phy2; |
| 617 | - |
| 618 | - /* clean DMA queues and unmap buffers first */ |
| 619 | - mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); |
| 620 | - mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); |
| 621 | - if (mphy_ext) { |
| 622 | - mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); |
| 623 | - mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); |
| 624 | - } |
| 625 | -} |
| 626 | - |
| 627 | -static void |
| 628 | -mt7915_mac_tx_free_done(struct mt7915_dev *dev, |
| 629 | - struct list_head *free_list, bool wake) |
| 630 | -{ |
| 631 | - struct sk_buff *skb, *tmp; |
| 632 | - |
| 633 | - mt7915_mac_sta_poll(dev); |
| 634 | - |
| 635 | - if (wake) |
| 636 | - mt76_set_tx_blocked(&dev->mt76, false); |
| 637 | - |
| 638 | - mt76_worker_schedule(&dev->mt76.tx_worker); |
| 639 | - |
| 640 | - list_for_each_entry_safe(skb, tmp, free_list, list) { |
| 641 | - skb_list_del_init(skb); |
| 642 | - napi_consume_skb(skb, 1); |
| 643 | - } |
| 644 | -} |
| 645 | - |
| 646 | static void |
| 647 | mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) |
| 648 | { |
| 649 | struct mt7915_tx_free *free = (struct mt7915_tx_free *)data; |
| 650 | struct mt76_dev *mdev = &dev->mt76; |
| 651 | + struct mt76_phy *mphy_ext = mdev->phy2; |
| 652 | struct mt76_txwi_cache *txwi; |
| 653 | struct ieee80211_sta *sta = NULL; |
developer | 68e1eb2 | 2022-05-09 17:02:12 +0800 | [diff] [blame] | 654 | struct mt7915_sta *msta = NULL; |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 655 | LIST_HEAD(free_list); |
| 656 | + struct sk_buff *skb, *tmp; |
| 657 | void *end = data + len; |
| 658 | bool v3, wake = false; |
| 659 | u16 total, count = 0; |
| 660 | u32 txd = le32_to_cpu(free->txd); |
| 661 | __le32 *cur_info; |
| 662 | |
| 663 | - mt7915_mac_tx_free_prepare(dev); |
| 664 | + /* clean DMA queues and unmap buffers first */ |
| 665 | + mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); |
| 666 | + mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); |
| 667 | + if (mphy_ext) { |
| 668 | + mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); |
| 669 | + mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); |
| 670 | + } |
| 671 | |
| 672 | total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); |
| 673 | v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 674 | @@ -1616,38 +1555,17 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 675 | } |
| 676 | } |
| 677 | |
| 678 | - mt7915_mac_tx_free_done(dev, &free_list, wake); |
| 679 | -} |
| 680 | - |
| 681 | -static void |
| 682 | -mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) |
| 683 | -{ |
| 684 | - struct mt7915_tx_free *free = (struct mt7915_tx_free *)data; |
| 685 | - struct mt76_dev *mdev = &dev->mt76; |
| 686 | - __le16 *info = (__le16 *)free->info; |
| 687 | - void *end = data + len; |
| 688 | - LIST_HEAD(free_list); |
| 689 | - bool wake = false; |
| 690 | - u8 i, count; |
| 691 | - |
| 692 | - mt7915_mac_tx_free_prepare(dev); |
| 693 | - |
| 694 | - count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); |
| 695 | - if (WARN_ON_ONCE((void *)&info[count] > end)) |
| 696 | - return; |
| 697 | + mt7915_mac_sta_poll(dev); |
| 698 | |
| 699 | - for (i = 0; i < count; i++) { |
| 700 | - struct mt76_txwi_cache *txwi; |
| 701 | - u16 msdu = le16_to_cpu(info[i]); |
| 702 | + if (wake) |
| 703 | + mt76_set_tx_blocked(&dev->mt76, false); |
| 704 | |
| 705 | - txwi = mt76_token_release(mdev, msdu, &wake); |
| 706 | - if (!txwi) |
| 707 | - continue; |
| 708 | + mt76_worker_schedule(&dev->mt76.tx_worker); |
| 709 | |
| 710 | - mt7915_txwi_free(dev, txwi, NULL, &free_list); |
| 711 | + list_for_each_entry_safe(skb, tmp, &free_list, list) { |
| 712 | + skb_list_del_init(skb); |
| 713 | + napi_consume_skb(skb, 1); |
| 714 | } |
| 715 | - |
| 716 | - mt7915_mac_tx_free_done(dev, &free_list, wake); |
| 717 | } |
| 718 | |
| 719 | static bool |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 720 | @@ -1827,9 +1745,6 @@ bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 721 | case PKT_TYPE_TXRX_NOTIFY: |
| 722 | mt7915_mac_tx_free(dev, data, len); |
| 723 | return false; |
| 724 | - case PKT_TYPE_TXRX_NOTIFY_V0: |
| 725 | - mt7915_mac_tx_free_v0(dev, data, len); |
| 726 | - return false; |
| 727 | case PKT_TYPE_TXS: |
| 728 | for (rxd += 2; rxd + 8 <= end; rxd += 8) |
| 729 | mt7915_mac_add_txs(dev, rxd); |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 730 | @@ -1857,10 +1772,6 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 731 | mt7915_mac_tx_free(dev, skb->data, skb->len); |
| 732 | napi_consume_skb(skb, 1); |
| 733 | break; |
| 734 | - case PKT_TYPE_TXRX_NOTIFY_V0: |
| 735 | - mt7915_mac_tx_free_v0(dev, skb->data, skb->len); |
| 736 | - napi_consume_skb(skb, 1); |
| 737 | - break; |
| 738 | case PKT_TYPE_RX_EVENT: |
| 739 | mt7915_mcu_rx_event(dev, skb); |
| 740 | break; |
| 741 | diff --git a/mt7915/mac.h b/mt7915/mac.h |
| 742 | index c5fd1a61..5add1dd3 100644 |
| 743 | --- a/mt7915/mac.h |
| 744 | +++ b/mt7915/mac.h |
| 745 | @@ -24,7 +24,6 @@ enum rx_pkt_type { |
| 746 | PKT_TYPE_TXRX_NOTIFY, |
| 747 | PKT_TYPE_RX_EVENT, |
| 748 | PKT_TYPE_RX_FW_MONITOR = 0x0c, |
| 749 | - PKT_TYPE_TXRX_NOTIFY_V0 = 0x18, |
| 750 | }; |
| 751 | |
| 752 | /* RXD DW1 */ |
| 753 | @@ -312,7 +311,6 @@ struct mt7915_tx_free { |
| 754 | |
| 755 | #define MT_TX_FREE_VER GENMASK(18, 16) |
| 756 | #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0) |
| 757 | -#define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0) |
| 758 | #define MT_TX_FREE_WLAN_ID GENMASK(23, 14) |
| 759 | #define MT_TX_FREE_LATENCY GENMASK(12, 0) |
| 760 | /* 0: success, others: dropped */ |
| 761 | diff --git a/mt7915/main.c b/mt7915/main.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 762 | index 64ba70fb..770090a1 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 763 | --- a/mt7915/main.c |
| 764 | +++ b/mt7915/main.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 765 | @@ -1403,39 +1403,6 @@ out: |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 766 | return ret; |
| 767 | } |
| 768 | |
| 769 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 770 | -static int |
| 771 | -mt7915_net_fill_forward_path(struct ieee80211_hw *hw, |
| 772 | - struct ieee80211_vif *vif, |
| 773 | - struct ieee80211_sta *sta, |
| 774 | - struct net_device_path_ctx *ctx, |
| 775 | - struct net_device_path *path) |
| 776 | -{ |
| 777 | - struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; |
| 778 | - struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; |
| 779 | - struct mt7915_dev *dev = mt7915_hw_dev(hw); |
| 780 | - struct mt7915_phy *phy = mt7915_hw_phy(hw); |
| 781 | - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 782 | - |
| 783 | - if (!mtk_wed_device_active(wed)) |
| 784 | - return -ENODEV; |
| 785 | - |
| 786 | - if (msta->wcid.idx > 0xff) |
| 787 | - return -EIO; |
| 788 | - |
| 789 | - path->type = DEV_PATH_MTK_WDMA; |
| 790 | - path->dev = ctx->dev; |
| 791 | - path->mtk_wdma.wdma_idx = wed->wdma_idx; |
| 792 | - path->mtk_wdma.bss = mvif->mt76.idx; |
| 793 | - path->mtk_wdma.wcid = msta->wcid.idx; |
| 794 | - path->mtk_wdma.queue = phy != &dev->phy; |
| 795 | - |
| 796 | - ctx->dev = NULL; |
| 797 | - |
| 798 | - return 0; |
| 799 | -} |
| 800 | -#endif |
| 801 | - |
| 802 | const struct ieee80211_ops mt7915_ops = { |
| 803 | .tx = mt7915_tx, |
| 804 | .start = mt7915_start, |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 805 | @@ -1483,7 +1450,4 @@ const struct ieee80211_ops mt7915_ops = { |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 806 | .sta_add_debugfs = mt7915_sta_add_debugfs, |
| 807 | #endif |
| 808 | .set_radar_background = mt7915_set_radar_background, |
| 809 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 810 | - .net_fill_forward_path = mt7915_net_fill_forward_path, |
| 811 | -#endif |
| 812 | }; |
| 813 | diff --git a/mt7915/mcu.c b/mt7915/mcu.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 814 | index 8ed8700d..899d7de7 100755 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 815 | --- a/mt7915/mcu.c |
| 816 | +++ b/mt7915/mcu.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 817 | @@ -2581,9 +2581,6 @@ int mt7915_run_firmware(struct mt7915_dev *dev) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 818 | if (ret) |
| 819 | return ret; |
| 820 | |
| 821 | - if (mtk_wed_device_active(&dev->mt76.mmio.wed)) |
| 822 | - mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0); |
| 823 | - |
| 824 | ret = mt7915_mcu_set_mwds(dev, 1); |
| 825 | if (ret) |
| 826 | return ret; |
| 827 | diff --git a/mt7915/mmio.c b/mt7915/mmio.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 828 | index bbf8b16c..a795dda3 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 829 | --- a/mt7915/mmio.c |
| 830 | +++ b/mt7915/mmio.c |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 831 | @@ -557,21 +557,15 @@ static void mt7915_rx_poll_complete(struct mt76_dev *mdev, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 832 | static void mt7915_irq_tasklet(struct tasklet_struct *t) |
| 833 | { |
| 834 | struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet); |
| 835 | - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 836 | u32 intr, intr1, mask; |
| 837 | |
| 838 | - if (mtk_wed_device_active(wed)) { |
| 839 | - mtk_wed_device_irq_set_mask(wed, 0); |
| 840 | - intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); |
| 841 | - } else { |
| 842 | - mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 843 | - if (dev->hif2) |
| 844 | - mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 845 | + mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 846 | + if (dev->hif2) |
| 847 | + mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 848 | |
| 849 | - intr = mt76_rr(dev, MT_INT_SOURCE_CSR); |
| 850 | - intr &= dev->mt76.mmio.irqmask; |
| 851 | - mt76_wr(dev, MT_INT_SOURCE_CSR, intr); |
| 852 | - } |
| 853 | + intr = mt76_rr(dev, MT_INT_SOURCE_CSR); |
| 854 | + intr &= dev->mt76.mmio.irqmask; |
| 855 | + mt76_wr(dev, MT_INT_SOURCE_CSR, intr); |
| 856 | |
| 857 | if (dev->hif2) { |
| 858 | intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 859 | @@ -625,15 +619,10 @@ static void mt7915_irq_tasklet(struct tasklet_struct *t) |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 860 | irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) |
| 861 | { |
| 862 | struct mt7915_dev *dev = dev_instance; |
| 863 | - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 864 | |
| 865 | - if (mtk_wed_device_active(wed)) { |
| 866 | - mtk_wed_device_irq_set_mask(wed, 0); |
| 867 | - } else { |
| 868 | - mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 869 | - if (dev->hif2) |
| 870 | - mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 871 | - } |
| 872 | + mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 873 | + if (dev->hif2) |
| 874 | + mt76_wr(dev, MT_INT1_MASK_CSR, 0); |
| 875 | |
| 876 | if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) |
| 877 | return IRQ_NONE; |
| 878 | diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 879 | index 6508cc26..d6c9e7ed 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 880 | --- a/mt7915/mt7915.h |
| 881 | +++ b/mt7915/mt7915.h |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 882 | @@ -528,8 +528,6 @@ struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 883 | void mt7915_wfsys_reset(struct mt7915_dev *dev); |
| 884 | irqreturn_t mt7915_irq_handler(int irq, void *dev_instance); |
| 885 | u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif); |
| 886 | -u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); |
| 887 | - |
| 888 | int mt7915_register_device(struct mt7915_dev *dev); |
| 889 | void mt7915_unregister_device(struct mt7915_dev *dev); |
| 890 | int mt7915_eeprom_init(struct mt7915_dev *dev); |
| 891 | diff --git a/mt7915/pci.c b/mt7915/pci.c |
| 892 | index f6222ef1..1bab1cbb 100644 |
| 893 | --- a/mt7915/pci.c |
| 894 | +++ b/mt7915/pci.c |
| 895 | @@ -12,9 +12,6 @@ |
| 896 | #include "mac.h" |
| 897 | #include "../trace.h" |
| 898 | |
| 899 | -static bool wed_enable = false; |
| 900 | -module_param(wed_enable, bool, 0644); |
| 901 | - |
| 902 | static LIST_HEAD(hif_list); |
| 903 | static DEFINE_SPINLOCK(hif_lock); |
| 904 | static u32 hif_idx; |
| 905 | @@ -95,79 +92,12 @@ static int mt7915_pci_hif2_probe(struct pci_dev *pdev) |
| 906 | return 0; |
| 907 | } |
| 908 | |
| 909 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 910 | -static int mt7915_wed_offload_enable(struct mtk_wed_device *wed) |
| 911 | -{ |
| 912 | - struct mt7915_dev *dev; |
| 913 | - int ret; |
| 914 | - |
| 915 | - dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); |
| 916 | - |
| 917 | - spin_lock_bh(&dev->mt76.token_lock); |
| 918 | - dev->mt76.token_size = wed->wlan.token_start; |
| 919 | - spin_unlock_bh(&dev->mt76.token_lock); |
| 920 | - |
| 921 | - ret = wait_event_timeout(dev->mt76.tx_wait, |
| 922 | - !dev->mt76.wed_token_count, HZ); |
| 923 | - if (!ret) |
| 924 | - return -EAGAIN; |
| 925 | - |
| 926 | - return 0; |
| 927 | -} |
| 928 | - |
| 929 | -static void mt7915_wed_offload_disable(struct mtk_wed_device *wed) |
| 930 | -{ |
| 931 | - struct mt7915_dev *dev; |
| 932 | - |
| 933 | - dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); |
| 934 | - |
| 935 | - spin_lock_bh(&dev->mt76.token_lock); |
| 936 | - dev->mt76.token_size = MT7915_TOKEN_SIZE; |
| 937 | - spin_unlock_bh(&dev->mt76.token_lock); |
| 938 | -} |
| 939 | -#endif |
| 940 | - |
| 941 | -static int |
| 942 | -mt7915_pci_wed_init(struct mt7915_dev *dev, struct pci_dev *pdev, int *irq) |
| 943 | -{ |
| 944 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 945 | - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 946 | - int ret; |
| 947 | - |
| 948 | - if (!wed_enable) |
| 949 | - return 0; |
| 950 | - |
| 951 | - wed->wlan.pci_dev = pdev; |
| 952 | - wed->wlan.wpdma_phys = pci_resource_start(pdev, 0) + |
| 953 | - MT_WFDMA_EXT_CSR_BASE; |
| 954 | - wed->wlan.nbuf = 4096; |
| 955 | - wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; |
| 956 | - wed->wlan.init_buf = mt7915_wed_init_buf; |
| 957 | - wed->wlan.offload_enable = mt7915_wed_offload_enable; |
| 958 | - wed->wlan.offload_disable = mt7915_wed_offload_disable; |
| 959 | - |
| 960 | - if (mtk_wed_device_attach(wed) != 0) |
| 961 | - return 0; |
| 962 | - |
| 963 | - *irq = wed->irq; |
| 964 | - dev->mt76.dma_dev = wed->dev; |
| 965 | - |
| 966 | - ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); |
| 967 | - if (ret) |
| 968 | - return ret; |
| 969 | - |
| 970 | - return 1; |
| 971 | -#else |
| 972 | - return 0; |
| 973 | -#endif |
| 974 | -} |
| 975 | - |
| 976 | static int mt7915_pci_probe(struct pci_dev *pdev, |
| 977 | const struct pci_device_id *id) |
| 978 | { |
| 979 | - struct mt7915_hif *hif2 = NULL; |
| 980 | struct mt7915_dev *dev; |
| 981 | struct mt76_dev *mdev; |
| 982 | + struct mt7915_hif *hif2; |
| 983 | int irq; |
| 984 | int ret; |
| 985 | |
| 986 | @@ -199,24 +129,15 @@ static int mt7915_pci_probe(struct pci_dev *pdev, |
| 987 | mt7915_wfsys_reset(dev); |
| 988 | hif2 = mt7915_pci_init_hif2(pdev); |
| 989 | |
| 990 | - ret = mt7915_pci_wed_init(dev, pdev, &irq); |
| 991 | + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
| 992 | if (ret < 0) |
| 993 | - goto free_wed_or_irq_vector; |
| 994 | - |
| 995 | - if (!ret) { |
| 996 | - hif2 = mt7915_pci_init_hif2(pdev); |
| 997 | - |
| 998 | - ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
| 999 | - if (ret < 0) |
| 1000 | - goto free_device; |
| 1001 | - |
| 1002 | - irq = pdev->irq; |
| 1003 | - } |
| 1004 | + goto free_device; |
| 1005 | |
| 1006 | + irq = pdev->irq; |
| 1007 | ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler, |
| 1008 | IRQF_SHARED, KBUILD_MODNAME, dev); |
| 1009 | if (ret) |
| 1010 | - goto free_wed_or_irq_vector; |
| 1011 | + goto free_irq_vector; |
| 1012 | |
| 1013 | mt76_wr(dev, MT_INT_MASK_CSR, 0); |
| 1014 | |
| 1015 | @@ -253,11 +174,8 @@ free_hif2: |
| 1016 | if (dev->hif2) |
| 1017 | put_device(dev->hif2->dev); |
| 1018 | devm_free_irq(mdev->dev, irq, dev); |
| 1019 | -free_wed_or_irq_vector: |
| 1020 | - if (mtk_wed_device_active(&mdev->mmio.wed)) |
| 1021 | - mtk_wed_device_detach(&mdev->mmio.wed); |
| 1022 | - else |
| 1023 | - pci_free_irq_vectors(pdev); |
| 1024 | +free_irq_vector: |
| 1025 | + pci_free_irq_vectors(pdev); |
| 1026 | free_device: |
| 1027 | mt76_free_device(&dev->mt76); |
| 1028 | |
| 1029 | diff --git a/mt7915/regs.h b/mt7915/regs.h |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 1030 | index 6ba5e9fe..0e1e05f9 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 1031 | --- a/mt7915/regs.h |
| 1032 | +++ b/mt7915/regs.h |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 1033 | @@ -594,31 +594,18 @@ enum offs_rev { |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 1034 | |
| 1035 | /* WFDMA CSR */ |
| 1036 | #define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR) |
| 1037 | -#define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000 |
| 1038 | #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) |
| 1039 | -#define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs)) |
| 1040 | |
| 1041 | -#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30) |
| 1042 | +#define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) |
| 1043 | #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) |
| 1044 | -#define MT_WFDMA_HOST_CONFIG_WED BIT(1) |
| 1045 | |
| 1046 | -#define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34) |
| 1047 | -#define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0) |
| 1048 | -#define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8) |
| 1049 | -#define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16) |
| 1050 | - |
| 1051 | -#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44) |
| 1052 | +#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) |
| 1053 | #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) |
| 1054 | |
| 1055 | #define MT_PCIE_RECOG_ID 0xd7090 |
| 1056 | #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) |
| 1057 | #define MT_PCIE_RECOG_ID_SEM BIT(31) |
| 1058 | |
| 1059 | -#define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204) |
| 1060 | - |
| 1061 | -#define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300) |
| 1062 | -#define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400) |
| 1063 | - |
| 1064 | /* WFDMA0 PCIE1 */ |
| 1065 | #define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR) |
| 1066 | #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) |
| 1067 | diff --git a/mt7921/dma.c b/mt7921/dma.c |
| 1068 | index 2939cf9b..ca7e20fb 100644 |
| 1069 | --- a/mt7921/dma.c |
| 1070 | +++ b/mt7921/dma.c |
| 1071 | @@ -9,7 +9,7 @@ static int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc) |
| 1072 | { |
| 1073 | int i, err; |
| 1074 | |
| 1075 | - err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE, 0); |
| 1076 | + err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE); |
| 1077 | if (err < 0) |
| 1078 | return err; |
| 1079 | |
| 1080 | diff --git a/tx.c b/tx.c |
developer | beb7437 | 2022-05-06 16:53:33 +0800 | [diff] [blame] | 1081 | index 0457c3eb..656b7090 100644 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 1082 | --- a/tx.c |
| 1083 | +++ b/tx.c |
| 1084 | @@ -725,12 +725,6 @@ int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) |
| 1085 | if (token >= 0) |
| 1086 | dev->token_count++; |
| 1087 | |
| 1088 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 1089 | - if (mtk_wed_device_active(&dev->mmio.wed) && |
| 1090 | - token >= dev->mmio.wed.wlan.token_start) |
| 1091 | - dev->wed_token_count++; |
| 1092 | -#endif |
| 1093 | - |
| 1094 | if (dev->token_count >= dev->token_size - MT76_TOKEN_FREE_THR) |
| 1095 | __mt76_set_tx_blocked(dev, true); |
| 1096 | |
| 1097 | @@ -748,17 +742,9 @@ mt76_token_release(struct mt76_dev *dev, int token, bool *wake) |
| 1098 | spin_lock_bh(&dev->token_lock); |
| 1099 | |
| 1100 | txwi = idr_remove(&dev->token, token); |
| 1101 | - if (txwi) { |
| 1102 | + if (txwi) |
| 1103 | dev->token_count--; |
| 1104 | |
| 1105 | -#ifdef CONFIG_NET_MEDIATEK_SOC_WED |
| 1106 | - if (mtk_wed_device_active(&dev->mmio.wed) && |
| 1107 | - token >= dev->mmio.wed.wlan.token_start && |
| 1108 | - --dev->wed_token_count == 0) |
| 1109 | - wake_up(&dev->tx_wait); |
| 1110 | -#endif |
| 1111 | - } |
| 1112 | - |
| 1113 | if (dev->token_count < dev->token_size - MT76_TOKEN_FREE_THR && |
| 1114 | dev->phy.q_tx[0]->blocked) |
| 1115 | *wake = true; |
| 1116 | -- |
developer | 4c6b600 | 2022-05-30 16:36:44 +0800 | [diff] [blame] | 1117 | 2.25.1 |
developer | f7d25b0 | 2022-04-12 16:20:16 +0800 | [diff] [blame] | 1118 | |