blob: 187a8a56922ed07deaa4025ffab1c59e561e7824 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4#include "mt7986-spim-nand-partition.dtsi"
5/ {
6 model = "MediaTek MT7986b RFB";
developercd6a1382022-01-11 15:45:19 +08007 compatible = "mediatek,mt7986b-2500wan-spim-snand-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16};
17
18&uart0 {
19 status = "okay";
20};
21
22/* Warning: pins shared with &snand */
23&uart1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins>;
26 status = "disabled";
27};
28
29/* Warning: pins shared with &spi1 */
30&uart2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&uart2_pins>;
33 status = "disabled";
34};
35
36&i2c0 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&i2c_pins>;
39 status = "okay";
40};
41
42&watchdog {
43 status = "okay";
44};
45
46&eth {
47 status = "okay";
48
49 gmac0: mac@0 {
50 compatible = "mediatek,eth-mac";
51 reg = <0>;
52 phy-mode = "2500base-x";
53
54 fixed-link {
55 speed = <2500>;
56 full-duplex;
57 pause;
58 };
59 };
60
61 gmac1: mac@1 {
62 compatible = "mediatek,eth-mac";
63 reg = <1>;
64 phy-mode = "2500base-x";
65
66 fixed-link {
67 speed = <2500>;
68 full-duplex;
69 pause;
70 };
71 };
72
73 mdio: mdio-bus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 phy5: phy@5 {
78 compatible = "ethernet-phy-id67c9.de0a";
79 reg = <5>;
80 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +080081 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +080082 reset-deassert-us = <20000>;
83 phy-mode = "2500base-x";
84 };
85
86 phy6: phy@6 {
87 compatible = "ethernet-phy-id67c9.de0a";
88 reg = <6>;
89 phy-mode = "2500base-x";
90 };
91
92 switch@0 {
93 compatible = "mediatek,mt7531";
94 reg = <31>;
95 reset-gpios = <&pio 5 0>;
96
97 ports {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 port@0 {
102 reg = <0>;
103 label = "lan0";
104 };
105
106 port@1 {
107 reg = <1>;
108 label = "lan1";
109 };
110
111 port@2 {
112 reg = <2>;
113 label = "lan2";
114 };
115
116 port@3 {
117 reg = <3>;
118 label = "lan3";
119 };
120
121 port@4 {
122 reg = <4>;
123 label = "lan4";
124 };
125
126 port@5 {
127 reg = <5>;
128 label = "lan5";
129 phy-mode = "2500base-x";
130
131 fixed-link {
132 speed = <2500>;
133 full-duplex;
134 pause;
135 };
136 };
137
138 port@6 {
139 reg = <6>;
140 label = "cpu";
141 ethernet = <&gmac0>;
142 phy-mode = "2500base-x";
143
144 fixed-link {
145 speed = <2500>;
146 full-duplex;
147 pause;
148 };
149 };
150 };
151 };
152 };
153};
154
155&hnat {
156 mtketh-wan = "eth1";
157 mtketh-lan = "lan";
158 mtketh-max-gmac = <2>;
159 status = "okay";
160};
161
162&spi0 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&spi_flash_pins>;
165 cs-gpios = <0>, <0>;
166 status = "okay";
167
168 spi_nor@0 {
169 #address-cells = <1>;
170 #size-cells = <1>;
171 compatible = "jedec,spi-nor";
172 reg = <0>;
173 spi-max-frequency = <20000000>;
174 spi-tx-buswidth = <4>;
175 spi-rx-buswidth = <4>;
176 };
177
178 spi_nand: spi_nand@1 {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 compatible = "spi-nand";
182 reg = <1>;
183 spi-max-frequency = <20000000>;
184 spi-tx-buswidth = <4>;
185 spi-rx-buswidth = <4>;
186 };
187};
188
189/* Warning: pins shared with &uart2 */
190&spi1 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&spic_pins>;
193 status = "okay";
194};
195
196&wbsys {
197 mediatek,mtd-eeprom = <&factory 0x0000>;
198 status = "okay";
developere138bcd2021-12-06 09:20:47 +0800199 pinctrl-names = "default", "dbdc";
200 pinctrl-0 = <&wf_2g_5g_pins>;
201 pinctrl-1 = <&wf_dbdc_pins>;
developer565bacb2021-09-28 21:26:32 +0800202};
203
204&pio {
205 spi_flash_pins: spi-flash-pins-33-to-38 {
206 mux {
207 function = "flash";
208 groups = "spi0", "spi0_wp_hold";
209 };
210 conf-pu {
211 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
212 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800213 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800214 };
215 conf-pd {
216 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
217 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800218 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800219 };
220
221 };
developere138bcd2021-12-06 09:20:47 +0800222
223 wf_2g_5g_pins: wf_2g_5g-pins {
224 mux {
225 function = "wifi";
226 groups = "wf_2g", "wf_5g";
227 };
228 conf {
229 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
230 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
231 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
232 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
233 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
234 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
235 "WF1_TOP_CLK", "WF1_TOP_DATA";
236 drive-strength = <MTK_DRIVE_4mA>;
237 };
238 };
239
240 wf_dbdc_pins: wf_dbdc-pins {
241 mux {
242 function = "wifi";
243 groups = "wf_dbdc";
244 };
245 conf {
246 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
247 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
248 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
249 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
250 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
251 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
252 "WF1_TOP_CLK", "WF1_TOP_DATA";
253 drive-strength = <MTK_DRIVE_4mA>;
254 };
255 };
developer565bacb2021-09-28 21:26:32 +0800256};