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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / a83363018da58c08b50bab8eec26e0bba9a8d5a5 / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / target / linux / mediatek / patches-5.4 / 999-3021-mtk-wed-add-wed3-support.patch
blob: 6b200f9c4d27cb581b720e9ed439f41b64a70640 [file] [log] [blame]
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1From 400f8349a31ffc48538aa7df64a88111de9a738b Mon Sep 17 00:00:00 2001
2From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Thu, 13 Apr 2023 15:51:08 +0800
4Subject: [PATCH] mtk:wed:add wed3 support
5
6Signed-off-by: sujuan.chen <sujuan.chen@mediatek.com>
7---
8 arch/arm64/boot/dts/mediatek/mt7988.dtsi | 152 ++-
9 .../dts/mediatek/mt7988a-dsa-10g-spim-nor.dts | 16 +-
10 .../dts/mediatek/mt7988d-dsa-10g-spim-nor.dts | 16 +-
11 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +-
12 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +-
13 drivers/net/ethernet/mediatek/mtk_ppe.c | 17 +-
14 drivers/net/ethernet/mediatek/mtk_ppe.h | 2 +-
15 .../net/ethernet/mediatek/mtk_ppe_offload.c | 13 +-
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]16 drivers/net/ethernet/mediatek/mtk_wed.c | 1148 +++++++++++++----
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]17 drivers/net/ethernet/mediatek/mtk_wed.h | 25 +-
18 .../net/ethernet/mediatek/mtk_wed_debugfs.c | 584 ++++++++-
19 drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 13 +-
20 drivers/net/ethernet/mediatek/mtk_wed_mcu.h | 5 +-
21 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 338 ++++-
22 include/linux/netdevice.h | 7 +
23 include/linux/soc/mediatek/mtk_wed.h | 81 +-
24 16 files changed, 1446 insertions(+), 333 deletions(-)
25 mode change 100755 => 100644 drivers/net/ethernet/mediatek/mtk_ppe.c
26
27diff --git a/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/arch/arm64/boot/dts/mediatek/mt7988.dtsi
28index 364deef..f9a0120 100644
29--- a/arch/arm64/boot/dts/mediatek/mt7988.dtsi
30+++ b/arch/arm64/boot/dts/mediatek/mt7988.dtsi
31@@ -191,44 +191,49 @@
32 status = "disabled";
33 };
34
35- wed: wed@15010000 {
36- compatible = "mediatek,wed";
37- wed_num = <3>;
38- /* add this property for wed get the pci slot number. */
39- pci_slot_map = <0>, <1>, <2>;
40- reg = <0 0x15010000 0 0x2000>,
41- <0 0x15012000 0 0x2000>,
42- <0 0x15014000 0 0x2000>;
43+ wed0: wed@15010000 {
44+ compatible = "mediatek,mt7988-wed",
45+ "syscon";
46+ reg = <0 0x15010000 0 0x2000>;
47 interrupt-parent = <&gic>;
48- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
49- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
50- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
51- };
52-
53- wed2: wed2@15012000 {
54- compatible = "mediatek,wed2";
55- wed_num = <3>;
56- /* add this property for wed get the pci slot number. */
57- reg = <0 0x15010000 0 0x2000>,
58- <0 0x15012000 0 0x2000>,
59- <0 0x15014000 0 0x2000>;
60+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
61+ mediatek,wed_pcie = <&wed_pcie>;
62+ mediatek,ap2woccif = <&ap2woccif0>;
63+ mediatek,wocpu_ilm = <&wocpu0_ilm>;
64+ mediatek,wocpu_dlm = <&wocpu0_dlm>;
65+ mediatek,wocpu_boot = <&cpu0_boot>;
66+ mediatek,wocpu_emi = <&wocpu0_emi>;
67+ mediatek,wocpu_data = <&wocpu_data>;
68+ };
69+
70+ wed1: wed@15012000 {
71+ compatible = "mediatek,mt7988-wed",
72+ "syscon";
73+ reg = <0 0x15012000 0 0x2000>;
74 interrupt-parent = <&gic>;
75- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
76- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
77- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
78- };
79-
80- wed3: wed3@15014000 {
81- compatible = "mediatek,wed3";
82- wed_num = <3>;
83- /* add this property for wed get the pci slot number. */
84- reg = <0 0x15010000 0 0x2000>,
85- <0 0x15012000 0 0x2000>,
86- <0 0x15014000 0 0x2000>;
87+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
88+ mediatek,wed_pcie = <&wed_pcie>;
89+ mediatek,ap2woccif = <&ap2woccif1>;
90+ mediatek,wocpu_ilm = <&wocpu1_ilm>;
91+ mediatek,wocpu_dlm = <&wocpu1_dlm>;
92+ mediatek,wocpu_boot = <&cpu1_boot>;
93+ mediatek,wocpu_emi = <&wocpu1_emi>;
94+ mediatek,wocpu_data = <&wocpu_data>;
95+ };
96+
97+ wed2: wed@15014000 {
98+ compatible = "mediatek,mt7988-wed",
99+ "syscon";
100+ reg = <0 0x15014000 0 0x2000>;
101 interrupt-parent = <&gic>;
102- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
103- <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
104- <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
105+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
106+ mediatek,wed_pcie = <&wed_pcie>;
107+ mediatek,ap2woccif = <&ap2woccif2>;
108+ mediatek,wocpu_ilm = <&wocpu2_ilm>;
109+ mediatek,wocpu_dlm = <&wocpu2_dlm>;
110+ mediatek,wocpu_boot = <&cpu2_boot>;
111+ mediatek,wocpu_emi = <&wocpu2_emi>;
112+ mediatek,wocpu_data = <&wocpu_data>;
113 };
114
115 wdma: wdma@15104800 {
116@@ -238,15 +243,25 @@
117 <0 0x15105000 0 0x400>;
118 };
119
120- ap2woccif: ap2woccif@151A5000 {
121- compatible = "mediatek,ap2woccif";
122- reg = <0 0x151A5000 0 0x1000>,
123- <0 0x152A5000 0 0x1000>,
124- <0 0x153A5000 0 0x1000>;
125+ ap2woccif0: ap2woccif@151A5000 {
126+ compatible = "mediatek,ap2woccif", "syscon";
127+ reg = <0 0x151A5000 0 0x1000>;
128+ interrupt-parent = <&gic>;
129+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
130+ };
131+
132+ ap2woccif1: ap2woccif@152A5000 {
133+ compatible = "mediatek,ap2woccif", "syscon";
134+ reg = <0 0x152A5000 0 0x1000>;
135 interrupt-parent = <&gic>;
136- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
137- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
138- <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
139+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
140+ };
141+
142+ ap2woccif2: ap2woccif@153A5000 {
143+ compatible = "mediatek,ap2woccif", "syscon";
144+ reg = <0 0x153A5000 0 0x1000>;
145+ interrupt-parent = <&gic>;
146+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
147 };
148
149 wocpu0_ilm: wocpu0_ilm@151E0000 {
150@@ -254,31 +269,53 @@
151 reg = <0 0x151E0000 0 0x8000>;
152 };
153
154- wocpu1_ilm: wocpu1_ilm@152E0000 {
155- compatible = "mediatek,wocpu1_ilm";
156+ wocpu1_ilm: wocpu_ilm@152E0000 {
157+ compatible = "mediatek,wocpu_ilm";
158 reg = <0 0x152E0000 0 0x8000>;
159 };
160
161- wocpu2_ilm: wocpu2_ilm@153E0000 {
162- compatible = "mediatek,wocpu2_ilm";
163- reg = <0 0x153E0000 0 0x8000>;
164+ wocpu2_ilm: wocpu_ilm@153E0000 {
165+ compatible = "mediatek,wocpu_ilm";
166+ reg = <0 0x153E0000 0 0x8000>;
167+ };
168+
169+ wocpu0_dlm: wocpu_dlm@151E8000 {
170+ compatible = "mediatek,wocpu_dlm";
171+ reg = <0 0x151E8000 0 0x2000>;
172+
173+ resets = <&ethsysrst 0>;
174+ reset-names = "wocpu_rst";
175+ };
176+
177+ wocpu1_dlm: wocpu_dlm@0x152E8000 {
178+ compatible = "mediatek,wocpu_dlm";
179+ reg = <0 0x152E8000 0 0x2000>;
180+
181+ resets = <&ethsysrst 0>;
182+ reset-names = "wocpu_rst";
183 };
184
185- wocpu_dlm: wocpu_dlm@151E8000 {
186+ wocpu2_dlm: wocpu_dlm@0x153E8000 {
187 compatible = "mediatek,wocpu_dlm";
188- reg = <0 0x151E8000 0 0x2000>,
189- <0 0x152E8000 0 0x2000>,
190- <0 0x153E8000 0 0x2000>;
191+ reg = <0 0x153E8000 0 0x2000>;
192
193 resets = <&ethsysrst 0>;
194 reset-names = "wocpu_rst";
195 };
196
197- cpu_boot: wocpu_boot@15194000 {
198- compatible = "mediatek,wocpu_boot";
199- reg = <0 0x15194000 0 0x1000>,
200- <0 0x15294000 0 0x1000>,
201- <0 0x15394000 0 0x1000>;
202+ cpu0_boot: wocpu_boot@15194000 {
203+ compatible = "mediatek,wocpu0_boot";
204+ reg = <0 0x15194000 0 0x1000>;
205+ };
206+
207+ cpu1_boot: wocpu_boot@15294000 {
208+ compatible = "mediatek,wocpu1_boot";
209+ reg = <0 0x15294000 0 0x1000>;
210+ };
211+
212+ cpu2_boot: wocpu_boot@15394000 {
213+ compatible = "mediatek,wocpu2_boot";
214+ reg = <0 0x15394000 0 0x1000>;
215 };
216
217 reserved-memory {
218@@ -827,6 +864,7 @@
219 <&topckgen CK_TOP_CB_SGM_325M>;
220 mediatek,ethsys = <&ethsys>;
221 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
222+ mediatek,wed = <&wed0>, <&wed1>, <&wed2>;
223 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
224 mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
225 mediatek,xfi_pll = <&xfi_pll>;
226diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts b/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
227index 7db5164..0a6db8b 100644
228--- a/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
229+++ b/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nor.dts
230@@ -341,9 +341,23 @@
231 status = "okay";
232 };
233
234-&wed {
235+&wed0 {
236 dy_txbm_enable = "true";
237 dy_txbm_budge = <8>;
238 txbm_init_sz = <10>;
239 status = "okay";
240 };
241+
242+&wed1 {
243+ dy_txbm_enable = "true";
244+ dy_txbm_budge = <8>;
245+ txbm_init_sz = <10>;
246+ status = "okay";
247+};
248+
249+&wed2 {
250+ dy_txbm_enable = "true";
251+ dy_txbm_budge = <8>;
252+ txbm_init_sz = <10>;
253+ status = "okay";
254+};
255\ No newline at end of file
256diff --git a/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts b/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts
257index 67c6508..c407b33 100644
258--- a/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts
259+++ b/arch/arm64/boot/dts/mediatek/mt7988d-dsa-10g-spim-nor.dts
260@@ -325,9 +325,23 @@
261 status = "okay";
262 };
263
264-&wed {
265+&wed0 {
266 dy_txbm_enable = "true";
267 dy_txbm_budge = <8>;
268 txbm_init_sz = <10>;
269 status = "okay";
270 };
271+
272+&wed1 {
273+ dy_txbm_enable = "true";
274+ dy_txbm_budge = <8>;
275+ txbm_init_sz = <10>;
276+ status = "okay";
277+};
278+
279+&wed2 {
280+ dy_txbm_enable = "true";
281+ dy_txbm_budge = <8>;
282+ txbm_init_sz = <10>;
283+ status = "okay";
284+};
285\ No newline at end of file
286diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
287index 388982c..d59c29f 100644
288--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
289+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
290@@ -4709,7 +4709,8 @@ static int mtk_probe(struct platform_device *pdev)
291 "mediatek,wed", i);
292 static const u32 wdma_regs[] = {
293 MTK_WDMA0_BASE,
294- MTK_WDMA1_BASE
295+ MTK_WDMA1_BASE,
296+ MTK_WDMA2_BASE
297 };
298 void __iomem *wdma;
299 u32 wdma_phy;
300diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
301index a9feaed..70e8377 100644
302--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
303+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
developer8c109ee2023-06-29 16:44:45 +0800[diff] [blame]304@@ -600,9 +600,12 @@
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]305 #define RX_DMA_SPORT_MASK 0x7
306 #define RX_DMA_SPORT_MASK_V2 0xf
307
308-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
309+#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
310 #define MTK_WDMA0_BASE 0x4800
311 #define MTK_WDMA1_BASE 0x4c00
312+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
313+#define MTK_WDMA2_BASE 0x5000
314+#endif
315 #else
316 #define MTK_WDMA0_BASE 0x2800
317 #define MTK_WDMA1_BASE 0x2c00
318diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
319old mode 100755
320new mode 100644
321index bc13a9b..3910163
322--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
323+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
324@@ -9,6 +9,7 @@
325 #include <linux/if_ether.h>
326 #include <linux/if_vlan.h>
327 #include <net/dsa.h>
328+#include <net/route.h>
329 #include "mtk_eth_soc.h"
330 #include "mtk_ppe.h"
331 #include "mtk_ppe_regs.h"
332@@ -396,7 +397,7 @@ int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)
333 }
334
335 int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
336- int bss, int wcid)
337+ int bss, int wcid, bool amsdu_en)
338 {
339 struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
340 u32 *ib2 = mtk_foe_entry_ib2(entry);
341@@ -408,6 +409,9 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
342
343 l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
344 FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
345+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
346+ l2->winfo_pao = FIELD_PREP(MTK_FOE_WINFO_PAO_AMSDU_EN, amsdu_en);
347+#endif
348 #else
349 if (wdma_idx)
350 *ib2 |= MTK_FOE_IB2_WDMA_DEVIDX;
351@@ -443,6 +447,17 @@ int mtk_foe_entry_set_dscp(struct mtk_foe_entry *entry, int dscp)
352 *ib2 &= ~MTK_FOE_IB2_DSCP;
353 *ib2 |= FIELD_PREP(MTK_FOE_IB2_DSCP, dscp);
354
355+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
356+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
357+
358+ if (*ib2 & MTK_FOE_IB2_WDMA_WINFO &&
359+ l2->winfo_pao & MTK_FOE_WINFO_PAO_AMSDU_EN) {
360+ u8 tid = rt_tos2priority(dscp) & 0xf;
361+
362+ l2->winfo_pao |= FIELD_PREP(MTK_FOE_WINFO_PAO_TID, tid);
363+ }
364+#endif
365+
366 return 0;
367 }
368
369diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
370index df10040..9e7d5aa 100644
371--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
372+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
373@@ -428,7 +428,7 @@ int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);
374 int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);
375 int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);
376 int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,
377- int bss, int wcid);
378+ int bss, int wcid, bool amsdu_en);
379 int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid);
380 int mtk_foe_entry_set_dscp(struct mtk_foe_entry *entry, int dscp);
381 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
382diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
383index 9bc0857..86fc9a1 100644
384--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
385+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
386@@ -112,6 +112,7 @@ mtk_flow_get_wdma_info(struct net_device *dev, const u8 *addr, struct mtk_wdma_i
387 info->queue = path.mtk_wdma.queue;
388 info->bss = path.mtk_wdma.bss;
389 info->wcid = path.mtk_wdma.wcid;
390+ info->amsdu_en = path.mtk_wdma.amsdu_en;
391
392 return 0;
393 }
394@@ -193,13 +194,15 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,
395
396 if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
397 mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,
398- info.wcid);
399+ info.wcid, info.amsdu_en);
400 pse_port = PSE_PPE0_PORT;
401 #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
402 if (info.wdma_idx == 0)
403 pse_port = PSE_WDMA0_PORT;
404 else if (info.wdma_idx == 1)
405 pse_port = PSE_WDMA1_PORT;
406+ else if (info.wdma_idx == 2)
407+ pse_port = PSE_WDMA2_PORT;
408 else
409 return -EOPNOTSUPP;
410 #endif
411@@ -458,8 +461,8 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)
412 if (err)
413 return err;
414
415- if (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0)
416- return err;
417+ /*if (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0)
418+ return err;*/
419
420 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
421 if (!entry)
422@@ -499,8 +502,8 @@ clear:
423 mtk_foe_entry_clear(eth->ppe[i], entry);
424 free:
425 kfree(entry);
426- if (wed_index >= 0)
427- mtk_wed_flow_remove(wed_index);
428+ /*if (wed_index >= 0)
429+ mtk_wed_flow_remove(wed_index);*/
430 return err;
431 }
432
433diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
434index 37a86c3..e3809db 100644
435--- a/drivers/net/ethernet/mediatek/mtk_wed.c
436+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
437@@ -28,7 +28,7 @@ struct wo_cmd_ring {
438 u32 cnt;
439 u32 unit;
440 };
441-static struct mtk_wed_hw *hw_list[2];
442+static struct mtk_wed_hw *hw_list[3];
443 static DEFINE_MUTEX(hw_lock);
444
445 static void
446@@ -73,6 +73,26 @@ mtk_wdma_read_reset(struct mtk_wed_device *dev)
447 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
448 }
449
450+static u32
451+mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
452+{
453+ if (wed_r32(dev, reg) & mask)
454+ return true;
455+
456+ return false;
457+}
458+
459+static int
460+mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
461+{
462+ int sleep = 1000;
463+ int timeout = 100 * sleep;
464+ u32 val;
465+
466+ return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
467+ timeout, false, dev, reg, mask);
468+}
469+
470 static int
471 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
472 {
473@@ -235,6 +255,8 @@ mtk_wed_assign(struct mtk_wed_device *dev)
474 continue;
475
476 hw->wed_dev = dev;
477+ hw->pci_base = MTK_WED_PCIE_BASE;
478+
479 return hw;
480 }
481
482@@ -242,23 +264,84 @@ mtk_wed_assign(struct mtk_wed_device *dev)
483 }
484
485 static int
486-mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
487+mtk_wed_pao_buffer_alloc(struct mtk_wed_device *dev)
488+{
489+ struct mtk_wed_pao *pao;
490+ int i, j;
491+
492+ pao = kzalloc(sizeof(struct mtk_wed_pao), GFP_KERNEL);
493+ if (!pao)
494+ return -ENOMEM;
495+
496+ dev->hw->wed_pao = pao;
497+
498+ for (i = 0; i < 32; i++) {
499+ /* each segment is 64K*/
500+ pao->hif_txd[i] = (char *)__get_free_pages(GFP_ATOMIC |
501+ GFP_DMA32 |
502+ __GFP_ZERO, 4);
503+ if (!pao->hif_txd[i])
504+ goto err;
505+
506+ pao->hif_txd_phys[i] = dma_map_single(dev->hw->dev,
507+ pao->hif_txd[i],
508+ 16 * PAGE_SIZE,
509+ DMA_TO_DEVICE);
510+ if (unlikely(dma_mapping_error(dev->hw->dev,
511+ pao->hif_txd_phys[i])))
512+ goto err;
513+ }
514+
515+ return 0;
516+
517+err:
518+ for (j = 0; j < i; j++)
519+ dma_unmap_single(dev->hw->dev, pao->hif_txd_phys[j],
520+ 16 * PAGE_SIZE, DMA_TO_DEVICE);
521+
522+ return -ENOMEM;
523+}
524+
525+static int
526+mtk_wed_pao_free_buffer(struct mtk_wed_device *dev)
527+{
528+ struct mtk_wed_pao *pao = dev->hw->wed_pao;
529+ int i;
530+
531+ for (i = 0; i < 32; i++) {
532+ dma_unmap_single(dev->hw->dev, pao->hif_txd_phys[i],
533+ 16 * PAGE_SIZE, DMA_TO_DEVICE);
534+ free_pages((unsigned long)pao->hif_txd[i], 4);
535+ }
536+
537+ return 0;
538+}
539+
540+static int
541+mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
542 {
543 struct mtk_wdma_desc *desc;
544+ void *desc_ptr;
545 dma_addr_t desc_phys;
546- void **page_list;
547+ struct dma_page_info *page_list;
548 u32 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG1;
549 int token = dev->wlan.token_start;
550- int ring_size, n_pages, page_idx;
551- int i;
552-
553+ int ring_size, pkt_nums, n_pages, page_idx;
554+ int i, ret = 0;
555
556 if (dev->ver == MTK_WED_V1) {
557 ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
558- } else {
559+ pkt_nums = ring_size;
560+ dev->tx_buf_ring.desc_size = sizeof(struct mtk_wdma_desc);
561+ } else if (dev->hw->version == 2) {
562 ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT +
563 MTK_WED_WDMA_RING_SIZE * 2;
564 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG0;
565+ dev->tx_buf_ring.desc_size = sizeof(struct mtk_wdma_desc);
566+ } else if (dev->hw->version == 3) {
567+ ring_size = MTK_WED_TX_BM_DMA_SIZE;
568+ pkt_nums = MTK_WED_TX_BM_PKT_CNT;
569+ dev->tx_buf_ring.desc_size = sizeof(struct mtk_rxbm_desc);
570 }
571
572 n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
573@@ -267,18 +350,20 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
574 if (!page_list)
575 return -ENOMEM;
576
577- dev->buf_ring.size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
578- dev->buf_ring.pages = page_list;
579+ dev->tx_buf_ring.size = ring_size;
580+ dev->tx_buf_ring.pages = page_list;
581+ dev->tx_buf_ring.pkt_nums = pkt_nums;
582
583- desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
584- &desc_phys, GFP_KERNEL);
585- if (!desc)
586+ desc_ptr = dma_alloc_coherent(dev->hw->dev,
587+ ring_size * dev->tx_buf_ring.desc_size,
588+ &desc_phys, GFP_KERNEL);
589+ if (!desc_ptr)
590 return -ENOMEM;
591
592- dev->buf_ring.desc = desc;
593- dev->buf_ring.desc_phys = desc_phys;
594+ dev->tx_buf_ring.desc = desc_ptr;
595+ dev->tx_buf_ring.desc_phys = desc_phys;
596
597- for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
598+ for (i = 0, page_idx = 0; i < pkt_nums; i += MTK_WED_BUF_PER_PAGE) {
599 dma_addr_t page_phys, buf_phys;
600 struct page *page;
601 void *buf;
602@@ -295,7 +380,10 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
603 return -ENOMEM;
604 }
605
606- page_list[page_idx++] = page;
607+ page_list[page_idx].addr = page;
608+ page_list[page_idx].addr_phys = page_phys;
609+ page_idx++;
610+
611 dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
612 DMA_BIDIRECTIONAL);
613
614@@ -303,19 +391,23 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
615 buf_phys = page_phys;
616
617 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
618- u32 txd_size;
619-
620- txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
621-
622+ desc = desc_ptr;
623 desc->buf0 = buf_phys;
624- desc->buf1 = buf_phys + txd_size;
625- desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,
626- txd_size) |
627- FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
628- MTK_WED_BUF_SIZE - txd_size) |
629- last_seg;
630- desc->info = 0;
631- desc++;
632+ if (dev->hw->version < 3) {
633+ u32 txd_size;
634+
635+ txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
636+ desc->buf1 = buf_phys + txd_size;
637+ desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,
638+ txd_size) |
639+ FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
640+ MTK_WED_BUF_SIZE - txd_size) |
641+ last_seg;
642+ desc->info = 0;
643+ } else {
644+ desc->ctrl = token << 16;
645+ }
646+ desc_ptr += dev->tx_buf_ring.desc_size;
647
648 buf += MTK_WED_BUF_SIZE;
649 buf_phys += MTK_WED_BUF_SIZE;
650@@ -325,15 +417,18 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
651 DMA_BIDIRECTIONAL);
652 }
653
654- return 0;
655+ if (dev->hw->version == 3)
656+ ret = mtk_wed_pao_buffer_alloc(dev);
657+
658+ return ret;
659 }
660
661 static void
662-mtk_wed_free_buffer(struct mtk_wed_device *dev)
663+mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
664 {
665- struct mtk_wdma_desc *desc = dev->buf_ring.desc;
666- void **page_list = dev->buf_ring.pages;
667- int ring_size, page_idx;
668+ struct mtk_rxbm_desc *desc = dev->tx_buf_ring.desc;
669+ struct dma_page_info *page_list = dev->tx_buf_ring.pages;
670+ int ring_size, page_idx, pkt_nums;
671 int i;
672
673 if (!page_list)
674@@ -342,33 +437,33 @@ mtk_wed_free_buffer(struct mtk_wed_device *dev)
675 if (!desc)
676 goto free_pagelist;
677
678- if (dev->ver == MTK_WED_V1) {
679- ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
680- } else {
681- ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT +
682- MTK_WED_WDMA_RING_SIZE * 2;
683+ pkt_nums = ring_size = dev->tx_buf_ring.size;
684+ if (dev->hw->version == 3) {
685+ mtk_wed_pao_free_buffer(dev);
686+ pkt_nums = dev->tx_buf_ring.pkt_nums;
687 }
688
689- for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
690- void *page = page_list[page_idx++];
691+ for (i = 0, page_idx = 0; i < pkt_nums; i += MTK_WED_BUF_PER_PAGE) {
692+ void *page = page_list[page_idx].addr;
693
694 if (!page)
695 break;
696
697- dma_unmap_page(dev->hw->dev, desc[i].buf0,
698+ dma_unmap_page(dev->hw->dev, page_list[page_idx].addr_phys,
699 PAGE_SIZE, DMA_BIDIRECTIONAL);
700 __free_page(page);
701+ page_idx++;
702 }
703
704- dma_free_coherent(dev->hw->dev, ring_size * sizeof(*desc),
705- desc, dev->buf_ring.desc_phys);
706+ dma_free_coherent(dev->hw->dev, ring_size * dev->tx_buf_ring.desc_size,
707+ dev->tx_buf_ring.desc, dev->tx_buf_ring.desc_phys);
708
709 free_pagelist:
710 kfree(page_list);
711 }
712
713 static int
714-mtk_wed_rx_bm_alloc(struct mtk_wed_device *dev)
715+mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
716 {
717 struct mtk_rxbm_desc *desc;
718 dma_addr_t desc_phys;
719@@ -389,7 +484,7 @@ mtk_wed_rx_bm_alloc(struct mtk_wed_device *dev)
720 }
721
722 static void
723-mtk_wed_free_rx_bm(struct mtk_wed_device *dev)
724+mtk_wed_free_rx_buffer(struct mtk_wed_device *dev)
725 {
726 struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc;
727 int ring_size = dev->rx_buf_ring.size;
728@@ -403,6 +498,113 @@ mtk_wed_free_rx_bm(struct mtk_wed_device *dev)
729 desc, dev->rx_buf_ring.desc_phys);
730 }
731
732+/* TODO */
733+static int
734+mtk_wed_rx_page_buffer_alloc(struct mtk_wed_device *dev)
735+{
736+ int ring_size = dev->wlan.rx_nbuf, buf_num = MTK_WED_RX_PG_BM_CNT;
737+ struct mtk_rxbm_desc *desc;
738+ dma_addr_t desc_phys;
739+ struct dma_page_info *page_list;
740+ int n_pages, page_idx;
741+ int i;
742+
743+ n_pages = buf_num / MTK_WED_RX_PAGE_BUF_PER_PAGE;
744+
745+ page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
746+ if (!page_list)
747+ return -ENOMEM;
748+
749+ dev->rx_page_buf_ring.size = ring_size & ~(MTK_WED_BUF_PER_PAGE - 1);
750+ dev->rx_page_buf_ring.pages = page_list;
751+ dev->rx_page_buf_ring.pkt_nums = buf_num;
752+
753+ desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
754+ &desc_phys, GFP_KERNEL);
755+ if (!desc)
756+ return -ENOMEM;
757+
758+ dev->rx_page_buf_ring.desc = desc;
759+ dev->rx_page_buf_ring.desc_phys = desc_phys;
760+
761+ for (i = 0, page_idx = 0; i < buf_num; i += MTK_WED_RX_PAGE_BUF_PER_PAGE) {
762+ dma_addr_t page_phys, buf_phys;
763+ struct page *page;
764+ void *buf;
765+ int s;
766+
767+ page = __dev_alloc_pages(GFP_KERNEL, 0);
768+ if (!page)
769+ return -ENOMEM;
770+
771+ page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
772+ DMA_BIDIRECTIONAL);
773+ if (dma_mapping_error(dev->hw->dev, page_phys)) {
774+ __free_page(page);
775+ return -ENOMEM;
776+ }
777+
778+ page_list[page_idx].addr= page;
779+ page_list[page_idx].addr_phys= page_phys;
780+ page_idx++;
781+
782+ dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
783+ DMA_BIDIRECTIONAL);
784+
785+ buf = page_to_virt(page);
786+ buf_phys = page_phys;
787+
788+ for (s = 0; s < MTK_WED_RX_PAGE_BUF_PER_PAGE; s++) {
789+
790+ desc->buf0 = cpu_to_le32(buf_phys);
791+ desc++;
792+
793+ buf += MTK_WED_PAGE_BUF_SIZE;
794+ buf_phys += MTK_WED_PAGE_BUF_SIZE;
795+ }
796+
797+ dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
798+ DMA_BIDIRECTIONAL);
799+ }
800+
801+ return 0;
802+}
803+
804+static void
805+mtk_wed_rx_page_free_buffer(struct mtk_wed_device *dev)
806+{
807+ struct mtk_rxbm_desc *desc = dev->rx_page_buf_ring.desc;
808+ struct dma_page_info *page_list = dev->rx_page_buf_ring.pages;
809+ int ring_size, page_idx;
810+ int i;
811+
812+ if (!page_list)
813+ return;
814+
815+ if (!desc)
816+ goto free_pagelist;
817+
818+ ring_size = dev->rx_page_buf_ring.pkt_nums;
819+
820+ for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_RX_PAGE_BUF_PER_PAGE) {
821+ void *page = page_list[page_idx].addr;
822+
823+ if (!page)
824+ break;
825+
826+ dma_unmap_page(dev->hw->dev, page_list[page_idx].addr_phys,
827+ PAGE_SIZE, DMA_BIDIRECTIONAL);
828+ __free_page(page);
829+ page_idx++;
830+ }
831+
developera60ce2b2023-06-16 13:07:18 +0800[diff] [blame]832+ dma_free_coherent(dev->hw->dev, dev->rx_page_buf_ring.size * sizeof(*desc),
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]833+ desc, dev->rx_page_buf_ring.desc_phys);
834+
835+free_pagelist:
836+ kfree(page_list);
837+}
838+
839 static void
840 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int scale)
841 {
842@@ -416,19 +618,25 @@ mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int sca
843 static void
844 mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
845 {
846- int i;
847+ int i, scale = dev->hw->version > 1 ? 2 : 1;
848
849 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
850- mtk_wed_free_ring(dev, &dev->tx_ring[i], 1);
851+ if (!(dev->rx_ring[i].flags & MTK_WED_RING_CONFIGURED))
852+ mtk_wed_free_ring(dev, &dev->tx_ring[i], 1);
853+
854 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
855- mtk_wed_free_ring(dev, &dev->tx_wdma[i], dev->ver);
856+ if ((dev->rx_ring[i].flags & MTK_WED_RING_CONFIGURED))
857+ mtk_wed_free_ring(dev, &dev->tx_wdma[i], scale);
858 }
859
860 static void
861 mtk_wed_free_rx_rings(struct mtk_wed_device *dev)
862 {
863- mtk_wed_free_rx_bm(dev);
864+ mtk_wed_free_rx_buffer(dev);
865 mtk_wed_free_ring(dev, &dev->rro.rro_ring, 1);
866+
867+ if (dev->wlan.hwrro)
868+ mtk_wed_rx_page_free_buffer(dev);
869 }
870
871 static void
872@@ -437,7 +645,7 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
873 u32 wdma_mask;
874
875 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
876- if (dev->ver > MTK_WED_V1)
877+ if (mtk_wed_get_rx_capa(dev))
878 wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
879 GENMASK(1, 0));
880 /* wed control cr set */
881@@ -447,7 +655,7 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
882 MTK_WED_CTRL_WED_TX_BM_EN |
883 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
884
885- if (dev->ver == MTK_WED_V1) {
886+ if (dev->hw->version == 1) {
887 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
888 MTK_WED_PCIE_INT_TRIGGER_STATUS);
889
890@@ -458,6 +666,8 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
891 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
892 MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
893 } else {
894+ if (dev->hw->version == 3)
895+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
896
897 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
898 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
899@@ -475,18 +685,20 @@ mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
900 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
901 dev->wlan.txfree_tbit));
902
903- wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
904- MTK_WED_WPDMA_INT_CTRL_RX0_EN |
905- MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
906- MTK_WED_WPDMA_INT_CTRL_RX1_EN |
907- MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
908- FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
909- dev->wlan.rx_tbit[0]) |
910- FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
911- dev->wlan.rx_tbit[1]));
912+ if (mtk_wed_get_rx_capa(dev))
913+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
914+ MTK_WED_WPDMA_INT_CTRL_RX0_EN |
915+ MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
916+ MTK_WED_WPDMA_INT_CTRL_RX1_EN |
917+ MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
918+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
919+ dev->wlan.rx_tbit[0]) |
920+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
921+ dev->wlan.rx_tbit[1]));
922 }
923+
924 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
925- if (dev->ver == MTK_WED_V1) {
926+ if (dev->hw->version == 1) {
927 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
928 } else {
929 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
930@@ -506,6 +718,21 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
931 {
932 u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
933
934+ switch (dev->hw->version) {
935+ case 1:
936+ mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
937+ break;
938+ case 2 :
939+ mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH2 |
940+ MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH2 |
941+ MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
942+ MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
943+ break;
944+ case 3:
945+ mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT;
946+ break;
947+ }
948+
949 if (!dev->hw->num_flows)
950 mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
951
952@@ -514,31 +741,86 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
953 }
954
955 static void
956-mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en)
957+mtk_wed_pao_init(struct mtk_wed_device *dev)
958 {
959- if (en) {
960- wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
961- wed_w32(dev, MTK_WED_TXP_DW1,
962- FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
963- } else {
964- wed_w32(dev, MTK_WED_TXP_DW1,
965- FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
966- wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
967+ struct mtk_wed_pao *pao = dev->hw->wed_pao;
968+ int i;
969+
970+ for (i = 0; i < 32; i++)
971+ wed_w32(dev, MTK_WED_PAO_HIFTXD_BASE_L(i),
972+ pao->hif_txd_phys[i]);
973+
974+ /* init all sta parameter */
975+ wed_w32(dev, MTK_WED_PAO_STA_INFO_INIT, MTK_WED_PAO_STA_RMVL |
976+ MTK_WED_PAO_STA_WTBL_HDRT_MODE |
977+ FIELD_PREP(MTK_WED_PAO_STA_MAX_AMSDU_LEN,
978+ dev->wlan.max_amsdu_len >> 8) |
979+ FIELD_PREP(MTK_WED_PAO_STA_MAX_AMSDU_NUM,
980+ dev->wlan.max_amsdu_nums));
981+
982+ wed_w32(dev, MTK_WED_PAO_STA_INFO, MTK_WED_PAO_STA_INFO_DO_INIT);
983+
984+ if (mtk_wed_poll_busy(dev, MTK_WED_PAO_STA_INFO,
985+ MTK_WED_PAO_STA_INFO_DO_INIT)) {
986+ dev_err(dev->hw->dev, "mtk_wed%d: pao init failed!\n",
987+ dev->hw->index);
988+ return;
989 }
990+
991+ /* init pao txd src */
992+ wed_set(dev, MTK_WED_PAO_HIFTXD_CFG,
993+ FIELD_PREP(MTK_WED_PAO_HIFTXD_SRC, dev->hw->index));
994+
995+ /* init qmem */
996+ wed_set(dev, MTK_WED_PAO_PSE, MTK_WED_PAO_PSE_RESET);
997+ if (mtk_wed_poll_busy(dev, MTK_WED_PAO_MON_QMEM_STS1, BIT(29))) {
998+ pr_info("%s: init pao qmem fail\n", __func__);
999+ return;
1000+ }
1001+
1002+ /* eagle E1 PCIE1 tx ring 22 flow control issue */
1003+ if (dev->wlan.chip_id == 0x7991) {
1004+ wed_clr(dev, MTK_WED_PAO_AMSDU_FIFO,
1005+ MTK_WED_PAO_AMSDU_IS_PRIOR0_RING);
1006+ }
1007+
1008+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_PAO_EN);
1009+
1010+ return;
1011 }
1012
1013-static void
1014-mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
1015+static int
1016+mtk_wed_hwrro_init(struct mtk_wed_device *dev)
1017 {
1018-#define MTK_WFMDA_RX_DMA_EN BIT(2)
1019+ if (!mtk_wed_get_rx_capa(dev))
1020+ return 0;
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1021+
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1022+ wed_set(dev, MTK_WED_RRO_PG_BM_RX_DMAM,
1023+ FIELD_PREP(MTK_WED_RRO_PG_BM_RX_SDL0, 128));
1024+
1025+ wed_w32(dev, MTK_WED_RRO_PG_BM_BASE,
1026+ dev->rx_page_buf_ring.desc_phys);
1027+
1028+ wed_w32(dev, MTK_WED_RRO_PG_BM_INIT_PTR,
1029+ MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX |
1030+ FIELD_PREP(MTK_WED_RRO_PG_BM_SW_TAIL_IDX,
1031+ MTK_WED_RX_PG_BM_CNT));
1032+
1033+ /* enable rx_page_bm to fetch dmad */
1034+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
1035+
1036+ return 0;
1037+}
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1038
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1039+static int
1040+mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev,
1041+ struct mtk_wed_ring *ring)
1042+{
1043 int timeout = 3;
1044- u32 cur_idx, regs;
1045+ u32 cur_idx;
1046
1047 do {
1048- regs = MTK_WED_WPDMA_RING_RX_DATA(idx) +
1049- MTK_WED_RING_OFS_CPU_IDX;
1050- cur_idx = wed_r32(dev, regs);
1051+ cur_idx = readl(ring->wpdma + MTK_WED_RING_OFS_CPU_IDX);
1052 if (cur_idx == MTK_WED_RX_RING_SIZE - 1)
1053 break;
1054
1055@@ -546,70 +828,133 @@ mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
1056 timeout--;
1057 } while (timeout > 0);
1058
1059- if (timeout) {
1060- unsigned int val;
1061+ return timeout;
1062+}
1063
1064- val = wifi_r32(dev, dev->wlan.wpdma_rx_glo -
1065- dev->wlan.phy_base);
1066- val |= MTK_WFMDA_RX_DMA_EN;
1067
1068- wifi_w32(dev, dev->wlan.wpdma_rx_glo -
1069- dev->wlan.phy_base, val);
1070+static void
1071+mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en)
1072+{
1073+ if (en) {
1074+ wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
1075+ wed_w32(dev, MTK_WED_TXP_DW1,
1076+ FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
1077 } else {
1078- dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
1079- dev->hw->index, idx);
1080+ wed_w32(dev, MTK_WED_TXP_DW1,
1081+ FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
1082+ wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
1083 }
1084 }
1085
1086 static void
1087 mtk_wed_dma_enable(struct mtk_wed_device *dev)
1088 {
1089- wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1090- MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
1091+#define MTK_WFMDA_RX_DMA_EN BIT(2)
1092+
1093+ if (dev->hw->version == 1)
1094+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1095+ MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
1096
1097 wed_set(dev, MTK_WED_GLO_CFG,
1098 MTK_WED_GLO_CFG_TX_DMA_EN |
1099 MTK_WED_GLO_CFG_RX_DMA_EN);
1100+
1101+ wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
1102+ FIELD_PREP(MTK_WED_WDMA_RX_PREF_BURST_SIZE, 0x10) |
1103+ FIELD_PREP(MTK_WED_WDMA_RX_PREF_LOW_THRES, 0x8));
1104+ wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
1105+ MTK_WED_WDMA_RX_PREF_DDONE2_EN);
1106+
1107+ wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG, MTK_WED_WDMA_RX_PREF_EN);
1108+
1109 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1110 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
1111- MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
1112+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN |
1113+ MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR);
1114 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1115 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
1116
1117 wdma_set(dev, MTK_WDMA_GLO_CFG,
1118- MTK_WDMA_GLO_CFG_TX_DMA_EN |
1119+ MTK_WDMA_GLO_CFG_TX_DMA_EN /*|
1120 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
1121- MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
1122+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES*/);
1123
1124- if (dev->ver == MTK_WED_V1) {
1125+ if (dev->hw->version == 1) {
1126 wdma_set(dev, MTK_WDMA_GLO_CFG,
1127 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
1128 } else {
1129 int idx = 0;
1130
1131- wed_set(dev, MTK_WED_WPDMA_CTRL,
1132- MTK_WED_WPDMA_CTRL_SDL1_FIXED);
1133-
1134- wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1135- MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
1136- MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1137+ if (mtk_wed_get_rx_capa(dev))
1138+ wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1139+ MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
1140+ MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1141
1142 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1143 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
1144 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
1145
1146+ if (dev->hw->version == 3) {
1147+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1148+ MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST);
1149+ wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1150+ MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK |
1151+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK |
1152+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
1153+
1154+ wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
1155+ //wdma_w32(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
1156+ if (mtk_wed_get_rx_capa(dev)) {
1157+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
1158+ MTK_WED_WPDMA_RX_D_PREF_EN |
1159+ FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE, 0x10) |
1160+ FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_LOW_THRES, 0x8));
1161+
1162+ wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
1163+
1164+ wdma_set(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
1165+
1166+ wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
1167+ }
1168+ }
1169+
1170 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1171 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
1172 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
1173
1174+ if (!mtk_wed_get_rx_capa(dev))
1175+ return;
1176+
1177+ wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RXD_READ_LEN);
1178 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1179 MTK_WED_WPDMA_RX_D_RX_DRV_EN |
1180 FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
1181 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
1182 0x2));
1183
1184- for (idx = 0; idx < dev->hw->ring_num; idx++)
1185- mtk_wed_check_wfdma_rx_fill(dev, idx);
1186+ for (idx = 0; idx < dev->hw->ring_num; idx++) {
1187+ struct mtk_wed_ring *ring = &dev->rx_ring[idx];
1188+
1189+ if(!(ring->flags & MTK_WED_RING_CONFIGURED))
1190+ continue;
1191+
1192+ if(mtk_wed_check_wfdma_rx_fill(dev, ring)) {
1193+ unsigned int val;
1194+
1195+ val = wifi_r32(dev, dev->wlan.wpdma_rx_glo -
1196+ dev->wlan.phy_base);
1197+ val |= MTK_WFMDA_RX_DMA_EN;
1198+
1199+ wifi_w32(dev, dev->wlan.wpdma_rx_glo -
1200+ dev->wlan.phy_base, val);
1201+
1202+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable successful!\n",
1203+ dev->hw->index, idx);
1204+ } else {
1205+ dev_err(dev->hw->dev, "mtk_wed%d: rx(%d) dma enable failed!\n",
1206+ dev->hw->index, idx);
1207+ }
1208+ }
1209 }
1210 }
1211
1212@@ -644,15 +989,20 @@ mtk_wed_dma_disable(struct mtk_wed_device *dev)
1213 MTK_WED_WPDMA_RX_D_RX_DRV_EN);
1214 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
1215 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1216- }
1217
1218- mtk_wed_set_512_support(dev, false);
1219+ if (dev->hw->version == 3 && mtk_wed_get_rx_capa(dev)) {
1220+ wdma_clr(dev, MTK_WDMA_PREF_TX_CFG,
1221+ MTK_WDMA_PREF_TX_CFG_PREF_EN);
1222+ wdma_clr(dev, MTK_WDMA_PREF_RX_CFG,
1223+ MTK_WDMA_PREF_RX_CFG_PREF_EN);
1224+ }
1225+ }
1226 }
1227
1228 static void
1229 mtk_wed_stop(struct mtk_wed_device *dev)
1230 {
1231- if (dev->ver > MTK_WED_V1) {
1232+ if (mtk_wed_get_rx_capa(dev)) {
1233 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
1234 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
1235 }
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1236@@ -677,13 +1027,21 @@ mtk_wed_deinit(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1237 MTK_WED_CTRL_WED_TX_BM_EN |
1238 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1239
1240- if (dev->hw->ver == 1)
1241+ if (dev->hw->version == 1)
1242 return;
1243
1244 wed_clr(dev, MTK_WED_CTRL,
1245 MTK_WED_CTRL_RX_ROUTE_QM_EN |
1246 MTK_WED_CTRL_WED_RX_BM_EN |
1247 MTK_WED_CTRL_RX_RRO_QM_EN);
1248+
1249+ if (dev->hw->version == 3) {
1250+ wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_PAO_EN);
1251+ wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_TX_PAO);
1252+ wed_clr(dev, MTK_WED_PCIE_INT_CTRL,
1253+ MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
1254+ MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER);
1255+ }
1256 }
1257
1258 static void
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1259@@ -702,9 +1060,9 @@ mtk_wed_detach(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1260
1261 mtk_wdma_tx_reset(dev);
1262
1263- mtk_wed_free_buffer(dev);
1264+ mtk_wed_free_tx_buffer(dev);
1265 mtk_wed_free_tx_rings(dev);
1266- if (dev->ver > MTK_WED_V1) {
1267+ if (mtk_wed_get_rx_capa(dev)) {
1268 mtk_wed_wo_reset(dev);
1269 mtk_wed_free_rx_rings(dev);
1270 mtk_wed_wo_exit(hw);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1271@@ -731,24 +1089,29 @@ mtk_wed_detach(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1272 static void
1273 mtk_wed_bus_init(struct mtk_wed_device *dev)
1274 {
1275-#define PCIE_BASE_ADDR0 0x11280000
1276+ switch (dev->wlan.bus_type) {
1277+ case MTK_WED_BUS_PCIE: {
1278+ struct device_node *np = dev->hw->eth->dev->of_node;
1279+ struct regmap *regs;
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1280
1281- if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
1282- struct device_node *node;
1283- void __iomem * base_addr;
1284- u32 value = 0;
1285+ if (dev->hw->version == 2) {
1286+ regs = syscon_regmap_lookup_by_phandle(np,
1287+ "mediatek,wed-pcie");
1288+ if (IS_ERR(regs))
1289+ break;
1290
1291- node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0);
1292- if (!node) {
1293- pr_err("%s: no wed_pcie node\n", __func__);
1294- return;
1295+ regmap_update_bits(regs, 0, BIT(0), BIT(0));
1296 }
1297
1298- base_addr = of_iomap(node, 0);
1299-
1300- value = readl(base_addr);
1301- value |= BIT(0);
1302- writel(value, base_addr);
1303+ if (dev->wlan.msi) {
1304+ wed_w32(dev, MTK_WED_PCIE_CFG_INTM, dev->hw->pci_base| 0xc08);
1305+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, dev->hw->pci_base | 0xc04);
1306+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8));
1307+ } else {
1308+ wed_w32(dev, MTK_WED_PCIE_CFG_INTM, dev->hw->pci_base | 0x180);
1309+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, dev->hw->pci_base | 0x184);
1310+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
1311+ }
1312
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1313 wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
1314 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
1315@@ -756,45 +1119,52 @@ mtk_wed_bus_init(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1316 /* pcie interrupt control: pola/source selection */
1317 wed_set(dev, MTK_WED_PCIE_INT_CTRL,
1318 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
1319- FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
1320- wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1321-
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1322- value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
1323- value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
1324- wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
1325- wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1326+ MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER |
1327+ FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, dev->hw->index));
1328
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1329- value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
1330- value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
1331-
1332- wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
1333- wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
1334-
1335- /* pola setting */
1336- value = wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
1337- wed_set(dev, MTK_WED_PCIE_INT_CTRL,
1338- MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
1339- } else if (dev->wlan.bus_type == MTK_WED_BUS_AXI) {
1340+ break;
1341+ }
1342+ case MTK_WED_BUS_AXI:
1343 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
1344 MTK_WED_WPDMA_INT_CTRL_SIG_SRC |
1345 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0));
1346+ break;
1347+ default:
1348+ break;
1349 }
1350+
1351 return;
1352 }
1353
1354 static void
1355 mtk_wed_set_wpdma(struct mtk_wed_device *dev)
1356 {
1357- if (dev->ver > MTK_WED_V1) {
1358+ if (dev->hw->version == 1) {
1359+ wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
1360+ } else {
1361+ mtk_wed_bus_init(dev);
1362+
1363 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
1364 wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
1365- wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
1366+ wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
1367 wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
1368
1369- wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
1370- wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
1371- } else {
1372- wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
1373+ if (mtk_wed_get_rx_capa(dev)) {
1374+ int i;
1375+
1376+ wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
1377+ wed_w32(dev, MTK_WED_WPDMA_RX_RING0, dev->wlan.wpdma_rx);
1378+ wed_w32(dev, MTK_WED_WPDMA_RX_RING1, dev->wlan.wpdma_rx + 0x10);
1379+
1380+ if (dev->wlan.hwrro) {
1381+ wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]);
1382+ wed_w32(dev, MTK_WED_RRO_RX_D_CFG(1), dev->wlan.wpdma_rx_rro[1]);
1383+ for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
1384+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING_CFG(i),
1385+ dev->wlan.wpdma_rx_pg + i * 0x10);
1386+ }
1387+ }
1388+ }
1389 }
1390 }
1391
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1392@@ -806,21 +1176,25 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1393 mtk_wed_deinit(dev);
1394 mtk_wed_reset(dev, MTK_WED_RESET_WED);
1395
1396- if (dev->ver > MTK_WED_V1)
1397- mtk_wed_bus_init(dev);
1398-
1399 mtk_wed_set_wpdma(dev);
1400
1401- mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
1402- MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
1403- MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
1404- set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
1405- MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
1406- MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
1407+ if (dev->hw->version == 3) {
1408+ mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE;
1409+ set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2);
1410+ } else {
1411+ mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
1412+ MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
1413+ MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
1414+ set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
1415+ MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
1416+ MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
1417+ }
1418+
1419 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
1420
1421- if (dev->ver == MTK_WED_V1) {
1422+ if (dev->hw->version == 1) {
1423 u32 offset;
1424+
1425 offset = dev->hw->index ? 0x04000400 : 0;
1426 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
1427 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1428@@ -907,11 +1281,16 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1429 } while (1);
1430
1431 /* configure RX_ROUTE_QM */
1432- wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1433- wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
1434- wed_set(dev, MTK_WED_RTQM_GLO_CFG,
1435- FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
1436- wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1437+ if (dev->hw->version == 2) {
1438+ wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1439+ wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
1440+ wed_set(dev, MTK_WED_RTQM_GLO_CFG,
1441+ FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
1442+ wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
1443+ } else {
1444+ wed_set(dev, MTK_WED_RTQM_ENQ_CFG0,
1445+ FIELD_PREP(MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT, 0x3 + dev->hw->index));
1446+ }
1447
1448 /* enable RX_ROUTE_QM */
1449 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1450@@ -920,23 +1299,45 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1451 static void
1452 mtk_wed_tx_hw_init(struct mtk_wed_device *dev)
1453 {
1454- int size = dev->buf_ring.size;
1455+ int size = dev->wlan.nbuf;
1456 int rev_size = MTK_WED_TX_RING_SIZE / 2;
1457- int thr = 1;
1458+ int thr_lo = 1, thr_hi = 1;
1459
1460- if (dev->ver > MTK_WED_V1) {
1461+ if (dev->hw->version == 1) {
1462+ wed_w32(dev, MTK_WED_TX_BM_CTRL,
1463+ MTK_WED_TX_BM_CTRL_PAUSE |
1464+ FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) |
1465+ FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128));
1466+ } else {
1467 size = MTK_WED_WDMA_RING_SIZE * ARRAY_SIZE(dev->tx_wdma) +
1468- dev->buf_ring.size;
1469+ dev->tx_buf_ring.size;
1470 rev_size = size;
1471- thr = 0;
1472+ thr_lo = 0;
1473+ thr_hi = MTK_WED_TX_BM_DYN_THR_HI;
1474+
1475+ wed_w32(dev, MTK_WED_TX_TKID_CTRL,
1476+ MTK_WED_TX_TKID_CTRL_PAUSE |
1477+ FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
1478+ size / 128) |
1479+ FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
1480+ size / 128));
1481+
1482+ /* return SKBID + SDP back to bm */
1483+ if (dev->ver == 3) {
1484+ wed_set(dev, MTK_WED_TX_TKID_CTRL,
1485+ MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
1486+ size = dev->wlan.nbuf;
1487+ rev_size = size;
1488+ } else {
1489+ wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1490+ FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1491+ MTK_WED_TX_TKID_DYN_THR_HI);
1492+ }
1493 }
1494
1495- wed_w32(dev, MTK_WED_TX_BM_CTRL,
1496- MTK_WED_TX_BM_CTRL_PAUSE |
1497- FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) |
1498- FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128));
1499+ mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1500
1501- wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);
1502+ wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
1503
1504 wed_w32(dev, MTK_WED_TX_BM_TKID,
1505 FIELD_PREP(MTK_WED_TX_BM_TKID_START,
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1506@@ -946,25 +1347,44 @@ mtk_wed_tx_hw_init(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1507
1508 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
1509
1510- wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
1511- FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr) |
1512- MTK_WED_TX_BM_DYN_THR_HI);
1513+ if (dev->hw->version < 3)
1514+ wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
1515+ FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr_lo) |
1516+ FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr_hi));
1517+ else {
1518+ /* change to new bm */
1519+ wed_w32(dev, MTK_WED_TX_BM_INIT_PTR, dev->tx_buf_ring.pkt_nums |
1520+ MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
1521+ wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_LEGACY_EN);
1522+ }
1523
1524- if (dev->ver > MTK_WED_V1) {
1525+ if (dev->hw->version != 1) {
1526 wed_w32(dev, MTK_WED_TX_TKID_CTRL,
1527 MTK_WED_TX_TKID_CTRL_PAUSE |
1528 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
1529- dev->buf_ring.size / 128) |
1530+ size / 128) |
1531 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
1532- dev->buf_ring.size / 128));
1533- wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1534- FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1535- MTK_WED_TX_TKID_DYN_THR_HI);
1536+ size / 128));
1537+
1538+ /* return SKBID + SDP back to bm */
1539+ if (dev->ver == 3)
1540+ wed_set(dev, MTK_WED_TX_TKID_CTRL,
1541+ MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
1542+ else
1543+ wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
1544+ FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
1545+ MTK_WED_TX_TKID_DYN_THR_HI);
1546 }
1547- mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1548+ wed_w32(dev, MTK_WED_TX_BM_TKID,
1549+ FIELD_PREP(MTK_WED_TX_BM_TKID_START,
1550+ dev->wlan.token_start) |
1551+ FIELD_PREP(MTK_WED_TX_BM_TKID_END,
1552+ dev->wlan.token_start + dev->wlan.nbuf - 1));
1553
1554+ wed_w32(dev, MTK_WED_TX_BM_INIT_PTR, dev->tx_buf_ring.pkt_nums |
1555+ MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
1556 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
1557- if (dev->ver > MTK_WED_V1)
1558+ if (dev->hw->version != 1)
1559 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
1560 }
1561
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1562@@ -977,7 +1397,26 @@ mtk_wed_rx_hw_init(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1563
1564 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
1565
1566+ /* reset prefetch index of ring */
1567+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
1568+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1569+ wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
1570+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1571+
1572+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
1573+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1574+ wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
1575+ MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
1576+
1577+ /* reset prefetch FIFO of ring */
1578+ wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG,
1579+ MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR |
1580+ MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR);
1581+ wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);
1582+
1583 mtk_wed_rx_bm_hw_init(dev);
1584+ if (dev->wlan.hwrro)
1585+ mtk_wed_hwrro_init(dev);
1586 mtk_wed_rro_hw_init(dev);
1587 mtk_wed_route_qm_hw_init(dev);
1588 }
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1589@@ -991,7 +1430,7 @@ mtk_wed_hw_init(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1590 dev->init_done = true;
1591 mtk_wed_set_ext_int(dev, false);
1592 mtk_wed_tx_hw_init(dev);
1593- if (dev->ver > MTK_WED_V1)
1594+ if (mtk_wed_get_rx_capa(dev))
1595 mtk_wed_rx_hw_init(dev);
1596 }
1597
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1598@@ -1015,26 +1454,6 @@ mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale, bool tx)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1599 }
1600 }
1601
1602-static u32
1603-mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
1604-{
1605- if (wed_r32(dev, reg) & mask)
1606- return true;
1607-
1608- return false;
1609-}
1610-
1611-static int
1612-mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
1613-{
1614- int sleep = 1000;
1615- int timeout = 100 * sleep;
1616- u32 val;
1617-
1618- return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
1619- timeout, false, dev, reg, mask);
1620-}
1621-
1622 static void
1623 mtk_wed_rx_reset(struct mtk_wed_device *dev)
1624 {
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1625@@ -1133,7 +1552,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1626 mtk_wed_ring_reset(desc, MTK_WED_RX_RING_SIZE, 1, false);
1627 }
1628
1629- mtk_wed_free_rx_bm(dev);
1630+ mtk_wed_free_rx_buffer(dev);
1631 }
1632
1633
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1634@@ -1271,12 +1690,15 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1635 int idx, int size, bool reset)
1636 {
1637 struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
1638+ int scale = dev->hw->version > 1 ? 2 : 1;
1639
1640 if(!reset)
1641 if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1642- dev->ver, true))
1643+ scale, true))
1644 return -ENOMEM;
1645
1646+ wdma->flags |= MTK_WED_RING_CONFIGURED;
1647+
1648 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
1649 wdma->desc_phys);
1650 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1651@@ -1296,12 +1718,31 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1652 int idx, int size, bool reset)
1653 {
1654 struct mtk_wed_ring *wdma = &dev->rx_wdma[idx];
1655+ int scale = dev->hw->version > 1 ? 2 : 1;
1656
1657 if (!reset)
1658 if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1659- dev->ver, true))
1660+ scale, true))
1661 return -ENOMEM;
1662
1663+ if (dev->hw->version == 3) {
1664+ struct mtk_wdma_desc *desc = wdma->desc;
1665+ int i;
1666+
1667+ for (i = 0; i < MTK_WED_WDMA_RING_SIZE; i++) {
1668+ desc->buf0 = 0;
1669+ desc->ctrl = MTK_WDMA_DESC_CTRL_DMA_DONE;
1670+ desc->buf1 = 0;
1671+ desc->info = MTK_WDMA_TXD0_DESC_INFO_DMA_DONE;
1672+ desc++;
1673+ desc->buf0 = 0;
1674+ desc->ctrl = MTK_WDMA_DESC_CTRL_DMA_DONE;
1675+ desc->buf1 = 0;
1676+ desc->info = MTK_WDMA_TXD1_DESC_INFO_DMA_DONE;
1677+ desc++;
1678+ }
1679+ }
1680+
1681 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
1682 wdma->desc_phys);
1683 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1684@@ -1312,7 +1753,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1685 MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
1686 if (reset)
1687 mtk_wed_ring_reset(wdma->desc, MTK_WED_WDMA_RING_SIZE,
1688- dev->ver, true);
1689+ scale, true);
1690 if (idx == 0) {
1691 wed_w32(dev, MTK_WED_WDMA_RING_TX
1692 + MTK_WED_RING_OFS_BASE, wdma->desc_phys);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1693@@ -1395,7 +1836,7 @@ mtk_wed_send_msg(struct mtk_wed_device *dev, int cmd_id, void *data, int len)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1694 {
1695 struct mtk_wed_wo *wo = dev->hw->wed_wo;
1696
1697- if (dev->ver == MTK_WED_V1)
1698+ if (!mtk_wed_get_rx_capa(dev))
1699 return 0;
1700
1701 return mtk_wed_mcu_send_msg(wo, MODULE_ID_WO, cmd_id, data, len, true);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1702@@ -1420,13 +1861,87 @@ mtk_wed_ppe_check(struct mtk_wed_device *dev, struct sk_buff *skb,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1703 }
1704 }
1705
1706+static void
1707+mtk_wed_start_hwrro(struct mtk_wed_device *dev, u32 irq_mask)
1708+{
1709+ int idx, ret;
1710+
1711+ wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
1712+ wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
1713+
1714+ if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hwrro)
1715+ return;
1716+
1717+ wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR);
1718+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, MTK_WED_RRO_MSDU_PG_DRV_CLR);
1719+
1720+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_RX,
1721+ MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN |
1722+ MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR |
1723+ MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN |
1724+ MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR |
1725+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG,
1726+ dev->wlan.rro_rx_tbit[0]) |
1727+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG,
1728+ dev->wlan.rro_rx_tbit[1]));
1729+
1730+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG,
1731+ MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN |
1732+ MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR |
1733+ MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN |
1734+ MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR |
1735+ MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN |
1736+ MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR |
1737+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG,
1738+ dev->wlan.rx_pg_tbit[0]) |
1739+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG,
1740+ dev->wlan.rx_pg_tbit[1])|
1741+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG,
1742+ dev->wlan.rx_pg_tbit[2]));
1743+
1744+ /*
1745+ * RRO_MSDU_PG_RING2_CFG1_FLD_DRV_EN should be enabled after
1746+ * WM FWDL completed, otherwise RRO_MSDU_PG ring may broken
1747+ */
1748+ wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, MTK_WED_RRO_MSDU_PG_DRV_EN);
1749+
1750+ for (idx = 0; idx < MTK_WED_RX_QUEUES; idx++) {
1751+ struct mtk_wed_ring *ring = &dev->rx_rro_ring[idx];
1752+
1753+ if(!(ring->flags & MTK_WED_RING_CONFIGURED))
1754+ continue;
1755+
1756+ ret = mtk_wed_check_wfdma_rx_fill(dev, ring);
1757+ if (!ret)
1758+ dev_err(dev->hw->dev, "mtk_wed%d: rx_rro_ring(%d) init failed!\n",
1759+ dev->hw->index, idx);
1760+ }
1761+
1762+ for (idx = 0; idx < MTK_WED_RX_PAGE_QUEUES; idx++){
1763+ struct mtk_wed_ring *ring = &dev->rx_page_ring[idx];
1764+ if(!(ring->flags & MTK_WED_RING_CONFIGURED))
1765+ continue;
1766+
1767+ ret = mtk_wed_check_wfdma_rx_fill(dev, ring);
1768+ if (!ret)
1769+ dev_err(dev->hw->dev, "mtk_wed%d: rx_page_ring(%d) init failed!\n",
1770+ dev->hw->index, idx);
1771+ }
1772+}
1773+
1774 static void
1775 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
1776 {
1777 int i, ret;
1778
1779- if (dev->ver > MTK_WED_V1)
1780- ret = mtk_wed_rx_bm_alloc(dev);
1781+ if (mtk_wed_get_rx_capa(dev)) {
1782+ ret = mtk_wed_rx_buffer_alloc(dev);
1783+ if (ret)
1784+ return;
1785+
1786+ if (dev->wlan.hwrro)
1787+ mtk_wed_rx_page_buffer_alloc(dev);
1788+ }
1789
1790 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
1791 if (!dev->tx_wdma[i].desc)
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1792@@ -1437,7 +1952,7 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1793 mtk_wed_set_int(dev, irq_mask);
1794 mtk_wed_set_ext_int(dev, true);
1795
1796- if (dev->ver == MTK_WED_V1) {
1797+ if (dev->hw->version == 1) {
1798 u32 val;
1799
1800 val = dev->wlan.wpdma_phys |
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1801@@ -1448,33 +1963,52 @@ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1802 val |= BIT(1);
1803 val |= BIT(0);
1804 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
1805- } else {
1806+ } else if (mtk_wed_get_rx_capa(dev)) {
1807 /* driver set mid ready and only once */
1808 wed_w32(dev, MTK_WED_EXT_INT_MASK1,
1809 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1810 wed_w32(dev, MTK_WED_EXT_INT_MASK2,
1811 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1812+ if (dev->hw->version == 3)
1813+ wed_w32(dev, MTK_WED_EXT_INT_MASK3,
1814+ MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1815
1816 wed_r32(dev, MTK_WED_EXT_INT_MASK1);
1817 wed_r32(dev, MTK_WED_EXT_INT_MASK2);
1818+ if (dev->hw->version == 3)
1819+ wed_r32(dev, MTK_WED_EXT_INT_MASK3);
1820
1821 ret = mtk_wed_rro_cfg(dev);
1822 if (ret)
1823 return;
1824 }
1825- mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
1826+
1827+ if (dev->hw->version == 2)
1828+ mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
1829+ else if (dev->hw->version == 3)
1830+ mtk_wed_pao_init(dev);
1831
1832 mtk_wed_dma_enable(dev);
1833 dev->running = true;
1834 }
1835
1836+static int
1837+mtk_wed_get_pci_base(struct mtk_wed_device *dev)
1838+{
1839+ if (dev->hw->index == 0)
1840+ return MTK_WED_PCIE_BASE0;
1841+ else if (dev->hw->index == 1)
1842+ return MTK_WED_PCIE_BASE1;
1843+ else
1844+ return MTK_WED_PCIE_BASE2;
1845+}
1846+
1847 static int
1848 mtk_wed_attach(struct mtk_wed_device *dev)
1849 __releases(RCU)
1850 {
1851 struct mtk_wed_hw *hw;
1852 struct device *device;
1853- u16 ver;
1854 int ret = 0;
1855
1856 RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1857@@ -1494,34 +2028,30 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1858 goto out;
1859 }
1860
1861- device = dev->wlan.bus_type == MTK_WED_BUS_PCIE
1862- ? &dev->wlan.pci_dev->dev
1863- : &dev->wlan.platform_dev->dev;
1864+ device = dev->wlan.bus_type == MTK_WED_BUS_PCIE ?
1865+ &dev->wlan.pci_dev->dev
1866+ : &dev->wlan.platform_dev->dev;
1867 dev_info(device, "attaching wed device %d version %d\n",
1868- hw->index, hw->ver);
1869+ hw->index, hw->version);
1870
1871 dev->hw = hw;
1872 dev->dev = hw->dev;
1873 dev->irq = hw->irq;
1874 dev->wdma_idx = hw->index;
1875+ dev->ver = hw->version;
1876+
1877+ if (dev->hw->version == 3)
1878+ dev->hw->pci_base = mtk_wed_get_pci_base(dev);
1879
1880 if (hw->eth->dma_dev == hw->eth->dev &&
1881 of_dma_is_coherent(hw->eth->dev->of_node))
1882 mtk_eth_set_dma_device(hw->eth, hw->dev);
1883
1884- dev->ver = FIELD_GET(MTK_WED_REV_ID_MAJOR,
1885- wed_r32(dev, MTK_WED_REV_ID));
1886- if (dev->ver > MTK_WED_V1)
1887- ver = FIELD_GET(MTK_WED_REV_ID_MINOR,
1888- wed_r32(dev, MTK_WED_REV_ID));
1889-
1890- dev->rev_id = ((dev->ver << 28) | ver << 16);
1891-
1892- ret = mtk_wed_buffer_alloc(dev);
1893+ ret = mtk_wed_tx_buffer_alloc(dev);
1894 if (ret)
1895 goto error;
1896
1897- if (dev->ver > MTK_WED_V1) {
1898+ if (mtk_wed_get_rx_capa(dev)) {
1899 ret = mtk_wed_rro_alloc(dev);
1900 if (ret)
1901 goto error;
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1902@@ -1533,15 +2063,20 @@ mtk_wed_attach(struct mtk_wed_device *dev)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1903 init_completion(&dev->wlan_reset_done);
1904 atomic_set(&dev->fe_reset, 0);
1905
1906- if (dev->ver == MTK_WED_V1)
1907+ if (dev->hw->version != 1)
1908+ dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
1909+ else
1910 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
1911 BIT(hw->index), 0);
1912- else
1913+
1914+ if (mtk_wed_get_rx_capa(dev))
1915 ret = mtk_wed_wo_init(hw);
1916
1917 error:
1918- if (ret)
1919+ if (ret) {
1920+ pr_info("%s: detach wed\n", __func__);
1921 mtk_wed_detach(dev);
1922+ }
1923 out:
1924 mutex_unlock(&hw_lock);
1925
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1926@@ -1576,8 +2111,26 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1927 if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE, reset))
1928 return -ENOMEM;
1929
1930+ if (dev->hw->version == 3 && idx == 1) {
1931+ /* reset prefetch index */
1932+ wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
1933+ MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
1934+ MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
1935+
1936+ wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
1937+ MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
1938+ MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
1939+
1940+ /* reset prefetch FIFO */
1941+ wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
1942+ MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR |
1943+ MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR);
1944+ wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
1945+ }
1946+
1947 ring->reg_base = MTK_WED_RING_TX(idx);
1948 ring->wpdma = regs;
1949+ ring->flags |= MTK_WED_RING_CONFIGURED;
1950
1951 /* WED -> WPDMA */
1952 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1953@@ -1599,7 +2152,7 @@ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1954 struct mtk_wed_ring *ring = &dev->txfree_ring;
1955 int i, idx = 1;
1956
1957- if(dev->ver > MTK_WED_V1)
1958+ if(dev->hw->version > 1)
1959 idx = 0;
1960
1961 /*
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]1962@@ -1652,6 +2205,129 @@ mtk_wed_rx_ring_setup(struct mtk_wed_device *dev,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]1963 return 0;
1964 }
1965
1966+static int
1967+mtk_wed_rro_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
1968+{
1969+ struct mtk_wed_ring *ring = &dev->rx_rro_ring[idx];
1970+
1971+ ring->wpdma = regs;
1972+
1973+ wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_BASE,
1974+ readl(regs));
1975+ wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_COUNT,
1976+ readl(regs + MTK_WED_RING_OFS_COUNT));
1977+
1978+ ring->flags |= MTK_WED_RING_CONFIGURED;
1979+
1980+ return 0;
1981+}
1982+
1983+static int
1984+mtk_wed_msdu_pg_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
1985+{
1986+ struct mtk_wed_ring *ring = &dev->rx_page_ring[idx];
1987+
1988+ ring->wpdma = regs;
1989+
1990+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_BASE,
1991+ readl(regs));
1992+ wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_COUNT,
1993+ readl(regs + MTK_WED_RING_OFS_COUNT));
1994+
1995+ ring->flags |= MTK_WED_RING_CONFIGURED;
1996+
1997+ return 0;
1998+}
1999+
2000+static int
2001+mtk_wed_ind_rx_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
2002+{
2003+ struct mtk_wed_ring *ring = &dev->ind_cmd_ring;
2004+ u32 val = readl(regs + MTK_WED_RING_OFS_COUNT);
2005+ int i = 0, cnt = 0;
2006+
2007+ ring->wpdma = regs;
2008+
2009+ if (readl(regs) & 0xf)
2010+ pr_info("%s(): address is not 16-byte alignment\n", __func__);
2011+
2012+ wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_BASE,
2013+ readl(regs) & 0xfffffff0);
2014+
2015+ wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_COUNT,
2016+ readl(regs + MTK_WED_RING_OFS_COUNT));
2017+
2018+ /* ack sn cr */
2019+ wed_w32(dev, MTK_WED_RRO_CFG0, dev->wlan.phy_base +
2020+ dev->wlan.ind_cmd.ack_sn_addr);
2021+ wed_w32(dev, MTK_WED_RRO_CFG1,
2022+ FIELD_PREP(MTK_WED_RRO_CFG1_MAX_WIN_SZ,
2023+ dev->wlan.ind_cmd.win_size) |
2024+ FIELD_PREP(MTK_WED_RRO_CFG1_PARTICL_SE_ID,
2025+ dev->wlan.ind_cmd.particular_sid));
2026+
2027+ /* particular session addr element */
2028+ wed_w32(dev, MTK_WED_ADDR_ELEM_CFG0, dev->wlan.ind_cmd.particular_se_phys);
2029+
2030+ for (i = 0; i < dev->wlan.ind_cmd.se_group_nums; i++) {
2031+ wed_w32(dev, MTK_WED_RADDR_ELEM_TBL_WDATA,
2032+ dev->wlan.ind_cmd.addr_elem_phys[i] >> 4);
2033+ wed_w32(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
2034+ MTK_WED_ADDR_ELEM_TBL_WR | (i & 0x7f));
2035+
2036+ val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2037+ while (!(val & MTK_WED_ADDR_ELEM_TBL_WR_RDY) &&
2038+ cnt < 100) {
2039+ val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
2040+ cnt++;
2041+ }
2042+ if (cnt >= 100) {
2043+ dev_err(dev->hw->dev, "mtk_wed%d: write ba session base failed!\n",
2044+ dev->hw->index);
2045+ }
2046+ /*if (mtk_wed_poll_busy(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
2047+ MTK_WED_ADDR_ELEM_TBL_WR_RDY)) {
2048+ dev_err(dev->hw->dev, "mtk_wed%d: write ba session base failed!\n",
2049+ dev->hw->index);
2050+ return -1;
2051+ }*/
2052+ }
2053+
2054+ /* pn check init */
2055+ for (i = 0; i < dev->wlan.ind_cmd.particular_sid; i++) {
2056+ wed_w32(dev, MTK_WED_PN_CHECK_WDATA_M,
2057+ MTK_WED_PN_CHECK_IS_FIRST);
2058+
2059+ wed_w32(dev, MTK_WED_PN_CHECK_CFG, MTK_WED_PN_CHECK_WR |
2060+ FIELD_PREP(MTK_WED_PN_CHECK_SE_ID, i));
2061+
2062+ cnt = 0;
2063+ val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2064+ while (!(val & MTK_WED_PN_CHECK_WR_RDY) &&
2065+ cnt < 100) {
2066+ val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
2067+ cnt++;
2068+ }
2069+ if (cnt >= 100) {
2070+ dev_err(dev->hw->dev, "mtk_wed%d: session(%d) init failed!\n",
2071+ dev->hw->index, i);
2072+ }
2073+ /*if (mtk_wed_poll_busy(dev, MTK_WED_PN_CHECK_CFG,
2074+ MTK_WED_PN_CHECK_WR_RDY)) {
2075+ dev_err(dev->hw->dev, "mtk_wed%d: session(%d) init failed!\n",
2076+ dev->hw->index, i);
2077+ //return -1;
2078+ }*/
2079+ }
2080+
2081+ wed_w32(dev, MTK_WED_RX_IND_CMD_CNT0, MTK_WED_RX_IND_CMD_DBG_CNT_EN);
2082+
2083+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
2084+
2085+ return 0;
2086+}
2087+
2088+
2089 static u32
2090 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
2091 {
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]2092@@ -1660,6 +2336,8 @@ mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]2093 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
2094 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
2095 val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;
2096+ if (dev->hw->version == 3)
2097+ val &= MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT;
2098 WARN_RATELIMIT(val, "mtk_wed%d: error status=%08x\n",
2099 dev->hw->index, val);
2100
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]2101@@ -1752,6 +2430,9 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]2102 .tx_ring_setup = mtk_wed_tx_ring_setup,
2103 .txfree_ring_setup = mtk_wed_txfree_ring_setup,
2104 .rx_ring_setup = mtk_wed_rx_ring_setup,
2105+ .rro_rx_ring_setup = mtk_wed_rro_rx_ring_setup,
2106+ .msdu_pg_rx_ring_setup = mtk_wed_msdu_pg_rx_ring_setup,
2107+ .ind_rx_ring_setup = mtk_wed_ind_rx_ring_setup,
2108 .msg_update = mtk_wed_send_msg,
2109 .start = mtk_wed_start,
2110 .stop = mtk_wed_stop,
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]2111@@ -1763,6 +2444,7 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]2112 .detach = mtk_wed_detach,
2113 .setup_tc = mtk_wed_eth_setup_tc,
2114 .ppe_check = mtk_wed_ppe_check,
2115+ .start_hwrro = mtk_wed_start_hwrro,
2116 };
2117 struct device_node *eth_np = eth->dev->of_node;
2118 struct platform_device *pdev;
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]2119@@ -1802,9 +2484,10 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]2120 hw->wdma_phy = wdma_phy;
2121 hw->index = index;
2122 hw->irq = irq;
2123- hw->ver = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
2124+ hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) ?
2125+ 3 : MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
2126
2127- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
2128+ if (hw->version == 1) {
2129 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
2130 "mediatek,pcie-mirror");
2131 hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
developera8336302023-07-07 11:29:01 +0800[diff] [blame^]2132@@ -1819,7 +2502,6 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
developer23f9f0f2023-06-15 13:06:25 +0800[diff] [blame]2133 regmap_write(hw->mirror, 0, 0);
2134 regmap_write(hw->mirror, 4, 0);
2135 }
2136- hw->ver = MTK_WED_V1;
2137 }
2138
2139 mtk_wed_hw_add_debugfs(hw);
2140diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h
2141index 490873c..fcf7bd0 100644
2142--- a/drivers/net/ethernet/mediatek/mtk_wed.h
2143+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
2144@@ -10,10 +10,13 @@
2145 #include <linux/netdevice.h>
2146 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
2147
2148-#define MTK_WED_PKT_SIZE 1900
2149+#define MTK_WED_PKT_SIZE 1920//1900
2150 #define MTK_WED_BUF_SIZE 2048
2151+#define MTK_WED_PAGE_BUF_SIZE 128
2152 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
2153+#define MTK_WED_RX_PAGE_BUF_PER_PAGE (PAGE_SIZE / 128)
2154 #define MTK_WED_RX_RING_SIZE 1536
2155+#define MTK_WED_RX_PG_BM_CNT 8192
2156
2157 #define MTK_WED_TX_RING_SIZE 2048
2158 #define MTK_WED_WDMA_RING_SIZE 512
2159@@ -27,6 +30,9 @@
2160 #define MTK_WED_RRO_QUE_CNT 8192
2161 #define MTK_WED_MIOD_ENTRY_CNT 128
2162
2163+#define MTK_WED_TX_BM_DMA_SIZE 65536
2164+#define MTK_WED_TX_BM_PKT_CNT 32768
2165+
2166 #define MODULE_ID_WO 1
2167
2168 struct mtk_eth;
2169@@ -43,6 +49,8 @@ struct mtk_wed_hw {
2170 struct dentry *debugfs_dir;
2171 struct mtk_wed_device *wed_dev;
2172 struct mtk_wed_wo *wed_wo;
2173+ struct mtk_wed_pao *wed_pao;
2174+ u32 pci_base;
2175 u32 debugfs_reg;
2176 u32 num_flows;
2177 u32 wdma_phy;
2178@@ -50,7 +58,8 @@ struct mtk_wed_hw {
2179 int ring_num;
2180 int irq;
2181 int index;
2182- u32 ver;
2183+ int token_id;
2184+ u32 version;
2185 };
2186
2187 struct mtk_wdma_info {
2188@@ -58,6 +67,18 @@ struct mtk_wdma_info {
2189 u8 queue;
2190 u16 wcid;
2191 u8 bss;
2192+ u32 usr_info;
2193+ u8 tid;
2194+ u8 is_fixedrate;
2195+ u8 is_prior;
2196+ u8 is_sp;
2197+ u8 hf;
2198+ u8 amsdu_en;
2199+};
2200+
2201+struct mtk_wed_pao {
2202+ char *hif_txd[32];
2203+ dma_addr_t hif_txd_phys[32];
2204 };
2205
2206 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
2207diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
2208index 4a9e684..51e3d7c 100644
2209--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
2210+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
2211@@ -11,9 +11,11 @@ struct reg_dump {
2212 u16 offset;
2213 u8 type;
2214 u8 base;
2215+ u32 mask;
2216 };
2217
2218 enum {
2219+ DUMP_TYPE_END,
2220 DUMP_TYPE_STRING,
2221 DUMP_TYPE_WED,
2222 DUMP_TYPE_WDMA,
2223@@ -23,8 +25,11 @@ enum {
2224 DUMP_TYPE_WED_RRO,
2225 };
2226
2227+#define DUMP_END() { .type = DUMP_TYPE_END }
2228 #define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
2229 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }
2230+#define DUMP_REG_MASK(_reg, _mask) { #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask }
2231+
2232 #define DUMP_RING(_prefix, _base, ...) \
2233 { _prefix " BASE", _base, __VA_ARGS__ }, \
2234 { _prefix " CNT", _base + 0x4, __VA_ARGS__ }, \
2235@@ -32,6 +37,7 @@ enum {
2236 { _prefix " DIDX", _base + 0xc, __VA_ARGS__ }
2237
2238 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)
2239+#define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask)
2240 #define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)
2241
2242 #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
2243@@ -52,36 +58,49 @@ print_reg_val(struct seq_file *s, const char *name, u32 val)
2244
2245 static void
2246 dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,
2247- const struct reg_dump *regs, int n_regs)
2248+ const struct reg_dump **regs)
2249 {
2250- const struct reg_dump *cur;
2251+ const struct reg_dump **cur_o = regs, *cur;
2252+ bool newline = false;
2253 u32 val;
2254
2255- for (cur = regs; cur < &regs[n_regs]; cur++) {
2256- switch (cur->type) {
2257- case DUMP_TYPE_STRING:
2258- seq_printf(s, "%s======== %s:\n",
2259- cur > regs ? "\n" : "",
2260- cur->name);
2261- continue;
2262- case DUMP_TYPE_WED:
2263- case DUMP_TYPE_WED_RRO:
2264- val = wed_r32(dev, cur->offset);
2265- break;
2266- case DUMP_TYPE_WDMA:
2267- val = wdma_r32(dev, cur->offset);
2268- break;
2269- case DUMP_TYPE_WPDMA_TX:
2270- val = wpdma_tx_r32(dev, cur->base, cur->offset);
2271- break;
2272- case DUMP_TYPE_WPDMA_TXFREE:
2273- val = wpdma_txfree_r32(dev, cur->offset);
2274- break;
2275- case DUMP_TYPE_WPDMA_RX:
2276- val = wpdma_rx_r32(dev, cur->base, cur->offset);
2277- break;
2278+ while (*cur_o) {
2279+ cur = *cur_o;
2280+
2281+ while (cur->type != DUMP_TYPE_END) {
2282+ switch (cur->type) {
2283+ case DUMP_TYPE_STRING:
2284+ seq_printf(s, "%s======== %s:\n",
2285+ newline ? "\n" : "",
2286+ cur->name);
2287+ newline = true;
2288+ cur++;
2289+ continue;
2290+ case DUMP_TYPE_WED:
2291+ case DUMP_TYPE_WED_RRO:
2292+ val = wed_r32(dev, cur->offset);
2293+ break;
2294+ case DUMP_TYPE_WDMA:
2295+ val = wdma_r32(dev, cur->offset);
2296+ break;
2297+ case DUMP_TYPE_WPDMA_TX:
2298+ val = wpdma_tx_r32(dev, cur->base, cur->offset);
2299+ break;
2300+ case DUMP_TYPE_WPDMA_TXFREE:
2301+ val = wpdma_txfree_r32(dev, cur->offset);
2302+ break;
2303+ case DUMP_TYPE_WPDMA_RX:
2304+ val = wpdma_rx_r32(dev, cur->base, cur->offset);
2305+ break;
2306+ }
2307+
2308+ if (cur->mask)
2309+ val = (cur->mask & val) >> (ffs(cur->mask) - 1);
2310+
2311+ print_reg_val(s, cur->name, val);
2312+ cur++;
2313 }
2314- print_reg_val(s, cur->name, val);
2315+ cur_o++;
2316 }
2317 }
2318
2319@@ -89,7 +108,7 @@ dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,
2320 static int
2321 wed_txinfo_show(struct seq_file *s, void *data)
2322 {
2323- static const struct reg_dump regs[] = {
2324+ static const struct reg_dump regs_common[] = {
2325 DUMP_STR("WED TX"),
2326 DUMP_WED(WED_TX_MIB(0)),
2327 DUMP_WED_RING(WED_RING_TX(0)),
2328@@ -128,16 +147,32 @@ wed_txinfo_show(struct seq_file *s, void *data)
2329 DUMP_WDMA_RING(WDMA_RING_RX(0)),
2330 DUMP_WDMA_RING(WDMA_RING_RX(1)),
2331
2332- DUMP_STR("TX FREE"),
2333+ DUMP_STR("WED TX FREE"),
2334 DUMP_WED(WED_RX_MIB(0)),
2335+ DUMP_WED_RING(WED_RING_RX(0)),
2336+ DUMP_WED(WED_WPDMA_RX_COHERENT_MIB(0)),
2337+
2338+ DUMP_WED(WED_RX_MIB(1)),
2339+ DUMP_WED_RING(WED_RING_RX(1)),
2340+ DUMP_WED(WED_WPDMA_RX_COHERENT_MIB(1)),
2341+ DUMP_STR("WED_WPDMA TX FREE"),
2342+ DUMP_WED_RING(WED_WPDMA_RING_RX(0)),
2343+ DUMP_WED_RING(WED_WPDMA_RING_RX(1)),
2344+ DUMP_END(),
2345+ };
2346+
2347+ static const struct reg_dump *regs[] = {
2348+ &regs_common[0],
2349+ NULL,
2350 };
2351+
2352 struct mtk_wed_hw *hw = s->private;
2353 struct mtk_wed_device *dev = hw->wed_dev;
2354
2355 if (!dev)
2356 return 0;
2357
2358- dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
2359+ dump_wed_regs(s, dev, regs);
2360
2361 return 0;
2362 }
2363@@ -146,7 +181,7 @@ DEFINE_SHOW_ATTRIBUTE(wed_txinfo);
2364 static int
2365 wed_rxinfo_show(struct seq_file *s, void *data)
2366 {
2367- static const struct reg_dump regs[] = {
2368+ static const struct reg_dump regs_common[] = {
2369 DUMP_STR("WPDMA RX"),
2370 DUMP_WPDMA_RX_RING(0),
2371 DUMP_WPDMA_RX_RING(1),
2372@@ -164,7 +199,7 @@ wed_rxinfo_show(struct seq_file *s, void *data)
2373 DUMP_WED_RING(WED_RING_RX_DATA(0)),
2374 DUMP_WED_RING(WED_RING_RX_DATA(1)),
2375
2376- DUMP_STR("WED RRO"),
2377+ DUMP_STR("WED WO RRO"),
2378 DUMP_WED_RRO_RING(WED_RROQM_MIOD_CTRL0),
2379 DUMP_WED(WED_RROQM_MID_MIB),
2380 DUMP_WED(WED_RROQM_MOD_MIB),
2381@@ -175,16 +210,6 @@ wed_rxinfo_show(struct seq_file *s, void *data)
2382 DUMP_WED(WED_RROQM_FDBK_ANC_MIB),
2383 DUMP_WED(WED_RROQM_FDBK_ANC2H_MIB),
2384
2385- DUMP_STR("WED Route QM"),
2386- DUMP_WED(WED_RTQM_R2H_MIB(0)),
2387- DUMP_WED(WED_RTQM_R2Q_MIB(0)),
2388- DUMP_WED(WED_RTQM_Q2H_MIB(0)),
2389- DUMP_WED(WED_RTQM_R2H_MIB(1)),
2390- DUMP_WED(WED_RTQM_R2Q_MIB(1)),
2391- DUMP_WED(WED_RTQM_Q2H_MIB(1)),
2392- DUMP_WED(WED_RTQM_Q2N_MIB),
2393- DUMP_WED(WED_RTQM_Q2B_MIB),
2394- DUMP_WED(WED_RTQM_PFDBK_MIB),
2395
2396 DUMP_STR("WED WDMA TX"),
2397 DUMP_WED(WED_WDMA_TX_MIB),
2398@@ -205,15 +230,99 @@ wed_rxinfo_show(struct seq_file *s, void *data)
2399 DUMP_WED(WED_RX_BM_INTF2),
2400 DUMP_WED(WED_RX_BM_INTF),
2401 DUMP_WED(WED_RX_BM_ERR_STS),
2402+ DUMP_END()
2403+ };
2404+
2405+ static const struct reg_dump regs_v2[] = {
2406+ DUMP_STR("WED Route QM"),
2407+ DUMP_WED(WED_RTQM_R2H_MIB(0)),
2408+ DUMP_WED(WED_RTQM_R2Q_MIB(0)),
2409+ DUMP_WED(WED_RTQM_Q2H_MIB(0)),
2410+ DUMP_WED(WED_RTQM_R2H_MIB(1)),
2411+ DUMP_WED(WED_RTQM_R2Q_MIB(1)),
2412+ DUMP_WED(WED_RTQM_Q2H_MIB(1)),
2413+ DUMP_WED(WED_RTQM_Q2N_MIB),
2414+ DUMP_WED(WED_RTQM_Q2B_MIB),
2415+ DUMP_WED(WED_RTQM_PFDBK_MIB),
2416+
2417+ DUMP_END()
2418+ };
2419+
2420+ static const struct reg_dump regs_v3[] = {
2421+ DUMP_STR("WED RX RRO DATA"),
2422+ DUMP_WED_RING(WED_RRO_RX_D_RX(0)),
2423+ DUMP_WED_RING(WED_RRO_RX_D_RX(1)),
2424+
2425+ DUMP_STR("WED RX MSDU PAGE"),
2426+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(0)),
2427+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(1)),
2428+ DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(2)),
2429+
2430+ DUMP_STR("WED RX IND CMD"),
2431+ DUMP_WED(WED_IND_CMD_RX_CTRL1),
2432+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL2, WED_IND_CMD_MAX_CNT),
2433+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_PROC_IDX),
2434+ DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_DMA_IDX),
2435+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_MAGIC_CNT),
2436+ DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_MAGIC_CNT),
2437+ DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0,
2438+ WED_IND_CMD_PREFETCH_FREE_CNT),
2439+ DUMP_WED_MASK(WED_RRO_CFG1, WED_RRO_CFG1_PARTICL_SE_ID),
2440+
2441+ DUMP_STR("WED ADDR ELEM"),
2442+ DUMP_WED(WED_ADDR_ELEM_CFG0),
2443+ DUMP_WED_MASK(WED_ADDR_ELEM_CFG1,
2444+ WED_ADDR_ELEM_PREFETCH_FREE_CNT),
2445+
2446+ DUMP_STR("WED Route QM"),
2447+ DUMP_WED(WED_RTQM_ENQ_I2Q_DMAD_CNT),
2448+ DUMP_WED(WED_RTQM_ENQ_I2N_DMAD_CNT),
2449+ DUMP_WED(WED_RTQM_ENQ_I2Q_PKT_CNT),
2450+ DUMP_WED(WED_RTQM_ENQ_I2N_PKT_CNT),
2451+ DUMP_WED(WED_RTQM_ENQ_USED_ENTRY_CNT),
2452+ DUMP_WED(WED_RTQM_ENQ_ERR_CNT),
2453+
2454+ DUMP_WED(WED_RTQM_DEQ_DMAD_CNT),
2455+ DUMP_WED(WED_RTQM_DEQ_Q2I_DMAD_CNT),
2456+ DUMP_WED(WED_RTQM_DEQ_PKT_CNT),
2457+ DUMP_WED(WED_RTQM_DEQ_Q2I_PKT_CNT),
2458+ DUMP_WED(WED_RTQM_DEQ_USED_PFDBK_CNT),
2459+ DUMP_WED(WED_RTQM_DEQ_ERR_CNT),
2460+
2461+ DUMP_END()
2462+ };
2463+
2464+ static const struct reg_dump *regs_new_v2[] = {
2465+ &regs_common[0],
2466+ &regs_v2[0],
2467+ NULL,
2468+ };
2469+
2470+ static const struct reg_dump *regs_new_v3[] = {
2471+ &regs_common[0],
2472+ &regs_v3[0],
2473+ NULL,
2474 };
2475
2476 struct mtk_wed_hw *hw = s->private;
2477 struct mtk_wed_device *dev = hw->wed_dev;
2478+ const struct reg_dump **regs;
2479
2480 if (!dev)
2481 return 0;
2482
2483- dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
2484+ switch(dev->hw->version) {
2485+ case 2:
2486+ regs = regs_new_v2;
2487+ break;
2488+ case 3:
2489+ regs = regs_new_v3;
2490+ break;
2491+ default:
2492+ return 0;
2493+ }
2494+
2495+ dump_wed_regs(s, dev, regs);
2496
2497 return 0;
2498 }
2499@@ -248,6 +357,383 @@ mtk_wed_reg_get(void *data, u64 *val)
2500 DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set,
2501 "0x%08llx\n");
2502
2503+static int
2504+wed_token_txd_show(struct seq_file *s, void *data)
2505+{
2506+ struct mtk_wed_hw *hw = s->private;
2507+ struct mtk_wed_device *dev = hw->wed_dev;
2508+ struct dma_page_info *page_list = dev->tx_buf_ring.pages;
2509+ int token = dev->wlan.token_start;
2510+ u32 val = hw->token_id, size = 1;
2511+ int page_idx = (val - token) / 2;
2512+ int i;
2513+
2514+ if (val < token) {
2515+ size = val;
2516+ page_idx = 0;
2517+ }
2518+
2519+ for (i = 0; i < size; i += MTK_WED_BUF_PER_PAGE) {
2520+ void *page = page_list[page_idx++].addr;
2521+ void *buf;
2522+ int j;
2523+
2524+ if (!page)
2525+ break;
2526+
2527+ buf = page_to_virt(page);
2528+
2529+ for (j = 0; j < MTK_WED_BUF_PER_PAGE; j++) {
2530+ printk("[TXD]:token id = %d\n", token + 2 * (page_idx - 1) + j);
2531+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)buf, 128, false);
2532+ seq_printf(s, "\n");
2533+
2534+ buf += MTK_WED_BUF_SIZE;
2535+ }
2536+ }
2537+
2538+ return 0;
2539+}
2540+
2541+DEFINE_SHOW_ATTRIBUTE(wed_token_txd);
2542+
2543+static int
2544+wed_pao_show(struct seq_file *s, void *data)
2545+{
2546+ static const struct reg_dump regs_common[] = {
2547+ DUMP_STR("PAO AMDSU INFO"),
2548+ DUMP_WED(WED_PAO_MON_AMSDU_FIFO_DMAD),
2549+
2550+ DUMP_STR("PAO AMDSU ENG0 INFO"),
2551+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(0)),
2552+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(0)),
2553+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(0)),
2554+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(0)),
2555+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(0)),
2556+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(0),
2557+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2558+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(0),
2559+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2560+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(0),
2561+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2562+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(0),
2563+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2564+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(0),
2565+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2566+
2567+ DUMP_STR("PAO AMDSU ENG1 INFO"),
2568+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(1)),
2569+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(1)),
2570+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(1)),
2571+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(1)),
2572+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(1)),
2573+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(1),
2574+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2575+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(1),
2576+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2577+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(1),
2578+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2579+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2580+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2581+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2582+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2583+
2584+ DUMP_STR("PAO AMDSU ENG2 INFO"),
2585+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(2)),
2586+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(2)),
2587+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(2)),
2588+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(2)),
2589+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(2)),
2590+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(2),
2591+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2592+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(2),
2593+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2594+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2595+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2596+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2597+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2598+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(2),
2599+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2600+
2601+ DUMP_STR("PAO AMDSU ENG3 INFO"),
2602+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(3)),
2603+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(3)),
2604+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(3)),
2605+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(3)),
2606+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(3)),
2607+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(3),
2608+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2609+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(3),
2610+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2611+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(3),
2612+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2613+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(3),
2614+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2615+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(3),
2616+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2617+
2618+ DUMP_STR("PAO AMDSU ENG4 INFO"),
2619+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(4)),
2620+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(4)),
2621+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(4)),
2622+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(4)),
2623+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(4)),
2624+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(4),
2625+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2626+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(4),
2627+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2628+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2629+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2630+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2631+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2632+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2633+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2634+
2635+ DUMP_STR("PAO AMDSU ENG5 INFO"),
2636+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(5)),
2637+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(5)),
2638+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(5)),
2639+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(5)),
2640+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(5)),
2641+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(5),
2642+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2643+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(5),
2644+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2645+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(5),
2646+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2647+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(5),
2648+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2649+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(5),
2650+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2651+
2652+ DUMP_STR("PAO AMDSU ENG6 INFO"),
2653+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(6)),
2654+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(6)),
2655+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(6)),
2656+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(6)),
2657+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(6)),
2658+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(6),
2659+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2660+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(6),
2661+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2662+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(6),
2663+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2664+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(6),
2665+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2666+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(6),
2667+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2668+
2669+ DUMP_STR("PAO AMDSU ENG7 INFO"),
2670+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(7)),
2671+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(7)),
2672+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(7)),
2673+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(7)),
2674+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(7)),
2675+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(7),
2676+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2677+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(7),
2678+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2679+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(7),
2680+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2681+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(7),
2682+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2683+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(4),
2684+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2685+
2686+ DUMP_STR("PAO AMDSU ENG8 INFO"),
2687+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_DMAD(8)),
2688+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QFPL(8)),
2689+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENI(8)),
2690+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_QENO(8)),
2691+ DUMP_WED(WED_PAO_MON_AMSDU_ENG_MERG(8)),
2692+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(8),
2693+ WED_PAO_AMSDU_ENG_MAX_PL_CNT),
2694+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT8(8),
2695+ WED_PAO_AMSDU_ENG_MAX_QGPP_CNT),
2696+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(8),
2697+ WED_PAO_AMSDU_ENG_CUR_ENTRY),
2698+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(8),
2699+ WED_PAO_AMSDU_ENG_MAX_BUF_MERGED),
2700+ DUMP_WED_MASK(WED_PAO_MON_AMSDU_ENG_CNT9(8),
2701+ WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED),
2702+
2703+ DUMP_STR("PAO QMEM INFO"),
2704+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(0), WED_PAO_QMEM_FQ_CNT),
2705+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(0), WED_PAO_QMEM_SP_QCNT),
2706+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(1), WED_PAO_QMEM_TID0_QCNT),
2707+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(1), WED_PAO_QMEM_TID1_QCNT),
2708+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(2), WED_PAO_QMEM_TID2_QCNT),
2709+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(2), WED_PAO_QMEM_TID3_QCNT),
2710+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(3), WED_PAO_QMEM_TID4_QCNT),
2711+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(3), WED_PAO_QMEM_TID5_QCNT),
2712+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(4), WED_PAO_QMEM_TID6_QCNT),
2713+ DUMP_WED_MASK(WED_PAO_MON_QMEM_CNT(4), WED_PAO_QMEM_TID7_QCNT),
2714+
2715+
2716+ DUMP_STR("PAO QMEM HEAD INFO"),
2717+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(0), WED_PAO_QMEM_FQ_HEAD),
2718+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(0), WED_PAO_QMEM_SP_QHEAD),
2719+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(1), WED_PAO_QMEM_TID0_QHEAD),
2720+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(1), WED_PAO_QMEM_TID1_QHEAD),
2721+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(2), WED_PAO_QMEM_TID2_QHEAD),
2722+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(2), WED_PAO_QMEM_TID3_QHEAD),
2723+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(3), WED_PAO_QMEM_TID4_QHEAD),
2724+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(3), WED_PAO_QMEM_TID5_QHEAD),
2725+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(4), WED_PAO_QMEM_TID6_QHEAD),
2726+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(4), WED_PAO_QMEM_TID7_QHEAD),
2727+
2728+ DUMP_STR("PAO QMEM TAIL INFO"),
2729+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(5), WED_PAO_QMEM_FQ_TAIL),
2730+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(5), WED_PAO_QMEM_SP_QTAIL),
2731+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(6), WED_PAO_QMEM_TID0_QTAIL),
2732+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(6), WED_PAO_QMEM_TID1_QTAIL),
2733+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(7), WED_PAO_QMEM_TID2_QTAIL),
2734+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(7), WED_PAO_QMEM_TID3_QTAIL),
2735+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(8), WED_PAO_QMEM_TID4_QTAIL),
2736+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(8), WED_PAO_QMEM_TID5_QTAIL),
2737+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(9), WED_PAO_QMEM_TID6_QTAIL),
2738+ DUMP_WED_MASK(WED_PAO_MON_QMEM_PTR(9), WED_PAO_QMEM_TID7_QTAIL),
2739+
2740+ DUMP_STR("PAO HIFTXD MSDU INFO"),
2741+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(1)),
2742+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(2)),
2743+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(3)),
2744+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(4)),
2745+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(5)),
2746+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(6)),
2747+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(7)),
2748+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(8)),
2749+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(9)),
2750+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(10)),
2751+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(11)),
2752+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(12)),
2753+ DUMP_WED(WED_PAO_MON_HIFTXD_FETCH_MSDU(13)),
2754+ DUMP_END()
2755+ };
2756+
2757+ static const struct reg_dump *regs[] = {
2758+ &regs_common[0],
2759+ NULL,
2760+ };
2761+ struct mtk_wed_hw *hw = s->private;
2762+ struct mtk_wed_device *dev = hw->wed_dev;
2763+
2764+ if (!dev)
2765+ return 0;
2766+
2767+ dump_wed_regs(s, dev, regs);
2768+
2769+ return 0;
2770+}
2771+DEFINE_SHOW_ATTRIBUTE(wed_pao);
2772+
2773+static int
2774+wed_rtqm_show(struct seq_file *s, void *data)
2775+{
2776+ static const struct reg_dump regs_common[] = {
2777+ DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"),
2778+ DUMP_WED(WED_RTQM_IGRS0_I2HW_DMAD_CNT),
2779+ DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(0)),
2780+ DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(1)),
2781+ DUMP_WED(WED_RTQM_IGRS0_I2HW_PKT_CNT),
2782+ DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
2783+ DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
2784+ DUMP_WED(WED_RTQM_IGRS0_FDROP_CNT),
2785+
2786+
2787+ DUMP_STR("WED Route QM IGRS1(Legacy)"),
2788+ DUMP_WED(WED_RTQM_IGRS1_I2HW_DMAD_CNT),
2789+ DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(0)),
2790+ DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(1)),
2791+ DUMP_WED(WED_RTQM_IGRS1_I2HW_PKT_CNT),
2792+ DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(0)),
2793+ DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(1)),
2794+ DUMP_WED(WED_RTQM_IGRS1_FDROP_CNT),
2795+
2796+ DUMP_STR("WED Route QM IGRS2(RRO3.0)"),
2797+ DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
2798+ DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(0)),
2799+ DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(1)),
2800+ DUMP_WED(WED_RTQM_IGRS2_I2HW_PKT_CNT),
2801+ DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(0)),
2802+ DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(1)),
2803+ DUMP_WED(WED_RTQM_IGRS2_FDROP_CNT),
2804+
2805+ DUMP_STR("WED Route QM IGRS3(DEBUG)"),
2806+ DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
2807+ DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(0)),
2808+ DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(1)),
2809+ DUMP_WED(WED_RTQM_IGRS3_I2HW_PKT_CNT),
2810+ DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(0)),
2811+ DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(1)),
2812+ DUMP_WED(WED_RTQM_IGRS3_FDROP_CNT),
2813+
2814+ DUMP_END()
2815+ };
2816+
2817+ static const struct reg_dump *regs[] = {
2818+ &regs_common[0],
2819+ NULL,
2820+ };
2821+ struct mtk_wed_hw *hw = s->private;
2822+ struct mtk_wed_device *dev = hw->wed_dev;
2823+
2824+ if (!dev)
2825+ return 0;
2826+
2827+ dump_wed_regs(s, dev, regs);
2828+
2829+ return 0;
2830+}
2831+DEFINE_SHOW_ATTRIBUTE(wed_rtqm);
2832+
2833+
2834+static int
2835+wed_rro_show(struct seq_file *s, void *data)
2836+{
2837+ static const struct reg_dump regs_common[] = {
2838+ DUMP_STR("RRO/IND CMD CNT"),
2839+ DUMP_WED(WED_RX_IND_CMD_CNT(1)),
2840+ DUMP_WED(WED_RX_IND_CMD_CNT(2)),
2841+ DUMP_WED(WED_RX_IND_CMD_CNT(3)),
2842+ DUMP_WED(WED_RX_IND_CMD_CNT(4)),
2843+ DUMP_WED(WED_RX_IND_CMD_CNT(5)),
2844+ DUMP_WED(WED_RX_IND_CMD_CNT(6)),
2845+ DUMP_WED(WED_RX_IND_CMD_CNT(7)),
2846+ DUMP_WED(WED_RX_IND_CMD_CNT(8)),
2847+ DUMP_WED_MASK(WED_RX_IND_CMD_CNT(9),
2848+ WED_IND_CMD_MAGIC_CNT_FAIL_CNT),
2849+
2850+ DUMP_WED(WED_RX_ADDR_ELEM_CNT(0)),
2851+ DUMP_WED_MASK(WED_RX_ADDR_ELEM_CNT(1),
2852+ WED_ADDR_ELEM_SIG_FAIL_CNT),
2853+ DUMP_WED(WED_RX_MSDU_PG_CNT(1)),
2854+ DUMP_WED(WED_RX_MSDU_PG_CNT(2)),
2855+ DUMP_WED(WED_RX_MSDU_PG_CNT(3)),
2856+ DUMP_WED(WED_RX_MSDU_PG_CNT(4)),
2857+ DUMP_WED(WED_RX_MSDU_PG_CNT(5)),
2858+ DUMP_WED_MASK(WED_RX_PN_CHK_CNT,
2859+ WED_PN_CHK_FAIL_CNT),
2860+
2861+ DUMP_END()
2862+ };
2863+
2864+ static const struct reg_dump *regs[] = {
2865+ &regs_common[0],
2866+ NULL,
2867+ };
2868+ struct mtk_wed_hw *hw = s->private;
2869+ struct mtk_wed_device *dev = hw->wed_dev;
2870+
2871+ if (!dev)
2872+ return 0;
2873+
2874+ dump_wed_regs(s, dev, regs);
2875+
2876+ return 0;
2877+}
2878+DEFINE_SHOW_ATTRIBUTE(wed_rro);
2879+
2880 void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
2881 {
2882 struct dentry *dir;
2883@@ -261,8 +747,18 @@ void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
2884 debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
2885 debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
2886 debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
2887- debugfs_create_file_unsafe("rxinfo", 0400, dir, hw, &wed_rxinfo_fops);
2888- if (hw->ver != MTK_WED_V1) {
2889+ debugfs_create_u32("token_id", 0600, dir, &hw->token_id);
2890+ debugfs_create_file_unsafe("token_txd", 0600, dir, hw, &wed_token_txd_fops);
2891+
2892+ if (hw->version == 3)
2893+ debugfs_create_file_unsafe("pao", 0400, dir, hw, &wed_pao_fops);
2894+
2895+ if (hw->version != 1) {
2896+ debugfs_create_file_unsafe("rxinfo", 0400, dir, hw, &wed_rxinfo_fops);
2897+ if (hw->version == 3) {
2898+ debugfs_create_file_unsafe("rtqm", 0400, dir, hw, &wed_rtqm_fops);
2899+ debugfs_create_file_unsafe("rro", 0400, dir, hw, &wed_rro_fops);
2900+ }
2901 wed_wo_mcu_debugfs(hw, dir);
2902 }
2903 }
2904diff --git a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
2905index 96e30a3..055594d 100644
2906--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
2907+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
2908@@ -242,7 +242,7 @@ mtk_wed_load_firmware(struct mtk_wed_wo *wo)
2909 u32 ofs = 0;
2910 u32 boot_cr, val;
2911
2912- mcu = wo->hw->index ? MT7986_FIRMWARE_WO_2 : MT7986_FIRMWARE_WO_1;
2913+ mcu = wo->hw->index ? MTK_FIRMWARE_WO_1 : MTK_FIRMWARE_WO_0;
2914
2915 ret = request_firmware(&fw, mcu, wo->hw->dev);
2916 if (ret)
2917@@ -289,8 +289,12 @@ mtk_wed_load_firmware(struct mtk_wed_wo *wo)
2918 }
2919
2920 /* write the start address */
2921- boot_cr = wo->hw->index ?
2922- WOX_MCU_CFG_LS_WA_BOOT_ADDR_ADDR : WOX_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
2923+ if (wo->hw->version == 3)
2924+ boot_cr = WOX_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
2925+ else
2926+ boot_cr = wo->hw->index ?
2927+ WOX_MCU_CFG_LS_WA_BOOT_ADDR_ADDR : WOX_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
2928+
2929 wo_w32(wo, boot_cr, (wo->region[WO_REGION_EMI].addr_pa >> 16));
2930
2931 /* wo firmware reset */
2932@@ -298,8 +302,7 @@ mtk_wed_load_firmware(struct mtk_wed_wo *wo)
2933
2934 val = wo_r32(wo, WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
2935
2936- val |= wo->hw->index ? WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_WA_CPU_RSTB_MASK :
2937- WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_WM_CPU_RSTB_MASK;
2938+ val |= WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_WM_CPU_RSTB_MASK;
2939
2940 wo_w32(wo, WOX_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
2941
2942diff --git a/drivers/net/ethernet/mediatek/mtk_wed_mcu.h b/drivers/net/ethernet/mediatek/mtk_wed_mcu.h
2943index 19e1199..c07bdb6 100644
2944--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.h
2945+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.h
2946@@ -16,8 +16,9 @@
2947 #define WARP_OK_STATUS (0)
2948 #define WARP_ALREADY_DONE_STATUS (1)
2949
2950-#define MT7986_FIRMWARE_WO_1 "mediatek/mt7986_wo_0.bin"
2951-#define MT7986_FIRMWARE_WO_2 "mediatek/mt7986_wo_1.bin"
2952+#define MTK_FIRMWARE_WO_0 "mediatek/mtk_wo_0.bin"
2953+#define MTK_FIRMWARE_WO_1 "mediatek/mtk_wo_1.bin"
2954+#define MTK_FIRMWARE_WO_2 "mediatek/mtk_wo_2.bin"
2955
2956 #define WOCPU_EMI_DEV_NODE "mediatek,wocpu_emi"
2957 #define WOCPU_ILM_DEV_NODE "mediatek,wocpu_ilm"
2958diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
2959index 403a36b..4e619ff 100644
2960--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
2961+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
2962@@ -20,6 +20,9 @@
2963 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
2964 #define MTK_WED_RX_BM_TOKEN GENMASK(31, 16)
2965
2966+#define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
2967+#define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
2968+
2969 struct mtk_wdma_desc {
2970 __le32 buf0;
2971 __le32 ctrl;
2972@@ -51,6 +54,7 @@ struct mtk_wdma_desc {
2973 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
2974 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
2975 #define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
2976+#define MTK_WED_RESET_TX_PAO BIT(22)
2977 #define MTK_WED_RESET_WED BIT(31)
2978
2979 #define MTK_WED_CTRL 0x00c
2980@@ -58,6 +62,9 @@ struct mtk_wdma_desc {
2981 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
2982 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
2983 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
2984+#define MTK_WED_CTRL_WED_RX_IND_CMD_EN BIT(5)
2985+#define MTK_WED_CTRL_WED_RX_PG_BM_EN BIT(6)
2986+#define MTK_WED_CTRL_WED_RX_PG_BM_BUSU BIT(7)
2987 #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
2988 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
2989 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
2990@@ -68,9 +75,14 @@ struct mtk_wdma_desc {
2991 #define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
2992 #define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
2993 #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
2994+#define MTK_WED_CTRL_TX_TKID_ALI_EN BIT(20)
2995+#define MTK_WED_CTRL_TX_TKID_ALI_BUSY BIT(21)
2996+#define MTK_WED_CTRL_TX_PAO_EN BIT(22)
2997+#define MTK_WED_CTRL_TX_PAO_BUSY BIT(23)
2998 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
2999 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
3000 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
3001+#define MTK_WED_CTRL_FLD_MIB_RD_CLR BIT(28)
3002
3003 #define MTK_WED_EXT_INT_STATUS 0x020
3004 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
3005@@ -78,12 +90,10 @@ struct mtk_wdma_desc {
3006 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
3007 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
3008 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
3009-#if defined(CONFIG_MEDIATEK_NETSYS_V2)
3010-#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10)
3011-#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11)
3012-#endif
3013-#define MTK_WED_EXT_INT_STATUS_RX_FREE_AT_EMPTY BIT(12)
3014-#define MTK_WED_EXT_INT_STATUS_RX_FBUF_DMAD_ER BIT(13)
3015+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH2 BIT(10)
3016+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH2 BIT(11)
3017+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12)
3018+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13)
3019 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
3020 #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)
3021 #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)
3022@@ -100,17 +110,15 @@ struct mtk_wdma_desc {
3023 #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
3024 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
3025 MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
3026- MTK_WED_EXT_INT_STATUS_RX_FREE_AT_EMPTY | \
3027- MTK_WED_EXT_INT_STATUS_RX_FBUF_DMAD_ER | \
3028 MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \
3029 MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \
3030 MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \
3031- MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \
3032- MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR)
3033+ MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR)
3034
3035 #define MTK_WED_EXT_INT_MASK 0x028
3036 #define MTK_WED_EXT_INT_MASK1 0x02c
3037 #define MTK_WED_EXT_INT_MASK2 0x030
3038+#define MTK_WED_EXT_INT_MASK3 0x034
3039
3040 #define MTK_WED_STATUS 0x060
3041 #define MTK_WED_STATUS_TX GENMASK(15, 8)
3042@@ -118,9 +126,14 @@ struct mtk_wdma_desc {
3043 #define MTK_WED_TX_BM_CTRL 0x080
3044 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
3045 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
3046+#define MTK_WED_TX_BM_CTRL_LEGACY_EN BIT(26)
3047+#define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)
3048 #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
3049
3050 #define MTK_WED_TX_BM_BASE 0x084
3051+#define MTK_WED_TX_BM_INIT_PTR 0x088
3052+#define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
3053+#define MTK_WED_TX_BM_INIT_SW_TAIL_IDX BIT(16)
3054
3055 #define MTK_WED_TX_BM_BUF_LEN 0x08c
3056
3057@@ -134,22 +147,24 @@ struct mtk_wdma_desc {
3058 #if defined(CONFIG_MEDIATEK_NETSYS_V2)
3059 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(8, 0)
3060 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(24, 16)
3061-
3062-#define MTK_WED_TX_BM_TKID 0x0c8
3063-#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
3064-#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
3065 #else
3066 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)
3067 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)
3068+#endif
3069
3070-#define MTK_WED_TX_BM_TKID 0x088
3071+#define MTK_WED_TX_BM_TKID 0x0c8
3072 #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
3073 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
3074-#endif
3075
3076 #define MTK_WED_TX_TKID_CTRL 0x0c0
3077+#if defined(CONFIG_MEDIATEK_NETSYS_V3)
3078+#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(7, 0)
3079+#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(23, 16)
3080+#else
3081 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0)
3082 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
3083+#endif
3084+
3085 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
3086
3087 #define MTK_WED_TX_TKID_DYN_THR 0x0e0
3088@@ -220,12 +235,15 @@ struct mtk_wdma_desc {
3089 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
3090 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
3091 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
3092-#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16)
3093+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(15, 12)
3094+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 BIT(18)
3095 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
3096-#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
3097+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK BIT(20)
3098 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
3099 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
3100+#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST BIT(25)
3101 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
3102+#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30)
3103
3104 /* CONFIG_MEDIATEK_NETSYS_V1 */
3105 #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)
3106@@ -288,9 +306,11 @@ struct mtk_wdma_desc {
3107 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
3108
3109 #define MTK_WED_PCIE_INT_CTRL 0x57c
3110-#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
3111-#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
3112 #define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12)
3113+#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
3114+#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
3115+#define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER BIT(21)
3116+
3117 #define MTK_WED_WPDMA_CFG_BASE 0x580
3118 #define MTK_WED_WPDMA_CFG_INT_MASK 0x584
3119 #define MTK_WED_WPDMA_CFG_TX 0x588
3120@@ -319,20 +339,50 @@ struct mtk_wdma_desc {
3121 #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX GENMASK(25, 24)
3122
3123 #define MTK_WED_WPDMA_RX_GLO_CFG 0x76c
3124-#define MTK_WED_WPDMA_RX_RING 0x770
3125+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
3126+#define MTK_WED_WPDMA_RX_RING0 0x770
3127+#else
3128+#define MTK_WED_WPDMA_RX_RING0 0x7d0
3129+#endif
3130+#define MTK_WED_WPDMA_RX_RING1 0x7d8
3131
3132 #define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4)
3133 #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)
3134 #define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c
3135
3136+#define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4
3137+#define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)
3138+#define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE GENMASK(12, 8)
3139+#define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)
3140+
3141+#define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX 0x7b8
3142+#define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR BIT(15)
3143+
3144+#define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX 0x7bc
3145+
3146+#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG 0x7c0
3147+#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0)
3148+#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR BIT(16)
3149+
3150 #define MTK_WED_WDMA_RING_TX 0x800
3151
3152 #define MTK_WED_WDMA_TX_MIB 0x810
3153
3154-
3155 #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
3156 #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
3157
3158+#define MTK_WED_WDMA_RX_PREF_CFG 0x950
3159+#define MTK_WED_WDMA_RX_PREF_EN BIT(0)
3160+#define MTK_WED_WDMA_RX_PREF_BURST_SIZE GENMASK(12, 8)
3161+#define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)
3162+#define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24)
3163+#define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25)
3164+#define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26)
3165+
3166+#define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C
3167+#define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)
3168+#define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR BIT(16)
3169+
3170 #define MTK_WED_WDMA_GLO_CFG 0xa04
3171 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
3172 #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
3173@@ -365,6 +415,7 @@ struct mtk_wdma_desc {
3174 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
3175
3176 #define MTK_WED_WDMA_INT_CTRL 0xa2c
3177+#define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0)
3178 #define MTK_WED_WDMA_INT_POLL_SRC_SEL GENMASK(17, 16)
3179
3180 #define MTK_WED_WDMA_CFG_BASE 0xaa0
3181@@ -426,6 +477,18 @@ struct mtk_wdma_desc {
3182 #define MTK_WDMA_INT_GRP1 0x250
3183 #define MTK_WDMA_INT_GRP2 0x254
3184
3185+#define MTK_WDMA_PREF_TX_CFG 0x2d0
3186+#define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)
3187+
3188+#define MTK_WDMA_PREF_RX_CFG 0x2dc
3189+#define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)
3190+
3191+#define MTK_WDMA_WRBK_TX_CFG 0x300
3192+#define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30)
3193+
3194+#define MTK_WDMA_WRBK_RX_CFG 0x344
3195+#define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30)
3196+
3197 #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)
3198 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
3199 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
3200@@ -439,6 +502,31 @@ struct mtk_wdma_desc {
3201 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
3202 #define MTK_WED_RTQM_TXDMAD_FPORT GENMASK(23, 20)
3203
3204+#define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c
3205+#define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4)
3206+#define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28
3207+#define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) (0xb2c + (_n) * 0x4)
3208+#define MTK_WED_RTQM_IGRS0_FDROP_CNT 0xb34
3209+
3210+
3211+#define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT 0xb44
3212+#define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) (0xb48 + (_n) * 0x4)
3213+#define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT 0xb50
3214+#define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) (0xb54+ (_n) * 0x4)
3215+#define MTK_WED_RTQM_IGRS1_FDROP_CNT 0xb5c
3216+
3217+#define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT 0xb6c
3218+#define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) (0xb70 + (_n) * 0x4)
3219+#define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT 0xb78
3220+#define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) (0xb7c+ (_n) * 0x4)
3221+#define MTK_WED_RTQM_IGRS2_FDROP_CNT 0xb84
3222+
3223+#define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT 0xb94
3224+#define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) (0xb98 + (_n) * 0x4)
3225+#define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT 0xba0
3226+#define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) (0xba4+ (_n) * 0x4)
3227+#define MTK_WED_RTQM_IGRS3_FDROP_CNT 0xbac
3228+
3229 #define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)
3230 #define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)
3231 #define MTK_WED_RTQM_Q2N_MIB 0xb80
3232@@ -447,6 +535,24 @@ struct mtk_wdma_desc {
3233 #define MTK_WED_RTQM_Q2B_MIB 0xb8c
3234 #define MTK_WED_RTQM_PFDBK_MIB 0xb90
3235
3236+#define MTK_WED_RTQM_ENQ_CFG0 0xbb8
3237+#define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT GENMASK(15, 12)
3238+
3239+#define MTK_WED_RTQM_FDROP_MIB 0xb84
3240+#define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT 0xbbc
3241+#define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT 0xbc0
3242+#define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT 0xbc4
3243+#define MTK_WED_RTQM_ENQ_I2N_PKT_CNT 0xbc8
3244+#define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT 0xbcc
3245+#define MTK_WED_RTQM_ENQ_ERR_CNT 0xbd0
3246+
3247+#define MTK_WED_RTQM_DEQ_DMAD_CNT 0xbd8
3248+#define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT 0xbdc
3249+#define MTK_WED_RTQM_DEQ_PKT_CNT 0xbe0
3250+#define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT 0xbe4
3251+#define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT 0xbe8
3252+#define MTK_WED_RTQM_DEQ_ERR_CNT 0xbec
3253+
3254 #define MTK_WED_RROQM_GLO_CFG 0xc04
3255 #define MTK_WED_RROQM_RST_IDX 0xc08
3256 #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
3257@@ -487,8 +593,8 @@ struct mtk_wdma_desc {
3258 #define MTK_WED_RX_BM_BASE 0xd84
3259 #define MTK_WED_RX_BM_INIT_PTR 0xd88
3260 #define MTK_WED_RX_BM_PTR 0xd8c
3261-#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
3262 #define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)
3263+#define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
3264
3265 #define MTK_WED_RX_BM_BLEN 0xd90
3266 #define MTK_WED_RX_BM_STS 0xd94
3267@@ -496,7 +602,193 @@ struct mtk_wdma_desc {
3268 #define MTK_WED_RX_BM_INTF 0xd9c
3269 #define MTK_WED_RX_BM_ERR_STS 0xda8
3270
3271+#define MTK_RRO_IND_CMD_SIGNATURE 0xe00
3272+#define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0)
3273+#define MTK_RRO_IND_CMD_MAGIC_CNT GENMASK(30, 28)
3274+
3275+#define MTK_WED_IND_CMD_RX_CTRL0 0xe04
3276+#define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0)
3277+#define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16)
3278+#define MTK_WED_IND_CMD_MAGIC_CNT GENMASK(30, 28)
3279+
3280+#define MTK_WED_IND_CMD_RX_CTRL1 0xe08
3281+#define MTK_WED_IND_CMD_RX_CTRL2 0xe0c
3282+#define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0)
3283+#define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16)
3284+
3285+#define MTK_WED_RRO_CFG0 0xe10
3286+#define MTK_WED_RRO_CFG1 0xe14
3287+#define MTK_WED_RRO_CFG1_MAX_WIN_SZ GENMASK(31, 29)
3288+#define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16)
3289+#define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0)
3290+
3291+#define MTK_WED_ADDR_ELEM_CFG0 0xe18
3292+#define MTK_WED_ADDR_ELEM_CFG1 0xe1c
3293+#define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16)
3294+
3295+#define MTK_WED_ADDR_ELEM_TBL_CFG 0xe20
3296+#define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0)
3297+#define MTK_WED_ADDR_ELEM_TBL_RD_RDY BIT(28)
3298+#define MTK_WED_ADDR_ELEM_TBL_WR_RDY BIT(29)
3299+#define MTK_WED_ADDR_ELEM_TBL_RD BIT(30)
3300+#define MTK_WED_ADDR_ELEM_TBL_WR BIT(31)
3301+
3302+#define MTK_WED_RADDR_ELEM_TBL_WDATA 0xe24
3303+#define MTK_WED_RADDR_ELEM_TBL_RDATA 0xe28
3304+
3305+#define MTK_WED_PN_CHECK_CFG 0xe30
3306+#define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0)
3307+#define MTK_WED_PN_CHECK_RD_RDY BIT(28)
3308+#define MTK_WED_PN_CHECK_WR_RDY BIT(29)
3309+#define MTK_WED_PN_CHECK_RD BIT(30)
3310+#define MTK_WED_PN_CHECK_WR BIT(31)
3311+
3312+#define MTK_WED_PN_CHECK_WDATA_M 0xe38
3313+#define MTK_WED_PN_CHECK_IS_FIRST BIT(17)
3314+
3315+#define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) (0xe44 + (_n) * 0x8)
3316+
3317+#define MTK_WED_RRO_MSDU_PG_RING2_CFG 0xe58
3318+#define MTK_WED_RRO_MSDU_PG_DRV_CLR BIT(26)
3319+#define MTK_WED_RRO_MSDU_PG_DRV_EN BIT(31)
3320+
3321+#define MTK_WED_RRO_MSDU_PG_CTRL0(_n) (0xe5c + (_n) * 0xc)
3322+#define MTK_WED_RRO_MSDU_PG_CTRL1(_n) (0xe60 + (_n) * 0xc)
3323+#define MTK_WED_RRO_MSDU_PG_CTRL2(_n) (0xe64 + (_n) * 0xc)
3324+
3325+#define MTK_WED_RRO_RX_D_RX(_n) (0xe80 + (_n) * 0x10)
3326+
3327+#define MTK_WED_RRO_RX_MAGIC_CNT BIT(13)
3328+
3329+#define MTK_WED_RRO_RX_D_CFG(_n) (0xea0 + (_n) * 0x4)
3330+#define MTK_WED_RRO_RX_D_DRV_CLR BIT(26)
3331+#define MTK_WED_RRO_RX_D_DRV_EN BIT(31)
3332+
3333+#define MTK_WED_RRO_PG_BM_RX_DMAM 0xeb0
3334+#define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0)
3335+
3336+#define MTK_WED_RRO_PG_BM_BASE 0xeb4
3337+#define MTK_WED_RRO_PG_BM_INIT_PTR 0xeb8
3338+#define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0)
3339+#define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX BIT(16)
3340+
3341+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX 0xeec
3342+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0)
3343+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR BIT(1)
3344+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG GENMASK(6, 2)
3345+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN BIT(8)
3346+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR BIT(9)
3347+#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG GENMASK(14, 10)
3348+
3349+#define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG 0xef4
3350+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0)
3351+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR BIT(1)
3352+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG GENMASK(6, 2)
3353+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN BIT(8)
3354+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR BIT(9)
3355+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG GENMASK(14, 10)
3356+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16)
3357+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17)
3358+#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG GENMASK(22, 18)
3359+
3360+#define MTK_WED_RX_IND_CMD_CNT0 0xf20
3361+#define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)
3362+
3363+#define MTK_WED_RX_IND_CMD_CNT(_n) (0xf20 + (_n) * 0x4)
3364+#define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0)
3365+
3366+#define MTK_WED_RX_ADDR_ELEM_CNT(_n) (0xf48 + (_n) * 0x4)
3367+#define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0)
3368+#define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16)
3369+#define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)
3370+
3371+#define MTK_WED_RX_MSDU_PG_CNT(_n) (0xf5c + (_n) * 0x4)
3372+
3373+#define MTK_WED_RX_PN_CHK_CNT 0xf70
3374+#define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0)
3375+
3376 #define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000
3377 #define MTK_WED_PCIE_INT_MASK 0x0
3378
3379+#define MTK_WED_PAO_AMSDU_FIFO 0x1800
3380+#define MTK_WED_PAO_AMSDU_IS_PRIOR0_RING BIT(10)
3381+
3382+#define MTK_WED_PAO_STA_INFO 0x01810
3383+#define MTK_WED_PAO_STA_INFO_DO_INIT BIT(0)
3384+#define MTK_WED_PAO_STA_INFO_SET_INIT BIT(1)
3385+
3386+#define MTK_WED_PAO_STA_INFO_INIT 0x01814
3387+#define MTK_WED_PAO_STA_WTBL_HDRT_MODE BIT(0)
3388+#define MTK_WED_PAO_STA_RMVL BIT(1)
3389+#define MTK_WED_PAO_STA_MAX_AMSDU_LEN GENMASK(7, 2)
3390+#define MTK_WED_PAO_STA_MAX_AMSDU_NUM GENMASK(11, 8)
3391+
3392+#define MTK_WED_PAO_HIFTXD_BASE_L(_n) (0x1980 + (_n) * 0x4)
3393+
3394+#define MTK_WED_PAO_PSE 0x1910
3395+#define MTK_WED_PAO_PSE_RESET BIT(16)
3396+
3397+#define MTK_WED_PAO_HIFTXD_CFG 0x1968
3398+#define MTK_WED_PAO_HIFTXD_SRC GENMASK(16, 15)
3399+
3400+#define MTK_WED_PAO_MON_AMSDU_FIFO_DMAD 0x1a34
3401+
3402+#define MTK_WED_PAO_MON_AMSDU_ENG_DMAD(_n) (0x1a80 + (_n) * 0x50)
3403+#define MTK_WED_PAO_MON_AMSDU_ENG_QFPL(_n) (0x1a84 + (_n) * 0x50)
3404+#define MTK_WED_PAO_MON_AMSDU_ENG_QENI(_n) (0x1a88 + (_n) * 0x50)
3405+#define MTK_WED_PAO_MON_AMSDU_ENG_QENO(_n) (0x1a8c + (_n) * 0x50)
3406+#define MTK_WED_PAO_MON_AMSDU_ENG_MERG(_n) (0x1a90 + (_n) * 0x50)
3407+
3408+#define MTK_WED_PAO_MON_AMSDU_ENG_CNT8(_n) (0x1a94 + (_n) * 0x50)
3409+#define MTK_WED_PAO_AMSDU_ENG_MAX_QGPP_CNT GENMASK(10, 0)
3410+#define MTK_WED_PAO_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)
3411+
3412+#define MTK_WED_PAO_MON_AMSDU_ENG_CNT9(_n) (0x1a98 + (_n) * 0x50)
3413+#define MTK_WED_PAO_AMSDU_ENG_CUR_ENTRY GENMASK(10, 0)
3414+#define MTK_WED_PAO_AMSDU_ENG_MAX_BUF_MERGED GENMASK(20, 16)
3415+#define MTK_WED_PAO_AMSDU_ENG_MAX_MSDU_MERGED GENMASK(28, 24)
3416+
3417+#define MTK_WED_PAO_MON_QMEM_STS1 0x1e04
3418+
3419+#define MTK_WED_PAO_MON_QMEM_CNT(_n) (0x1e0c + (_n) * 0x4)
3420+#define MTK_WED_PAO_QMEM_FQ_CNT GENMASK(27, 16)
3421+#define MTK_WED_PAO_QMEM_SP_QCNT GENMASK(11, 0)
3422+#define MTK_WED_PAO_QMEM_TID0_QCNT GENMASK(27, 16)
3423+#define MTK_WED_PAO_QMEM_TID1_QCNT GENMASK(11, 0)
3424+#define MTK_WED_PAO_QMEM_TID2_QCNT GENMASK(27, 16)
3425+#define MTK_WED_PAO_QMEM_TID3_QCNT GENMASK(11, 0)
3426+#define MTK_WED_PAO_QMEM_TID4_QCNT GENMASK(27, 16)
3427+#define MTK_WED_PAO_QMEM_TID5_QCNT GENMASK(11, 0)
3428+#define MTK_WED_PAO_QMEM_TID6_QCNT GENMASK(27, 16)
3429+#define MTK_WED_PAO_QMEM_TID7_QCNT GENMASK(11, 0)
3430+
3431+#define MTK_WED_PAO_MON_QMEM_PTR(_n) (0x1e20 + (_n) * 0x4)
3432+#define MTK_WED_PAO_QMEM_FQ_HEAD GENMASK(27, 16)
3433+#define MTK_WED_PAO_QMEM_SP_QHEAD GENMASK(11, 0)
3434+#define MTK_WED_PAO_QMEM_TID0_QHEAD GENMASK(27, 16)
3435+#define MTK_WED_PAO_QMEM_TID1_QHEAD GENMASK(11, 0)
3436+#define MTK_WED_PAO_QMEM_TID2_QHEAD GENMASK(27, 16)
3437+#define MTK_WED_PAO_QMEM_TID3_QHEAD GENMASK(11, 0)
3438+#define MTK_WED_PAO_QMEM_TID4_QHEAD GENMASK(27, 16)
3439+#define MTK_WED_PAO_QMEM_TID5_QHEAD GENMASK(11, 0)
3440+#define MTK_WED_PAO_QMEM_TID6_QHEAD GENMASK(27, 16)
3441+#define MTK_WED_PAO_QMEM_TID7_QHEAD GENMASK(11, 0)
3442+#define MTK_WED_PAO_QMEM_FQ_TAIL GENMASK(27, 16)
3443+#define MTK_WED_PAO_QMEM_SP_QTAIL GENMASK(11, 0)
3444+#define MTK_WED_PAO_QMEM_TID0_QTAIL GENMASK(27, 16)
3445+#define MTK_WED_PAO_QMEM_TID1_QTAIL GENMASK(11, 0)
3446+#define MTK_WED_PAO_QMEM_TID2_QTAIL GENMASK(27, 16)
3447+#define MTK_WED_PAO_QMEM_TID3_QTAIL GENMASK(11, 0)
3448+#define MTK_WED_PAO_QMEM_TID4_QTAIL GENMASK(27, 16)
3449+#define MTK_WED_PAO_QMEM_TID5_QTAIL GENMASK(11, 0)
3450+#define MTK_WED_PAO_QMEM_TID6_QTAIL GENMASK(27, 16)
3451+#define MTK_WED_PAO_QMEM_TID7_QTAIL GENMASK(11, 0)
3452+
3453+#define MTK_WED_PAO_MON_HIFTXD_FETCH_MSDU(_n) (0x1ec4 + (_n) * 0x4)
3454+
3455+#define MTK_WED_PCIE_BASE 0x11280000
3456+
3457+#define MTK_WED_PCIE_BASE0 0x11300000
3458+#define MTK_WED_PCIE_BASE1 0x11310000
3459+#define MTK_WED_PCIE_BASE2 0x11290000
3460 #endif
3461diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
3462index 58b5ce6..5e51790 100644
3463--- a/include/linux/netdevice.h
3464+++ b/include/linux/netdevice.h
3465@@ -873,6 +873,13 @@ struct net_device_path {
3466 u8 queue;
3467 u16 wcid;
3468 u8 bss;
3469+ u32 usr_info;
3470+ u8 tid;
3471+ u8 is_fixedrate;
3472+ u8 is_prior;
3473+ u8 is_sp;
3474+ u8 hf;
3475+ u8 amsdu_en;
3476 } mtk_wdma;
3477 };
3478 };
3479diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h
3480index 27cf284..60336e0 100644
3481--- a/include/linux/soc/mediatek/mtk_wed.h
3482+++ b/include/linux/soc/mediatek/mtk_wed.h
3483@@ -5,11 +5,14 @@
3484 #include <linux/rcupdate.h>
3485 #include <linux/regmap.h>
3486 #include <linux/pci.h>
3487+#include <linux/skbuff.h>
3488+#include <linux/iopoll.h>
3489
3490 #define WED_WO_STA_REC 0x6
3491
3492 #define MTK_WED_TX_QUEUES 2
3493 #define MTK_WED_RX_QUEUES 2
3494+#define MTK_WED_RX_PAGE_QUEUES 3
3495
3496 enum mtk_wed_wo_cmd {
3497 MTK_WED_WO_CMD_WED_CFG,
3498@@ -55,10 +58,13 @@ enum mtk_wed_bus_tye {
3499 struct mtk_wed_hw;
3500 struct mtk_wdma_desc;
3501
3502+#define MTK_WED_RING_CONFIGURED BIT(0)
3503+
3504 struct mtk_wed_ring {
3505 struct mtk_wdma_desc *desc;
3506 dma_addr_t desc_phys;
3507 int size;
3508+ u32 flags;
3509
3510 u32 reg_base;
3511 void __iomem *wpdma;
3512@@ -69,11 +75,18 @@ struct mtk_rxbm_desc {
3513 __le32 token;
3514 } __packed __aligned(4);
3515
3516+struct dma_page_info {
3517+ void *addr;
3518+ dma_addr_t addr_phys;
3519+};
3520+
3521 struct dma_buf {
3522 int size;
3523- void **pages;
3524- struct mtk_wdma_desc *desc;
3525+ int pkt_nums;
3526+ void *desc;
3527+ int desc_size;
3528 dma_addr_t desc_phys;
3529+ struct dma_page_info *pages;
3530 };
3531
3532 struct dma_entry {
3533@@ -97,6 +110,7 @@ struct mtk_wed_device {
3534 struct device *dev;
3535 struct mtk_wed_hw *hw;
3536 bool init_done, running;
3537+ bool wdma_init_done;
3538 int wdma_idx;
3539 int irq;
3540 u8 ver;
3541@@ -108,7 +122,11 @@ struct mtk_wed_device {
3542 struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES];
3543 struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
3544
3545- struct dma_buf buf_ring;
3546+ struct mtk_wed_ring rx_rro_ring[MTK_WED_RX_QUEUES];
3547+ struct mtk_wed_ring rx_page_ring[MTK_WED_RX_PAGE_QUEUES];
3548+ struct mtk_wed_ring ind_cmd_ring;
3549+
3550+ struct dma_buf tx_buf_ring;
3551
3552 struct {
3553 int size;
3554@@ -117,6 +135,8 @@ struct mtk_wed_device {
3555 dma_addr_t desc_phys;
3556 } rx_buf_ring;
3557
3558+ struct dma_buf rx_page_buf_ring;
3559+
3560 struct {
3561 struct mtk_wed_ring rro_ring;
3562 void __iomem *rro_desc;
3563@@ -131,8 +151,9 @@ struct mtk_wed_device {
3564 struct platform_device *platform_dev;
3565 struct pci_dev *pci_dev;
3566 };
3567+ enum mtk_wed_bus_tye bus_type;
3568 void __iomem *base;
3569- u32 bus_type;
3570+ void __iomem *regs;
3571 u32 phy_base;
3572
3573 u32 wpdma_phys;
3574@@ -142,9 +163,13 @@ struct mtk_wed_device {
3575 u32 wpdma_txfree;
3576 u32 wpdma_rx_glo;
3577 u32 wpdma_rx;
3578+ u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
3579+ u32 wpdma_rx_pg;
3580
3581 u8 tx_tbit[MTK_WED_TX_QUEUES];
3582 u8 rx_tbit[MTK_WED_RX_QUEUES];
3583+ u8 rro_rx_tbit[MTK_WED_RX_QUEUES];
3584+ u8 rx_pg_tbit[MTK_WED_RX_PAGE_QUEUES];
3585 u8 txfree_tbit;
3586
3587 u16 token_start;
3588@@ -154,12 +179,26 @@ struct mtk_wed_device {
3589 unsigned int rx_size;
3590
3591 bool wcid_512;
3592-
3593+ bool hwrro;
3594+ bool msi;
3595+
3596+ u8 max_amsdu_nums;
3597+ u32 max_amsdu_len;
3598+
3599+ struct {
3600+ u8 se_group_nums;
3601+ u16 win_size;
3602+ u16 particular_sid;
3603+ u32 ack_sn_addr;
3604+ dma_addr_t particular_se_phys;
3605+ dma_addr_t addr_elem_phys[1024];
3606+ } ind_cmd;
3607+
3608+ u32 chip_id;
3609 u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
3610 int (*offload_enable)(struct mtk_wed_device *wed);
3611 void (*offload_disable)(struct mtk_wed_device *wed);
3612- u32 (*init_rx_buf)(struct mtk_wed_device *wed,
3613- int pkt_num);
3614+ u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size);
3615 void (*release_rx_buf)(struct mtk_wed_device *wed);
3616 void (*update_wo_rx_stats)(struct mtk_wed_device *wed,
3617 struct mtk_wed_wo_rx_stats *stats);
3618@@ -180,6 +219,11 @@ struct mtk_wed_ops {
3619 void __iomem *regs);
3620 int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring,
3621 void __iomem *regs, bool reset);
3622+ int (*rro_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
3623+ void __iomem *regs);
3624+ int (*msdu_pg_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
3625+ void __iomem *regs);
3626+ int (*ind_rx_ring_setup)(struct mtk_wed_device *dev, void __iomem *regs);
3627 int (*msg_update)(struct mtk_wed_device *dev, int cmd_id,
3628 void *data, int len);
3629 void (*detach)(struct mtk_wed_device *dev);
3630@@ -196,6 +240,7 @@ struct mtk_wed_ops {
3631 void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);
3632 void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb,
3633 u32 reason, u32 hash);
3634+ void (*start_hwrro)(struct mtk_wed_device *dev, u32 irq_mask);
3635 };
3636
3637 extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;
3638@@ -224,12 +269,21 @@ static inline bool
3639 mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
3640 {
3641 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
3642+ if (dev->ver == 3 && !dev->wlan.hwrro)
3643+ return false;
3644+
3645 return dev->ver != 1;
3646 #else
3647 return false;
3648 #endif
3649 }
3650
3651+static inline bool
3652+mtk_wed_device_support_pao(struct mtk_wed_device *dev)
3653+{
3654+ return dev->ver == 3;
3655+}
3656+
3657 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
3658 #define mtk_wed_device_active(_dev) !!(_dev)->ops
3659 #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
3660@@ -243,6 +297,12 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
3661 (_dev)->ops->txfree_ring_setup(_dev, _regs)
3662 #define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \
3663 (_dev)->ops->rx_ring_setup(_dev, _ring, _regs, _reset)
3664+#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) \
3665+ (_dev)->ops->rro_rx_ring_setup(_dev, _ring, _regs)
3666+#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) \
3667+ (_dev)->ops->msdu_pg_rx_ring_setup(_dev, _ring, _regs)
3668+#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) \
3669+ (_dev)->ops->ind_rx_ring_setup(_dev, _regs)
3670 #define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \
3671 (_dev)->ops->msg_update(_dev, _id, _msg, _len)
3672 #define mtk_wed_device_reg_read(_dev, _reg) \
3673@@ -257,6 +317,9 @@ mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
3674 (_dev)->ops->reset_dma(_dev)
3675 #define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \
3676 (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash)
3677+#define mtk_wed_device_start_hwrro(_dev, _mask) \
3678+ (_dev)->ops->start_hwrro(_dev, _mask)
3679+
3680 #else
3681 static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
3682 {
3683@@ -268,6 +331,9 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
3684 #define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
3685 #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
3686 #define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV
3687+#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) -ENODEV
3688+#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) -ENODEV
3689+#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) -ENODEV
3690 #define mtk_wed_device_reg_read(_dev, _reg) 0
3691 #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
3692 #define mtk_wed_device_irq_get(_dev, _mask) 0
3693@@ -275,6 +341,7 @@ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
3694 #define mtk_wed_device_dma_reset(_dev) do {} while (0)
3695 #define mtk_wed_device_setup_tc(_dev, _ndev, _type, _data) do {} while (0)
3696 #define mtk_wed_device_ppe_check(_dev, _hash) do {} while (0)
3697+#define mtk_wed_device_start_hwrro(_dev, _mask) do {} while (0)
3698 #endif
3699
3700 #endif
3701--
37022.18.0
3703