blob: 85c5ceb6050e239edc1faef9314226133522f6bb [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +08001From 21c1013ecce400652b42489935190df542c9fa4b Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:08 +0800
4Subject: [PATCH]
5 [slow-speed-io][999-2150-sound-add-some-helpers-to-control-mtk_memif.patch]
6
7---
8 sound/soc/mediatek/common/mtk-afe-fe-dai.c | 216 +++++++++++++++++++++
9 sound/soc/mediatek/common/mtk-afe-fe-dai.h | 16 ++
10 sound/soc/mediatek/common/mtk-base-afe.h | 28 ++-
11 3 files changed, 259 insertions(+), 1 deletion(-)
12
13diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c
14index 10ea4fdbe..309dc1ef6 100644
developerbe797a32021-12-16 16:56:09 +080015--- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c
16+++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c
developer5d148cb2023-06-02 13:08:11 +080017@@ -361,6 +361,222 @@ int mtk_afe_dai_resume(struct snd_soc_dai *dai)
developerbe797a32021-12-16 16:56:09 +080018 }
19 EXPORT_SYMBOL_GPL(mtk_afe_dai_resume);
20
21+int mtk_memif_set_enable(struct mtk_base_afe *afe, int id)
22+{
23+ struct mtk_base_afe_memif *memif = &afe->memif[id];
24+
25+ if (memif->data->enable_shift < 0) {
26+ dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n",
27+ __func__, id);
28+ return 0;
29+ }
30+ return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg,
31+ 1, 1, memif->data->enable_shift);
32+}
33+EXPORT_SYMBOL_GPL(mtk_memif_set_enable);
34+
35+int mtk_memif_set_disable(struct mtk_base_afe *afe, int id)
36+{
37+ struct mtk_base_afe_memif *memif = &afe->memif[id];
38+
39+ if (memif->data->enable_shift < 0) {
40+ dev_warn(afe->dev, "%s(), error, id %d, enable_shift < 0\n",
41+ __func__, id);
42+ return 0;
43+ }
44+ return mtk_regmap_update_bits(afe->regmap, memif->data->enable_reg,
45+ 1, 0, memif->data->enable_shift);
46+}
47+EXPORT_SYMBOL_GPL(mtk_memif_set_disable);
48+
49+int mtk_memif_set_addr(struct mtk_base_afe *afe, int id,
50+ unsigned char *dma_area,
51+ dma_addr_t dma_addr,
52+ size_t dma_bytes)
53+{
54+ struct mtk_base_afe_memif *memif = &afe->memif[id];
55+ int msb_at_bit33 = upper_32_bits(dma_addr) ? 1 : 0;
56+ unsigned int phys_buf_addr = lower_32_bits(dma_addr);
57+ unsigned int phys_buf_addr_upper_32 = upper_32_bits(dma_addr);
58+
59+ memif->dma_area = dma_area;
60+ memif->dma_addr = dma_addr;
61+ memif->dma_bytes = dma_bytes;
62+
63+ /* start */
64+ mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base,
65+ phys_buf_addr);
66+ /* end */
67+ if (memif->data->reg_ofs_end)
68+ mtk_regmap_write(afe->regmap,
69+ memif->data->reg_ofs_end,
70+ phys_buf_addr + dma_bytes - 1);
71+ else
72+ mtk_regmap_write(afe->regmap,
73+ memif->data->reg_ofs_base +
74+ AFE_BASE_END_OFFSET,
75+ phys_buf_addr + dma_bytes - 1);
76+
77+ /* set start, end, upper 32 bits */
78+ if (memif->data->reg_ofs_base_msb) {
79+ mtk_regmap_write(afe->regmap, memif->data->reg_ofs_base_msb,
80+ phys_buf_addr_upper_32);
81+ mtk_regmap_write(afe->regmap,
82+ memif->data->reg_ofs_end_msb,
83+ phys_buf_addr_upper_32);
84+ }
85+
86+ /* set MSB to 33-bit */
87+ if (memif->data->msb_reg >= 0)
88+ mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg,
89+ 1, msb_at_bit33, memif->data->msb_shift);
90+
91+ return 0;
92+}
93+EXPORT_SYMBOL_GPL(mtk_memif_set_addr);
94+
95+int mtk_memif_set_channel(struct mtk_base_afe *afe,
96+ int id, unsigned int channel)
97+{
98+ struct mtk_base_afe_memif *memif = &afe->memif[id];
99+ unsigned int mono;
100+
101+ if (memif->data->mono_shift < 0)
102+ return 0;
103+
104+ if (memif->data->quad_ch_mask) {
105+ unsigned int quad_ch = (channel == 4) ? 1 : 0;
106+
107+ mtk_regmap_update_bits(afe->regmap, memif->data->quad_ch_reg,
108+ memif->data->quad_ch_mask,
109+ quad_ch, memif->data->quad_ch_shift);
110+ }
111+
112+ if (memif->data->mono_invert)
113+ mono = (channel == 1) ? 0 : 1;
114+ else
115+ mono = (channel == 1) ? 1 : 0;
116+
117+ return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
118+ 1, mono, memif->data->mono_shift);
119+}
120+EXPORT_SYMBOL_GPL(mtk_memif_set_channel);
121+
122+static int mtk_memif_set_rate_fs(struct mtk_base_afe *afe,
123+ int id, int fs)
124+{
125+ struct mtk_base_afe_memif *memif = &afe->memif[id];
126+
127+ if (memif->data->fs_shift >= 0)
128+ mtk_regmap_update_bits(afe->regmap, memif->data->fs_reg,
129+ memif->data->fs_maskbit,
130+ fs, memif->data->fs_shift);
131+
132+ return 0;
133+}
134+
135+int mtk_memif_set_rate(struct mtk_base_afe *afe,
136+ int id, unsigned int rate)
137+{
138+ int fs = 0;
139+
140+ if (!afe->get_dai_fs) {
141+ dev_err(afe->dev, "%s(), error, afe->get_dai_fs == NULL\n",
142+ __func__);
143+ return -EINVAL;
144+ }
145+
146+ fs = afe->get_dai_fs(afe, id, rate);
147+
148+ if (fs < 0)
149+ return -EINVAL;
150+
151+ return mtk_memif_set_rate_fs(afe, id, fs);
152+}
153+EXPORT_SYMBOL_GPL(mtk_memif_set_rate);
154+
155+int mtk_memif_set_rate_substream(struct snd_pcm_substream *substream,
156+ int id, unsigned int rate)
157+{
158+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
159+ struct snd_soc_component *component =
160+ snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
161+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
162+
163+ int fs = 0;
164+
165+ if (!afe->memif_fs) {
166+ dev_err(afe->dev, "%s(), error, afe->memif_fs == NULL\n",
167+ __func__);
168+ return -EINVAL;
169+ }
170+
171+ fs = afe->memif_fs(substream, rate);
172+
173+ if (fs < 0)
174+ return -EINVAL;
175+
176+ return mtk_memif_set_rate_fs(afe, id, fs);
177+}
178+EXPORT_SYMBOL_GPL(mtk_memif_set_rate_substream);
179+
180+int mtk_memif_set_format(struct mtk_base_afe *afe,
181+ int id, snd_pcm_format_t format)
182+{
183+ struct mtk_base_afe_memif *memif = &afe->memif[id];
184+ int hd_audio = 0;
185+ int hd_align = 0;
186+
187+ /* set hd mode */
188+ switch (format) {
189+ case SNDRV_PCM_FORMAT_S16_LE:
190+ case SNDRV_PCM_FORMAT_U16_LE:
191+ hd_audio = 0;
192+ break;
193+ case SNDRV_PCM_FORMAT_S32_LE:
194+ case SNDRV_PCM_FORMAT_U32_LE:
195+ hd_audio = 1;
196+ hd_align = 1;
197+ break;
198+ case SNDRV_PCM_FORMAT_S24_LE:
199+ case SNDRV_PCM_FORMAT_U24_LE:
200+ hd_audio = 1;
201+ break;
202+ default:
203+ dev_err(afe->dev, "%s() error: unsupported format %d\n",
204+ __func__, format);
205+ break;
206+ }
207+
208+ mtk_regmap_update_bits(afe->regmap, memif->data->hd_reg,
209+ 1, hd_audio, memif->data->hd_shift);
210+
211+ mtk_regmap_update_bits(afe->regmap, memif->data->hd_align_reg,
212+ 1, hd_align, memif->data->hd_align_mshift);
213+
214+ return 0;
215+}
216+EXPORT_SYMBOL_GPL(mtk_memif_set_format);
217+
218+int mtk_memif_set_pbuf_size(struct mtk_base_afe *afe,
219+ int id, int pbuf_size)
220+{
221+ const struct mtk_base_memif_data *memif_data = afe->memif[id].data;
222+
223+ if (memif_data->pbuf_mask == 0 || memif_data->minlen_mask == 0)
224+ return 0;
225+
226+ mtk_regmap_update_bits(afe->regmap, memif_data->pbuf_reg,
227+ memif_data->pbuf_mask,
228+ pbuf_size, memif_data->pbuf_shift);
229+
230+ mtk_regmap_update_bits(afe->regmap, memif_data->minlen_reg,
231+ memif_data->minlen_mask,
232+ pbuf_size, memif_data->minlen_shift);
233+ return 0;
234+}
235+EXPORT_SYMBOL_GPL(mtk_memif_set_pbuf_size);
236+
237 MODULE_DESCRIPTION("Mediatek simple fe dai operator");
238 MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
239 MODULE_LICENSE("GPL v2");
developer5d148cb2023-06-02 13:08:11 +0800240diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.h b/sound/soc/mediatek/common/mtk-afe-fe-dai.h
241index 55074fb98..507e3e7c3 100644
developerbe797a32021-12-16 16:56:09 +0800242--- a/sound/soc/mediatek/common/mtk-afe-fe-dai.h
243+++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.h
developer5d148cb2023-06-02 13:08:11 +0800244@@ -34,4 +34,20 @@ int mtk_dynamic_irq_release(struct mtk_base_afe *afe, int irq_id);
developerbe797a32021-12-16 16:56:09 +0800245 int mtk_afe_dai_suspend(struct snd_soc_dai *dai);
246 int mtk_afe_dai_resume(struct snd_soc_dai *dai);
247
248+int mtk_memif_set_enable(struct mtk_base_afe *afe, int id);
249+int mtk_memif_set_disable(struct mtk_base_afe *afe, int id);
250+int mtk_memif_set_addr(struct mtk_base_afe *afe, int id,
251+ unsigned char *dma_area,
252+ dma_addr_t dma_addr,
253+ size_t dma_bytes);
254+int mtk_memif_set_channel(struct mtk_base_afe *afe,
255+ int id, unsigned int channel);
256+int mtk_memif_set_rate(struct mtk_base_afe *afe,
257+ int id, unsigned int rate);
258+int mtk_memif_set_rate_substream(struct snd_pcm_substream *substream,
259+ int id, unsigned int rate);
260+int mtk_memif_set_format(struct mtk_base_afe *afe,
261+ int id, snd_pcm_format_t format);
262+int mtk_memif_set_pbuf_size(struct mtk_base_afe *afe,
263+ int id, int pbuf_size);
264 #endif
developer5d148cb2023-06-02 13:08:11 +0800265diff --git a/sound/soc/mediatek/common/mtk-base-afe.h b/sound/soc/mediatek/common/mtk-base-afe.h
266index 60cb609a9..a8cf44d98 100644
developerbe797a32021-12-16 16:56:09 +0800267--- a/sound/soc/mediatek/common/mtk-base-afe.h
268+++ b/sound/soc/mediatek/common/mtk-base-afe.h
developer5d148cb2023-06-02 13:08:11 +0800269@@ -16,21 +16,38 @@ struct mtk_base_memif_data {
developerbe797a32021-12-16 16:56:09 +0800270 const char *name;
271 int reg_ofs_base;
272 int reg_ofs_cur;
273+ int reg_ofs_end;
274+ int reg_ofs_base_msb;
275+ int reg_ofs_cur_msb;
276+ int reg_ofs_end_msb;
277 int fs_reg;
278 int fs_shift;
279 int fs_maskbit;
280 int mono_reg;
281 int mono_shift;
282+ int mono_invert;
283+ int quad_ch_reg;
284+ int quad_ch_mask;
285+ int quad_ch_shift;
286 int enable_reg;
287 int enable_shift;
288 int hd_reg;
289- int hd_align_reg;
290 int hd_shift;
291+ int hd_align_reg;
292 int hd_align_mshift;
293 int msb_reg;
294 int msb_shift;
295+ int msb2_reg;
296+ int msb2_shift;
297 int agent_disable_reg;
298 int agent_disable_shift;
299+ /* playback memif only */
300+ int pbuf_reg;
301+ int pbuf_mask;
302+ int pbuf_shift;
303+ int minlen_reg;
304+ int minlen_mask;
305+ int minlen_shift;
306 };
307
308 struct mtk_base_irq_data {
developer5d148cb2023-06-02 13:08:11 +0800309@@ -84,6 +101,12 @@ struct mtk_base_afe {
developerbe797a32021-12-16 16:56:09 +0800310 unsigned int rate);
311 int (*irq_fs)(struct snd_pcm_substream *substream,
312 unsigned int rate);
313+ int (*get_dai_fs)(struct mtk_base_afe *afe,
314+ int dai_id, unsigned int rate);
315+ int (*get_memif_pbuf_size)(struct snd_pcm_substream *substream);
316+
317+ int (*request_dram_resource)(struct device *dev);
318+ int (*release_dram_resource)(struct device *dev);
319
320 void *platform_priv;
321 };
developer5d148cb2023-06-02 13:08:11 +0800322@@ -95,6 +118,9 @@ struct mtk_base_afe_memif {
developerbe797a32021-12-16 16:56:09 +0800323 const struct mtk_base_memif_data *data;
324 int irq_usage;
325 int const_irq;
326+ unsigned char *dma_area;
327+ dma_addr_t dma_addr;
328+ size_t dma_bytes;
329 };
330
331 struct mtk_base_afe_irq {
developer5d148cb2023-06-02 13:08:11 +0800332--
3332.34.1
334