blob: a63471d9183e55a4942ba8844be0179f1952be1f [file] [log] [blame]
developera72bbd82024-02-04 18:27:28 +08001From 8e71bf60aeb05d38f45e680d55ffdb894f8af4bc Mon Sep 17 00:00:00 2001
developerade48b12023-12-12 10:37:24 +08002From: Rex Lu <rex.lu@mediatek.com>
3Date: Mon, 11 Dec 2023 19:21:16 +0800
developera72bbd82024-02-04 18:27:28 +08004Subject: [PATCH] wifi: mt76: mt7915: support backaward compatiable
developerade48b12023-12-12 10:37:24 +08005
6---
developera72bbd82024-02-04 18:27:28 +08007 wed.c | 22 +---------------------
8 1 file changed, 1 insertion(+), 21 deletions(-)
developerade48b12023-12-12 10:37:24 +08009
developera72bbd82024-02-04 18:27:28 +080010diff --git a/wed.c b/wed.c
11index 5ed681e..2d6a944 100644
12--- a/wed.c
13+++ b/wed.c
14@@ -55,7 +55,7 @@ EXPORT_SYMBOL_GPL(mt76_wed_release_rx_buf);
15 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size)
16 {
17 struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed);
18- struct mtk_wed_bm_desc *desc = wed->rx_buf_ring.desc;
19+ struct mtk_rxbm_desc *desc = wed->rx_buf_ring.desc;
20 u32 length;
21 int i;
22
23@@ -166,26 +166,6 @@ int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset)
developerade48b12023-12-12 10:37:24 +080024 if (!ret)
25 q->wed_regs = q->wed->rx_ring[ring].reg_base;
26 break;
27- case MT76_WED_RRO_Q_DATA:
28- q->flags &= ~MT_QFLAG_WED;
29- __mt76_dma_queue_reset(dev, q, false);
30- mtk_wed_device_rro_rx_ring_setup(q->wed, ring, q->regs);
31- q->head = q->ndesc - 1;
32- q->queued = q->head;
33- break;
34- case MT76_WED_RRO_Q_MSDU_PG:
35- q->flags &= ~MT_QFLAG_WED;
developera72bbd82024-02-04 18:27:28 +080036- __mt76_dma_queue_reset(dev, q);
developerade48b12023-12-12 10:37:24 +080037- mtk_wed_device_msdu_pg_rx_ring_setup(q->wed, ring, q->regs);
38- q->head = q->ndesc - 1;
39- q->queued = q->head;
40- break;
41- case MT76_WED_RRO_Q_IND:
42- q->flags &= ~MT_QFLAG_WED;
43- mt76_dma_queue_reset(dev, q);
44- mt76_dma_rx_fill(dev, q);
45- mtk_wed_device_ind_rx_ring_setup(q->wed, q->regs);
46- break;
47 default:
48 ret = -EINVAL;
49 break;
developerade48b12023-12-12 10:37:24 +080050--
512.18.0
52