developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 1 | From a75a445f60dd12ccd14c21e04eb5bab872546926 Mon Sep 17 00:00:00 2001 |
developer | 711759c | 2022-09-21 18:38:10 +0800 | [diff] [blame] | 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 3 | Date: Thu, 22 Sep 2022 09:54:53 +0800 |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 4 | Subject: [PATCH 3008/3010] mt76: mt7915: update mt7916 trinfo when hw path |
developer | c226de8 | 2022-10-03 12:24:57 +0800 | [diff] [blame] | 5 | enable |
developer | 711759c | 2022-09-21 18:38:10 +0800 | [diff] [blame] | 6 | |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 7 | Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
developer | 711759c | 2022-09-21 18:38:10 +0800 | [diff] [blame] | 8 | --- |
| 9 | mt7915/mt7915_debug.h | 10 ++++++++++ |
| 10 | mt7915/mtk_debugfs.c | 16 +++++++++++++--- |
| 11 | 2 files changed, 23 insertions(+), 3 deletions(-) |
| 12 | |
| 13 | diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 14 | index ecdc02a..0a1ee80 100644 |
developer | 711759c | 2022-09-21 18:38:10 +0800 | [diff] [blame] | 15 | --- a/mt7915/mt7915_debug.h |
| 16 | +++ b/mt7915/mt7915_debug.h |
| 17 | @@ -133,6 +133,8 @@ enum dbg_reg_rev { |
| 18 | DBG_MIB_M0ARNG0, |
| 19 | DBG_MIB_M0DR2, |
| 20 | DBG_MIB_M0DR13, |
| 21 | + DBG_WFDMA_WED_TX_CTRL, |
| 22 | + DBG_WFDMA_WED_RX_CTRL, |
| 23 | __MT_DBG_REG_REV_MAX, |
| 24 | }; |
| 25 | |
| 26 | @@ -177,6 +179,8 @@ static const u32 mt7986_dbg_base[] = { |
| 27 | |
| 28 | /* mt7915 regs with different base and offset */ |
| 29 | static const struct __dbg_reg mt7915_dbg_reg[] = { |
| 30 | + [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 }, |
| 31 | + [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 }, |
| 32 | [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 }, |
| 33 | [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 }, |
| 34 | [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 }, |
| 35 | @@ -281,6 +285,8 @@ static const struct __dbg_reg mt7915_dbg_reg[] = { |
| 36 | |
| 37 | /* mt7986/mt7916 regs with different base and offset */ |
| 38 | static const struct __dbg_reg mt7916_dbg_reg[] = { |
| 39 | + [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 }, |
| 40 | + [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 }, |
| 41 | [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 }, |
| 42 | [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 }, |
| 43 | [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 }, |
| 44 | @@ -450,11 +456,15 @@ struct bin_debug_hdr { |
| 45 | #define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE) |
| 46 | #define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE) |
| 47 | #define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE) |
| 48 | +#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL) |
| 49 | +#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL) |
| 50 | |
| 51 | #define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n))) |
| 52 | #define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n))) |
| 53 | #define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n))) |
| 54 | |
| 55 | +#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n))) |
| 56 | +#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n))) |
| 57 | /* WFDMA COMMON */ |
| 58 | #define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR) |
| 59 | #define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR) |
| 60 | diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 61 | index c5e0472..41bd0ff 100644 |
developer | 711759c | 2022-09-21 18:38:10 +0800 | [diff] [blame] | 62 | --- a/mt7915/mtk_debugfs.c |
| 63 | +++ b/mt7915/mtk_debugfs.c |
| 64 | @@ -855,12 +855,22 @@ mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev) |
| 65 | "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| 66 | dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0)); |
| 67 | dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1)); |
| 68 | - dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2)); |
| 69 | - dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3)); |
| 70 | + |
| 71 | + if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 72 | + dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0)); |
| 73 | + dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1)); |
| 74 | + } else { |
| 75 | + dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2)); |
| 76 | + dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3)); |
| 77 | + } |
| 78 | + |
| 79 | dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4)); |
| 80 | dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0)); |
| 81 | dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1)); |
| 82 | - dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2)); |
| 83 | + if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) |
| 84 | + dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1)); |
| 85 | + else |
| 86 | + dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2)); |
| 87 | dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3)); |
| 88 | dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0)); |
| 89 | dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1)); |
| 90 | -- |
developer | 887da63 | 2022-10-28 09:35:38 +0800 | [diff] [blame] | 91 | 2.18.0 |
developer | 711759c | 2022-09-21 18:38:10 +0800 | [diff] [blame] | 92 | |