| developer | e0cea0f | 2021-12-16 16:08:26 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Author(s): |
| 4 | * laj |
| 5 | * |
| 6 | * Distributed by: |
| 7 | * Silicon Laboratories, Inc |
| 8 | * |
| 9 | * This file contains proprietary information. |
| 10 | * No dissemination allowed without prior written permission from |
| 11 | * Silicon Laboratories, Inc. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef SI3050REGS_H |
| 16 | #define SI3050REGS_H |
| 17 | |
| 18 | |
| 19 | enum REGISTERS |
| 20 | { |
| 21 | CTRL1 = 1, /* Control */ |
| 22 | CTRL2 = 2, /* Control */ |
| 23 | INTE_MSK = 3, /* Interrupt Mask */ |
| 24 | INTE_SRC = 4, /* Interrupt Source */ |
| 25 | DAA_CTRL1 = 5, /* DAA Control 1 */ |
| 26 | DAA_CTRL2 = 6, /* DAA Control 2 */ |
| 27 | SMPL_CTRL = 7, /* Sample Rate Control */ |
| 28 | RESVD8 = 8, /* Reserved */ |
| 29 | RESVD9 = 9, /* Reserved */ |
| 30 | DAA_CTRL3 = 10, /* DAA Control 3 */ |
| 31 | SYS_LINE_DEV_REV = 11, /* System- and Line-Side Device Revision */ |
| 32 | LSIDE_STAT = 12, /* Line-Side Device Status */ |
| 33 | LSIDE_REV = 13, /* Line-Side Device Revision */ |
| 34 | DAA_CTRL4 = 14, /* DAA Control 4 RPOL */ |
| 35 | TXRX_GN_CTRL = 15, /* TX/RX Gain Control 1 */ |
| 36 | INTL_CTRL1 = 16, /* International Control 1 */ |
| 37 | INTL_CTRL2 = 17, /* International Control 2 */ |
| 38 | INTL_CTRL3 = 18, /* International Control 3 */ |
| 39 | INTL_CTRL4 = 19, /* International Control 4 */ |
| 40 | RXCALL_PROG_ATTEN = 20, /* Call Progress RX Attenuation */ |
| 41 | TXCALL_PROG_ATTEN = 21, /* Call Progress TX Attenuation */ |
| 42 | RNG_VLD_CTRL1 = 22, /* Ring Validation Control 1 */ |
| 43 | RNG_VLD_CTRL2 = 23, /* Ring Validation Control 2 */ |
| 44 | RNG_VLD_CTRL3 = 24, /* ing Validation Control 3 */ |
| 45 | RES_CALIB = 25, /* Resistor Calibration */ |
| 46 | DC_TERM_CTRL = 26, /* DC Termination Control */ |
| 47 | RESVD27 = 27, /* Reserved */ |
| 48 | LP_CRNT_STAT = 28, /* Loop Current Status */ |
| 49 | LINE_VOLT_STAT = 29, /* Line Voltage Status */ |
| 50 | AC_TERM_CTRL = 30, /* AC Termination Control */ |
| 51 | DAA_CTRL5 = 31, /* DAA Control 5 */ |
| 52 | GND_STRT_CTRL = 32, /* Ground Start Control */ |
| 53 | PCM_SPI_CTRL = 33, /* PCM/SPI Mode Select */ |
| 54 | PCMTX_CNT_LO = 34, /* PCM Transmit Start Count - Low Byte */ |
| 55 | PCMTX_CNT_HI = 35, /* PCM Transmit Start Count - High Byte */ |
| 56 | PCMRX_CNT_LO = 36, /* PCM Receive Start Count - Low Byte */ |
| 57 | PCMRX_CNT_HI = 37, /* PCM Receive Start Count - High Byte */ |
| 58 | TX_GN_CTRL2 = 38, /* TX Gain Control 2 */ |
| 59 | RX_GN_CTRL2 = 39, /* RX Gain Control 2 */ |
| 60 | TX_GN_CTRL3 = 40, /* TX Gain Control 3 */ |
| 61 | RX_GN_CTRL3 = 41, /* RX Gain Control 3 */ |
| 62 | GCI_CTRL = 42, /* GCI Control */ |
| 63 | LN_VI_THRESH_INTE = 43, /* Line Current/Voltage Threshold Interrupt */ |
| 64 | LN_VI_THRESH_INTE_CTRL=44, /* Line Current/Voltage Threshold Interrupt Control */ |
| 65 | HYB1 = 45, /* Programmable Hybrid Register 1 */ |
| 66 | HYB2 = 46, /* Programmable Hybrid Register 2 */ |
| 67 | HYB3 = 47, /* Programmable Hybrid Register 3 */ |
| 68 | HYB4 = 48, /* Programmable Hybrid Register 4 */ |
| 69 | HYB5 = 49, /* Programmable Hybrid Register 5 */ |
| 70 | HYB6 = 50, /* Programmable Hybrid Register 6 */ |
| 71 | HYB7 = 51, /* Programmable Hybrid Register 7 */ |
| 72 | HYB8 = 52, /* Programmable Hybrid Register 8 */ |
| 73 | RESVD53 = 53, /* Reserved 53 */ |
| 74 | RESVD54 = 54, /* Reserved 54 */ |
| 75 | RESVD55 = 55, /* Reserved 55 */ |
| 76 | RESVD56 = 56, /* Reserved 56 */ |
| 77 | RESVD57 = 57, /* Reserved 57 */ |
| 78 | RESVD58 = 58, /* Reserved 58 */ |
| 79 | SPRK_QNCH_CTRL = 59 /* Spark Quenching Control */ |
| 80 | |
| 81 | }; |
| 82 | |
| 83 | #endif |
| 84 | |