developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From f001395855db2d04f499a2e2936f1d54dcaab225 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:24 +0800 |
| 4 | Subject: [PATCH] [high-speed-io][999-2601-pcie-add-multi-MSI-support.patch] |
| 5 | |
| 6 | --- |
| 7 | drivers/pci/controller/pcie-mediatek.c | 24 ++++++++++++------------ |
| 8 | 1 file changed, 12 insertions(+), 12 deletions(-) |
| 9 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 10 | diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 11 | index db3672917..44a046005 100644 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 12 | --- a/drivers/pci/controller/pcie-mediatek.c |
| 13 | +++ b/drivers/pci/controller/pcie-mediatek.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 14 | @@ -440,24 +440,24 @@ static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int vir |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 15 | unsigned int nr_irqs, void *args) |
| 16 | { |
| 17 | struct mtk_pcie_port *port = domain->host_data; |
| 18 | - unsigned long bit; |
| 19 | + int bit, i; |
| 20 | |
| 21 | - WARN_ON(nr_irqs != 1); |
| 22 | mutex_lock(&port->lock); |
| 23 | |
| 24 | - bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); |
| 25 | - if (bit >= MTK_MSI_IRQS_NUM) { |
| 26 | + bit = bitmap_find_free_region(port->msi_irq_in_use, MTK_MSI_IRQS_NUM, |
| 27 | + order_base_2(nr_irqs)); |
| 28 | + if (bit < 0) { |
| 29 | mutex_unlock(&port->lock); |
| 30 | return -ENOSPC; |
| 31 | } |
| 32 | |
| 33 | - __set_bit(bit, port->msi_irq_in_use); |
| 34 | - |
| 35 | mutex_unlock(&port->lock); |
| 36 | |
| 37 | - irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, |
| 38 | - domain->host_data, handle_edge_irq, |
| 39 | - NULL, NULL); |
| 40 | + for (i = 0; i < nr_irqs; i++) { |
| 41 | + irq_domain_set_info(domain, virq + i, bit + i, |
| 42 | + &mtk_msi_bottom_irq_chip, domain->host_data, |
| 43 | + handle_edge_irq, NULL, NULL); |
| 44 | + } |
| 45 | |
| 46 | return 0; |
| 47 | } |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 48 | @@ -495,7 +495,7 @@ static struct irq_chip mtk_msi_irq_chip = { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 49 | |
| 50 | static struct msi_domain_info mtk_msi_domain_info = { |
| 51 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
| 52 | - MSI_FLAG_PCI_MSIX), |
| 53 | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), |
| 54 | .chip = &mtk_msi_irq_chip, |
| 55 | }; |
| 56 | |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 57 | @@ -627,14 +627,14 @@ static void mtk_pcie_intr_handler(struct irq_desc *desc) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 58 | if (status & MSI_STATUS){ |
| 59 | unsigned long imsi_status; |
| 60 | |
| 61 | + /* Clear MSI interrupt status */ |
| 62 | + writel(MSI_STATUS, port->base + PCIE_INT_STATUS); |
| 63 | while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { |
| 64 | for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { |
| 65 | virq = irq_find_mapping(port->inner_domain, bit); |
| 66 | generic_handle_irq(virq); |
| 67 | } |
| 68 | } |
| 69 | - /* Clear MSI interrupt status */ |
| 70 | - writel(MSI_STATUS, port->base + PCIE_INT_STATUS); |
| 71 | } |
| 72 | } |
| 73 | |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 74 | -- |
| 75 | 2.34.1 |
| 76 | |