developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __MT76X02_MAC_H |
| 8 | #define __MT76X02_MAC_H |
| 9 | |
| 10 | struct mt76x02_dev; |
| 11 | |
| 12 | struct mt76x02_tx_status { |
| 13 | u8 valid:1; |
| 14 | u8 success:1; |
| 15 | u8 aggr:1; |
| 16 | u8 ack_req:1; |
| 17 | u8 wcid; |
| 18 | u8 pktid; |
| 19 | u8 retry; |
| 20 | u16 rate; |
| 21 | } __packed __aligned(2); |
| 22 | |
| 23 | #define MT_VIF_WCID(_n) (254 - ((_n) & 7)) |
| 24 | #define MT_MAX_VIFS 8 |
| 25 | |
| 26 | #define MT_PKTID_RATE GENMASK(4, 0) |
| 27 | #define MT_PKTID_AC GENMASK(6, 5) |
| 28 | |
| 29 | struct mt76x02_vif { |
| 30 | struct mt76_wcid group_wcid; /* must be first */ |
| 31 | u8 idx; |
| 32 | }; |
| 33 | |
| 34 | DECLARE_EWMA(pktlen, 8, 8); |
| 35 | |
| 36 | struct mt76x02_sta { |
| 37 | struct mt76_wcid wcid; /* must be first */ |
| 38 | |
| 39 | struct mt76x02_vif *vif; |
| 40 | struct mt76x02_tx_status status; |
| 41 | int n_frames; |
| 42 | |
| 43 | struct ewma_pktlen pktlen; |
| 44 | }; |
| 45 | |
| 46 | #define MT_RXINFO_BA BIT(0) |
| 47 | #define MT_RXINFO_DATA BIT(1) |
| 48 | #define MT_RXINFO_NULL BIT(2) |
| 49 | #define MT_RXINFO_FRAG BIT(3) |
| 50 | #define MT_RXINFO_UNICAST BIT(4) |
| 51 | #define MT_RXINFO_MULTICAST BIT(5) |
| 52 | #define MT_RXINFO_BROADCAST BIT(6) |
| 53 | #define MT_RXINFO_MYBSS BIT(7) |
| 54 | #define MT_RXINFO_CRCERR BIT(8) |
| 55 | #define MT_RXINFO_ICVERR BIT(9) |
| 56 | #define MT_RXINFO_MICERR BIT(10) |
| 57 | #define MT_RXINFO_AMSDU BIT(11) |
| 58 | #define MT_RXINFO_HTC BIT(12) |
| 59 | #define MT_RXINFO_RSSI BIT(13) |
| 60 | #define MT_RXINFO_L2PAD BIT(14) |
| 61 | #define MT_RXINFO_AMPDU BIT(15) |
| 62 | #define MT_RXINFO_DECRYPT BIT(16) |
| 63 | #define MT_RXINFO_BSSIDX3 BIT(17) |
| 64 | #define MT_RXINFO_WAPI_KEY BIT(18) |
| 65 | #define MT_RXINFO_PN_LEN GENMASK(21, 19) |
| 66 | #define MT_RXINFO_SW_FTYPE0 BIT(22) |
| 67 | #define MT_RXINFO_SW_FTYPE1 BIT(23) |
| 68 | #define MT_RXINFO_PROBE_RESP BIT(24) |
| 69 | #define MT_RXINFO_BEACON BIT(25) |
| 70 | #define MT_RXINFO_DISASSOC BIT(26) |
| 71 | #define MT_RXINFO_DEAUTH BIT(27) |
| 72 | #define MT_RXINFO_ACTION BIT(28) |
| 73 | #define MT_RXINFO_TCP_SUM_ERR BIT(30) |
| 74 | #define MT_RXINFO_IP_SUM_ERR BIT(31) |
| 75 | |
| 76 | #define MT_RXWI_CTL_WCID GENMASK(7, 0) |
| 77 | #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) |
| 78 | #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) |
| 79 | #define MT_RXWI_CTL_UDF GENMASK(15, 13) |
| 80 | #define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16) |
| 81 | #define MT_RXWI_CTL_EOF BIT(31) |
| 82 | |
| 83 | #define MT_RXWI_TID GENMASK(3, 0) |
| 84 | #define MT_RXWI_SN GENMASK(15, 4) |
| 85 | |
| 86 | #define MT_RXWI_RATE_INDEX GENMASK(5, 0) |
| 87 | #define MT_RXWI_RATE_LDPC BIT(6) |
| 88 | #define MT_RXWI_RATE_BW GENMASK(8, 7) |
| 89 | #define MT_RXWI_RATE_SGI BIT(9) |
| 90 | #define MT_RXWI_RATE_STBC BIT(10) |
| 91 | #define MT_RXWI_RATE_LDPC_EXSYM BIT(11) |
| 92 | #define MT_RXWI_RATE_PHY GENMASK(15, 13) |
| 93 | |
| 94 | #define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0) |
| 95 | #define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4) |
| 96 | |
| 97 | struct mt76x02_rxwi { |
| 98 | __le32 rxinfo; |
| 99 | |
| 100 | __le32 ctl; |
| 101 | |
| 102 | __le16 tid_sn; |
| 103 | __le16 rate; |
| 104 | |
| 105 | u8 rssi[4]; |
| 106 | |
| 107 | __le32 bbp_rxinfo[4]; |
| 108 | }; |
| 109 | |
| 110 | #define MT_TX_PWR_ADJ GENMASK(3, 0) |
| 111 | |
| 112 | enum mt76x2_phy_bandwidth { |
| 113 | MT_PHY_BW_20, |
| 114 | MT_PHY_BW_40, |
| 115 | MT_PHY_BW_80, |
| 116 | }; |
| 117 | |
| 118 | #define MT_TXWI_FLAGS_FRAG BIT(0) |
| 119 | #define MT_TXWI_FLAGS_MMPS BIT(1) |
| 120 | #define MT_TXWI_FLAGS_CFACK BIT(2) |
| 121 | #define MT_TXWI_FLAGS_TS BIT(3) |
| 122 | #define MT_TXWI_FLAGS_AMPDU BIT(4) |
| 123 | #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) |
| 124 | #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) |
| 125 | #define MT_TXWI_FLAGS_NDPS BIT(10) |
| 126 | #define MT_TXWI_FLAGS_RTSBWSIG BIT(11) |
| 127 | #define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12) |
| 128 | #define MT_TXWI_FLAGS_SOUND BIT(14) |
| 129 | #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) |
| 130 | |
| 131 | #define MT_TXWI_ACK_CTL_REQ BIT(0) |
| 132 | #define MT_TXWI_ACK_CTL_NSEQ BIT(1) |
| 133 | #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) |
| 134 | |
| 135 | struct mt76x02_txwi { |
| 136 | __le16 flags; |
| 137 | __le16 rate; |
| 138 | u8 ack_ctl; |
| 139 | u8 wcid; |
| 140 | __le16 len_ctl; |
| 141 | __le32 iv; |
| 142 | __le32 eiv; |
| 143 | u8 aid; |
| 144 | u8 txstream; |
| 145 | u8 ctl2; |
| 146 | u8 pktid; |
| 147 | } __packed __aligned(4); |
| 148 | |
| 149 | static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev) |
| 150 | { |
| 151 | const u32 MAC_CSR0 = 0x1000; |
| 152 | int i; |
| 153 | |
| 154 | for (i = 0; i < 500; i++) { |
| 155 | if (test_bit(MT76_REMOVED, &dev->phy.state)) |
| 156 | return false; |
| 157 | |
| 158 | switch (dev->bus->rr(dev, MAC_CSR0)) { |
| 159 | case 0: |
| 160 | case ~0: |
| 161 | break; |
| 162 | default: |
| 163 | return true; |
| 164 | } |
| 165 | usleep_range(5000, 10000); |
| 166 | } |
| 167 | return false; |
| 168 | } |
| 169 | |
| 170 | void mt76x02_mac_reset_counters(struct mt76x02_dev *dev); |
| 171 | void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable); |
| 172 | int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx, |
| 173 | u8 key_idx, struct ieee80211_key_conf *key); |
| 174 | int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx, |
| 175 | struct ieee80211_key_conf *key); |
| 176 | void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx, |
| 177 | struct ieee80211_key_conf *key); |
| 178 | void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx, |
| 179 | u8 *mac); |
| 180 | void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop); |
| 181 | void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid, |
| 182 | const struct ieee80211_tx_rate *rate); |
| 183 | bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev, |
| 184 | struct mt76x02_tx_status *stat); |
| 185 | void mt76x02_send_tx_status(struct mt76x02_dev *dev, |
| 186 | struct mt76x02_tx_status *stat, u8 *update); |
| 187 | int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, |
| 188 | void *rxi); |
| 189 | void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot, |
| 190 | int ht_mode); |
| 191 | void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val); |
| 192 | void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr); |
| 193 | void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi, |
| 194 | struct sk_buff *skb, struct mt76_wcid *wcid, |
| 195 | struct ieee80211_sta *sta, int len); |
| 196 | void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq); |
| 197 | void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e); |
| 198 | void mt76x02_update_channel(struct mt76_phy *mphy); |
| 199 | void mt76x02_mac_work(struct work_struct *work); |
| 200 | |
| 201 | void mt76x02_mac_cc_reset(struct mt76x02_dev *dev); |
| 202 | void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr); |
| 203 | void mt76x02_mac_set_beacon(struct mt76x02_dev *dev, struct sk_buff *skb); |
| 204 | void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev, |
| 205 | struct ieee80211_vif *vif, bool enable); |
| 206 | |
| 207 | void mt76x02_edcca_init(struct mt76x02_dev *dev); |
| 208 | #endif |