developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MT76_H |
| 7 | #define __MT76_H |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <linux/spinlock.h> |
| 12 | #include <linux/skbuff.h> |
| 13 | #include <linux/leds.h> |
| 14 | #include <linux/usb.h> |
| 15 | #include <linux/average.h> |
| 16 | #include <net/mac80211.h> |
| 17 | #include "util.h" |
| 18 | #include "testmode.h" |
| 19 | |
| 20 | #define MT_MCU_RING_SIZE 32 |
| 21 | #define MT_RX_BUF_SIZE 2048 |
| 22 | #define MT_SKB_HEAD_LEN 256 |
| 23 | |
| 24 | #define MT_MAX_NON_AQL_PKT 16 |
| 25 | #define MT_TXQ_FREE_THR 32 |
| 26 | |
| 27 | #define MT76_TOKEN_FREE_THR 64 |
| 28 | |
| 29 | struct mt76_dev; |
| 30 | struct mt76_phy; |
| 31 | struct mt76_wcid; |
| 32 | struct mt76s_intr; |
| 33 | |
| 34 | struct mt76_reg_pair { |
| 35 | u32 reg; |
| 36 | u32 value; |
| 37 | }; |
| 38 | |
| 39 | enum mt76_bus_type { |
| 40 | MT76_BUS_MMIO, |
| 41 | MT76_BUS_USB, |
| 42 | MT76_BUS_SDIO, |
| 43 | }; |
| 44 | |
| 45 | struct mt76_bus_ops { |
| 46 | u32 (*rr)(struct mt76_dev *dev, u32 offset); |
| 47 | void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); |
| 48 | u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); |
| 49 | void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, |
| 50 | int len); |
| 51 | void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, |
| 52 | int len); |
| 53 | int (*wr_rp)(struct mt76_dev *dev, u32 base, |
| 54 | const struct mt76_reg_pair *rp, int len); |
| 55 | int (*rd_rp)(struct mt76_dev *dev, u32 base, |
| 56 | struct mt76_reg_pair *rp, int len); |
| 57 | enum mt76_bus_type type; |
| 58 | }; |
| 59 | |
| 60 | #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) |
| 61 | #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) |
| 62 | #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) |
| 63 | |
| 64 | enum mt76_band_id { |
| 65 | MT_BAND0 = 0, |
| 66 | MT_BAND1, |
| 67 | MT_BAND2, |
| 68 | __MT_MAX_BAND, |
| 69 | }; |
| 70 | |
| 71 | enum mt76_phy_id { |
| 72 | MT_MAIN_PHY = 0, |
| 73 | MT_EXT_PHY, |
| 74 | MT_TRI_PHY, |
| 75 | __MT_MAX_PHY_ID, |
| 76 | }; |
| 77 | |
| 78 | enum mt76_txq_id { |
| 79 | MT_TXQ_VO = IEEE80211_AC_VO, |
| 80 | MT_TXQ_VI = IEEE80211_AC_VI, |
| 81 | MT_TXQ_BE = IEEE80211_AC_BE, |
| 82 | MT_TXQ_BK = IEEE80211_AC_BK, |
| 83 | MT_TXQ_PSD, |
| 84 | MT_TXQ_BEACON, |
| 85 | MT_TXQ_CAB, |
| 86 | __MT_TXQ_MAX |
| 87 | }; |
| 88 | |
| 89 | enum mt76_mcuq_id { |
| 90 | MT_MCUQ_WM, |
| 91 | MT_MCUQ_WA, |
| 92 | MT_MCUQ_FWDL, |
| 93 | __MT_MCUQ_MAX |
| 94 | }; |
| 95 | |
| 96 | enum mt76_rxq_id { |
| 97 | MT_RXQ_MAIN, |
| 98 | MT_RXQ_MCU, |
| 99 | MT_RXQ_MCU_WA, |
| 100 | MT_RXQ_EXT, |
| 101 | MT_RXQ_EXT_WA, |
| 102 | MT_RXQ_MAIN_WA, |
| 103 | MT_RXQ_TRI, |
| 104 | MT_RXQ_TRI_WA, |
| 105 | __MT_RXQ_MAX |
| 106 | }; |
| 107 | |
| 108 | enum mt76_cipher_type { |
| 109 | MT_CIPHER_NONE, |
| 110 | MT_CIPHER_WEP40, |
| 111 | MT_CIPHER_TKIP, |
| 112 | MT_CIPHER_TKIP_NO_MIC, |
| 113 | MT_CIPHER_AES_CCMP, |
| 114 | MT_CIPHER_WEP104, |
| 115 | MT_CIPHER_BIP_CMAC_128, |
| 116 | MT_CIPHER_WEP128, |
| 117 | MT_CIPHER_WAPI, |
| 118 | MT_CIPHER_CCMP_CCX, |
| 119 | MT_CIPHER_CCMP_256, |
| 120 | MT_CIPHER_GCMP, |
| 121 | MT_CIPHER_GCMP_256, |
| 122 | }; |
| 123 | |
| 124 | enum mt76_dfs_state { |
| 125 | MT_DFS_STATE_UNKNOWN, |
| 126 | MT_DFS_STATE_DISABLED, |
| 127 | MT_DFS_STATE_CAC, |
| 128 | MT_DFS_STATE_ACTIVE, |
| 129 | }; |
| 130 | |
| 131 | struct mt76_queue_buf { |
| 132 | dma_addr_t addr; |
| 133 | u16 len; |
| 134 | bool skip_unmap; |
| 135 | }; |
| 136 | |
| 137 | struct mt76_tx_info { |
| 138 | struct mt76_queue_buf buf[32]; |
| 139 | struct sk_buff *skb; |
| 140 | int nbuf; |
| 141 | u32 info; |
| 142 | }; |
| 143 | |
| 144 | struct mt76_queue_entry { |
| 145 | union { |
| 146 | void *buf; |
| 147 | struct sk_buff *skb; |
| 148 | }; |
| 149 | union { |
| 150 | struct mt76_txwi_cache *txwi; |
| 151 | struct urb *urb; |
| 152 | int buf_sz; |
| 153 | }; |
| 154 | u32 dma_addr[2]; |
| 155 | u16 dma_len[2]; |
| 156 | u16 wcid; |
| 157 | bool skip_buf0:1; |
| 158 | bool skip_buf1:1; |
| 159 | bool done:1; |
| 160 | }; |
| 161 | |
| 162 | struct mt76_queue_regs { |
| 163 | u32 desc_base; |
| 164 | u32 ring_size; |
| 165 | u32 cpu_idx; |
| 166 | u32 dma_idx; |
| 167 | } __packed __aligned(4); |
| 168 | |
| 169 | struct mt76_queue { |
| 170 | struct mt76_queue_regs __iomem *regs; |
| 171 | |
| 172 | spinlock_t lock; |
| 173 | spinlock_t cleanup_lock; |
| 174 | struct mt76_queue_entry *entry; |
| 175 | struct mt76_desc *desc; |
| 176 | |
| 177 | u16 first; |
| 178 | u16 head; |
| 179 | u16 tail; |
| 180 | int ndesc; |
| 181 | int queued; |
| 182 | int buf_size; |
| 183 | bool stopped; |
| 184 | bool blocked; |
| 185 | |
| 186 | u8 buf_offset; |
| 187 | u8 hw_idx; |
| 188 | u8 qid; |
| 189 | |
| 190 | dma_addr_t desc_dma; |
| 191 | struct sk_buff *rx_head; |
| 192 | struct page_frag_cache rx_page; |
| 193 | }; |
| 194 | |
| 195 | struct mt76_mcu_ops { |
| 196 | u32 headroom; |
| 197 | u32 tailroom; |
| 198 | |
| 199 | int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, |
| 200 | int len, bool wait_resp); |
| 201 | int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, |
| 202 | int cmd, int *seq); |
| 203 | int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, |
| 204 | struct sk_buff *skb, int seq); |
| 205 | u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); |
| 206 | void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); |
| 207 | int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, |
| 208 | const struct mt76_reg_pair *rp, int len); |
| 209 | int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, |
| 210 | struct mt76_reg_pair *rp, int len); |
| 211 | int (*mcu_restart)(struct mt76_dev *dev); |
| 212 | }; |
| 213 | |
| 214 | struct mt76_queue_ops { |
| 215 | int (*init)(struct mt76_dev *dev, |
| 216 | int (*poll)(struct napi_struct *napi, int budget)); |
| 217 | |
| 218 | int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, |
| 219 | int idx, int n_desc, int bufsize, |
| 220 | u32 ring_base); |
| 221 | |
| 222 | int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, |
| 223 | struct sk_buff *skb, struct mt76_wcid *wcid, |
| 224 | struct ieee80211_sta *sta); |
| 225 | |
| 226 | int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, |
| 227 | struct sk_buff *skb, u32 tx_info); |
| 228 | |
| 229 | void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, |
| 230 | int *len, u32 *info, bool *more); |
| 231 | |
| 232 | void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); |
| 233 | |
| 234 | void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, |
| 235 | bool flush); |
| 236 | |
| 237 | void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); |
| 238 | |
| 239 | void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); |
| 240 | |
| 241 | void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); |
| 242 | }; |
| 243 | |
| 244 | enum mt76_wcid_flags { |
| 245 | MT_WCID_FLAG_CHECK_PS, |
| 246 | MT_WCID_FLAG_PS, |
| 247 | MT_WCID_FLAG_4ADDR, |
| 248 | MT_WCID_FLAG_HDR_TRANS, |
| 249 | }; |
| 250 | |
| 251 | #define MT76_N_WCIDS 544 |
| 252 | |
| 253 | /* stored in ieee80211_tx_info::hw_queue */ |
| 254 | #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) |
| 255 | #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) |
| 256 | |
| 257 | DECLARE_EWMA(signal, 10, 8); |
| 258 | |
| 259 | #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) |
| 260 | #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) |
| 261 | #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) |
| 262 | #define MT_WCID_TX_INFO_SET BIT(31) |
| 263 | |
| 264 | struct mt76_wcid { |
| 265 | struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; |
| 266 | |
| 267 | atomic_t non_aql_packets; |
| 268 | unsigned long flags; |
| 269 | |
| 270 | struct ewma_signal rssi; |
| 271 | int inactive_count; |
| 272 | |
| 273 | struct rate_info rate; |
| 274 | |
| 275 | u16 idx; |
| 276 | u8 hw_key_idx; |
| 277 | u8 hw_key_idx2; |
| 278 | |
| 279 | u8 sta:1; |
| 280 | u8 phy_idx:2; |
| 281 | u8 amsdu:1; |
| 282 | |
| 283 | u8 rx_check_pn; |
| 284 | u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; |
| 285 | u16 cipher; |
| 286 | |
| 287 | u32 tx_info; |
| 288 | bool sw_iv; |
| 289 | |
| 290 | struct list_head list; |
| 291 | struct idr pktid; |
| 292 | }; |
| 293 | |
| 294 | struct mt76_txq { |
| 295 | u16 wcid; |
| 296 | |
| 297 | u16 agg_ssn; |
| 298 | bool send_bar; |
| 299 | bool aggr; |
| 300 | }; |
| 301 | |
| 302 | struct mt76_txwi_cache { |
| 303 | struct list_head list; |
| 304 | dma_addr_t dma_addr; |
| 305 | |
| 306 | struct sk_buff *skb; |
| 307 | }; |
| 308 | |
| 309 | struct mt76_rx_tid { |
| 310 | struct rcu_head rcu_head; |
| 311 | |
| 312 | struct mt76_dev *dev; |
| 313 | |
| 314 | spinlock_t lock; |
| 315 | struct delayed_work reorder_work; |
| 316 | |
| 317 | u16 head; |
| 318 | u16 size; |
| 319 | u16 nframes; |
| 320 | |
| 321 | u8 num; |
| 322 | |
| 323 | u8 started:1, stopped:1, timer_pending:1; |
| 324 | |
| 325 | struct sk_buff *reorder_buf[]; |
| 326 | }; |
| 327 | |
| 328 | #define MT_TX_CB_DMA_DONE BIT(0) |
| 329 | #define MT_TX_CB_TXS_DONE BIT(1) |
| 330 | #define MT_TX_CB_TXS_FAILED BIT(2) |
| 331 | |
| 332 | #define MT_PACKET_ID_MASK GENMASK(6, 0) |
| 333 | #define MT_PACKET_ID_NO_ACK 0 |
| 334 | #define MT_PACKET_ID_NO_SKB 1 |
| 335 | #define MT_PACKET_ID_FIRST 2 |
| 336 | #define MT_PACKET_ID_HAS_RATE BIT(7) |
| 337 | /* This is timer for when to give up when waiting for TXS callback, |
| 338 | * with starting time being the time at which the DMA_DONE callback |
| 339 | * was seen (so, we know packet was processed then, it should not take |
| 340 | * long after that for firmware to send the TXS callback if it is going |
| 341 | * to do so.) |
| 342 | */ |
| 343 | #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) |
| 344 | |
| 345 | struct mt76_tx_cb { |
| 346 | unsigned long jiffies; |
| 347 | u16 wcid; |
| 348 | u8 pktid; |
| 349 | u8 flags; |
| 350 | }; |
| 351 | |
| 352 | enum { |
| 353 | MT76_STATE_INITIALIZED, |
| 354 | MT76_STATE_RUNNING, |
| 355 | MT76_STATE_MCU_RUNNING, |
| 356 | MT76_SCANNING, |
| 357 | MT76_HW_SCANNING, |
| 358 | MT76_HW_SCHED_SCANNING, |
| 359 | MT76_RESTART, |
| 360 | MT76_RESET, |
| 361 | MT76_MCU_RESET, |
| 362 | MT76_REMOVED, |
| 363 | MT76_READING_STATS, |
| 364 | MT76_STATE_POWER_OFF, |
| 365 | MT76_STATE_SUSPEND, |
| 366 | MT76_STATE_ROC, |
| 367 | MT76_STATE_PM, |
| 368 | }; |
| 369 | |
| 370 | struct mt76_hw_cap { |
| 371 | bool has_2ghz; |
| 372 | bool has_5ghz; |
| 373 | bool has_6ghz; |
| 374 | }; |
| 375 | |
| 376 | #define MT_DRV_TXWI_NO_FREE BIT(0) |
| 377 | #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) |
| 378 | #define MT_DRV_SW_RX_AIRTIME BIT(2) |
| 379 | #define MT_DRV_RX_DMA_HDR BIT(3) |
| 380 | #define MT_DRV_HW_MGMT_TXQ BIT(4) |
| 381 | |
| 382 | struct mt76_driver_ops { |
| 383 | u32 drv_flags; |
| 384 | u32 survey_flags; |
| 385 | u16 txwi_size; |
| 386 | u16 token_size; |
| 387 | u8 mcs_rates; |
| 388 | |
| 389 | void (*update_survey)(struct mt76_phy *phy); |
| 390 | |
| 391 | int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, |
| 392 | enum mt76_txq_id qid, struct mt76_wcid *wcid, |
| 393 | struct ieee80211_sta *sta, |
| 394 | struct mt76_tx_info *tx_info); |
| 395 | |
| 396 | void (*tx_complete_skb)(struct mt76_dev *dev, |
| 397 | struct mt76_queue_entry *e); |
| 398 | |
| 399 | bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); |
| 400 | |
| 401 | bool (*rx_check)(struct mt76_dev *dev, enum mt76_rxq_id q, void *data, int len); |
| 402 | |
| 403 | void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, |
| 404 | struct sk_buff *skb); |
| 405 | |
| 406 | void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); |
| 407 | |
| 408 | void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, |
| 409 | bool ps); |
| 410 | |
| 411 | int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 412 | struct ieee80211_sta *sta); |
| 413 | |
| 414 | void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 415 | struct ieee80211_sta *sta); |
| 416 | |
| 417 | void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 418 | struct ieee80211_sta *sta); |
| 419 | }; |
| 420 | |
| 421 | struct mt76_channel_state { |
| 422 | u64 cc_active; |
| 423 | u64 cc_busy; |
| 424 | u64 cc_rx; |
| 425 | u64 cc_bss_rx; |
| 426 | u64 cc_tx; |
| 427 | |
| 428 | s8 noise; |
| 429 | }; |
| 430 | |
| 431 | struct mt76_sband { |
| 432 | struct ieee80211_supported_band sband; |
| 433 | struct mt76_channel_state *chan; |
| 434 | }; |
| 435 | |
| 436 | struct mt76_rate_power { |
| 437 | union { |
| 438 | struct { |
| 439 | s8 cck[4]; |
| 440 | s8 ofdm[8]; |
| 441 | s8 stbc[10]; |
| 442 | s8 ht[16]; |
| 443 | s8 vht[10]; |
| 444 | }; |
| 445 | s8 all[48]; |
| 446 | }; |
| 447 | }; |
| 448 | |
| 449 | /* addr req mask */ |
| 450 | #define MT_VEND_TYPE_EEPROM BIT(31) |
| 451 | #define MT_VEND_TYPE_CFG BIT(30) |
| 452 | #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) |
| 453 | |
| 454 | #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) |
| 455 | enum mt_vendor_req { |
| 456 | MT_VEND_DEV_MODE = 0x1, |
| 457 | MT_VEND_WRITE = 0x2, |
| 458 | MT_VEND_POWER_ON = 0x4, |
| 459 | MT_VEND_MULTI_WRITE = 0x6, |
| 460 | MT_VEND_MULTI_READ = 0x7, |
| 461 | MT_VEND_READ_EEPROM = 0x9, |
| 462 | MT_VEND_WRITE_FCE = 0x42, |
| 463 | MT_VEND_WRITE_CFG = 0x46, |
| 464 | MT_VEND_READ_CFG = 0x47, |
| 465 | MT_VEND_READ_EXT = 0x63, |
| 466 | MT_VEND_WRITE_EXT = 0x66, |
| 467 | MT_VEND_FEATURE_SET = 0x91, |
| 468 | }; |
| 469 | |
| 470 | enum mt76u_in_ep { |
| 471 | MT_EP_IN_PKT_RX, |
| 472 | MT_EP_IN_CMD_RESP, |
| 473 | __MT_EP_IN_MAX, |
| 474 | }; |
| 475 | |
| 476 | enum mt76u_out_ep { |
| 477 | MT_EP_OUT_INBAND_CMD, |
| 478 | MT_EP_OUT_AC_BE, |
| 479 | MT_EP_OUT_AC_BK, |
| 480 | MT_EP_OUT_AC_VI, |
| 481 | MT_EP_OUT_AC_VO, |
| 482 | MT_EP_OUT_HCCA, |
| 483 | __MT_EP_OUT_MAX, |
| 484 | }; |
| 485 | |
| 486 | struct mt76_mcu { |
| 487 | struct mutex mutex; |
| 488 | u32 msg_seq; |
| 489 | int timeout; |
| 490 | |
| 491 | struct sk_buff_head res_q; |
| 492 | wait_queue_head_t wait; |
| 493 | }; |
| 494 | |
| 495 | #define MT_TX_SG_MAX_SIZE 8 |
| 496 | #define MT_RX_SG_MAX_SIZE 4 |
| 497 | #define MT_NUM_TX_ENTRIES 256 |
| 498 | #define MT_NUM_RX_ENTRIES 128 |
| 499 | #define MCU_RESP_URB_SIZE 1024 |
| 500 | struct mt76_usb { |
| 501 | struct mutex usb_ctrl_mtx; |
| 502 | u8 *data; |
| 503 | u16 data_len; |
| 504 | |
| 505 | struct mt76_worker status_worker; |
| 506 | struct mt76_worker rx_worker; |
| 507 | |
| 508 | struct work_struct stat_work; |
| 509 | |
| 510 | u8 out_ep[__MT_EP_OUT_MAX]; |
| 511 | u8 in_ep[__MT_EP_IN_MAX]; |
| 512 | bool sg_en; |
| 513 | |
| 514 | struct mt76u_mcu { |
| 515 | u8 *data; |
| 516 | /* multiple reads */ |
| 517 | struct mt76_reg_pair *rp; |
| 518 | int rp_len; |
| 519 | u32 base; |
| 520 | bool burst; |
| 521 | } mcu; |
| 522 | }; |
| 523 | |
| 524 | #define MT76S_XMIT_BUF_SZ 0x3fe00 |
| 525 | #define MT76S_NUM_TX_ENTRIES 256 |
| 526 | #define MT76S_NUM_RX_ENTRIES 512 |
| 527 | struct mt76_sdio { |
| 528 | struct mt76_worker txrx_worker; |
| 529 | struct mt76_worker status_worker; |
| 530 | struct mt76_worker net_worker; |
| 531 | |
| 532 | struct work_struct stat_work; |
| 533 | |
| 534 | u8 *xmit_buf; |
| 535 | u32 xmit_buf_sz; |
| 536 | |
| 537 | struct sdio_func *func; |
| 538 | void *intr_data; |
| 539 | u8 hw_ver; |
| 540 | wait_queue_head_t wait; |
| 541 | |
| 542 | struct { |
| 543 | int pse_data_quota; |
| 544 | int ple_data_quota; |
| 545 | int pse_mcu_quota; |
| 546 | int pse_page_size; |
| 547 | int deficit; |
| 548 | } sched; |
| 549 | |
| 550 | int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); |
| 551 | }; |
| 552 | |
| 553 | struct mt76_mmio { |
| 554 | void __iomem *regs; |
| 555 | spinlock_t irq_lock; |
| 556 | u32 irqmask; |
| 557 | }; |
| 558 | |
| 559 | struct mt76_rx_status { |
| 560 | union { |
| 561 | struct mt76_wcid *wcid; |
| 562 | u16 wcid_idx; |
| 563 | }; |
| 564 | |
| 565 | u32 reorder_time; |
| 566 | |
| 567 | u32 ampdu_ref; |
| 568 | u32 timestamp; |
| 569 | |
| 570 | u8 iv[6]; |
| 571 | |
| 572 | u8 phy_idx:2; |
| 573 | u8 aggr:1; |
| 574 | u8 qos_ctl; |
| 575 | u16 seqno; |
| 576 | |
| 577 | u16 freq; |
| 578 | u32 flag; |
| 579 | u8 enc_flags; |
| 580 | u8 encoding:2, bw:3, he_ru:3; |
| 581 | u8 he_gi:2, he_dcm:1; |
| 582 | u8 amsdu:1, first_amsdu:1, last_amsdu:1; |
| 583 | u8 rate_idx; |
| 584 | u8 nss; |
| 585 | u8 band; |
| 586 | s8 signal; |
| 587 | u8 chains; |
| 588 | s8 chain_signal[IEEE80211_MAX_CHAINS]; |
| 589 | }; |
| 590 | |
| 591 | struct mt76_freq_range_power { |
| 592 | const struct cfg80211_sar_freq_ranges *range; |
| 593 | s8 power; |
| 594 | }; |
| 595 | |
| 596 | struct mt76_testmode_ops { |
| 597 | int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); |
| 598 | int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, |
| 599 | enum mt76_testmode_state new_state); |
| 600 | int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); |
| 601 | }; |
| 602 | |
| 603 | struct mt76_testmode_data { |
| 604 | enum mt76_testmode_state state; |
| 605 | |
| 606 | u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; |
| 607 | struct sk_buff *tx_skb; |
| 608 | |
| 609 | u32 tx_count; |
| 610 | u16 tx_mpdu_len; |
| 611 | |
| 612 | u8 tx_rate_mode; |
| 613 | u8 tx_rate_idx; |
| 614 | u8 tx_rate_nss; |
| 615 | u8 tx_rate_sgi; |
| 616 | u8 tx_rate_ldpc; |
| 617 | u8 tx_rate_stbc; |
| 618 | u8 tx_ltf; |
| 619 | |
| 620 | u8 tx_antenna_mask; |
| 621 | u8 tx_spe_idx; |
| 622 | |
| 623 | u8 tx_duty_cycle; |
| 624 | u32 tx_time; |
| 625 | u32 tx_ipg; |
| 626 | |
| 627 | u32 freq_offset; |
| 628 | |
| 629 | u8 tx_power[4]; |
| 630 | u8 tx_power_control; |
| 631 | |
| 632 | u8 addr[3][ETH_ALEN]; |
| 633 | |
| 634 | u32 tx_pending; |
| 635 | u32 tx_queued; |
| 636 | u16 tx_queued_limit; |
| 637 | u32 tx_done; |
| 638 | struct { |
| 639 | u64 packets[__MT_RXQ_MAX]; |
| 640 | u64 fcs_error[__MT_RXQ_MAX]; |
| 641 | } rx_stats; |
| 642 | }; |
| 643 | |
| 644 | struct mt76_vif { |
| 645 | u8 idx; |
| 646 | u8 omac_idx; |
| 647 | u8 band_idx; |
| 648 | u8 wmm_idx; |
| 649 | u8 scan_seq_num; |
| 650 | u8 cipher; |
| 651 | }; |
| 652 | |
| 653 | struct mt76_phy { |
| 654 | struct ieee80211_hw *hw; |
| 655 | struct mt76_dev *dev; |
| 656 | void *priv; |
| 657 | |
| 658 | unsigned long state; |
| 659 | |
| 660 | struct mt76_queue *q_tx[__MT_TXQ_MAX]; |
| 661 | |
| 662 | struct cfg80211_chan_def chandef; |
| 663 | struct ieee80211_channel *main_chan; |
| 664 | |
| 665 | struct mt76_channel_state *chan_state; |
| 666 | enum mt76_dfs_state dfs_state; |
| 667 | ktime_t survey_time; |
| 668 | |
| 669 | struct mt76_hw_cap cap; |
| 670 | struct mt76_sband sband_2g; |
| 671 | struct mt76_sband sband_5g; |
| 672 | struct mt76_sband sband_6g; |
| 673 | u8 band_idx; |
| 674 | |
| 675 | u8 macaddr[ETH_ALEN]; |
| 676 | |
| 677 | int txpower_cur; |
| 678 | u8 antenna_mask; |
| 679 | u32 chainmask; |
| 680 | |
| 681 | #ifdef CONFIG_NL80211_TESTMODE |
| 682 | struct mt76_testmode_data test; |
| 683 | #endif |
| 684 | |
| 685 | struct delayed_work mac_work; |
| 686 | u8 mac_work_count; |
| 687 | |
| 688 | struct { |
| 689 | struct sk_buff *head; |
| 690 | struct sk_buff **tail; |
| 691 | u16 seqno; |
| 692 | } rx_amsdu[__MT_RXQ_MAX]; |
| 693 | |
| 694 | struct mt76_freq_range_power *frp; |
| 695 | }; |
| 696 | |
| 697 | struct mt76_dev { |
| 698 | struct mt76_phy phy; /* must be first */ |
| 699 | |
| 700 | struct mt76_phy *phy2; |
| 701 | struct mt76_phy *phy3; |
| 702 | |
| 703 | struct ieee80211_hw *hw; |
| 704 | |
| 705 | spinlock_t lock; |
| 706 | spinlock_t cc_lock; |
| 707 | |
| 708 | u32 cur_cc_bss_rx; |
| 709 | |
| 710 | struct mt76_rx_status rx_ampdu_status; |
| 711 | u32 rx_ampdu_len; |
| 712 | u32 rx_ampdu_ref; |
| 713 | |
| 714 | struct mutex mutex; |
| 715 | |
| 716 | const struct mt76_bus_ops *bus; |
| 717 | const struct mt76_driver_ops *drv; |
| 718 | const struct mt76_mcu_ops *mcu_ops; |
| 719 | struct device *dev; |
| 720 | |
| 721 | struct mt76_mcu mcu; |
| 722 | |
| 723 | struct net_device napi_dev; |
| 724 | struct net_device tx_napi_dev; |
| 725 | spinlock_t rx_lock; |
| 726 | struct napi_struct napi[__MT_RXQ_MAX]; |
| 727 | struct sk_buff_head rx_skb[__MT_RXQ_MAX]; |
| 728 | |
| 729 | struct list_head txwi_cache; |
| 730 | struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; |
| 731 | struct mt76_queue q_rx[__MT_RXQ_MAX]; |
| 732 | const struct mt76_queue_ops *queue_ops; |
| 733 | int tx_dma_idx[4]; |
| 734 | |
| 735 | struct mt76_worker tx_worker; |
| 736 | struct napi_struct tx_napi; |
| 737 | |
| 738 | spinlock_t token_lock; |
| 739 | struct idr token; |
| 740 | int token_count; |
| 741 | |
| 742 | wait_queue_head_t tx_wait; |
| 743 | /* spinclock used to protect wcid pktid linked list */ |
| 744 | spinlock_t status_lock; |
| 745 | |
| 746 | u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; |
| 747 | u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; |
| 748 | u32 wcid_phy3_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; |
| 749 | |
| 750 | u64 vif_mask; |
| 751 | |
| 752 | struct mt76_wcid global_wcid; |
| 753 | struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; |
| 754 | struct list_head wcid_list; |
| 755 | |
| 756 | u32 rev; |
| 757 | |
| 758 | u32 aggr_stats[32]; |
| 759 | |
| 760 | struct tasklet_struct pre_tbtt_tasklet; |
| 761 | int beacon_int; |
| 762 | u8 beacon_mask; |
| 763 | |
| 764 | struct debugfs_blob_wrapper eeprom; |
| 765 | struct debugfs_blob_wrapper otp; |
| 766 | |
| 767 | struct mt76_rate_power rate_power; |
| 768 | |
| 769 | char alpha2[3]; |
| 770 | enum nl80211_dfs_regions region; |
| 771 | |
| 772 | u32 debugfs_reg; |
| 773 | |
| 774 | struct led_classdev led_cdev; |
| 775 | char led_name[32]; |
| 776 | bool led_al; |
| 777 | u8 led_pin; |
| 778 | |
| 779 | u8 csa_complete; |
| 780 | |
| 781 | u32 rxfilter; |
| 782 | |
| 783 | #ifdef CONFIG_NL80211_TESTMODE |
| 784 | const struct mt76_testmode_ops *test_ops; |
| 785 | struct { |
| 786 | const char *name; |
| 787 | u32 offset; |
| 788 | } test_mtd; |
| 789 | #endif |
| 790 | struct workqueue_struct *wq; |
| 791 | |
| 792 | union { |
| 793 | struct mt76_mmio mmio; |
| 794 | struct mt76_usb usb; |
| 795 | struct mt76_sdio sdio; |
| 796 | }; |
| 797 | }; |
| 798 | |
| 799 | struct mt76_power_limits { |
| 800 | s8 cck[4]; |
| 801 | s8 ofdm[8]; |
| 802 | s8 mcs[4][10]; |
| 803 | s8 ru[7][12]; |
| 804 | }; |
| 805 | |
| 806 | enum mt76_phy_type { |
| 807 | MT_PHY_TYPE_CCK, |
| 808 | MT_PHY_TYPE_OFDM, |
| 809 | MT_PHY_TYPE_HT, |
| 810 | MT_PHY_TYPE_HT_GF, |
| 811 | MT_PHY_TYPE_VHT, |
| 812 | MT_PHY_TYPE_HE_SU = 8, |
| 813 | MT_PHY_TYPE_HE_EXT_SU, |
| 814 | MT_PHY_TYPE_HE_TB, |
| 815 | MT_PHY_TYPE_HE_MU, |
| 816 | __MT_PHY_TYPE_HE_MAX, |
| 817 | }; |
| 818 | |
| 819 | struct mt76_sta_stats { |
| 820 | u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; |
| 821 | u64 tx_bw[4]; /* 20, 40, 80, 160 */ |
| 822 | u64 tx_nss[4]; /* 1, 2, 3, 4 */ |
| 823 | u64 tx_mcs[16]; /* mcs idx */ |
| 824 | }; |
| 825 | |
| 826 | struct mt76_ethtool_worker_info { |
| 827 | u64 *data; |
| 828 | int idx; |
| 829 | int initial_stat_idx; |
| 830 | int worker_stat_count; |
| 831 | int sta_count; |
| 832 | }; |
| 833 | |
| 834 | #define CCK_RATE(_idx, _rate) { \ |
| 835 | .bitrate = _rate, \ |
| 836 | .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ |
| 837 | .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ |
| 838 | .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ |
| 839 | } |
| 840 | |
| 841 | #define OFDM_RATE(_idx, _rate) { \ |
| 842 | .bitrate = _rate, \ |
| 843 | .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ |
| 844 | .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ |
| 845 | } |
| 846 | |
| 847 | extern struct ieee80211_rate mt76_rates[12]; |
| 848 | |
| 849 | #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) |
| 850 | #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) |
| 851 | #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) |
| 852 | #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) |
| 853 | #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) |
| 854 | |
| 855 | #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) |
| 856 | #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) |
| 857 | |
| 858 | #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) |
| 859 | #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) |
| 860 | #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) |
| 861 | #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) |
| 862 | #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) |
| 863 | #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) |
| 864 | #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) |
| 865 | |
| 866 | |
| 867 | #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) |
| 868 | #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) |
| 869 | |
| 870 | #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) |
| 871 | #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) |
| 872 | |
| 873 | #define mt76_get_field(_dev, _reg, _field) \ |
| 874 | FIELD_GET(_field, mt76_rr(dev, _reg)) |
| 875 | |
| 876 | #define mt76_rmw_field(_dev, _reg, _field, _val) \ |
| 877 | mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) |
| 878 | |
| 879 | #define __mt76_rmw_field(_dev, _reg, _field, _val) \ |
| 880 | __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) |
| 881 | |
| 882 | #define mt76_hw(dev) (dev)->mphy.hw |
| 883 | |
| 884 | static inline struct ieee80211_hw * |
| 885 | mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) |
| 886 | { |
| 887 | if (wcid <= MT76_N_WCIDS && |
| 888 | mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) |
| 889 | return dev->phy2->hw; |
| 890 | |
| 891 | if (wcid <= MT76_N_WCIDS && |
| 892 | mt76_wcid_mask_test(dev->wcid_phy3_mask, wcid)) |
| 893 | return dev->phy3->hw; |
| 894 | |
| 895 | return dev->phy.hw; |
| 896 | } |
| 897 | |
| 898 | bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, |
| 899 | int timeout); |
| 900 | |
| 901 | #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) |
| 902 | |
| 903 | bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, |
| 904 | int timeout); |
| 905 | |
| 906 | #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) |
| 907 | |
| 908 | void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); |
| 909 | void mt76_pci_disable_aspm(struct pci_dev *pdev); |
| 910 | |
| 911 | static inline u16 mt76_chip(struct mt76_dev *dev) |
| 912 | { |
| 913 | return dev->rev >> 16; |
| 914 | } |
| 915 | |
| 916 | static inline u16 mt76_rev(struct mt76_dev *dev) |
| 917 | { |
| 918 | return dev->rev & 0xffff; |
| 919 | } |
| 920 | |
| 921 | static inline u8 mt76_get_phy_id(struct mt76_phy *phy) |
| 922 | { |
| 923 | if (phy == &phy->dev->phy) |
| 924 | return MT_MAIN_PHY; |
| 925 | |
| 926 | if (phy == phy->dev->phy2) |
| 927 | return MT_EXT_PHY; |
| 928 | |
| 929 | return MT_TRI_PHY; |
| 930 | } |
| 931 | |
| 932 | #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) |
| 933 | #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) |
| 934 | |
| 935 | #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) |
| 936 | #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) |
| 937 | #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) |
| 938 | #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) |
| 939 | #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) |
| 940 | #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) |
| 941 | #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) |
| 942 | #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) |
| 943 | #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) |
| 944 | |
| 945 | #define mt76_for_each_q_rx(dev, i) \ |
| 946 | for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ |
| 947 | if ((dev)->q_rx[i].ndesc) |
| 948 | |
| 949 | struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, |
| 950 | const struct ieee80211_ops *ops, |
| 951 | const struct mt76_driver_ops *drv_ops); |
| 952 | int mt76_register_device(struct mt76_dev *dev, bool vht, |
| 953 | struct ieee80211_rate *rates, int n_rates); |
| 954 | void mt76_unregister_device(struct mt76_dev *dev); |
| 955 | void mt76_free_device(struct mt76_dev *dev); |
| 956 | void mt76_unregister_phy(struct mt76_phy *phy); |
| 957 | |
| 958 | struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, |
| 959 | const struct ieee80211_ops *ops, u8 idx); |
| 960 | int mt76_register_phy(struct mt76_phy *phy, bool vht, |
| 961 | struct ieee80211_rate *rates, int n_rates); |
| 962 | |
| 963 | struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, |
| 964 | const struct file_operations *ops); |
| 965 | static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) |
| 966 | { |
| 967 | return mt76_register_debugfs_fops(&dev->phy, NULL); |
| 968 | } |
| 969 | |
| 970 | int mt76_queues_read(struct seq_file *s, void *data); |
| 971 | void mt76_seq_puts_array(struct seq_file *file, const char *str, |
| 972 | s8 *val, int len); |
| 973 | |
| 974 | int mt76_eeprom_init(struct mt76_dev *dev, int len); |
| 975 | void mt76_eeprom_override(struct mt76_phy *phy); |
| 976 | int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); |
| 977 | |
| 978 | struct mt76_queue * |
| 979 | mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, |
| 980 | int ring_base); |
| 981 | u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); |
| 982 | static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, |
| 983 | int n_desc, int ring_base) |
| 984 | { |
| 985 | struct mt76_queue *q; |
| 986 | |
| 987 | q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); |
| 988 | if (IS_ERR(q)) |
| 989 | return PTR_ERR(q); |
| 990 | |
| 991 | q->qid = qid; |
| 992 | phy->q_tx[qid] = q; |
| 993 | |
| 994 | return 0; |
| 995 | } |
| 996 | |
| 997 | static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, |
| 998 | int n_desc, int ring_base) |
| 999 | { |
| 1000 | struct mt76_queue *q; |
| 1001 | |
| 1002 | q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); |
| 1003 | if (IS_ERR(q)) |
| 1004 | return PTR_ERR(q); |
| 1005 | |
| 1006 | q->qid = __MT_TXQ_MAX + qid; |
| 1007 | dev->q_mcu[qid] = q; |
| 1008 | |
| 1009 | return 0; |
| 1010 | } |
| 1011 | |
| 1012 | static inline struct mt76_phy * |
| 1013 | mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) |
| 1014 | { |
| 1015 | if ((phy_idx == MT_EXT_PHY) && dev->phy2) |
| 1016 | return dev->phy2; |
| 1017 | |
| 1018 | if ((phy_idx == MT_TRI_PHY) && dev->phy3) |
| 1019 | return dev->phy3; |
| 1020 | |
| 1021 | return &dev->phy; |
| 1022 | } |
| 1023 | |
| 1024 | static inline struct ieee80211_hw * |
| 1025 | mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) |
| 1026 | { |
| 1027 | return mt76_dev_phy(dev, phy_idx)->hw; |
| 1028 | } |
| 1029 | |
| 1030 | static inline struct mt76_phy * |
| 1031 | mt76_dev_phy_by_band(struct mt76_dev *dev, u8 band_idx) |
| 1032 | { |
| 1033 | if (dev->phy3 && band_idx == dev->phy3->band_idx) |
| 1034 | return dev->phy3; |
| 1035 | |
| 1036 | if (dev->phy2 && band_idx == dev->phy2->band_idx) |
| 1037 | return dev->phy2; |
| 1038 | |
| 1039 | return &dev->phy; |
| 1040 | } |
| 1041 | |
| 1042 | static inline u8 * |
| 1043 | mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) |
| 1044 | { |
| 1045 | return (u8 *)t - dev->drv->txwi_size; |
| 1046 | } |
| 1047 | |
| 1048 | /* increment with wrap-around */ |
| 1049 | static inline int mt76_incr(int val, int size) |
| 1050 | { |
| 1051 | return (val + 1) & (size - 1); |
| 1052 | } |
| 1053 | |
| 1054 | /* decrement with wrap-around */ |
| 1055 | static inline int mt76_decr(int val, int size) |
| 1056 | { |
| 1057 | return (val - 1) & (size - 1); |
| 1058 | } |
| 1059 | |
| 1060 | u8 mt76_ac_to_hwq(u8 ac); |
| 1061 | |
| 1062 | static inline struct ieee80211_txq * |
| 1063 | mtxq_to_txq(struct mt76_txq *mtxq) |
| 1064 | { |
| 1065 | void *ptr = mtxq; |
| 1066 | |
| 1067 | return container_of(ptr, struct ieee80211_txq, drv_priv); |
| 1068 | } |
| 1069 | |
| 1070 | static inline struct ieee80211_sta * |
| 1071 | wcid_to_sta(struct mt76_wcid *wcid) |
| 1072 | { |
| 1073 | void *ptr = wcid; |
| 1074 | |
| 1075 | if (!wcid || !wcid->sta) |
| 1076 | return NULL; |
| 1077 | |
| 1078 | return container_of(ptr, struct ieee80211_sta, drv_priv); |
| 1079 | } |
| 1080 | |
| 1081 | static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) |
| 1082 | { |
| 1083 | BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > |
| 1084 | sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); |
| 1085 | return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); |
| 1086 | } |
| 1087 | |
| 1088 | static inline void *mt76_skb_get_hdr(struct sk_buff *skb) |
| 1089 | { |
| 1090 | struct mt76_rx_status mstat; |
| 1091 | u8 *data = skb->data; |
| 1092 | |
| 1093 | /* Alignment concerns */ |
| 1094 | BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); |
| 1095 | BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); |
| 1096 | |
| 1097 | mstat = *((struct mt76_rx_status *)skb->cb); |
| 1098 | |
| 1099 | if (mstat.flag & RX_FLAG_RADIOTAP_HE) |
| 1100 | data += sizeof(struct ieee80211_radiotap_he); |
| 1101 | if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) |
| 1102 | data += sizeof(struct ieee80211_radiotap_he_mu); |
| 1103 | |
| 1104 | return data; |
| 1105 | } |
| 1106 | |
| 1107 | static inline void mt76_insert_hdr_pad(struct sk_buff *skb) |
| 1108 | { |
| 1109 | int len = ieee80211_get_hdrlen_from_skb(skb); |
| 1110 | |
| 1111 | if (len % 4 == 0) |
| 1112 | return; |
| 1113 | |
| 1114 | skb_push(skb, 2); |
| 1115 | memmove(skb->data, skb->data + 2, len); |
| 1116 | |
| 1117 | skb->data[len] = 0; |
| 1118 | skb->data[len + 1] = 0; |
| 1119 | } |
| 1120 | |
| 1121 | static inline bool mt76_is_skb_pktid(u8 pktid) |
| 1122 | { |
| 1123 | if (pktid & MT_PACKET_ID_HAS_RATE) |
| 1124 | return false; |
| 1125 | |
| 1126 | return pktid >= MT_PACKET_ID_FIRST; |
| 1127 | } |
| 1128 | |
| 1129 | static inline u8 mt76_tx_power_nss_delta(u8 nss) |
| 1130 | { |
| 1131 | static const u8 nss_delta[4] = { 0, 6, 9, 12 }; |
| 1132 | |
| 1133 | return nss_delta[nss - 1]; |
| 1134 | } |
| 1135 | |
| 1136 | static inline bool mt76_testmode_enabled(struct mt76_phy *phy) |
| 1137 | { |
| 1138 | #ifdef CONFIG_NL80211_TESTMODE |
| 1139 | return phy->test.state != MT76_TM_STATE_OFF; |
| 1140 | #else |
| 1141 | return false; |
| 1142 | #endif |
| 1143 | } |
| 1144 | |
| 1145 | static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, |
| 1146 | struct sk_buff *skb, |
| 1147 | struct ieee80211_hw **hw) |
| 1148 | { |
| 1149 | #ifdef CONFIG_NL80211_TESTMODE |
| 1150 | if (skb == dev->phy.test.tx_skb) |
| 1151 | *hw = dev->phy.hw; |
| 1152 | else if (dev->phy2 && skb == dev->phy2->test.tx_skb) |
| 1153 | *hw = dev->phy2->hw; |
| 1154 | else if (dev->phy3 && skb == dev->phy3->test.tx_skb) |
| 1155 | *hw = dev->phy3->hw; |
| 1156 | else |
| 1157 | return false; |
| 1158 | return true; |
| 1159 | #else |
| 1160 | return false; |
| 1161 | #endif |
| 1162 | } |
| 1163 | |
| 1164 | void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); |
| 1165 | void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, |
| 1166 | struct mt76_wcid *wcid, struct sk_buff *skb); |
| 1167 | void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); |
| 1168 | void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, |
| 1169 | bool send_bar); |
| 1170 | void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); |
| 1171 | void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); |
| 1172 | void mt76_txq_schedule_all(struct mt76_phy *phy); |
| 1173 | void mt76_tx_worker_run(struct mt76_dev *dev); |
| 1174 | void mt76_tx_worker(struct mt76_worker *w); |
| 1175 | void mt76_release_buffered_frames(struct ieee80211_hw *hw, |
| 1176 | struct ieee80211_sta *sta, |
| 1177 | u16 tids, int nframes, |
| 1178 | enum ieee80211_frame_release_type reason, |
| 1179 | bool more_data); |
| 1180 | bool mt76_has_tx_pending(struct mt76_phy *phy); |
| 1181 | void mt76_set_channel(struct mt76_phy *phy); |
| 1182 | void mt76_update_survey(struct mt76_phy *phy); |
| 1183 | void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); |
| 1184 | int mt76_get_survey(struct ieee80211_hw *hw, int idx, |
| 1185 | struct survey_info *survey); |
| 1186 | void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); |
| 1187 | |
| 1188 | int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, |
| 1189 | u16 ssn, u16 size); |
| 1190 | void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); |
| 1191 | |
| 1192 | void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, |
| 1193 | struct ieee80211_key_conf *key); |
| 1194 | |
| 1195 | void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) |
| 1196 | __acquires(&dev->status_lock); |
| 1197 | void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) |
| 1198 | __releases(&dev->status_lock); |
| 1199 | |
| 1200 | int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, |
| 1201 | struct sk_buff *skb); |
| 1202 | struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, |
| 1203 | struct mt76_wcid *wcid, int pktid, |
| 1204 | struct sk_buff_head *list); |
| 1205 | void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, |
| 1206 | struct sk_buff_head *list); |
| 1207 | void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, |
| 1208 | struct list_head *free_list); |
| 1209 | static inline void |
| 1210 | mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) |
| 1211 | { |
| 1212 | __mt76_tx_complete_skb(dev, wcid, skb, NULL); |
| 1213 | } |
| 1214 | |
| 1215 | void mt76_tx_status_check(struct mt76_dev *dev, bool flush); |
| 1216 | int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1217 | struct ieee80211_sta *sta, |
| 1218 | enum ieee80211_sta_state old_state, |
| 1219 | enum ieee80211_sta_state new_state); |
| 1220 | void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, |
| 1221 | struct ieee80211_sta *sta); |
| 1222 | void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1223 | struct ieee80211_sta *sta); |
| 1224 | |
| 1225 | int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 band); |
| 1226 | |
| 1227 | int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1228 | int *dbm); |
| 1229 | int mt76_init_sar_power(struct ieee80211_hw *hw, |
| 1230 | const struct cfg80211_sar_specs *sar); |
| 1231 | int mt76_get_sar_power(struct mt76_phy *phy, |
| 1232 | struct ieee80211_channel *chan, |
| 1233 | int power); |
| 1234 | |
| 1235 | void mt76_csa_check(struct mt76_dev *dev); |
| 1236 | void mt76_csa_finish(struct mt76_dev *dev); |
| 1237 | |
| 1238 | int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); |
| 1239 | int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); |
| 1240 | void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); |
| 1241 | int mt76_get_rate(struct mt76_dev *dev, |
| 1242 | struct ieee80211_supported_band *sband, |
| 1243 | int idx, bool cck); |
| 1244 | void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1245 | const u8 *mac); |
| 1246 | void mt76_sw_scan_complete(struct ieee80211_hw *hw, |
| 1247 | struct ieee80211_vif *vif); |
| 1248 | enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); |
| 1249 | int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1250 | void *data, int len); |
| 1251 | int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, |
| 1252 | struct netlink_callback *cb, void *data, int len); |
| 1253 | int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); |
| 1254 | int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); |
| 1255 | |
| 1256 | static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) |
| 1257 | { |
| 1258 | #ifdef CONFIG_NL80211_TESTMODE |
| 1259 | enum mt76_testmode_state state = MT76_TM_STATE_IDLE; |
| 1260 | |
| 1261 | if (disable || phy->test.state == MT76_TM_STATE_OFF) |
| 1262 | state = MT76_TM_STATE_OFF; |
| 1263 | |
| 1264 | mt76_testmode_set_state(phy, state); |
| 1265 | #endif |
| 1266 | } |
| 1267 | |
| 1268 | |
| 1269 | /* internal */ |
| 1270 | static inline struct ieee80211_hw * |
| 1271 | mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) |
| 1272 | { |
| 1273 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
| 1274 | struct ieee80211_hw *hw = dev->phy.hw; |
| 1275 | u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; |
| 1276 | |
| 1277 | hw = mt76_phy_hw(dev, phy_idx); |
| 1278 | |
| 1279 | info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; |
| 1280 | |
| 1281 | return hw; |
| 1282 | } |
| 1283 | |
| 1284 | void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); |
| 1285 | void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, |
| 1286 | struct napi_struct *napi); |
| 1287 | void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, |
| 1288 | struct napi_struct *napi); |
| 1289 | void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); |
| 1290 | void mt76_testmode_tx_pending(struct mt76_phy *phy); |
| 1291 | void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, |
| 1292 | struct mt76_queue_entry *e); |
| 1293 | |
| 1294 | /* usb */ |
| 1295 | static inline bool mt76u_urb_error(struct urb *urb) |
| 1296 | { |
| 1297 | return urb->status && |
| 1298 | urb->status != -ECONNRESET && |
| 1299 | urb->status != -ESHUTDOWN && |
| 1300 | urb->status != -ENOENT; |
| 1301 | } |
| 1302 | |
| 1303 | /* Map hardware queues to usb endpoints */ |
| 1304 | static inline u8 q2ep(u8 qid) |
| 1305 | { |
| 1306 | /* TODO: take management packets to queue 5 */ |
| 1307 | return qid + 1; |
| 1308 | } |
| 1309 | |
| 1310 | static inline int |
| 1311 | mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, |
| 1312 | int timeout, int ep) |
| 1313 | { |
| 1314 | struct usb_interface *uintf = to_usb_interface(dev->dev); |
| 1315 | struct usb_device *udev = interface_to_usbdev(uintf); |
| 1316 | struct mt76_usb *usb = &dev->usb; |
| 1317 | unsigned int pipe; |
| 1318 | |
| 1319 | if (actual_len) |
| 1320 | pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); |
| 1321 | else |
| 1322 | pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); |
| 1323 | |
| 1324 | return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); |
| 1325 | } |
| 1326 | |
| 1327 | void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, |
| 1328 | struct mt76_sta_stats *stats); |
| 1329 | int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); |
| 1330 | int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, |
| 1331 | u16 val, u16 offset, void *buf, size_t len); |
| 1332 | int mt76u_vendor_request(struct mt76_dev *dev, u8 req, |
| 1333 | u8 req_type, u16 val, u16 offset, |
| 1334 | void *buf, size_t len); |
| 1335 | void mt76u_single_wr(struct mt76_dev *dev, const u8 req, |
| 1336 | const u16 offset, const u32 val); |
| 1337 | void mt76u_read_copy(struct mt76_dev *dev, u32 offset, |
| 1338 | void *data, int len); |
| 1339 | u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); |
| 1340 | void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, |
| 1341 | u32 addr, u32 val); |
| 1342 | int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, |
| 1343 | struct mt76_bus_ops *ops); |
| 1344 | int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); |
| 1345 | int mt76u_alloc_mcu_queue(struct mt76_dev *dev); |
| 1346 | int mt76u_alloc_queues(struct mt76_dev *dev); |
| 1347 | void mt76u_stop_tx(struct mt76_dev *dev); |
| 1348 | void mt76u_stop_rx(struct mt76_dev *dev); |
| 1349 | int mt76u_resume_rx(struct mt76_dev *dev); |
| 1350 | void mt76u_queues_deinit(struct mt76_dev *dev); |
| 1351 | |
| 1352 | int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, |
| 1353 | const struct mt76_bus_ops *bus_ops); |
| 1354 | int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); |
| 1355 | int mt76s_alloc_tx(struct mt76_dev *dev); |
| 1356 | void mt76s_deinit(struct mt76_dev *dev); |
| 1357 | void mt76s_sdio_irq(struct sdio_func *func); |
| 1358 | void mt76s_txrx_worker(struct mt76_sdio *sdio); |
| 1359 | bool mt76s_txqs_empty(struct mt76_dev *dev); |
| 1360 | int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, |
| 1361 | int hw_ver); |
| 1362 | u32 mt76s_rr(struct mt76_dev *dev, u32 offset); |
| 1363 | void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); |
| 1364 | u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); |
| 1365 | u32 mt76s_read_pcr(struct mt76_dev *dev); |
| 1366 | void mt76s_write_copy(struct mt76_dev *dev, u32 offset, |
| 1367 | const void *data, int len); |
| 1368 | void mt76s_read_copy(struct mt76_dev *dev, u32 offset, |
| 1369 | void *data, int len); |
| 1370 | int mt76s_wr_rp(struct mt76_dev *dev, u32 base, |
| 1371 | const struct mt76_reg_pair *data, |
| 1372 | int len); |
| 1373 | int mt76s_rd_rp(struct mt76_dev *dev, u32 base, |
| 1374 | struct mt76_reg_pair *data, int len); |
| 1375 | |
| 1376 | struct sk_buff * |
| 1377 | mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, |
| 1378 | int data_len); |
| 1379 | void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); |
| 1380 | struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, |
| 1381 | unsigned long expires); |
| 1382 | int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, |
| 1383 | int len, bool wait_resp, struct sk_buff **ret); |
| 1384 | int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, |
| 1385 | int cmd, bool wait_resp, struct sk_buff **ret); |
| 1386 | int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, |
| 1387 | int len, int max_len); |
| 1388 | static inline int |
| 1389 | mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, |
| 1390 | int len) |
| 1391 | { |
| 1392 | int max_len = 4096 - dev->mcu_ops->headroom; |
| 1393 | |
| 1394 | return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); |
| 1395 | } |
| 1396 | |
| 1397 | static inline int |
| 1398 | mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, |
| 1399 | bool wait_resp) |
| 1400 | { |
| 1401 | return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); |
| 1402 | } |
| 1403 | |
| 1404 | static inline int |
| 1405 | mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, |
| 1406 | bool wait_resp) |
| 1407 | { |
| 1408 | return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); |
| 1409 | } |
| 1410 | |
| 1411 | void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); |
| 1412 | |
| 1413 | s8 mt76_get_rate_power_limits(struct mt76_phy *phy, |
| 1414 | struct ieee80211_channel *chan, |
| 1415 | struct mt76_power_limits *dest, |
| 1416 | s8 target_power); |
| 1417 | |
| 1418 | struct mt76_txwi_cache * |
| 1419 | mt76_token_release(struct mt76_dev *dev, int token, bool *wake); |
| 1420 | int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); |
| 1421 | void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); |
| 1422 | |
| 1423 | static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) |
| 1424 | { |
| 1425 | spin_lock_bh(&dev->token_lock); |
| 1426 | __mt76_set_tx_blocked(dev, blocked); |
| 1427 | spin_unlock_bh(&dev->token_lock); |
| 1428 | } |
| 1429 | |
| 1430 | static inline int |
| 1431 | mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) |
| 1432 | { |
| 1433 | int token; |
| 1434 | |
| 1435 | spin_lock_bh(&dev->token_lock); |
| 1436 | token = idr_alloc(&dev->token, *ptxwi, 0, dev->drv->token_size, |
| 1437 | GFP_ATOMIC); |
| 1438 | spin_unlock_bh(&dev->token_lock); |
| 1439 | |
| 1440 | return token; |
| 1441 | } |
| 1442 | |
| 1443 | static inline struct mt76_txwi_cache * |
| 1444 | mt76_token_put(struct mt76_dev *dev, int token) |
| 1445 | { |
| 1446 | struct mt76_txwi_cache *txwi; |
| 1447 | |
| 1448 | spin_lock_bh(&dev->token_lock); |
| 1449 | txwi = idr_remove(&dev->token, token); |
| 1450 | spin_unlock_bh(&dev->token_lock); |
| 1451 | |
| 1452 | return txwi; |
| 1453 | } |
| 1454 | |
| 1455 | static inline void mt76_packet_id_init(struct mt76_wcid *wcid) |
| 1456 | { |
| 1457 | INIT_LIST_HEAD(&wcid->list); |
| 1458 | idr_init(&wcid->pktid); |
| 1459 | } |
| 1460 | |
| 1461 | static inline void |
| 1462 | mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) |
| 1463 | { |
| 1464 | struct sk_buff_head list; |
| 1465 | |
| 1466 | mt76_tx_status_lock(dev, &list); |
| 1467 | mt76_tx_status_skb_get(dev, wcid, -1, &list); |
| 1468 | mt76_tx_status_unlock(dev, &list); |
| 1469 | |
| 1470 | idr_destroy(&wcid->pktid); |
| 1471 | } |
| 1472 | |
| 1473 | #endif |