developer | 7e32f7e | 2022-05-18 21:10:08 +0800 | [diff] [blame] | 1 | From 1bbe0ecc2a1a008bcfeb7fd2d8f95c8e9a1867c6 Mon Sep 17 00:00:00 2001 |
| 2 | From: Antoine Tenart <antoine.tenart@bootlin.com> |
| 3 | Date: Mon, 13 Jan 2020 23:31:45 +0100 |
| 4 | Subject: net: phy: mscc: macsec initialization |
| 5 | |
| 6 | This patch adds support for initializing the MACsec engine found within |
| 7 | some Microsemi PHYs. The engine is initialized in a passthrough mode and |
| 8 | does not modify any incoming or outgoing packet. But thanks to this it |
| 9 | now can be configured to perform MACsec transformations on packets, |
| 10 | which will be supported by a future patch. |
| 11 | |
| 12 | The MACsec read and write functions are wrapped into two versions: one |
| 13 | called during the init phase, and the other one later on. This is |
| 14 | because the init functions in the Microsemi PHY driver are called while |
| 15 | the MDIO bus lock is taken. |
| 16 | |
| 17 | Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> |
| 18 | Signed-off-by: David S. Miller <davem@davemloft.net> |
| 19 | --- |
| 20 | drivers/net/phy/mscc.c | 382 +++++++++++++++++++++++++++++++++++++++ |
| 21 | drivers/net/phy/mscc_fc_buffer.h | 64 +++++++ |
| 22 | drivers/net/phy/mscc_mac.h | 159 ++++++++++++++++ |
| 23 | drivers/net/phy/mscc_macsec.h | 260 ++++++++++++++++++++++++++ |
| 24 | 4 files changed, 865 insertions(+) |
| 25 | create mode 100644 drivers/net/phy/mscc_fc_buffer.h |
| 26 | create mode 100644 drivers/net/phy/mscc_mac.h |
| 27 | create mode 100644 drivers/net/phy/mscc_macsec.h |
| 28 | |
| 29 | diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c |
| 30 | index 50214c081164f..8579a59a1336a 100644 |
| 31 | --- a/drivers/net/phy/mscc.c |
| 32 | +++ b/drivers/net/phy/mscc.c |
| 33 | @@ -18,6 +18,10 @@ |
| 34 | #include <linux/netdevice.h> |
| 35 | #include <dt-bindings/net/mscc-phy-vsc8531.h> |
| 36 | |
| 37 | +#include "mscc_macsec.h" |
| 38 | +#include "mscc_mac.h" |
| 39 | +#include "mscc_fc_buffer.h" |
| 40 | + |
| 41 | enum rgmii_rx_clock_delay { |
| 42 | RGMII_RX_CLK_DELAY_0_2_NS = 0, |
| 43 | RGMII_RX_CLK_DELAY_0_8_NS = 1, |
| 44 | @@ -121,6 +125,26 @@ enum rgmii_rx_clock_delay { |
| 45 | #define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8 |
| 46 | #define PHY_S6G_PLL_FSM_ENA_POS 7 |
| 47 | |
| 48 | +#define MSCC_EXT_PAGE_MACSEC_17 17 |
| 49 | +#define MSCC_EXT_PAGE_MACSEC_18 18 |
| 50 | + |
| 51 | +#define MSCC_EXT_PAGE_MACSEC_19 19 |
| 52 | +#define MSCC_PHY_MACSEC_19_REG_ADDR(x) (x) |
| 53 | +#define MSCC_PHY_MACSEC_19_TARGET(x) ((x) << 12) |
| 54 | +#define MSCC_PHY_MACSEC_19_READ BIT(14) |
| 55 | +#define MSCC_PHY_MACSEC_19_CMD BIT(15) |
| 56 | + |
| 57 | +#define MSCC_EXT_PAGE_MACSEC_20 20 |
| 58 | +#define MSCC_PHY_MACSEC_20_TARGET(x) (x) |
| 59 | +enum macsec_bank { |
| 60 | + FC_BUFFER = 0x04, |
| 61 | + HOST_MAC = 0x05, |
| 62 | + LINE_MAC = 0x06, |
| 63 | + IP_1588 = 0x0e, |
| 64 | + MACSEC_INGR = 0x38, |
| 65 | + MACSEC_EGR = 0x3c, |
| 66 | +}; |
| 67 | + |
| 68 | #define MSCC_EXT_PAGE_ACCESS 31 |
| 69 | #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */ |
| 70 | #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */ |
| 71 | @@ -128,6 +152,7 @@ enum rgmii_rx_clock_delay { |
| 72 | #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */ |
| 73 | #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */ |
| 74 | #define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4 |
| 75 | +#define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4 |
| 76 | /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs |
| 77 | * in the same package. |
| 78 | */ |
| 79 | @@ -1584,6 +1609,350 @@ out: |
| 80 | return ret; |
| 81 | } |
| 82 | |
| 83 | +#if IS_ENABLED(CONFIG_MACSEC) |
| 84 | +static u32 vsc8584_macsec_phy_read(struct phy_device *phydev, |
| 85 | + enum macsec_bank bank, u32 reg) |
| 86 | +{ |
| 87 | + u32 val, val_l = 0, val_h = 0; |
| 88 | + unsigned long deadline; |
| 89 | + int rc; |
| 90 | + |
| 91 | + rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC); |
| 92 | + if (rc < 0) |
| 93 | + goto failed; |
| 94 | + |
| 95 | + __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20, |
| 96 | + MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); |
| 97 | + |
| 98 | + if (bank >> 2 == 0x1) |
| 99 | + /* non-MACsec access */ |
| 100 | + bank &= 0x3; |
| 101 | + else |
| 102 | + bank = 0; |
| 103 | + |
| 104 | + __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19, |
| 105 | + MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_READ | |
| 106 | + MSCC_PHY_MACSEC_19_REG_ADDR(reg) | |
| 107 | + MSCC_PHY_MACSEC_19_TARGET(bank)); |
| 108 | + |
| 109 | + deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); |
| 110 | + do { |
| 111 | + val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19); |
| 112 | + } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD)); |
| 113 | + |
| 114 | + val_l = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_17); |
| 115 | + val_h = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_18); |
| 116 | + |
| 117 | +failed: |
| 118 | + phy_restore_page(phydev, rc, rc); |
| 119 | + |
| 120 | + return (val_h << 16) | val_l; |
| 121 | +} |
| 122 | + |
| 123 | +static void vsc8584_macsec_phy_write(struct phy_device *phydev, |
| 124 | + enum macsec_bank bank, u32 reg, u32 val) |
| 125 | +{ |
| 126 | + unsigned long deadline; |
| 127 | + int rc; |
| 128 | + |
| 129 | + rc = phy_select_page(phydev, MSCC_PHY_PAGE_MACSEC); |
| 130 | + if (rc < 0) |
| 131 | + goto failed; |
| 132 | + |
| 133 | + __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_20, |
| 134 | + MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); |
| 135 | + |
| 136 | + if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) |
| 137 | + bank &= 0x3; |
| 138 | + else |
| 139 | + /* MACsec access */ |
| 140 | + bank = 0; |
| 141 | + |
| 142 | + __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_17, (u16)val); |
| 143 | + __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_18, (u16)(val >> 16)); |
| 144 | + |
| 145 | + __phy_write(phydev, MSCC_EXT_PAGE_MACSEC_19, |
| 146 | + MSCC_PHY_MACSEC_19_CMD | MSCC_PHY_MACSEC_19_REG_ADDR(reg) | |
| 147 | + MSCC_PHY_MACSEC_19_TARGET(bank)); |
| 148 | + |
| 149 | + deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); |
| 150 | + do { |
| 151 | + val = __phy_read(phydev, MSCC_EXT_PAGE_MACSEC_19); |
| 152 | + } while (time_before(jiffies, deadline) && !(val & MSCC_PHY_MACSEC_19_CMD)); |
| 153 | + |
| 154 | +failed: |
| 155 | + phy_restore_page(phydev, rc, rc); |
| 156 | +} |
| 157 | + |
| 158 | +static void vsc8584_macsec_classification(struct phy_device *phydev, |
| 159 | + enum macsec_bank bank) |
| 160 | +{ |
| 161 | + /* enable VLAN tag parsing */ |
| 162 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG, |
| 163 | + MSCC_MS_SAM_CP_TAG_PARSE_STAG | |
| 164 | + MSCC_MS_SAM_CP_TAG_PARSE_QTAG | |
| 165 | + MSCC_MS_SAM_CP_TAG_PARSE_QINQ); |
| 166 | +} |
| 167 | + |
| 168 | +static void vsc8584_macsec_flow_default_action(struct phy_device *phydev, |
| 169 | + enum macsec_bank bank, |
| 170 | + bool block) |
| 171 | +{ |
| 172 | + u32 port = (bank == MACSEC_INGR) ? |
| 173 | + MSCC_MS_PORT_UNCONTROLLED : MSCC_MS_PORT_COMMON; |
| 174 | + u32 action = MSCC_MS_FLOW_BYPASS; |
| 175 | + |
| 176 | + if (block) |
| 177 | + action = MSCC_MS_FLOW_DROP; |
| 178 | + |
| 179 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP, |
| 180 | + /* MACsec untagged */ |
| 181 | + MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) | |
| 182 | + MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 183 | + MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(port) | |
| 184 | + /* MACsec tagged */ |
| 185 | + MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) | |
| 186 | + MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 187 | + MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(port) | |
| 188 | + /* Bad tag */ |
| 189 | + MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) | |
| 190 | + MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 191 | + MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(port) | |
| 192 | + /* Kay tag */ |
| 193 | + MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) | |
| 194 | + MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 195 | + MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(port)); |
| 196 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP, |
| 197 | + /* MACsec untagged */ |
| 198 | + MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(action) | |
| 199 | + MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 200 | + MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(port) | |
| 201 | + /* MACsec tagged */ |
| 202 | + MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(action) | |
| 203 | + MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 204 | + MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(port) | |
| 205 | + /* Bad tag */ |
| 206 | + MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(action) | |
| 207 | + MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 208 | + MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(port) | |
| 209 | + /* Kay tag */ |
| 210 | + MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(action) | |
| 211 | + MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(MSCC_MS_ACTION_DROP) | |
| 212 | + MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(port)); |
| 213 | +} |
| 214 | + |
| 215 | +static void vsc8584_macsec_integrity_checks(struct phy_device *phydev, |
| 216 | + enum macsec_bank bank) |
| 217 | +{ |
| 218 | + u32 val; |
| 219 | + |
| 220 | + if (bank != MACSEC_INGR) |
| 221 | + return; |
| 222 | + |
| 223 | + /* Set default rules to pass unmatched frames */ |
| 224 | + val = vsc8584_macsec_phy_read(phydev, bank, |
| 225 | + MSCC_MS_PARAMS2_IG_CC_CONTROL); |
| 226 | + val |= MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT | |
| 227 | + MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT; |
| 228 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL, |
| 229 | + val); |
| 230 | + |
| 231 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG, |
| 232 | + MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG | |
| 233 | + MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG | |
| 234 | + MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ); |
| 235 | +} |
| 236 | + |
| 237 | +static void vsc8584_macsec_block_init(struct phy_device *phydev, |
| 238 | + enum macsec_bank bank) |
| 239 | +{ |
| 240 | + u32 val; |
| 241 | + int i; |
| 242 | + |
| 243 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, |
| 244 | + MSCC_MS_ENA_CFG_SW_RST | |
| 245 | + MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA); |
| 246 | + |
| 247 | + /* Set the MACsec block out of s/w reset and enable clocks */ |
| 248 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, |
| 249 | + MSCC_MS_ENA_CFG_CLK_ENA); |
| 250 | + |
| 251 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL, |
| 252 | + bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218); |
| 253 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL, |
| 254 | + MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) | |
| 255 | + MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2)); |
| 256 | + |
| 257 | + /* Clear the counters */ |
| 258 | + val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL); |
| 259 | + val |= MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET; |
| 260 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val); |
| 261 | + |
| 262 | + /* Enable octet increment mode */ |
| 263 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL, |
| 264 | + MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE); |
| 265 | + |
| 266 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3); |
| 267 | + |
| 268 | + val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL); |
| 269 | + val |= MSCC_MS_COUNT_CONTROL_RESET_ALL; |
| 270 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val); |
| 271 | + |
| 272 | + /* Set the MTU */ |
| 273 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK, |
| 274 | + MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(32761) | |
| 275 | + MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP); |
| 276 | + |
| 277 | + for (i = 0; i < 8; i++) |
| 278 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i), |
| 279 | + MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(32761) | |
| 280 | + MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP); |
| 281 | + |
| 282 | + if (bank == MACSEC_EGR) { |
| 283 | + val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS); |
| 284 | + val &= ~MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M; |
| 285 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val); |
| 286 | + |
| 287 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG, |
| 288 | + MSCC_MS_FC_CFG_FCBUF_ENA | |
| 289 | + MSCC_MS_FC_CFG_LOW_THRESH(0x1) | |
| 290 | + MSCC_MS_FC_CFG_HIGH_THRESH(0x4) | |
| 291 | + MSCC_MS_FC_CFG_LOW_BYTES_VAL(0x4) | |
| 292 | + MSCC_MS_FC_CFG_HIGH_BYTES_VAL(0x6)); |
| 293 | + } |
| 294 | + |
| 295 | + vsc8584_macsec_classification(phydev, bank); |
| 296 | + vsc8584_macsec_flow_default_action(phydev, bank, false); |
| 297 | + vsc8584_macsec_integrity_checks(phydev, bank); |
| 298 | + |
| 299 | + /* Enable the MACsec block */ |
| 300 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, |
| 301 | + MSCC_MS_ENA_CFG_CLK_ENA | |
| 302 | + MSCC_MS_ENA_CFG_MACSEC_ENA | |
| 303 | + MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(0x5)); |
| 304 | +} |
| 305 | + |
| 306 | +static void vsc8584_macsec_mac_init(struct phy_device *phydev, |
| 307 | + enum macsec_bank bank) |
| 308 | +{ |
| 309 | + u32 val; |
| 310 | + int i; |
| 311 | + |
| 312 | + /* Clear host & line stats */ |
| 313 | + for (i = 0; i < 36; i++) |
| 314 | + vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0); |
| 315 | + |
| 316 | + val = vsc8584_macsec_phy_read(phydev, bank, |
| 317 | + MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL); |
| 318 | + val &= ~MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M; |
| 319 | + val |= MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(2) | |
| 320 | + MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(0xffff); |
| 321 | + vsc8584_macsec_phy_write(phydev, bank, |
| 322 | + MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL, val); |
| 323 | + |
| 324 | + val = vsc8584_macsec_phy_read(phydev, bank, |
| 325 | + MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2); |
| 326 | + val |= 0xffff; |
| 327 | + vsc8584_macsec_phy_write(phydev, bank, |
| 328 | + MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2, val); |
| 329 | + |
| 330 | + val = vsc8584_macsec_phy_read(phydev, bank, |
| 331 | + MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL); |
| 332 | + if (bank == HOST_MAC) |
| 333 | + val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA | |
| 334 | + MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA; |
| 335 | + else |
| 336 | + val |= MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA | |
| 337 | + MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA | |
| 338 | + MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE | |
| 339 | + MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA; |
| 340 | + vsc8584_macsec_phy_write(phydev, bank, |
| 341 | + MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL, val); |
| 342 | + |
| 343 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG, |
| 344 | + MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA | |
| 345 | + MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA | |
| 346 | + MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA | |
| 347 | + MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA | |
| 348 | + MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA | |
| 349 | + (bank == HOST_MAC ? |
| 350 | + MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING : 0)); |
| 351 | + |
| 352 | + val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG); |
| 353 | + val &= ~MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC; |
| 354 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val); |
| 355 | + |
| 356 | + val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG); |
| 357 | + val &= ~MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M; |
| 358 | + val |= MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(10240); |
| 359 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val); |
| 360 | + |
| 361 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG, |
| 362 | + MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA | |
| 363 | + MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA | |
| 364 | + MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA | |
| 365 | + MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA); |
| 366 | + |
| 367 | + val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG); |
| 368 | + val &= ~MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA; |
| 369 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val); |
| 370 | + |
| 371 | + vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG, |
| 372 | + MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA | |
| 373 | + MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA | |
| 374 | + MSCC_MAC_CFG_ENA_CFG_RX_ENA | |
| 375 | + MSCC_MAC_CFG_ENA_CFG_TX_ENA); |
| 376 | +} |
| 377 | + |
| 378 | +/* Must be called with mdio_lock taken */ |
| 379 | +static int vsc8584_macsec_init(struct phy_device *phydev) |
| 380 | +{ |
| 381 | + u32 val; |
| 382 | + |
| 383 | + vsc8584_macsec_block_init(phydev, MACSEC_INGR); |
| 384 | + vsc8584_macsec_block_init(phydev, MACSEC_EGR); |
| 385 | + vsc8584_macsec_mac_init(phydev, HOST_MAC); |
| 386 | + vsc8584_macsec_mac_init(phydev, LINE_MAC); |
| 387 | + |
| 388 | + vsc8584_macsec_phy_write(phydev, FC_BUFFER, |
| 389 | + MSCC_FCBUF_FC_READ_THRESH_CFG, |
| 390 | + MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(4) | |
| 391 | + MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(5)); |
| 392 | + |
| 393 | + val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG); |
| 394 | + val |= MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA | |
| 395 | + MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA | |
| 396 | + MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA; |
| 397 | + vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_MODE_CFG, val); |
| 398 | + |
| 399 | + vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG, |
| 400 | + MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(8) | |
| 401 | + MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(9)); |
| 402 | + |
| 403 | + val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, |
| 404 | + MSCC_FCBUF_TX_DATA_QUEUE_CFG); |
| 405 | + val &= ~(MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M | |
| 406 | + MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M); |
| 407 | + val |= MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(0) | |
| 408 | + MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(5119); |
| 409 | + vsc8584_macsec_phy_write(phydev, FC_BUFFER, |
| 410 | + MSCC_FCBUF_TX_DATA_QUEUE_CFG, val); |
| 411 | + |
| 412 | + val = vsc8584_macsec_phy_read(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG); |
| 413 | + val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA; |
| 414 | + vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val); |
| 415 | + |
| 416 | + val = vsc8584_macsec_phy_read(phydev, IP_1588, |
| 417 | + MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL); |
| 418 | + val &= ~MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M; |
| 419 | + val |= MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4); |
| 420 | + vsc8584_macsec_phy_write(phydev, IP_1588, |
| 421 | + MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL, val); |
| 422 | + |
| 423 | + return 0; |
| 424 | +} |
| 425 | +#endif /* CONFIG_MACSEC */ |
| 426 | + |
| 427 | /* Check if one PHY has already done the init of the parts common to all PHYs |
| 428 | * in the Quad PHY package. |
| 429 | */ |
| 430 | @@ -1733,6 +2102,19 @@ static int vsc8584_config_init(struct phy_device *phydev) |
| 431 | |
| 432 | mutex_unlock(&phydev->mdio.bus->mdio_lock); |
| 433 | |
| 434 | +#if IS_ENABLED(CONFIG_MACSEC) |
| 435 | + /* MACsec */ |
| 436 | + switch (phydev->phy_id & phydev->drv->phy_id_mask) { |
| 437 | + case PHY_ID_VSC856X: |
| 438 | + case PHY_ID_VSC8575: |
| 439 | + case PHY_ID_VSC8582: |
| 440 | + case PHY_ID_VSC8584: |
| 441 | + ret = vsc8584_macsec_init(phydev); |
| 442 | + if (ret) |
| 443 | + goto err; |
| 444 | + } |
| 445 | +#endif |
| 446 | + |
| 447 | phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); |
| 448 | |
| 449 | val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); |
| 450 | diff --git a/drivers/net/phy/mscc_fc_buffer.h b/drivers/net/phy/mscc_fc_buffer.h |
| 451 | new file mode 100644 |
| 452 | index 0000000000000..7e9c0e8778952 |
| 453 | --- /dev/null |
| 454 | +++ b/drivers/net/phy/mscc_fc_buffer.h |
| 455 | @@ -0,0 +1,64 @@ |
| 456 | +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 457 | +/* |
| 458 | + * Microsemi Ocelot Switch driver |
| 459 | + * |
| 460 | + * Copyright (C) 2019 Microsemi Corporation |
| 461 | + */ |
| 462 | + |
| 463 | +#ifndef _MSCC_OCELOT_FC_BUFFER_H_ |
| 464 | +#define _MSCC_OCELOT_FC_BUFFER_H_ |
| 465 | + |
| 466 | +#define MSCC_FCBUF_ENA_CFG 0x00 |
| 467 | +#define MSCC_FCBUF_MODE_CFG 0x01 |
| 468 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG 0x02 |
| 469 | +#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG 0x03 |
| 470 | +#define MSCC_FCBUF_TX_DATA_QUEUE_CFG 0x04 |
| 471 | +#define MSCC_FCBUF_RX_DATA_QUEUE_CFG 0x05 |
| 472 | +#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG 0x06 |
| 473 | +#define MSCC_FCBUF_FC_READ_THRESH_CFG 0x07 |
| 474 | +#define MSCC_FCBUF_TX_FRM_GAP_COMP 0x08 |
| 475 | + |
| 476 | +#define MSCC_FCBUF_ENA_CFG_TX_ENA BIT(0) |
| 477 | +#define MSCC_FCBUF_ENA_CFG_RX_ENA BIT(4) |
| 478 | + |
| 479 | +#define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR BIT(4) |
| 480 | +#define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA BIT(8) |
| 481 | +#define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA BIT(12) |
| 482 | +#define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA BIT(16) |
| 483 | +#define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA BIT(20) |
| 484 | +#define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA BIT(24) |
| 485 | +#define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN BIT(28) |
| 486 | + |
| 487 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x) (x) |
| 488 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M GENMASK(15, 0) |
| 489 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x) ((x) << 16) |
| 490 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M GENMASK(19, 16) |
| 491 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x) ((x) << 20) |
| 492 | +#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M GENMASK(31, 20) |
| 493 | + |
| 494 | +#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x) (x) |
| 495 | +#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M GENMASK(15, 0) |
| 496 | +#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x) ((x) << 16) |
| 497 | +#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M GENMASK(31, 16) |
| 498 | + |
| 499 | +#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x) (x) |
| 500 | +#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M GENMASK(15, 0) |
| 501 | +#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x) ((x) << 16) |
| 502 | +#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M GENMASK(31, 16) |
| 503 | + |
| 504 | +#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x) (x) |
| 505 | +#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M GENMASK(15, 0) |
| 506 | +#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x) ((x) << 16) |
| 507 | +#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M GENMASK(31, 16) |
| 508 | + |
| 509 | +#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x) (x) |
| 510 | +#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M GENMASK(15, 0) |
| 511 | +#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x) ((x) << 16) |
| 512 | +#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16) |
| 513 | + |
| 514 | +#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x) (x) |
| 515 | +#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M GENMASK(15, 0) |
| 516 | +#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x) ((x) << 16) |
| 517 | +#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16) |
| 518 | + |
| 519 | +#endif |
| 520 | diff --git a/drivers/net/phy/mscc_mac.h b/drivers/net/phy/mscc_mac.h |
| 521 | new file mode 100644 |
| 522 | index 0000000000000..9420ee5175a61 |
| 523 | --- /dev/null |
| 524 | +++ b/drivers/net/phy/mscc_mac.h |
| 525 | @@ -0,0 +1,159 @@ |
| 526 | +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 527 | +/* |
| 528 | + * Microsemi Ocelot Switch driver |
| 529 | + * |
| 530 | + * Copyright (c) 2017 Microsemi Corporation |
| 531 | + */ |
| 532 | + |
| 533 | +#ifndef _MSCC_OCELOT_LINE_MAC_H_ |
| 534 | +#define _MSCC_OCELOT_LINE_MAC_H_ |
| 535 | + |
| 536 | +#define MSCC_MAC_CFG_ENA_CFG 0x00 |
| 537 | +#define MSCC_MAC_CFG_MODE_CFG 0x01 |
| 538 | +#define MSCC_MAC_CFG_MAXLEN_CFG 0x02 |
| 539 | +#define MSCC_MAC_CFG_NUM_TAGS_CFG 0x03 |
| 540 | +#define MSCC_MAC_CFG_TAGS_CFG 0x04 |
| 541 | +#define MSCC_MAC_CFG_ADV_CHK_CFG 0x07 |
| 542 | +#define MSCC_MAC_CFG_LFS_CFG 0x08 |
| 543 | +#define MSCC_MAC_CFG_LB_CFG 0x09 |
| 544 | +#define MSCC_MAC_CFG_PKTINF_CFG 0x0a |
| 545 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL 0x0b |
| 546 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2 0x0c |
| 547 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL 0x0d |
| 548 | +#define MSCC_MAC_PAUSE_CFG_STATE 0x0e |
| 549 | +#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_LSB 0x0f |
| 550 | +#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_MSB 0x10 |
| 551 | +#define MSCC_MAC_STATUS_RX_LANE_STICKY_0 0x11 |
| 552 | +#define MSCC_MAC_STATUS_RX_LANE_STICKY_1 0x12 |
| 553 | +#define MSCC_MAC_STATUS_TX_MONITOR_STICKY 0x13 |
| 554 | +#define MSCC_MAC_STATUS_TX_MONITOR_STICKY_MASK 0x14 |
| 555 | +#define MSCC_MAC_STATUS_STICKY 0x15 |
| 556 | +#define MSCC_MAC_STATUS_STICKY_MASK 0x16 |
| 557 | +#define MSCC_MAC_STATS_32BIT_RX_HIH_CKSM_ERR_CNT 0x17 |
| 558 | +#define MSCC_MAC_STATS_32BIT_RX_XGMII_PROT_ERR_CNT 0x18 |
| 559 | +#define MSCC_MAC_STATS_32BIT_RX_SYMBOL_ERR_CNT 0x19 |
| 560 | +#define MSCC_MAC_STATS_32BIT_RX_PAUSE_CNT 0x1a |
| 561 | +#define MSCC_MAC_STATS_32BIT_RX_UNSUP_OPCODE_CNT 0x1b |
| 562 | +#define MSCC_MAC_STATS_32BIT_RX_UC_CNT 0x1c |
| 563 | +#define MSCC_MAC_STATS_32BIT_RX_MC_CNT 0x1d |
| 564 | +#define MSCC_MAC_STATS_32BIT_RX_BC_CNT 0x1e |
| 565 | +#define MSCC_MAC_STATS_32BIT_RX_CRC_ERR_CNT 0x1f |
| 566 | +#define MSCC_MAC_STATS_32BIT_RX_UNDERSIZE_CNT 0x20 |
| 567 | +#define MSCC_MAC_STATS_32BIT_RX_FRAGMENTS_CNT 0x21 |
| 568 | +#define MSCC_MAC_STATS_32BIT_RX_IN_RANGE_LEN_ERR_CNT 0x22 |
| 569 | +#define MSCC_MAC_STATS_32BIT_RX_OUT_OF_RANGE_LEN_ERR_CNT 0x23 |
| 570 | +#define MSCC_MAC_STATS_32BIT_RX_OVERSIZE_CNT 0x24 |
| 571 | +#define MSCC_MAC_STATS_32BIT_RX_JABBERS_CNT 0x25 |
| 572 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE64_CNT 0x26 |
| 573 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE65TO127_CNT 0x27 |
| 574 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE128TO255_CNT 0x28 |
| 575 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE256TO511_CNT 0x29 |
| 576 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE512TO1023_CNT 0x2a |
| 577 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE1024TO1518_CNT 0x2b |
| 578 | +#define MSCC_MAC_STATS_32BIT_RX_SIZE1519TOMAX_CNT 0x2c |
| 579 | +#define MSCC_MAC_STATS_32BIT_RX_IPG_SHRINK_CNT 0x2d |
| 580 | +#define MSCC_MAC_STATS_32BIT_TX_PAUSE_CNT 0x2e |
| 581 | +#define MSCC_MAC_STATS_32BIT_TX_UC_CNT 0x2f |
| 582 | +#define MSCC_MAC_STATS_32BIT_TX_MC_CNT 0x30 |
| 583 | +#define MSCC_MAC_STATS_32BIT_TX_BC_CNT 0x31 |
| 584 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE64_CNT 0x32 |
| 585 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE65TO127_CNT 0x33 |
| 586 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE128TO255_CNT 0x34 |
| 587 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE256TO511_CNT 0x35 |
| 588 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE512TO1023_CNT 0x36 |
| 589 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE1024TO1518_CNT 0x37 |
| 590 | +#define MSCC_MAC_STATS_32BIT_TX_SIZE1519TOMAX_CNT 0x38 |
| 591 | +#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_CNT 0x39 |
| 592 | +#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_MSB_CNT 0x3a |
| 593 | +#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_CNT 0x3b |
| 594 | +#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_MSB_CNT 0x3c |
| 595 | +#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_CNT 0x3d |
| 596 | +#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_MSB_CNT 0x3e |
| 597 | +#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_CNT 0x3f |
| 598 | +#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_MSB_CNT 0x40 |
| 599 | +#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_CNT 0x41 |
| 600 | +#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_MSB_CNT 0x42 |
| 601 | + |
| 602 | +#define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA BIT(0) |
| 603 | +#define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA BIT(4) |
| 604 | +#define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST BIT(8) |
| 605 | +#define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST BIT(12) |
| 606 | +#define MSCC_MAC_CFG_ENA_CFG_RX_ENA BIT(16) |
| 607 | +#define MSCC_MAC_CFG_ENA_CFG_TX_ENA BIT(20) |
| 608 | + |
| 609 | +#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x) ((x) << 20) |
| 610 | +#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M GENMASK(29, 20) |
| 611 | +#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE BIT(16) |
| 612 | +#define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES BIT(14) |
| 613 | +#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG(x) ((x) << 10) |
| 614 | +#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG_M GENMASK(12, 10) |
| 615 | +#define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG BIT(6) |
| 616 | +#define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA BIT(4) |
| 617 | +#define MSCC_MAC_CFG_MODE_CFG_HIH_CRC_CHECK BIT(2) |
| 618 | +#define MSCC_MAC_CFG_MODE_CFG_UNDERSIZED_FRAME_DROP_DIS BIT(1) |
| 619 | +#define MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC BIT(0) |
| 620 | + |
| 621 | +#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) |
| 622 | +#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(x) (x) |
| 623 | +#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M GENMASK(15, 0) |
| 624 | + |
| 625 | +#define MSCC_MAC_CFG_TAGS_CFG_RSZ 0x4 |
| 626 | +#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID(x) ((x) << 16) |
| 627 | +#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID_M GENMASK(31, 16) |
| 628 | +#define MSCC_MAC_CFG_TAGS_CFG_TAG_ENA BIT(4) |
| 629 | + |
| 630 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) |
| 631 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) |
| 632 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) |
| 633 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) |
| 634 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) |
| 635 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) |
| 636 | +#define MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA BIT(0) |
| 637 | + |
| 638 | +#define MSCC_MAC_CFG_LFS_CFG_LFS_INH_TX BIT(8) |
| 639 | +#define MSCC_MAC_CFG_LFS_CFG_LFS_DIS_TX BIT(4) |
| 640 | +#define MSCC_MAC_CFG_LFS_CFG_LFS_UNIDIR_ENA BIT(3) |
| 641 | +#define MSCC_MAC_CFG_LFS_CFG_USE_LEADING_EDGE_DETECT BIT(2) |
| 642 | +#define MSCC_MAC_CFG_LFS_CFG_SPURIOUS_Q_DIS BIT(1) |
| 643 | +#define MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA BIT(0) |
| 644 | + |
| 645 | +#define MSCC_MAC_CFG_LB_CFG_XGMII_HOST_LB_ENA BIT(4) |
| 646 | +#define MSCC_MAC_CFG_LB_CFG_XGMII_PHY_LB_ENA BIT(0) |
| 647 | + |
| 648 | +#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA BIT(0) |
| 649 | +#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA BIT(4) |
| 650 | +#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA BIT(8) |
| 651 | +#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA BIT(12) |
| 652 | +#define MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA BIT(16) |
| 653 | +#define MSCC_MAC_CFG_PKTINF_CFG_LF_RELAY_ENA BIT(20) |
| 654 | +#define MSCC_MAC_CFG_PKTINF_CFG_RF_RELAY_ENA BIT(24) |
| 655 | +#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING BIT(25) |
| 656 | +#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_RX_PADDING BIT(26) |
| 657 | +#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_4BYTE_PREAMBLE BIT(27) |
| 658 | +#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(x) ((x) << 28) |
| 659 | +#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS_M GENMASK(30, 28) |
| 660 | + |
| 661 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(x) ((x) << 16) |
| 662 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE_M GENMASK(31, 16) |
| 663 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_WAIT_FOR_LPI_LOW BIT(12) |
| 664 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_USE_PAUSE_STALL_ENA BIT(8) |
| 665 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_REPL_MODE BIT(4) |
| 666 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_FRC_FRAME BIT(2) |
| 667 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(x) (x) |
| 668 | +#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M GENMASK(1, 0) |
| 669 | + |
| 670 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA BIT(16) |
| 671 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PRE_CRC_MODE BIT(20) |
| 672 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA BIT(12) |
| 673 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA BIT(8) |
| 674 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA BIT(4) |
| 675 | +#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE BIT(0) |
| 676 | + |
| 677 | +#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0) |
| 678 | +#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4) |
| 679 | + |
| 680 | +#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2 |
| 681 | +#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x) |
| 682 | +#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0) |
| 683 | + |
| 684 | +#endif /* _MSCC_OCELOT_LINE_MAC_H_ */ |
| 685 | diff --git a/drivers/net/phy/mscc_macsec.h b/drivers/net/phy/mscc_macsec.h |
| 686 | new file mode 100644 |
| 687 | index 0000000000000..0d108da28dad2 |
| 688 | --- /dev/null |
| 689 | +++ b/drivers/net/phy/mscc_macsec.h |
| 690 | @@ -0,0 +1,260 @@ |
| 691 | +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 692 | +/* |
| 693 | + * Microsemi Ocelot Switch driver |
| 694 | + * |
| 695 | + * Copyright (c) 2018 Microsemi Corporation |
| 696 | + */ |
| 697 | + |
| 698 | +#ifndef _MSCC_OCELOT_MACSEC_H_ |
| 699 | +#define _MSCC_OCELOT_MACSEC_H_ |
| 700 | + |
| 701 | +#define CONTROL_TYPE_EGRESS 0x6 |
| 702 | +#define CONTROL_TYPE_INGRESS 0xf |
| 703 | +#define CONTROL_IV0 BIT(5) |
| 704 | +#define CONTROL_IV1 BIT(6) |
| 705 | +#define CONTROL_IV2 BIT(7) |
| 706 | +#define CONTROL_UPDATE_SEQ BIT(13) |
| 707 | +#define CONTROL_IV_IN_SEQ BIT(14) |
| 708 | +#define CONTROL_ENCRYPT_AUTH BIT(15) |
| 709 | +#define CONTROL_KEY_IN_CTX BIT(16) |
| 710 | +#define CONTROL_CRYPTO_ALG(x) ((x) << 17) |
| 711 | +#define CTRYPTO_ALG_AES_CTR_128 0x5 |
| 712 | +#define CTRYPTO_ALG_AES_CTR_192 0x6 |
| 713 | +#define CTRYPTO_ALG_AES_CTR_256 0x7 |
| 714 | +#define CONTROL_DIGEST_TYPE(x) ((x) << 21) |
| 715 | +#define CONTROL_AUTH_ALG(x) ((x) << 23) |
| 716 | +#define AUTH_ALG_AES_GHAS 0x4 |
| 717 | +#define CONTROL_AN(x) ((x) << 26) |
| 718 | +#define CONTROL_SEQ_TYPE(x) ((x) << 28) |
| 719 | +#define CONTROL_SEQ_MASK BIT(30) |
| 720 | +#define CONTROL_CONTEXT_ID BIT(31) |
| 721 | + |
| 722 | +enum mscc_macsec_destination_ports { |
| 723 | + MSCC_MS_PORT_COMMON = 0, |
| 724 | + MSCC_MS_PORT_RSVD = 1, |
| 725 | + MSCC_MS_PORT_CONTROLLED = 2, |
| 726 | + MSCC_MS_PORT_UNCONTROLLED = 3, |
| 727 | +}; |
| 728 | + |
| 729 | +enum mscc_macsec_drop_actions { |
| 730 | + MSCC_MS_ACTION_BYPASS_CRC = 0, |
| 731 | + MSCC_MS_ACTION_BYPASS_BAD = 1, |
| 732 | + MSCC_MS_ACTION_DROP = 2, |
| 733 | + MSCC_MS_ACTION_BYPASS = 3, |
| 734 | +}; |
| 735 | + |
| 736 | +enum mscc_macsec_flow_types { |
| 737 | + MSCC_MS_FLOW_BYPASS = 0, |
| 738 | + MSCC_MS_FLOW_DROP = 1, |
| 739 | + MSCC_MS_FLOW_INGRESS = 2, |
| 740 | + MSCC_MS_FLOW_EGRESS = 3, |
| 741 | +}; |
| 742 | + |
| 743 | +enum mscc_macsec_validate_levels { |
| 744 | + MSCC_MS_VALIDATE_DISABLED = 0, |
| 745 | + MSCC_MS_VALIDATE_CHECK = 1, |
| 746 | + MSCC_MS_VALIDATE_STRICT = 2, |
| 747 | +}; |
| 748 | + |
| 749 | +#define MSCC_MS_XFORM_REC(x, y) (((x) << 5) + (y)) |
| 750 | +#define MSCC_MS_ENA_CFG 0x800 |
| 751 | +#define MSCC_MS_FC_CFG 0x804 |
| 752 | +#define MSCC_MS_SAM_MISC_MATCH(x) (0x1004 + ((x) << 4)) |
| 753 | +#define MSCC_MS_SAM_MATCH_SCI_LO(x) (0x1005 + ((x) << 4)) |
| 754 | +#define MSCC_MS_SAM_MATCH_SCI_HI(x) (0x1006 + ((x) << 4)) |
| 755 | +#define MSCC_MS_SAM_MASK(x) (0x1007 + ((x) << 4)) |
| 756 | +#define MSCC_MS_SAM_ENTRY_SET1 0x1808 |
| 757 | +#define MSCC_MS_SAM_ENTRY_CLEAR1 0x180c |
| 758 | +#define MSCC_MS_SAM_FLOW_CTRL(x) (0x1c00 + (x)) |
| 759 | +#define MSCC_MS_SAM_CP_TAG 0x1e40 |
| 760 | +#define MSCC_MS_SAM_NM_FLOW_NCP 0x1e51 |
| 761 | +#define MSCC_MS_SAM_NM_FLOW_CP 0x1e52 |
| 762 | +#define MSCC_MS_MISC_CONTROL 0x1e5f |
| 763 | +#define MSCC_MS_COUNT_CONTROL 0x3204 |
| 764 | +#define MSCC_MS_PARAMS2_IG_CC_CONTROL 0x3a10 |
| 765 | +#define MSCC_MS_PARAMS2_IG_CP_TAG 0x3a14 |
| 766 | +#define MSCC_MS_VLAN_MTU_CHECK(x) (0x3c40 + (x)) |
| 767 | +#define MSCC_MS_NON_VLAN_MTU_CHECK 0x3c48 |
| 768 | +#define MSCC_MS_PP_CTRL 0x3c4b |
| 769 | +#define MSCC_MS_STATUS_CONTEXT_CTRL 0x3d02 |
| 770 | +#define MSCC_MS_INTR_CTRL_STATUS 0x3d04 |
| 771 | +#define MSCC_MS_BLOCK_CTX_UPDATE 0x3d0c |
| 772 | + |
| 773 | +/* MACSEC_ENA_CFG */ |
| 774 | +#define MSCC_MS_ENA_CFG_CLK_ENA BIT(0) |
| 775 | +#define MSCC_MS_ENA_CFG_SW_RST BIT(1) |
| 776 | +#define MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA BIT(8) |
| 777 | +#define MSCC_MS_ENA_CFG_MACSEC_ENA BIT(9) |
| 778 | +#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(x) ((x) << 10) |
| 779 | +#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE_M GENMASK(12, 10) |
| 780 | + |
| 781 | +/* MACSEC_FC_CFG */ |
| 782 | +#define MSCC_MS_FC_CFG_FCBUF_ENA BIT(0) |
| 783 | +#define MSCC_MS_FC_CFG_USE_PKT_EXPANSION_INDICATION BIT(1) |
| 784 | +#define MSCC_MS_FC_CFG_LOW_THRESH(x) ((x) << 4) |
| 785 | +#define MSCC_MS_FC_CFG_LOW_THRESH_M GENMASK(7, 4) |
| 786 | +#define MSCC_MS_FC_CFG_HIGH_THRESH(x) ((x) << 8) |
| 787 | +#define MSCC_MS_FC_CFG_HIGH_THRESH_M GENMASK(11, 8) |
| 788 | +#define MSCC_MS_FC_CFG_LOW_BYTES_VAL(x) ((x) << 12) |
| 789 | +#define MSCC_MS_FC_CFG_LOW_BYTES_VAL_M GENMASK(14, 12) |
| 790 | +#define MSCC_MS_FC_CFG_HIGH_BYTES_VAL(x) ((x) << 16) |
| 791 | +#define MSCC_MS_FC_CFG_HIGH_BYTES_VAL_M GENMASK(18, 16) |
| 792 | + |
| 793 | +/* MSCC_MS_SAM_MAC_SA_MATCH_HI */ |
| 794 | +#define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(x) ((x) << 16) |
| 795 | +#define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE_M GENMASK(31, 16) |
| 796 | + |
| 797 | +/* MACSEC_SAM_MISC_MATCH */ |
| 798 | +#define MSCC_MS_SAM_MISC_MATCH_VLAN_VALID BIT(0) |
| 799 | +#define MSCC_MS_SAM_MISC_MATCH_QINQ_FOUND BIT(1) |
| 800 | +#define MSCC_MS_SAM_MISC_MATCH_STAG_VALID BIT(2) |
| 801 | +#define MSCC_MS_SAM_MISC_MATCH_QTAG_VALID BIT(3) |
| 802 | +#define MSCC_MS_SAM_MISC_MATCH_VLAN_UP(x) ((x) << 4) |
| 803 | +#define MSCC_MS_SAM_MISC_MATCH_VLAN_UP_M GENMASK(6, 4) |
| 804 | +#define MSCC_MS_SAM_MISC_MATCH_CONTROL_PACKET BIT(7) |
| 805 | +#define MSCC_MS_SAM_MISC_MATCH_UNTAGGED BIT(8) |
| 806 | +#define MSCC_MS_SAM_MISC_MATCH_TAGGED BIT(9) |
| 807 | +#define MSCC_MS_SAM_MISC_MATCH_BAD_TAG BIT(10) |
| 808 | +#define MSCC_MS_SAM_MISC_MATCH_KAY_TAG BIT(11) |
| 809 | +#define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT(x) ((x) << 12) |
| 810 | +#define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT_M GENMASK(13, 12) |
| 811 | +#define MSCC_MS_SAM_MISC_MATCH_PRIORITY(x) ((x) << 16) |
| 812 | +#define MSCC_MS_SAM_MISC_MATCH_PRIORITY_M GENMASK(19, 16) |
| 813 | +#define MSCC_MS_SAM_MISC_MATCH_AN(x) ((x) << 24) |
| 814 | +#define MSCC_MS_SAM_MISC_MATCH_TCI(x) ((x) << 26) |
| 815 | + |
| 816 | +/* MACSEC_SAM_MASK */ |
| 817 | +#define MSCC_MS_SAM_MASK_MAC_SA_MASK(x) (x) |
| 818 | +#define MSCC_MS_SAM_MASK_MAC_SA_MASK_M GENMASK(5, 0) |
| 819 | +#define MSCC_MS_SAM_MASK_MAC_DA_MASK(x) ((x) << 6) |
| 820 | +#define MSCC_MS_SAM_MASK_MAC_DA_MASK_M GENMASK(11, 6) |
| 821 | +#define MSCC_MS_SAM_MASK_MAC_ETYPE_MASK BIT(12) |
| 822 | +#define MSCC_MS_SAM_MASK_VLAN_VLD_MASK BIT(13) |
| 823 | +#define MSCC_MS_SAM_MASK_QINQ_FOUND_MASK BIT(14) |
| 824 | +#define MSCC_MS_SAM_MASK_STAG_VLD_MASK BIT(15) |
| 825 | +#define MSCC_MS_SAM_MASK_QTAG_VLD_MASK BIT(16) |
| 826 | +#define MSCC_MS_SAM_MASK_VLAN_UP_MASK BIT(17) |
| 827 | +#define MSCC_MS_SAM_MASK_VLAN_ID_MASK BIT(18) |
| 828 | +#define MSCC_MS_SAM_MASK_SOURCE_PORT_MASK BIT(19) |
| 829 | +#define MSCC_MS_SAM_MASK_CTL_PACKET_MASK BIT(20) |
| 830 | +#define MSCC_MS_SAM_MASK_VLAN_UP_INNER_MASK BIT(21) |
| 831 | +#define MSCC_MS_SAM_MASK_VLAN_ID_INNER_MASK BIT(22) |
| 832 | +#define MSCC_MS_SAM_MASK_SCI_MASK BIT(23) |
| 833 | +#define MSCC_MS_SAM_MASK_AN_MASK(x) ((x) << 24) |
| 834 | +#define MSCC_MS_SAM_MASK_TCI_MASK(x) ((x) << 26) |
| 835 | + |
| 836 | +/* MACSEC_SAM_FLOW_CTRL_EGR */ |
| 837 | +#define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(x) (x) |
| 838 | +#define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE_M GENMASK(1, 0) |
| 839 | +#define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(x) ((x) << 2) |
| 840 | +#define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT_M GENMASK(3, 2) |
| 841 | +#define MSCC_MS_SAM_FLOW_CTRL_RESV_4 BIT(4) |
| 842 | +#define MSCC_MS_SAM_FLOW_CTRL_FLOW_CRYPT_AUTH BIT(5) |
| 843 | +#define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(x) ((x) << 6) |
| 844 | +#define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION_M GENMASK(7, 6) |
| 845 | +#define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8(x) ((x) << 8) |
| 846 | +#define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8_M GENMASK(15, 8) |
| 847 | +#define MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME BIT(16) |
| 848 | +#define MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT BIT(16) |
| 849 | +#define MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE BIT(17) |
| 850 | +#define MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI BIT(18) |
| 851 | +#define MSCC_MS_SAM_FLOW_CTRL_USE_ES BIT(19) |
| 852 | +#define MSCC_MS_SAM_FLOW_CTRL_USE_SCB BIT(20) |
| 853 | +#define MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(x) ((x) << 19) |
| 854 | +#define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE(x) ((x) << 21) |
| 855 | +#define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE_M GENMASK(22, 21) |
| 856 | +#define MSCC_MS_SAM_FLOW_CTRL_RESV_23 BIT(23) |
| 857 | +#define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET(x) ((x) << 24) |
| 858 | +#define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET_M GENMASK(30, 24) |
| 859 | +#define MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT BIT(31) |
| 860 | + |
| 861 | +/* MACSEC_SAM_CP_TAG */ |
| 862 | +#define MSCC_MS_SAM_CP_TAG_MAP_TBL(x) (x) |
| 863 | +#define MSCC_MS_SAM_CP_TAG_MAP_TBL_M GENMASK(23, 0) |
| 864 | +#define MSCC_MS_SAM_CP_TAG_DEF_UP(x) ((x) << 24) |
| 865 | +#define MSCC_MS_SAM_CP_TAG_DEF_UP_M GENMASK(26, 24) |
| 866 | +#define MSCC_MS_SAM_CP_TAG_STAG_UP_EN BIT(27) |
| 867 | +#define MSCC_MS_SAM_CP_TAG_QTAG_UP_EN BIT(28) |
| 868 | +#define MSCC_MS_SAM_CP_TAG_PARSE_QINQ BIT(29) |
| 869 | +#define MSCC_MS_SAM_CP_TAG_PARSE_STAG BIT(30) |
| 870 | +#define MSCC_MS_SAM_CP_TAG_PARSE_QTAG BIT(31) |
| 871 | + |
| 872 | +/* MACSEC_SAM_NM_FLOW_NCP */ |
| 873 | +#define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(x) (x) |
| 874 | +#define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(x) ((x) << 2) |
| 875 | +#define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(x) ((x) << 6) |
| 876 | +#define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(x) ((x) << 8) |
| 877 | +#define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(x) ((x) << 10) |
| 878 | +#define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(x) ((x) << 14) |
| 879 | +#define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(x) ((x) << 16) |
| 880 | +#define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(x) ((x) << 18) |
| 881 | +#define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(x) ((x) << 22) |
| 882 | +#define MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(x) ((x) << 24) |
| 883 | +#define MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(x) ((x) << 26) |
| 884 | +#define MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(x) ((x) << 30) |
| 885 | + |
| 886 | +/* MACSEC_SAM_NM_FLOW_CP */ |
| 887 | +#define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_FLOW_TYPE(x) (x) |
| 888 | +#define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(x) ((x) << 2) |
| 889 | +#define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(x) ((x) << 6) |
| 890 | +#define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_FLOW_TYPE(x) ((x) << 8) |
| 891 | +#define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(x) ((x) << 10) |
| 892 | +#define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(x) ((x) << 14) |
| 893 | +#define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_FLOW_TYPE(x) ((x) << 16) |
| 894 | +#define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(x) ((x) << 18) |
| 895 | +#define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(x) ((x) << 22) |
| 896 | +#define MSCC_MS_SAM_NM_FLOW_CP_KAY_FLOW_TYPE(x) ((x) << 24) |
| 897 | +#define MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(x) ((x) << 26) |
| 898 | +#define MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(x) ((x) << 30) |
| 899 | + |
| 900 | +/* MACSEC_MISC_CONTROL */ |
| 901 | +#define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(x) (x) |
| 902 | +#define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX_M GENMASK(5, 0) |
| 903 | +#define MSCC_MS_MISC_CONTROL_STATIC_BYPASS BIT(8) |
| 904 | +#define MSCC_MS_MISC_CONTROL_NM_MACSEC_EN BIT(9) |
| 905 | +#define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES(x) ((x) << 10) |
| 906 | +#define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES_M GENMASK(11, 10) |
| 907 | +#define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(x) ((x) << 24) |
| 908 | +#define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE_M GENMASK(25, 24) |
| 909 | + |
| 910 | +/* MACSEC_COUNT_CONTROL */ |
| 911 | +#define MSCC_MS_COUNT_CONTROL_RESET_ALL BIT(0) |
| 912 | +#define MSCC_MS_COUNT_CONTROL_DEBUG_ACCESS BIT(1) |
| 913 | +#define MSCC_MS_COUNT_CONTROL_SATURATE_CNTRS BIT(2) |
| 914 | +#define MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET BIT(3) |
| 915 | + |
| 916 | +/* MACSEC_PARAMS2_IG_CC_CONTROL */ |
| 917 | +#define MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT BIT(14) |
| 918 | +#define MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT BIT(15) |
| 919 | + |
| 920 | +/* MACSEC_PARAMS2_IG_CP_TAG */ |
| 921 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL(x) (x) |
| 922 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL_M GENMASK(23, 0) |
| 923 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP(x) ((x) << 24) |
| 924 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP_M GENMASK(26, 24) |
| 925 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_STAG_UP_EN BIT(27) |
| 926 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_QTAG_UP_EN BIT(28) |
| 927 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ BIT(29) |
| 928 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG BIT(30) |
| 929 | +#define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG BIT(31) |
| 930 | + |
| 931 | +/* MACSEC_VLAN_MTU_CHECK */ |
| 932 | +#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(x) (x) |
| 933 | +#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE_M GENMASK(14, 0) |
| 934 | +#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP BIT(15) |
| 935 | + |
| 936 | +/* MACSEC_NON_VLAN_MTU_CHECK */ |
| 937 | +#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(x) (x) |
| 938 | +#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE_M GENMASK(14, 0) |
| 939 | +#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP BIT(15) |
| 940 | + |
| 941 | +/* MACSEC_PP_CTRL */ |
| 942 | +#define MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE BIT(0) |
| 943 | + |
| 944 | +/* MACSEC_INTR_CTRL_STATUS */ |
| 945 | +#define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS(x) (x) |
| 946 | +#define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M GENMASK(15, 0) |
| 947 | +#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(x) ((x) << 16) |
| 948 | +#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M GENMASK(31, 16) |
| 949 | + |
| 950 | +#endif |
| 951 | -- |
| 952 | cgit 1.2.3-1.el7 |
| 953 | |