developer | ba28e03 | 2021-12-07 10:40:00 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * xHCI host controller toolkit driver for hstx-srctrl |
| 4 | * |
| 5 | * Copyright (C) 2021 MediaTek Inc. |
| 6 | * |
| 7 | * Author: Zhanyong Wang <zhanyong.wang@mediatek.com> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/platform_device.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/slab.h> |
| 13 | #include <linux/usb.h> |
| 14 | #include "xhci-mtk.h" |
| 15 | #include "xhci-mtk-test.h" |
| 16 | #include "xhci-mtk-unusual.h" |
| 17 | |
| 18 | static ssize_t RG_USB20_HSTX_SRCTRL_show(struct device *dev, |
| 19 | struct device_attribute *attr, char *buf) |
| 20 | { |
| 21 | struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
| 22 | struct usb_hcd *hcd = mtk->hcd; |
| 23 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
developer | abd06d7 | 2022-03-03 16:13:41 +0800 | [diff] [blame] | 24 | struct device_node *node = dev->of_node; |
developer | ba28e03 | 2021-12-07 10:40:00 +0800 | [diff] [blame] | 25 | ssize_t cnt = 0; |
| 26 | void __iomem *addr; |
| 27 | u32 val; |
| 28 | u32 i; |
| 29 | int ports; |
| 30 | char str[32]; |
| 31 | int index = 0; |
| 32 | u32 io, length; |
| 33 | int ret; |
| 34 | |
| 35 | ports = mtk->num_u3_ports + mtk->num_u2_ports; |
| 36 | cnt += sprintf(buf + cnt, " RG_USB20_HSTX_SRCTRL usage:\n"); |
| 37 | cnt += sprintf(buf + cnt, |
| 38 | " echo u2p index 3b011 > RG_USB20_HSTX_SRCTRL\n"); |
| 39 | if (mtk->num_u3_ports + 1 != ports) |
| 40 | cnt += sprintf(buf + cnt, " parameter: u2p: %i ~ %i\n", |
| 41 | mtk->num_u3_ports + 1, ports); |
| 42 | else |
| 43 | cnt += sprintf(buf + cnt, " parameter: u2p: %i\n", |
| 44 | mtk->num_u3_ports + 1); |
| 45 | |
| 46 | if (mtk->num_u2_ports > 1) |
| 47 | cnt += sprintf(buf + cnt, " parameter: index: 0 ~ %i\n", |
| 48 | mtk->num_u2_ports); |
| 49 | else |
| 50 | cnt += sprintf(buf + cnt, " parameter: index: 0\n"); |
| 51 | |
| 52 | cnt += sprintf(buf + cnt, |
| 53 | " e.g.: echo 2 0 3b010 > RG_USB20_HSTX_SRCTRL\n"); |
| 54 | cnt += sprintf(buf + cnt, |
| 55 | " port2 binding phy 0, tune 3b'010 as HSTX_SRCTRL value\n"); |
| 56 | |
| 57 | cnt += sprintf(buf + cnt, |
| 58 | "\n=========current HQA setting check=========\n"); |
| 59 | for (i = 1; i <= ports; i++) { |
| 60 | addr = &xhci->op_regs->port_status_base + |
| 61 | NUM_PORT_REGS * ((i - 1) & 0xff); |
| 62 | val = readl(addr); |
| 63 | if (i <= mtk->num_u3_ports) { |
| 64 | cnt += sprintf(buf + cnt, |
| 65 | "USB30 Port%i: 0x%08X\n", i, val); |
| 66 | } else { |
| 67 | cnt += sprintf(buf + cnt, |
| 68 | "USB20 Port%i: 0x%08X\n", i, val); |
| 69 | |
developer | abd06d7 | 2022-03-03 16:13:41 +0800 | [diff] [blame] | 70 | ret = query_phy_addr(node, |
| 71 | &index, &io, &length, PHY_TYPE_USB2); |
developer | ba28e03 | 2021-12-07 10:40:00 +0800 | [diff] [blame] | 72 | if (ret && ret != -EACCES) { |
| 73 | if (ret == -EPERM) |
| 74 | cnt += sprintf(buf + cnt, |
| 75 | "USB20 Port%i (Phy%i: absent)\n", |
| 76 | i, index); |
| 77 | else |
| 78 | cnt += sprintf(buf + cnt, |
| 79 | "USB20 Port%i (Phy%i) failure %i\n", |
| 80 | i, index, ret); |
| 81 | continue; |
| 82 | } |
| 83 | |
| 84 | cnt += sprintf(buf + cnt, |
| 85 | "USB20 Port%i (Phy%i:%sable): 0x%08X 0x%08X\n", |
| 86 | i, index, ret ? " dis" : " en", io, length); |
| 87 | |
| 88 | addr = ioremap_nocache(io, length); |
| 89 | addr += (length != 0x100) ? 0x300 : 0; |
| 90 | |
| 91 | HQA_INFORMACTION_COLLECTS(); |
| 92 | |
| 93 | iounmap(addr); |
| 94 | index ++; |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | if (mtk->hqa_pos) { |
| 99 | cnt += sprintf(buf + cnt, "%s", mtk->hqa_buf); |
| 100 | mtk->hqa_pos = 0; |
| 101 | } |
| 102 | |
| 103 | return cnt; |
| 104 | } |
| 105 | |
| 106 | static ssize_t RG_USB20_HSTX_SRCTRL_store(struct device *dev, |
| 107 | struct device_attribute *attr, |
| 108 | const char *buf, size_t n) |
| 109 | { |
| 110 | u32 val; |
| 111 | u32 io; |
| 112 | u32 length; |
| 113 | int ports; |
| 114 | int words; |
| 115 | int port; |
| 116 | int index; |
| 117 | int ret; |
| 118 | char *str = NULL; |
| 119 | void __iomem *addr; |
| 120 | struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); |
| 121 | struct device_node *node = dev->of_node; |
| 122 | |
| 123 | ports = mtk->num_u3_ports + mtk->num_u2_ports; |
| 124 | mtk->hqa_pos = 0; |
| 125 | |
| 126 | memset(mtk->hqa_buf, 0, mtk->hqa_size); |
| 127 | |
| 128 | str = kzalloc(n, GFP_ATOMIC); |
| 129 | |
| 130 | hqa_info(mtk, "RG_USB20_HSTX_SRCTRL(%lu): %s\n", n, buf); |
| 131 | |
| 132 | words = sscanf(buf, "%i %i 3b%3[0,1]", &port, &index, str); |
| 133 | if ((words != 3) || |
| 134 | (port < mtk->num_u3_ports || port > ports)) { |
| 135 | hqa_info(mtk, "Check params(%i):\" %i %i %s\", Please!\n", |
| 136 | words, port, index, str); |
| 137 | |
| 138 | ret = -EINVAL; |
| 139 | goto error; |
| 140 | } |
| 141 | |
| 142 | hqa_info(mtk, " params: %i %i %s\n", |
| 143 | port, index, str); |
| 144 | |
developer | abd06d7 | 2022-03-03 16:13:41 +0800 | [diff] [blame] | 145 | ret = query_phy_addr(node, &index, &io, &length, PHY_TYPE_USB2); |
developer | ba28e03 | 2021-12-07 10:40:00 +0800 | [diff] [blame] | 146 | if (ret && ret != -EACCES) |
| 147 | goto error; |
| 148 | |
| 149 | io += (length != 0x100) ? 0x300 : 0; |
| 150 | io += USB20_PHY_USBPHYACR5; |
| 151 | |
| 152 | addr = ioremap_nocache(io, 4); |
| 153 | val = binary_write_width3(addr, SHFT_RG_USB20_HSTX_SRCTRL, str); |
| 154 | hqa_info(mtk, "Port%i(Phy%i)[0x%08X]: 0x%08X but 0x%08X\n", |
| 155 | port, index, io, val, readl(addr)); |
| 156 | |
| 157 | iounmap(addr); |
| 158 | ret = n; |
| 159 | |
| 160 | error: |
| 161 | kfree(str); |
| 162 | return ret; |
| 163 | } |
| 164 | DEVICE_ATTR_RW(RG_USB20_HSTX_SRCTRL); |