developer | 41370d5 | 2022-03-16 16:01:59 +0800 | [diff] [blame] | 1 | From 469b992489852b500d39048aa0013639dfe9f2e6 Mon Sep 17 00:00:00 2001 |
| 2 | From: Reto Schneider <reto.schneider@husqvarnagroup.com> |
| 3 | Date: Thu, 11 Feb 2021 12:36:19 +0100 |
| 4 | Subject: [PATCH] mtd: spinand: gigadevice: Support GD5F1GQ5UExxG |
| 5 | |
| 6 | The relevant changes to the already existing GD5F1GQ4UExxG support has |
| 7 | been determined by consulting the GigaDevice product change notice |
| 8 | AN-0392-10, version 1.0 from November 30, 2020. |
| 9 | |
| 10 | As the overlaps are huge, variable names have been generalized |
| 11 | accordingly. |
| 12 | |
| 13 | Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes), |
| 14 | the new device ID, and the extra quad IO dummy byte, no changes had to |
| 15 | be taken into account. |
| 16 | |
| 17 | New hardware features are not supported, namely: |
| 18 | - Power on reset |
| 19 | - Unique ID |
| 20 | - Double transfer rate (DTR) |
| 21 | - Parameter page |
| 22 | - Random data quad IO |
| 23 | |
| 24 | The inverted semantic of the "driver strength" register bits, defaulting |
| 25 | to 100% instead of 50% for the Q5 devices, got ignored as the driver has |
| 26 | never touched them anyway. |
| 27 | |
| 28 | The no longer supported "read from cache during block erase" |
| 29 | functionality is not reflected as the current SPI NAND core does not |
| 30 | support it anyway. |
| 31 | |
| 32 | Implementation has been tested on MediaTek MT7688 based GARDENA smart |
| 33 | Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG. |
| 34 | |
| 35 | Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> |
| 36 | Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> |
| 37 | Reviewed-by: Stefan Roese <sr@denx.de> |
| 38 | Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> |
| 39 | Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch |
| 40 | --- |
| 41 | drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++---- |
| 42 | 1 file changed, 60 insertions(+), 9 deletions(-) |
| 43 | |
| 44 | diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c |
| 45 | index 33c67403c4aa1e..1dd1c589809341 100644 |
| 46 | --- a/drivers/mtd/nand/spi/gigadevice.c |
| 47 | +++ b/drivers/mtd/nand/spi/gigadevice.c |
| 48 | @@ -13,7 +13,10 @@ |
| 49 | #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) |
| 50 | #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) |
| 51 | |
| 52 | -#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0 |
| 53 | +#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4) |
| 54 | +#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4) |
| 55 | + |
| 56 | +#define GD5FXGQXXEXXG_REG_STATUS2 0xf0 |
| 57 | |
| 58 | #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) |
| 59 | #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| 60 | @@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand, |
| 61 | return -EINVAL; |
| 62 | } |
| 63 | |
| 64 | -static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 65 | +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 66 | struct mtd_oob_region *region) |
| 67 | { |
| 68 | if (section) |
| 69 | @@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | -static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| 74 | +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| 75 | struct mtd_oob_region *region) |
| 76 | { |
| 77 | if (section) |
| 78 | @@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | -static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = { |
| 83 | - .ecc = gd5fxgq4_variant2_ooblayout_ecc, |
| 84 | - .free = gd5fxgq4_variant2_ooblayout_free, |
| 85 | +/* Valid for Q4/Q5 and Q6 (untested) devices */ |
| 86 | +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { |
| 87 | + .ecc = gd5fxgqx_variant2_ooblayout_ecc, |
| 88 | + .free = gd5fxgqx_variant2_ooblayout_free, |
| 89 | }; |
| 90 | |
| 91 | static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, |
| 92 | @@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, |
| 93 | u8 status) |
| 94 | { |
| 95 | u8 status2; |
| 96 | - struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2, |
| 97 | + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| 98 | &status2); |
| 99 | int ret; |
| 100 | |
| 101 | @@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, |
| 102 | return -EINVAL; |
| 103 | } |
| 104 | |
| 105 | +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, |
| 106 | + u8 status) |
| 107 | +{ |
| 108 | + u8 status2; |
| 109 | + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| 110 | + &status2); |
| 111 | + int ret; |
| 112 | + |
| 113 | + switch (status & STATUS_ECC_MASK) { |
| 114 | + case STATUS_ECC_NO_BITFLIPS: |
| 115 | + return 0; |
| 116 | + |
| 117 | + case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS: |
| 118 | + /* |
| 119 | + * Read status2 register to determine a more fine grained |
| 120 | + * bit error status |
| 121 | + */ |
| 122 | + ret = spi_mem_exec_op(spinand->spimem, &op); |
| 123 | + if (ret) |
| 124 | + return ret; |
| 125 | + |
| 126 | + /* |
| 127 | + * 1 ... 4 bits are flipped (and corrected) |
| 128 | + */ |
| 129 | + /* bits sorted this way (1...0): ECCSE1, ECCSE0 */ |
| 130 | + return ((status2 & STATUS_ECC_MASK) >> 4) + 1; |
| 131 | + |
| 132 | + case STATUS_ECC_UNCOR_ERROR: |
| 133 | + return -EBADMSG; |
| 134 | + |
| 135 | + default: |
| 136 | + break; |
| 137 | + } |
| 138 | + |
| 139 | + return -EINVAL; |
| 140 | +} |
| 141 | + |
| 142 | static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, |
| 143 | u8 status) |
| 144 | { |
| 145 | @@ -282,7 +323,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { |
| 146 | &write_cache_variants, |
| 147 | &update_cache_variants), |
| 148 | SPINAND_HAS_QE_BIT, |
| 149 | - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| 150 | + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| 151 | gd5fxgq4uexxg_ecc_get_status)), |
| 152 | SPINAND_INFO("GD5F1GQ4UFxxG", |
| 153 | SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), |
| 154 | @@ -292,8 +333,18 @@ static const struct spinand_info gigadevice_spinand_table[] = { |
| 155 | &write_cache_variants, |
| 156 | &update_cache_variants), |
| 157 | SPINAND_HAS_QE_BIT, |
| 158 | - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| 159 | + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| 160 | gd5fxgq4ufxxg_ecc_get_status)), |
| 161 | + SPINAND_INFO("GD5F1GQ5UExxG", |
| 162 | + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| 163 | + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| 164 | + NAND_ECCREQ(4, 512), |
| 165 | + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| 166 | + &write_cache_variants, |
| 167 | + &update_cache_variants), |
| 168 | + SPINAND_HAS_QE_BIT, |
| 169 | + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| 170 | + gd5fxgq5xexxg_ecc_get_status)), |
| 171 | }; |
| 172 | |
| 173 | static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |