| developer | e5c01a4 | 2022-12-23 18:17:33 +0800 | [diff] [blame] | 1 | From 6098317d391c07b301bede6002c03ea0eed72103 Mon Sep 17 00:00:00 2001 |
| 2 | From: Shayne Chen <shayne.chen@mediatek.com> |
| 3 | Date: Thu, 1 Dec 2022 14:23:35 +0800 |
| 4 | Subject: [PATCH 2/7] wifi: mt76: mt7996: update register for CFEND_RATE |
| 5 | |
| 6 | In newer chipsets, CFEND_RATE setting has been moved to different hw |
| 7 | module. |
| 8 | |
| 9 | Fixes: 98686cd21624 ("wifi: mt76: mt7996: add driver for MediaTek Wi-Fi 7 (802.11be) devices") |
| 10 | Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> |
| 11 | Change-Id: I41dd443010ede910d934f38f4d86aaa3e7f31032 |
| 12 | --- |
| 13 | mt7996/mac.c | 2 +- |
| 14 | mt7996/mmio.c | 1 + |
| 15 | mt7996/regs.h | 15 ++++++++------- |
| 16 | 3 files changed, 10 insertions(+), 8 deletions(-) |
| 17 | |
| 18 | diff --git a/mt7996/mac.c b/mt7996/mac.c |
| 19 | index 0b3e287..ce4242f 100644 |
| 20 | --- a/mt7996/mac.c |
| 21 | +++ b/mt7996/mac.c |
| 22 | @@ -1690,7 +1690,7 @@ void mt7996_mac_set_timing(struct mt7996_phy *phy) |
| 23 | else |
| 24 | val = MT7996_CFEND_RATE_11B; |
| 25 | |
| 26 | - mt76_rmw_field(dev, MT_AGG_ACR0(band_idx), MT_AGG_ACR_CFEND_RATE, val); |
| 27 | + mt76_rmw_field(dev, MT_RATE_HRCR0(band_idx), MT_RATE_HRCR0_CFEND_RATE, val); |
| 28 | mt76_clear(dev, MT_ARB_SCR(band_idx), |
| 29 | MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); |
| 30 | } |
| 31 | diff --git a/mt7996/mmio.c b/mt7996/mmio.c |
| 32 | index 60781d0..d8a2c1a 100644 |
| 33 | --- a/mt7996/mmio.c |
| 34 | +++ b/mt7996/mmio.c |
| 35 | @@ -21,6 +21,7 @@ static const struct __base mt7996_reg_base[] = { |
| 36 | [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, |
| 37 | [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, |
| 38 | [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, |
| 39 | + [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } }, |
| 40 | }; |
| 41 | |
| 42 | static const struct __map mt7996_reg_map[] = { |
| 43 | diff --git a/mt7996/regs.h b/mt7996/regs.h |
| 44 | index 42980b9..7a28cae 100644 |
| 45 | --- a/mt7996/regs.h |
| 46 | +++ b/mt7996/regs.h |
| 47 | @@ -33,6 +33,7 @@ enum base_rev { |
| 48 | WF_ETBF_BASE, |
| 49 | WF_LPON_BASE, |
| 50 | WF_MIB_BASE, |
| 51 | + WF_RATE_BASE, |
| 52 | __MT_REG_BASE_MAX, |
| 53 | }; |
| 54 | |
| 55 | @@ -235,13 +236,6 @@ enum base_rev { |
| 56 | FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ |
| 57 | FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) |
| 58 | |
| 59 | -/* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */ |
| 60 | -#define MT_WF_AGG_BASE(_band) __BASE(WF_AGG_BASE, (_band)) |
| 61 | -#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) |
| 62 | - |
| 63 | -#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x054) |
| 64 | -#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) |
| 65 | - |
| 66 | /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */ |
| 67 | #define MT_WF_ARB_BASE(_band) __BASE(WF_ARB_BASE, (_band)) |
| 68 | #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) |
| 69 | @@ -300,6 +294,13 @@ enum base_rev { |
| 70 | #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0) |
| 71 | #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) |
| 72 | |
| 73 | +/* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */ |
| 74 | +#define MT_WF_RATE_BASE(_band) __BASE(WF_RATE_BASE, (_band)) |
| 75 | +#define MT_WF_RATE(_band, ofs) (MT_WF_RATE_BASE(_band) + (ofs)) |
| 76 | + |
| 77 | +#define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050) |
| 78 | +#define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0) |
| 79 | + |
| 80 | /* WFDMA0 */ |
| 81 | #define MT_WFDMA0_BASE 0xd4000 |
| 82 | #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) |
| 83 | -- |
| 84 | 2.36.1 |
| 85 | |