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developerc54ce9d2023-01-03 13:30:49 +08001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7988.dtsi"
9
10/ {
11 model = "MediaTek MT7988C DSA 10G eMMC RFB";
12 compatible = "mediatek,mt7988c-dsa-10g-emmc",
13 /* Reserve this for DVFS if creating new dts */
14 "mediatek,mt7988";
15 chosen {
16 bootargs = "console=ttyS0,115200n1 loglevel=8 \
17 earlycon=uart8250,mmio32,0x11000000 \
18 root=PARTLABEL=rootfs rootwait \
19 rootfstype=squashfs,f2fs pci=pcie_bus_perf";
20 };
21
22 memory {
23 reg = <0 0x40000000 0 0x10000000>;
24 };
25
26 wsys_adie: wsys_adie@0 {
27 // fpga cases need to manual change adie_id / sku_type for dvt only
28 compatible = "mediatek,rebb-mt7988-adie";
29 adie_id = <7976>;
30 sku_type = <3000>;
31 };
32
33 reg_1p8v: regulator-1p8v {
34 compatible = "regulator-fixed";
35 regulator-name = "fixed-1.8V";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <1800000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41
42 reg_3p3v: regulator-3p3v {
43 compatible = "regulator-fixed";
44 regulator-name = "fixed-3.3V";
45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>;
47 regulator-boot-on;
48 regulator-always-on;
49 };
50};
51
52&fan {
53 pwms = <&pwm 0 50000 0>;
54 status = "okay";
55};
56
57&pwm {
58 status = "okay";
59};
60
61&uart0 {
62 status = "okay";
63};
64
65&spi1 {
66 pinctrl-names = "default";
67 /* pin shared with snfi */
68 pinctrl-0 = <&spic_pins>;
69 status = "disabled";
70};
71
72&pcie0 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pcie0_pins>;
75 status = "okay";
76};
77
78&pcie1 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pcie1_pins>;
81 status = "disabled";
82};
83
84&pcie2 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pcie2_pins>;
87 status = "disabled";
88};
89
90&pcie3 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pcie3_pins>;
93 status = "okay";
94};
95
96&pio {
97 mdio0_pins: mdio0-pins {
98 mux {
99 function = "mdio";
100 groups = "mdc_mdio0";
101 };
102
103 conf {
104 groups = "mdc_mdio0";
105 drive-strength = <MTK_DRIVE_8mA>;
106 };
107 };
108
developer447cb002023-04-06 17:54:54 +0800109 gbe_led0_pins: gbe-pins {
110 mux {
111 function = "led";
112 groups = "gbe_led0";
113 };
114 };
115
developerc54ce9d2023-01-03 13:30:49 +0800116 pcie0_pins: pcie0-pins {
117 mux {
118 function = "pcie";
119 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
120 "pcie_wake_n0_0";
121 };
122 };
123
124 pcie1_pins: pcie1-pins {
125 mux {
126 function = "pcie";
127 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
128 "pcie_wake_n1_0";
129 };
130 };
131
132 pcie2_pins: pcie2-pins {
133 mux {
134 function = "pcie";
135 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
136 "pcie_wake_n2_0";
137 };
138 };
139
140 pcie3_pins: pcie3-pins {
141 mux {
142 function = "pcie";
143 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
144 "pcie_wake_n3_0";
145 };
146 };
147
148 spic_pins: spi1-pins {
149 mux {
150 function = "spi";
developer1ceb26a2023-02-16 15:43:43 +0800151 groups = "spi1";
developerc54ce9d2023-01-03 13:30:49 +0800152 };
153 };
154
155 mmc0_pins_default: mmc0-pins-default {
156 mux {
157 function = "flash";
158 groups = "emmc_51";
159 };
160 };
161
162 mmc0_pins_uhs: mmc0-pins-uhs {
163 mux {
164 function = "flash";
165 groups = "emmc_51";
166 };
167 };
168};
169
170&watchdog {
171 status = "disabled";
172};
173
174&eth {
175 pinctrl-names = "default";
developer941468f2023-04-10 15:21:02 +0800176 pinctrl-0 = <&mdio0_pins>;
developerc54ce9d2023-01-03 13:30:49 +0800177 status = "okay";
178
179 gmac0: mac@0 {
180 compatible = "mediatek,eth-mac";
181 reg = <0>;
182 mac-type = "xgdm";
183 phy-mode = "10gbase-kr";
184
185 fixed-link {
developerf0145c92023-03-23 23:16:17 +0800186 speed = <10000>;
developerc54ce9d2023-01-03 13:30:49 +0800187 full-duplex;
188 pause;
189 };
190 };
191
192 gmac1: mac@1 {
193 compatible = "mediatek,eth-mac";
194 reg = <1>;
195 mac-type = "xgdm";
developerf0145c92023-03-23 23:16:17 +0800196 phy-mode = "usxgmii";
developerc54ce9d2023-01-03 13:30:49 +0800197 phy-handle = <&phy0>;
198 };
199
200 mdio: mdio-bus {
201 #address-cells = <1>;
202 #size-cells = <0>;
developerc4d8da72023-03-16 14:37:28 +0800203 clock-frequency = <10500000>;
developerc54ce9d2023-01-03 13:30:49 +0800204
205 phy0: ethernet-phy@0 {
206 reg = <0>;
207 compatible = "ethernet-phy-ieee802.3-c45";
208 reset-gpios = <&pio 72 1>;
developer265607f2023-03-01 18:37:46 +0800209 reset-assert-us = <100000>;
210 reset-deassert-us = <221000>;
developerc54ce9d2023-01-03 13:30:49 +0800211 };
212
213 switch@0 {
214 compatible = "mediatek,mt7988";
215 reg = <31>;
216 ports {
217 #address-cells = <1>;
218 #size-cells = <0>;
219
220 port@0 {
221 reg = <0>;
222 label = "lan0";
223 phy-mode = "gmii";
224 phy-handle = <&sphy0>;
225 };
226
227 port@1 {
228 reg = <1>;
229 label = "lan1";
230 phy-mode = "gmii";
231 phy-handle = <&sphy1>;
232 };
233
234 port@2 {
235 reg = <2>;
236 label = "lan2";
237 phy-mode = "gmii";
238 phy-handle = <&sphy2>;
239 };
240
241 port@3 {
242 reg = <3>;
243 label = "lan3";
244 phy-mode = "gmii";
245 phy-handle = <&sphy3>;
246 };
247
248 port@6 {
249 reg = <6>;
250 label = "cpu";
251 ethernet = <&gmac0>;
252 phy-mode = "10gbase-kr";
253
254 fixed-link {
255 speed = <10000>;
256 full-duplex;
257 pause;
258 };
259 };
260 };
261
262 mdio {
263 compatible = "mediatek,dsa-slave-mdio";
264 #address-cells = <1>;
265 #size-cells = <0>;
developer941468f2023-04-10 15:21:02 +0800266 pinctrl-names = "default";
267 pinctrl-0 = <&gbe_led0_pins>;
developerc54ce9d2023-01-03 13:30:49 +0800268
269 sphy0: switch_phy0@0 {
270 compatible = "ethernet-phy-id03a2.9481";
271 reg = <0>;
272 phy-mode = "gmii";
273 rext = "efuse";
274 tx_r50 = "efuse";
275 nvmem-cells = <&phy_calibration_p0>;
276 nvmem-cell-names = "phy-cal-data";
277 };
278
279 sphy1: switch_phy1@1 {
280 compatible = "ethernet-phy-id03a2.9481";
281 reg = <1>;
282 phy-mode = "gmii";
283 rext = "efuse";
284 tx_r50 = "efuse";
285 nvmem-cells = <&phy_calibration_p1>;
286 nvmem-cell-names = "phy-cal-data";
287 };
288
289 sphy2: switch_phy2@2 {
290 compatible = "ethernet-phy-id03a2.9481";
291 reg = <2>;
292 phy-mode = "gmii";
293 rext = "efuse";
294 tx_r50 = "efuse";
295 nvmem-cells = <&phy_calibration_p2>;
296 nvmem-cell-names = "phy-cal-data";
297 };
298
299 sphy3: switch_phy3@3 {
300 compatible = "ethernet-phy-id03a2.9481";
301 reg = <3>;
302 phy-mode = "gmii";
303 rext = "efuse";
304 tx_r50 = "efuse";
305 nvmem-cells = <&phy_calibration_p3>;
306 nvmem-cell-names = "phy-cal-data";
307 };
308 };
309 };
310 };
311};
312
313&hnat {
314 mtketh-wan = "eth1";
315 mtketh-lan = "lan";
316 mtketh-lan2 = "eth2";
317 mtketh-max-gmac = <3>;
318 status = "okay";
319};
320
321&mmc0 {
322 pinctrl-names = "default", "state_uhs";
323 pinctrl-0 = <&mmc0_pins_default>;
324 pinctrl-1 = <&mmc0_pins_uhs>;
325 bus-width = <8>;
326 max-frequency = <200000000>;
327 cap-mmc-highspeed;
328 mmc-hs200-1_8v;
329 mmc-hs400-1_8v;
330 hs400-ds-delay = <0x12814>;
331 vqmmc-supply = <&reg_1p8v>;
332 vmmc-supply = <&reg_3p3v>;
333 non-removable;
334 no-sd;
335 no-sdio;
336 status = "okay";
337};