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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 92086057c5f4aeed780e41f9e99daf2e0f7935ee / . / openwrt_patches-21.02 / 420-master-mt76-internal-debug.patch
blob: 2879ee9ffa5476e682997b88584b362fe6f7cc78 [file] [log] [blame]
developer5f11e9e2022-03-10 15:03:47 +0800[diff] [blame]1diff --git a/package/kernel/mt76/patches/1001-mt76-mt7915-add-mtk-internal-debug-tools-for-mt76.patch b/package/kernel/mt76/patches/1001-mt76-mt7915-add-mtk-internal-debug-tools-for-mt76.patch
2new file mode 100644
3index 00000000..cb2847a8
4--- /dev/null
5+++ b/package/kernel/mt76/patches/1001-mt76-mt7915-add-mtk-internal-debug-tools-for-mt76.patch
6@@ -0,0 +1,4653 @@
7+From 966d2913e6b839773f74c75ec51dc73ec24adec0 Mon Sep 17 00:00:00 2001
8+From: Shayne Chen <shayne.chen@mediatek.com>
9+Date: Thu, 17 Feb 2022 00:17:39 +0800
10+Subject: [PATCH 1001/1006] mt76: mt7915: add mtk internal debug tools for mt76
11+
12+---
13+ .../wireless/mediatek/mt76/mt76_connac_mcu.h | 6 +
14+ .../wireless/mediatek/mt76/mt7915/Makefile | 2 +-
15+ .../wireless/mediatek/mt76/mt7915/debugfs.c | 61 +-
16+ .../net/wireless/mediatek/mt76/mt7915/mcu.c | 37 +
17+ .../net/wireless/mediatek/mt76/mt7915/mcu.h | 4 +
18+ .../wireless/mediatek/mt76/mt7915/mt7915.h | 25 +
19+ .../mediatek/mt76/mt7915/mt7915_debug.h | 1342 ++++++++
20+ .../mediatek/mt76/mt7915/mtk_debugfs.c | 2869 +++++++++++++++++
21+ .../wireless/mediatek/mt76/mt7915/mtk_mcu.c | 51 +
22+ .../net/wireless/mediatek/mt76/tools/fwlog.c | 26 +-
23+ 10 files changed, 4412 insertions(+), 11 deletions(-)
24+ create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/mt7915_debug.h
25+ create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/mtk_debugfs.c
26+ create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/mtk_mcu.c
27+
28+diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
29+index 384c3ea..d4a56f3 100644
30+--- a/mt76_connac_mcu.h
31++++ b/mt76_connac_mcu.h
32+@@ -968,6 +968,12 @@ enum {
33+ MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
34+ MCU_EXT_CMD_RXDCOC_CAL = 0x59,
35+ MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
36++#ifdef MTK_DEBUG
37++ MCU_EXT_CMD_RED_ENABLE = 0x68,
38++ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
39++ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
40++ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
41++#endif
42+ MCU_EXT_CMD_TXDPD_CAL = 0x60,
43+ MCU_EXT_CMD_CAL_CACHE = 0x67,
44+ MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
45+diff --git a/mt7915/Makefile b/mt7915/Makefile
46+index b794ceb..a3474e2 100644
47+--- a/mt7915/Makefile
48++++ b/mt7915/Makefile
49+@@ -3,7 +3,7 @@
50+ obj-$(CONFIG_MT7915E) += mt7915e.o
51+
52+ mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
53+- debugfs.o mmio.o
54++ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
55+
56+ mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
57+ mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
58+\ No newline at end of file
59+diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
60+index 4e1ecae..6dd1ceb 100644
61+--- a/mt7915/debugfs.c
62++++ b/mt7915/debugfs.c
63+@@ -8,6 +8,9 @@
64+ #include "mac.h"
65+
66+ #define FW_BIN_LOG_MAGIC 0x44e98caf
67++#ifdef MTK_DEBUG
68++#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
69++#endif
70+
71+ /** global debugfs **/
72+
73+@@ -370,6 +373,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
74+ int ret;
75+
76+ dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
77++#ifdef MTK_DEBUG
78++ dev->fw_debug_wm = val;
79++#endif
80+
81+ if (dev->fw_debug_bin)
82+ val = 16;
83+@@ -394,6 +400,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
84+ if (ret)
85+ return ret;
86+ }
87++#ifdef MTK_DEBUG
88++ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
89++#endif
90+
91+ /* WM CPU info record control */
92+ mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
93+@@ -401,6 +410,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
94+ mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
95+ mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
96+
97++#ifdef MTK_DEBUG
98++ if (dev->fw_debug_bin & BIT(3))
99++ /* use bit 7 to indicate v2 magic number */
100++ dev->fw_debug_wm |= BIT(7);
101++#endif
102++
103+ return 0;
104+ }
105+
106+@@ -409,7 +424,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
107+ {
108+ struct mt7915_dev *dev = data;
109+
110+- *val = dev->fw_debug_wm;
111++#ifdef MTK_DEBUG
112++ *val = dev->fw_debug_wm & ~BIT(7);
113++#else
114++ val = dev->fw_debug_wm;
115++#endif
116+
117+ return 0;
118+ }
119+@@ -910,6 +929,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
120+ if (!ext_phy)
121+ dev->debugfs_dir = dir;
122+
123++#ifdef MTK_DEBUG
124++ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
125++ mt7915_mtk_init_debugfs(phy, dir);
126++#endif
127++
128+ return 0;
129+ }
130+
131+@@ -950,17 +974,52 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
132+ .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
133+ };
134+
135++#ifdef MTK_DEBUG
136++ struct {
137++ __le32 magic;
138++ u8 version;
139++ u8 _rsv;
140++ __le16 serial_id;
141++ __le32 timestamp;
142++ __le16 msg_type;
143++ __le16 len;
144++ } hdr2 = {
145++ .version = 0x1,
146++ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
147++ .msg_type = PKT_TYPE_RX_FW_MONITOR,
148++ };
149++#endif
150++
151+ if (!dev->relay_fwlog)
152+ return;
153+
154++#ifdef MTK_DEBUG
155++ /* old magic num */
156++ if (!(dev->fw_debug_wm & BIT(7))) {
157++ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
158++ hdr.len = *(__le16 *)data;
159++ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
160++ } else {
161++ hdr2.serial_id = dev->dbg.fwlog_seq++;
162++ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
163++ hdr2.len = *(__le16 *)data;
164++ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
165++ }
166++#else
167+ hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
168+ hdr.len = *(__le16 *)data;
169+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
170++#endif
171+ }
172+
173+ bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
174+ {
175++#ifdef MTK_DEBUG
176++ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
177++ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2)
178++#else
179+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
180++#endif
181+ return false;
182+
183+ if (dev->relay_fwlog)
184+diff --git a/mt7915/mcu.c b/mt7915/mcu.c
185+index b529b53..f9215f4 100644
186+--- a/mt7915/mcu.c
187++++ b/mt7915/mcu.c
188+@@ -3593,3 +3593,40 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
189+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TWT_AGRT_UPDATE),
190+ &req, sizeof(req), true);
191+ }
192++
193++#ifdef MTK_DEBUG
194++int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
195++{
196++ struct {
197++ __le32 args[3];
198++ } req = {
199++ .args = {
200++ cpu_to_le32(a1),
201++ cpu_to_le32(a2),
202++ cpu_to_le32(a3),
203++ },
204++ };
205++
206++ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
207++}
208++
209++int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
210++{
211++#define RED_DISABLE 0
212++#define RED_BY_HOST_ENABLE 1
213++#define RED_BY_WA_ENABLE 2
214++ int ret;
215++ u32 red_type = enabled > 0 ? RED_BY_WA_ENABLE : RED_DISABLE;
216++ __le32 req = cpu_to_le32(red_type);
217++
218++ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RED_ENABLE), &req,
219++ sizeof(req), false);
220++ if (ret < 0)
221++ return ret;
222++
223++ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
224++ MCU_WA_PARAM_RED, enabled, 0, true);
225++
226++ return 0;
227++}
228++#endif
229+diff --git a/mt7915/mcu.h b/mt7915/mcu.h
230+index 960072a..f1fd983 100644
231+--- a/mt7915/mcu.h
232++++ b/mt7915/mcu.h
233+@@ -295,6 +295,10 @@ enum {
234+ MCU_WA_PARAM_PDMA_RX = 0x04,
235+ MCU_WA_PARAM_CPU_UTIL = 0x0b,
236+ MCU_WA_PARAM_RED = 0x0e,
237++#ifdef MTK_DEBUG
238++ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
239++ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
240++#endif
241+ };
242+
243+ enum mcu_mmps_mode {
244+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
245+index 52b848d..85c7e5d 100644
246+--- a/mt7915/mt7915.h
247++++ b/mt7915/mt7915.h
248+@@ -9,6 +9,7 @@
249+ #include "../mt76_connac.h"
250+ #include "regs.h"
251+
252++#define MTK_DEBUG 1
253+ #define MT7915_MAX_INTERFACES 19
254+ #define MT7915_MAX_WMM_SETS 4
255+ #define MT7915_WTBL_SIZE 288
256+@@ -324,6 +325,22 @@ struct mt7915_dev {
257+ struct reset_control *rstc;
258+ void __iomem *dcm;
259+ void __iomem *sku;
260++
261++#ifdef MTK_DEBUG
262++ u16 wlan_idx;
263++ struct {
264++ u32 fixed_rate;
265++ u32 l1debugfs_reg;
266++ u32 l2debugfs_reg;
267++ u32 mac_reg;
268++ u32 fw_dbg_module;
269++ u8 fw_dbg_lv;
270++ u32 bcn_total_cnt[2];
271++ u16 fwlog_seq;
272++ u32 token_idx;
273++ } dbg;
274++ const struct mt7915_dbg_reg_desc *dbg_reg;
275++#endif
276+ };
277+
278+ enum {
279+@@ -591,4 +608,12 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
280+ struct ieee80211_sta *sta, struct dentry *dir);
281+ #endif
282+
283++#ifdef MTK_DEBUG
284++int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
285++int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
286++int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
287++void mt7915_dump_tmac_info(u8 *tmac_info);
288++int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
289++#endif
290++
291+ #endif
292+diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
293+new file mode 100644
294+index 0000000..cc6fca3
295+--- /dev/null
296++++ b/mt7915/mt7915_debug.h
297+@@ -0,0 +1,1342 @@
298++#ifndef __MT7915_DEBUG_H
299++#define __MT7915_DEBUG_H
300++
301++#ifdef MTK_DEBUG
302++
303++#define DBG_INVALID_BASE 0xffffffff
304++#define DBG_INVALID_OFFSET 0x0
305++
306++struct __dbg_map {
307++ u32 phys;
308++ u32 maps;
309++ u32 size;
310++};
311++
312++struct __dbg_reg {
313++ u32 base;
314++ u32 offs;
315++};
316++
317++struct __dbg_mask {
318++ u32 end;
319++ u32 start;
320++};
321++
322++enum dbg_base_rev {
323++ MT_DBG_WFDMA0_BASE,
324++ MT_DBG_WFDMA1_BASE,
325++ MT_DBG_WFDMA0_PCIE1_BASE,
326++ MT_DBG_WFDMA1_PCIE1_BASE,
327++ MT_DBG_WFDMA_EXT_CSR_BASE,
328++ MT_DBG_SWDEF_BASE,
329++ __MT_DBG_BASE_REV_MAX,
330++};
331++
332++enum dbg_reg_rev {
333++ DBG_INT_SOURCE_CSR,
334++ DBG_INT_MASK_CSR,
335++ DBG_INT1_SOURCE_CSR,
336++ DBG_INT1_MASK_CSR,
337++ DBG_TX_RING_BASE,
338++ DBG_RX_EVENT_RING_BASE,
339++ DBG_RX_STS_RING_BASE,
340++ DBG_RX_DATA_RING_BASE,
341++ DBG_DMA_ICSC_FR0,
342++ DBG_DMA_ICSC_FR1,
343++ DBG_TMAC_ICSCR0,
344++ DBG_RMAC_RXICSRPT,
345++ DBG_MIB_M0SDR0,
346++ DBG_MIB_M0SDR3,
347++ DBG_MIB_M0SDR4,
348++ DBG_MIB_M0SDR5,
349++ DBG_MIB_M0SDR7,
350++ DBG_MIB_M0SDR8,
351++ DBG_MIB_M0SDR9,
352++ DBG_MIB_M0SDR10,
353++ DBG_MIB_M0SDR11,
354++ DBG_MIB_M0SDR12,
355++ DBG_MIB_M0SDR14,
356++ DBG_MIB_M0SDR15,
357++ DBG_MIB_M0SDR16,
358++ DBG_MIB_M0SDR17,
359++ DBG_MIB_M0SDR18,
360++ DBG_MIB_M0SDR19,
361++ DBG_MIB_M0SDR20,
362++ DBG_MIB_M0SDR21,
363++ DBG_MIB_M0SDR22,
364++ DBG_MIB_M0SDR23,
365++ DBG_MIB_M0DR0,
366++ DBG_MIB_M0DR1,
367++ DBG_MIB_MUBF,
368++ DBG_MIB_M0DR6,
369++ DBG_MIB_M0DR7,
370++ DBG_MIB_M0DR8,
371++ DBG_MIB_M0DR9,
372++ DBG_MIB_M0DR10,
373++ DBG_MIB_M0DR11,
374++ DBG_MIB_M0DR12,
375++ DBG_WTBLON_WDUCR,
376++ DBG_UWTBL_WDUCR,
377++ DBG_PLE_DRR_TABLE_CTRL,
378++ DBG_PLE_DRR_TABLE_RDATA,
379++ DBG_PLE_PBUF_CTRL,
380++ DBG_PLE_QUEUE_EMPTY,
381++ DBG_PLE_FREEPG_CNT,
382++ DBG_PLE_FREEPG_HEAD_TAIL,
383++ DBG_PLE_PG_HIF_GROUP,
384++ DBG_PLE_HIF_PG_INFO,
385++ DBG_PLE_PG_HIF_TXCMD_GROUP,
386++ DBG_PLE_HIF_TXCMD_PG_INFO,
387++ DBG_PLE_PG_CPU_GROUP,
388++ DBG_PLE_CPU_PG_INFO,
389++ DBG_PLE_FL_QUE_CTRL,
390++ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
391++ DBG_PLE_TXCMD_Q_EMPTY,
392++ DBG_PLE_AC_QEMPTY,
393++ DBG_PLE_AC_OFFSET,
394++ DBG_PLE_STATION_PAUSE,
395++ DBG_PLE_DIS_STA_MAP,
396++ DBG_PSE_PBUF_CTRL,
397++ DBG_PSE_FREEPG_CNT,
398++ DBG_PSE_FREEPG_HEAD_TAIL,
399++ DBG_PSE_HIF0_PG_INFO,
400++ DBG_PSE_PG_HIF1_GROUP,
401++ DBG_PSE_HIF1_PG_INFO,
402++ DBG_PSE_PG_CPU_GROUP,
403++ DBG_PSE_CPU_PG_INFO,
404++ DBG_PSE_PG_PLE_GROUP,
405++ DBG_PSE_PLE_PG_INFO,
406++ DBG_PSE_PG_LMAC0_GROUP,
407++ DBG_PSE_LMAC0_PG_INFO,
408++ DBG_PSE_PG_LMAC1_GROUP,
409++ DBG_PSE_LMAC1_PG_INFO,
410++ DBG_PSE_PG_LMAC2_GROUP,
411++ DBG_PSE_LMAC2_PG_INFO,
412++ DBG_PSE_PG_LMAC3_GROUP,
413++ DBG_PSE_LMAC3_PG_INFO,
414++ DBG_PSE_PG_MDP_GROUP,
415++ DBG_PSE_MDP_PG_INFO,
416++ DBG_PSE_PG_PLE1_GROUP,
417++ DBG_PSE_PLE1_PG_INFO,
418++ DBG_AGG_AALCR0,
419++ DBG_AGG_AALCR1,
420++ DBG_AGG_AALCR2,
421++ DBG_AGG_AALCR3,
422++ DBG_AGG_AALCR4,
423++ DBG_AGG_B0BRR0,
424++ DBG_AGG_B1BRR0,
425++ DBG_AGG_B2BRR0,
426++ DBG_AGG_B3BRR0,
427++ DBG_AGG_AWSCR0,
428++ DBG_AGG_PCR0,
429++ DBG_AGG_TTCR0,
430++ DBG_MIB_M0ARNG0,
431++ DBG_MIB_M0DR2,
432++ DBG_MIB_M0DR13,
433++ __MT_DBG_REG_REV_MAX,
434++};
435++
436++enum dbg_mask_rev {
437++ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
438++ DBG_MIB_M0SDR14_AMPDU,
439++ DBG_MIB_M0SDR15_AMPDU_ACKED,
440++ DBG_MIB_RX_FCS_ERROR_COUNT,
441++ __MT_DBG_MASK_REV_MAX,
442++};
443++
444++enum dbg_bit_rev {
445++ __MT_DBG_BIT_REV_MAX,
446++};
447++
448++static const u32 mt7915_dbg_base[] = {
449++ [MT_DBG_WFDMA0_BASE] = 0xd4000,
450++ [MT_DBG_WFDMA1_BASE] = 0xd5000,
451++ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
452++ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
453++ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
454++ [MT_DBG_SWDEF_BASE] = 0x41f200,
455++};
456++
457++static const u32 mt7916_dbg_base[] = {
458++ [MT_DBG_WFDMA0_BASE] = 0xd4000,
459++ [MT_DBG_WFDMA1_BASE] = 0xd5000,
460++ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
461++ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
462++ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
463++ [MT_DBG_SWDEF_BASE] = 0x411400,
464++};
465++
466++static const u32 mt7986_dbg_base[] = {
467++ [MT_DBG_WFDMA0_BASE] = 0x24000,
468++ [MT_DBG_WFDMA1_BASE] = 0x25000,
469++ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
470++ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
471++ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
472++ [MT_DBG_SWDEF_BASE] = 0x411400,
473++};
474++
475++/* mt7915 regs with different base and offset */
476++static const struct __dbg_reg mt7915_dbg_reg[] = {
477++ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
478++ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
479++ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
480++ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
481++ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
482++ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
483++ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
484++ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
485++ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
486++ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
487++ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
488++ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
489++ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
490++ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
491++ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
492++ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
493++ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
494++ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
495++ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
496++ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
497++ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
498++ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
499++ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
500++ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
501++ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
502++ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
503++ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
504++ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
505++ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
506++ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
507++ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
508++ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
509++ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
510++ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
511++ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
512++ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
513++ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
514++ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
515++ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
516++ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
517++ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
518++ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
519++ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
520++ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
521++ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
522++ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
523++ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
524++ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
525++ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
526++ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
527++ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
528++ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
529++ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
530++ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
531++ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
532++ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
533++ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
534++ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
535++ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
536++ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
537++ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
538++ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
539++ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
540++ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
541++ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
542++ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
543++ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
544++ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
545++ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
546++ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
547++ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
548++ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
549++ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
550++ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
551++ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
552++ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
553++ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
554++ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
555++ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
556++ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
557++ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
558++ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
559++ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
560++ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
561++ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
562++ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
563++ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
564++ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
565++ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
566++ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
567++ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
568++ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
569++ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
570++ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
571++ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
572++ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
573++ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
574++ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
575++ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
576++ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
577++};
578++
579++/* mt7986/mt7916 regs with different base and offset */
580++static const struct __dbg_reg mt7916_dbg_reg[] = {
581++ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
582++ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
583++ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
584++ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
585++ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
586++ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
587++ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
588++ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
589++ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
590++ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
591++ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
592++ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
593++ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
594++ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
595++ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
596++ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
597++ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
598++ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
599++ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
600++ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
601++ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
602++ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
603++ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
604++ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
605++ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
606++ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
607++ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
608++ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
609++ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
610++ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
611++ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
612++ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
613++ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
614++ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
615++ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
616++ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
617++ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
618++ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
619++ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
620++ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
621++ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
622++ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
623++ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
624++ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
625++ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
626++ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
627++ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
628++ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
629++ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
630++ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
631++ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
632++ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
633++ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
634++ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
635++ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
636++ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
637++ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
638++ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
639++ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x374},
640++ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
641++ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
642++ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
643++ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
644++ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
645++ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
646++ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
647++ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
648++ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
649++ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
650++ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
651++ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
652++ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
653++ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
654++ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
655++ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
656++ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
657++ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
658++ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
659++ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
660++ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
661++ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
662++ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
663++ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
664++ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
665++ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
666++ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
667++ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
668++ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
669++ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
670++ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
671++ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
672++ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
673++ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
674++ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
675++ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
676++ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
677++ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
678++ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
679++ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
680++ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
681++};
682++
683++static const struct __dbg_mask mt7915_dbg_mask[] = {
684++ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
685++ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
686++ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
687++ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
688++};
689++
690++static const struct __dbg_mask mt7916_dbg_mask[] = {
691++ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
692++ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
693++ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
694++ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
695++};
696++
697++/* used to differentiate between generations */
698++struct mt7915_dbg_reg_desc {
699++ const u32 id;
700++ const u32 *base_rev;
701++ const struct __dbg_reg *reg_rev;
702++ const struct __dbg_mask *mask_rev;
703++};
704++
705++static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
706++ { 0x7915,
707++ mt7915_dbg_base,
708++ mt7915_dbg_reg,
709++ mt7915_dbg_mask
710++ },
711++ { 0x7906,
712++ mt7916_dbg_base,
713++ mt7916_dbg_reg,
714++ mt7916_dbg_mask
715++ },
716++ { 0x7986,
717++ mt7986_dbg_base,
718++ mt7916_dbg_reg,
719++ mt7916_dbg_mask
720++ },
721++};
722++
723++#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
724++#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
725++#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
726++
727++#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
728++ (_dev)->dbg_reg->mask_rev[(id)].start)
729++#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
730++ __DBG_REG_OFFS((_dev), (id)))
731++
732++#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
733++ dev->dbg_reg->mask_rev[(id)].start)
734++#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
735++ __DBG_MASK(dev, (id)))
736++
737++
738++#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
739++#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
740++#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
741++#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
742++
743++#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
744++#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
745++#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
746++
747++/* WFDMA COMMON */
748++#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
749++#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
750++#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
751++#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
752++
753++/* WFDMA0 */
754++#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
755++
756++#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
757++#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
758++
759++#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
760++#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
761++#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
762++#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
763++#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
764++
765++
766++/* WFDMA1 */
767++#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
768++#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
769++#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
770++
771++#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
772++
773++#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
774++#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
775++#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
776++#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
777++
778++/* WFDMA0 PCIE1 */
779++#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
780++
781++#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
782++#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
783++#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
784++#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
785++
786++#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
787++#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
788++#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
789++#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
790++
791++/* WFDMA1 PCIE1 */
792++#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
793++#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
794++#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
795++#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
796++#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
797++#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
798++
799++#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
800++#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
801++#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
802++#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
803++
804++#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
805++#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
806++#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
807++#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
808++
809++
810++/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
811++#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
812++#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
813++
814++#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
815++#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
816++#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
817++
818++#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
819++#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
820++#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
821++#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
822++#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
823++#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
824++
825++#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
826++#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
827++#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
828++
829++/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
830++#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
831++#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
832++
833++#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
834++#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
835++
836++/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
837++#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
838++#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
839++
840++#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
841++#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
842++
843++/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
844++#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
845++#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
846++
847++
848++#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
849++#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
850++
851++#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
852++#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
853++#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
854++#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
855++#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
856++#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
857++#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
858++#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
859++#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
860++#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
861++#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
862++#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
863++
864++#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
865++
866++#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
867++#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
868++#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
869++#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
870++#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
871++#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
872++#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
873++#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
874++#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
875++#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
876++#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
877++#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
878++#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
879++#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
880++
881++#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
882++#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
883++#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
884++#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
885++#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
886++#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
887++#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
888++ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
889++
890++/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
891++#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
892++#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
893++#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
894++#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
895++
896++#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
897++#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
898++#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
899++#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
900++#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
901++#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
902++#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
903++#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
904++#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
905++#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
906++
907++#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
908++
909++/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
910++#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
911++#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
912++
913++#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
914++
915++#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
916++#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
917++
918++
919++/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
920++#define MT_DBG_WTBL_BASE 0x820D8000
921++
922++/* PLE related CRs. */
923++#define MT_DBG_PLE_BASE 0x820C0000
924++#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
925++
926++#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
927++#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
928++
929++#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
930++#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
931++#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
932++#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
933++#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
934++#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
935++#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
936++#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
937++
938++#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
939++#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
940++#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
941++#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
942++#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
943++#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
944++#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
945++#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
946++#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
947++#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
948++#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
949++#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
950++#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
951++#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
952++#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
953++#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
954++#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
955++
956++#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
957++#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
958++#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
959++
960++#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
961++#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
962++#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
963++#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
964++#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
965++#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
966++
967++#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
968++#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
969++
970++#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
971++#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
972++
973++#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
974++#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
975++
976++#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
977++#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
978++
979++#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
980++#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
981++
982++#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
983++#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
984++
985++#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
986++#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
987++#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
988++
989++#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
990++#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
991++
992++#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
993++#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
994++#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
995++
996++#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
997++#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
998++#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
999++ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1000++
1001++#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1002++
1003++/* pseinfo related CRs. */
1004++#define MT_DBG_PSE_BASE 0x820C8000
1005++#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1006++
1007++#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1008++#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PLE(0x0b0)
1009++#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1010++#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1011++#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PLE(0x110)
1012++#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1013++#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1014++#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1015++#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1016++#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1017++#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1018++#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1019++#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1020++#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1021++#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1022++#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1023++#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1024++#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1025++#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1026++#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1027++#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1028++#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1029++#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1030++#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
1031++
1032++#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1033++#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1034++#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1035++#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1036++#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1037++#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1038++#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1039++#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1040++#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1041++#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1042++#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1043++#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1044++#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1045++#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1046++#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1047++#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1048++#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1049++#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1050++#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1051++#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1052++#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1053++#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1054++#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1055++#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1056++#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1057++#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1058++#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1059++#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1060++#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1061++#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1062++#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1063++#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1064++#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1065++#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1066++#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1067++#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1068++#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1069++#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1070++#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1071++#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1072++#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1073++#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1074++#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1075++#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1076++#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1077++#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1078++#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1079++#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1080++#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1081++#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1082++#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1083++#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1084++#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1085++#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1086++#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1087++#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1088++#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1089++#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1090++#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1091++#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1092++#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1093++#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1094++#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1095++#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1096++#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1097++#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1098++
1099++#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1100++#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1101++#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1102++#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1103++#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1104++
1105++#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1106++#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1107++#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1108++
1109++#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1110++#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1111++
1112++
1113++/* AGG */
1114++#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1115++#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1116++
1117++#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1118++#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1119++#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1120++#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1121++#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1122++#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1123++#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1124++#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1125++#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1126++#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1127++#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1128++#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1129++#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1130++#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1131++#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1132++
1133++#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1134++#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1135++#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1136++#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1137++#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1138++
1139++#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1140++#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1141++#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1142++#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1143++
1144++#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1145++#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1146++#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1147++#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1148++
1149++#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1150++#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1151++#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1152++#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1153++
1154++#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1155++#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1156++#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1157++
1158++#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1159++#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1160++#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1161++#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1162++
1163++#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1164++#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1165++#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1166++#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1167++
1168++#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1169++#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1170++#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1171++#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1172++
1173++#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1174++#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1175++#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1176++
1177++#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1178++#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1179++#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1180++#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1181++#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1182++#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1183++#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1184++#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1185++#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1186++#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1187++#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1188++#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1189++#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1190++#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1191++#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1192++#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1193++
1194++/* mt7915 host DMA*/
1195++#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1196++#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1197++#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1198++
1199++#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1200++#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1201++#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1202++#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1203++#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1204++
1205++#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1206++#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1207++
1208++/* mt7986 host DMA */
1209++#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1210++#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1211++#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1212++#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1213++#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1214++#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1215++
1216++#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1217++#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1218++#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1219++#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1220++#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1221++
1222++/* MCU DMA */
1223++#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1224++#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1225++#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1226++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1227++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1228++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1229++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1230++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1231++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1232++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1233++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1234++#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1235++
1236++#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1237++#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1238++#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1239++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1240++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1241++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1242++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1243++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1244++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1245++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1246++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1247++#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1248++#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1249++#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1250++#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1251++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1252++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1253++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1254++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1255++#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1256++
1257++#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1258++#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1259++#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1260++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1261++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1262++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1263++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1264++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1265++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1266++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1267++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1268++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1269++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1270++#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1271++
1272++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1273++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1274++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1275++/* mt7986 add */
1276++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1277++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1278++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1279++#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1280++
1281++
1282++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1283++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1284++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1285++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1286++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1287++
1288++/* mt7986 add */
1289++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1290++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1291++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1292++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1293++#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1294++
1295++/* MEM DMA */
1296++#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1297++#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1298++#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1299++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1300++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1301++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1302++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1303++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1304++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1305++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1306++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1307++#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1308++#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1309++#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1310++#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1311++#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1312++
1313++enum resource_attr {
1314++ HIF_TX_DATA,
1315++ HIF_TX_CMD,
1316++ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1317++ HIF_TX_FWDL,
1318++ HIF_RX_DATA,
1319++ HIF_RX_EVENT,
1320++ RING_ATTR_NUM
1321++};
1322++
1323++struct hif_pci_tx_ring_desc {
1324++ u32 hw_int_mask;
1325++ u16 ring_size;
1326++ enum resource_attr ring_attr;
1327++ u8 band_idx;
1328++ char *const ring_info;
1329++};
1330++
1331++struct hif_pci_rx_ring_desc {
1332++ u32 hw_desc_base;
1333++ u32 hw_int_mask;
1334++ u16 ring_size;
1335++ enum resource_attr ring_attr;
1336++ u16 max_rx_process_cnt;
1337++ u16 max_sw_read_idx_inc;
1338++ char *const ring_info;
1339++};
1340++
1341++const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1342++ {
1343++ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1344++ .ring_size = 128,
1345++ .ring_attr = HIF_TX_FWDL,
1346++ .ring_info = "FWDL"
1347++ },
1348++ {
1349++ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1350++ .ring_size = 256,
1351++ .ring_attr = HIF_TX_CMD_WM,
1352++ .ring_info = "cmd to WM"
1353++ },
1354++ {
1355++ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1356++ .ring_size = 2048,
1357++ .ring_attr = HIF_TX_DATA,
1358++ .ring_info = "band0 TXD"
1359++ },
1360++ {
1361++ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1362++ .ring_size = 2048,
1363++ .ring_attr = HIF_TX_DATA,
1364++ .ring_info = "band1 TXD"
1365++ },
1366++ {
1367++ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1368++ .ring_size = 256,
1369++ .ring_attr = HIF_TX_CMD,
1370++ .ring_info = "cmd to WA"
1371++ }
1372++};
1373++
1374++const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1375++ {
1376++ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1377++ .ring_size = 1536,
1378++ .ring_attr = HIF_RX_DATA,
1379++ .ring_info = "band0 RX data"
1380++ },
1381++ {
1382++ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1383++ .ring_size = 1536,
1384++ .ring_attr = HIF_RX_DATA,
1385++ .ring_info = "band1 RX data"
1386++ },
1387++ {
1388++ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1389++ .ring_size = 512,
1390++ .ring_attr = HIF_RX_EVENT,
1391++ .ring_info = "event from WM"
1392++ },
1393++ {
1394++ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1395++ .ring_size = 1024,
1396++ .ring_attr = HIF_RX_EVENT,
1397++ .ring_info = "event from WA band0"
1398++ },
1399++ {
1400++ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1401++ .ring_size = 512,
1402++ .ring_attr = HIF_RX_EVENT,
1403++ .ring_info = "event from WA band1"
1404++ }
1405++};
1406++
1407++const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1408++ {
1409++ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1410++ .ring_size = 128,
1411++ .ring_attr = HIF_TX_FWDL,
1412++ .ring_info = "FWDL"
1413++ },
1414++ {
1415++ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1416++ .ring_size = 256,
1417++ .ring_attr = HIF_TX_CMD_WM,
1418++ .ring_info = "cmd to WM"
1419++ },
1420++ {
1421++ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1422++ .ring_size = 2048,
1423++ .ring_attr = HIF_TX_DATA,
1424++ .ring_info = "band0 TXD"
1425++ },
1426++ {
1427++ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1428++ .ring_size = 2048,
1429++ .ring_attr = HIF_TX_DATA,
1430++ .ring_info = "band1 TXD"
1431++ },
1432++ {
1433++ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1434++ .ring_size = 256,
1435++ .ring_attr = HIF_TX_CMD,
1436++ .ring_info = "cmd to WA"
1437++ }
1438++};
1439++
1440++const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1441++ {
1442++ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1443++ .ring_size = 1536,
1444++ .ring_attr = HIF_RX_DATA,
1445++ .ring_info = "band0 RX data"
1446++ },
1447++ {
1448++ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1449++ .ring_size = 1536,
1450++ .ring_attr = HIF_RX_DATA,
1451++ .ring_info = "band1 RX data"
1452++ },
1453++ {
1454++ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1455++ .ring_size = 512,
1456++ .ring_attr = HIF_RX_EVENT,
1457++ .ring_info = "event from WM"
1458++ },
1459++ {
1460++ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1461++ .ring_size = 512,
1462++ .ring_attr = HIF_RX_EVENT,
1463++ .ring_info = "event from WA"
1464++ },
1465++ {
1466++ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1467++ .ring_size = 1024,
1468++ .ring_attr = HIF_RX_EVENT,
1469++ .ring_info = "STS WA band0"
1470++ },
1471++ {
1472++ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1473++ .ring_size = 512,
1474++ .ring_attr = HIF_RX_EVENT,
1475++ .ring_info = "STS WA band1"
1476++ },
1477++};
1478++
1479++/* mibinfo related CRs. */
1480++#define BN0_WF_MIB_TOP_BASE 0x820ed000
1481++#define BN1_WF_MIB_TOP_BASE 0x820fd000
1482++
1483++#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1484++#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1485++#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1486++
1487++#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1488++#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1489++
1490++#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1491++#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1492++#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1493++#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1494++#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1495++
1496++#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1497++#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1498++#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1499++
1500++#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1501++
1502++#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1503++
1504++#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1505++
1506++#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1507++
1508++#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1509++
1510++#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1511++#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1512++#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1513++
1514++#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1515++
1516++#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1517++#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1518++#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1519++#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1520++#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1521++#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1522++
1523++#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1524++#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1525++
1526++#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1527++
1528++#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1529++#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1530++#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1531++#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1532++
1533++#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1534++#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1535++#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1536++#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1537++
1538++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1539++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1540++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1541++#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1542++
1543++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1544++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1545++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1546++#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1547++
1548++#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1549++
1550++#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1551++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1552++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1553++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1554++#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1555++#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1556++#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1557++#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1558++#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1559++#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1560++#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1561++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1562++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1563++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1564++#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1565++#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1566++#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1567++#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1568++#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1569++
1570++
1571++#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1572++#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1573++#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1574++#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1575++
1576++#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1577++#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1578++#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1579++#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1580++
1581++#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1582++#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1583++#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1584++#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1585++
1586++#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1587++#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1588++#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1589++#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1590++
1591++#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1592++#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1593++#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1594++#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1595++
1596++#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1597++#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1598++#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1599++#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1600++
1601++#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1602++#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1603++#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1604++#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1605++
1606++#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1607++#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1608++#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1609++#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1610++
1611++#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1612++#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1613++#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1614++#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1615++
1616++#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1617++#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1618++#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1619++#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1620++
1621++#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1622++#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1623++#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1624++#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1625++/* TXD */
1626++
1627++#define MT_TXD1_ETYP BIT(15)
1628++#define MT_TXD1_VLAN BIT(14)
1629++#define MT_TXD1_RMVL BIT(13)
1630++#define MT_TXD1_AMS BIT(13)
1631++#define MT_TXD1_EOSP BIT(12)
1632++#define MT_TXD1_MRD BIT(11)
1633++
1634++#define MT_TXD7_CTXD BIT(26)
1635++#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1636++#define MT_TXD7_TAT GENMASK(9, 0)
1637++
1638++#endif
1639++#endif
1640+diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1641+new file mode 100644
1642+index 0000000..2616fbf
1643+--- /dev/null
1644++++ b/mt7915/mtk_debugfs.c
1645+@@ -0,0 +1,2869 @@
1646++#include<linux/inet.h>
1647++#include "mt7915.h"
1648++#include "mt7915_debug.h"
1649++#include "mac.h"
1650++#include "mcu.h"
1651++
1652++#ifdef MTK_DEBUG
1653++#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1654++#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1655++#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1656++ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1657++ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1658++
1659++#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1660++#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1661++#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1662++ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1663++ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1664++
1665++#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1666++#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1667++#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1668++ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1669++ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1670++
1671++enum mt7915_wtbl_type {
1672++ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1673++ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1674++ WTBL_TYPE_KEY, /* Key Table */
1675++ MAX_NUM_WTBL_TYPE
1676++};
1677++
1678++static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1679++ enum mt7915_wtbl_type type, u16 start_dw,
1680++ u16 len, void *buf)
1681++{
1682++ u32 *dest_cpy = (u32 *)buf;
1683++ u32 size_dw = len;
1684++ u32 src = 0;
1685++
1686++ if (!buf)
1687++ return 0xFF;
1688++
1689++ if (type == WTBL_TYPE_LMAC) {
1690++ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1691++ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1692++ src = LWTBL_IDX2BASE(idx, start_dw);
1693++ } else if (type == WTBL_TYPE_UMAC) {
1694++ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1695++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1696++ src = UWTBL_IDX2BASE(idx, start_dw);
1697++ } else if (type == WTBL_TYPE_KEY) {
1698++ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1699++ MT_UWTBL_TOP_WDUCR_TARGET |
1700++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1701++ src = KEYTBL_IDX2BASE(idx, start_dw);
1702++ }
1703++
1704++ while (size_dw--) {
1705++ *dest_cpy++ = mt76_rr(dev, src);
1706++ src += 4;
1707++ };
1708++
1709++ return 0;
1710++}
1711++
1712++static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1713++ enum mt7915_wtbl_type type, u16 start_dw,
1714++ u32 val)
1715++{
1716++ u32 addr = 0;
1717++
1718++ if (type == WTBL_TYPE_LMAC) {
1719++ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1720++ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1721++ addr = LWTBL_IDX2BASE(idx, start_dw);
1722++ } else if (type == WTBL_TYPE_UMAC) {
1723++ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1724++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1725++ addr = UWTBL_IDX2BASE(idx, start_dw);
1726++ } else if (type == WTBL_TYPE_KEY) {
1727++ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1728++ MT_UWTBL_TOP_WDUCR_TARGET |
1729++ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1730++ addr = KEYTBL_IDX2BASE(idx, start_dw);
1731++ }
1732++
1733++ mt76_wr(dev, addr, val);
1734++
1735++ return 0;
1736++}
1737++
1738++static int
1739++mt7915_fw_debug_module_set(void *data, u64 module)
1740++{
1741++ struct mt7915_dev *dev = data;
1742++
1743++ dev->dbg.fw_dbg_module = module;
1744++ return 0;
1745++}
1746++
1747++static int
1748++mt7915_fw_debug_module_get(void *data, u64 *module)
1749++{
1750++ struct mt7915_dev *dev = data;
1751++
1752++ *module = dev->dbg.fw_dbg_module;
1753++ return 0;
1754++}
1755++
1756++DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
1757++ mt7915_fw_debug_module_set, "%lld\n");
1758++
1759++static int
1760++mt7915_fw_debug_level_set(void *data, u64 level)
1761++{
1762++ struct mt7915_dev *dev = data;
1763++
1764++ dev->dbg.fw_dbg_lv = level;
1765++ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
1766++ return 0;
1767++}
1768++
1769++static int
1770++mt7915_fw_debug_level_get(void *data, u64 *level)
1771++{
1772++ struct mt7915_dev *dev = data;
1773++
1774++ *level = dev->dbg.fw_dbg_lv;
1775++ return 0;
1776++}
1777++
1778++DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
1779++ mt7915_fw_debug_level_set, "%lld\n");
1780++
1781++#define MAX_TX_MODE 12
1782++static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
1783++ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
1784++ "HE_TRIG", "HE_MU", "N/A"};
1785++static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
1786++ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
1787++ "N/A"};
1788++static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
1789++ "48M", "54M", "N/A"};
1790++static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
1791++ "20/40/80/160/80+80MHz"};
1792++
1793++static char *hw_rate_ofdm_str(u16 ofdm_idx)
1794++{
1795++ switch (ofdm_idx) {
1796++ case 11: /* 6M */
1797++ return HW_TX_RATE_OFDM_STR[0];
1798++
1799++ case 15: /* 9M */
1800++ return HW_TX_RATE_OFDM_STR[1];
1801++
1802++ case 10: /* 12M */
1803++ return HW_TX_RATE_OFDM_STR[2];
1804++
1805++ case 14: /* 18M */
1806++ return HW_TX_RATE_OFDM_STR[3];
1807++
1808++ case 9: /* 24M */
1809++ return HW_TX_RATE_OFDM_STR[4];
1810++
1811++ case 13: /* 36M */
1812++ return HW_TX_RATE_OFDM_STR[5];
1813++
1814++ case 8: /* 48M */
1815++ return HW_TX_RATE_OFDM_STR[6];
1816++
1817++ case 12: /* 54M */
1818++ return HW_TX_RATE_OFDM_STR[7];
1819++
1820++ default:
1821++ return HW_TX_RATE_OFDM_STR[8];
1822++ }
1823++}
1824++
1825++static char *hw_rate_str(u8 mode, u16 rate_idx)
1826++{
1827++ if (mode == 0)
1828++ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
1829++ else if (mode == 1)
1830++ return hw_rate_ofdm_str(rate_idx);
1831++ else
1832++ return "MCS";
1833++}
1834++
1835++static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
1836++{
1837++ u16 txmode, mcs, nss, stbc;
1838++
1839++ txmode = FIELD_GET(GENMASK(9, 6), txrate);
1840++ mcs = FIELD_GET(GENMASK(5, 0), txrate);
1841++ nss = FIELD_GET(GENMASK(12, 10), txrate);
1842++ stbc = FIELD_GET(BIT(13), txrate);
1843++
1844++ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
1845++ rate_idx + 1, txrate,
1846++ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
1847++ mcs, hw_rate_str(txmode, mcs), nss, stbc);
1848++}
1849++
1850++#define LWTBL_LEN_IN_DW 32
1851++#define UWTBL_LEN_IN_DW 8
1852++#define ONE_KEY_ENTRY_LEN_IN_DW 8
1853++static int mt7915_wtbl_read(struct seq_file *s, void *data)
1854++{
1855++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
1856++ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
1857++ int x;
1858++ u32 *addr = 0;
1859++ u32 dw_value = 0;
1860++
1861++ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
1862++ LWTBL_LEN_IN_DW, lwtbl);
1863++ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
1864++ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
1865++ MT_DBG_WTBLON_TOP_WDUCR,
1866++ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
1867++ LWTBL_IDX2BASE(dev->wlan_idx, 0));
1868++ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
1869++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
1870++ x,
1871++ lwtbl[x * 4 + 3],
1872++ lwtbl[x * 4 + 2],
1873++ lwtbl[x * 4 + 1],
1874++ lwtbl[x * 4]);
1875++ }
1876++
1877++ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
1878++ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
1879++
1880++ // DW0, DW1
1881++ seq_printf(s, "LWTBL DW 0/1\n\t");
1882++ addr = (u32 *)&(lwtbl[0]);
1883++ dw_value = *addr;
1884++ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
1885++ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
1886++ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
1887++ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
1888++ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
1889++ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
1890++ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
1891++ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
1892++ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
1893++
1894++ // DW2
1895++ seq_printf(s, "LWTBL DW 2\n\t");
1896++ addr = (u32 *)&(lwtbl[2*4]);
1897++ dw_value = *addr;
1898++ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
1899++ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
1900++ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
1901++ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
1902++ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
1903++ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
1904++ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
1905++ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
1906++ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
1907++ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
1908++ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
1909++ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
1910++ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
1911++ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
1912++ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
1913++
1914++ // DW3
1915++ seq_printf(s, "LWTBL DW 3\n\t");
1916++ addr = (u32 *)&(lwtbl[3*4]);
1917++ dw_value = *addr;
1918++ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
1919++ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
1920++ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
1921++ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
1922++ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
1923++ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
1924++ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
1925++ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
1926++ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
1927++ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
1928++ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
1929++ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
1930++ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
1931++
1932++ // DW4
1933++ seq_printf(s, "LWTBL DW 4\n\t");
1934++ addr = (u32 *)&(lwtbl[4*4]);
1935++ dw_value = *addr;
1936++ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
1937++ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
1938++ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
1939++ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
1940++ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
1941++ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
1942++ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
1943++ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
1944++ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
1945++ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
1946++ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
1947++ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
1948++ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
1949++ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
1950++ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
1951++ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
1952++
1953++ // DW5
1954++ seq_printf(s, "LWTBL DW 5\n\t");
1955++ addr = (u32 *)&(lwtbl[5*4]);
1956++ dw_value = *addr;
1957++ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
1958++ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
1959++ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
1960++ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
1961++ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
1962++ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
1963++ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
1964++ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
1965++ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
1966++ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
1967++ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
1968++ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
1969++ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
1970++ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
1971++ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
1972++ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
1973++ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
1974++ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
1975++
1976++ // DW6
1977++ seq_printf(s, "LWTBL DW 6\n\t");
1978++ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
1979++ addr = (u32 *)&(lwtbl[6*4]);
1980++ dw_value = *addr;
1981++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
1982++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
1983++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
1984++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
1985++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
1986++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
1987++ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
1988++ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
1989++
1990++ // DW7
1991++ seq_printf(s, "LWTBL DW 7\n\t");
1992++ addr = (u32 *)&(lwtbl[7*4]);
1993++ dw_value = *addr;
1994++ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
1995++ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
1996++ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
1997++ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
1998++ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
1999++ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2000++ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2001++ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2002++ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2003++ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2004++ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2005++ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2006++ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2007++ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2008++ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2009++ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2010++ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2011++ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2012++
2013++ // DW8
2014++ seq_printf(s, "LWTBL DW 8\n\t");
2015++ addr = (u32 *)&(lwtbl[8*4]);
2016++ dw_value = *addr;
2017++ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2018++ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2019++ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2020++ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2021++ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2022++ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2023++
2024++ // DW9
2025++ seq_printf(s, "LWTBL DW 9\n\t");
2026++ addr = (u32 *)&(lwtbl[9*4]);
2027++ dw_value = *addr;
2028++ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2029++ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2030++ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2031++ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2032++ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2033++ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2034++ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2035++ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2036++ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2037++ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2038++
2039++ // DW10
2040++ seq_printf(s, "LWTBL DW 10\n");
2041++ addr = (u32 *)&(lwtbl[10*4]);
2042++ dw_value = *addr;
2043++ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2044++ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2045++ // DW11
2046++ seq_printf(s, "LWTBL DW 11\n");
2047++ addr = (u32 *)&(lwtbl[11*4]);
2048++ dw_value = *addr;
2049++ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2050++ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2051++ // DW12
2052++ seq_printf(s, "LWTBL DW 12\n");
2053++ addr = (u32 *)&(lwtbl[12*4]);
2054++ dw_value = *addr;
2055++ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2056++ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2057++ // DW13
2058++ seq_printf(s, "LWTBL DW 13\n");
2059++ addr = (u32 *)&(lwtbl[13*4]);
2060++ dw_value = *addr;
2061++ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2062++ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2063++
2064++ //DW28
2065++ seq_printf(s, "LWTBL DW 28\n\t");
2066++ addr = (u32 *)&(lwtbl[28*4]);
2067++ dw_value = *addr;
2068++ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2069++ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2070++
2071++ //DW29
2072++ seq_printf(s, "LWTBL DW 29\n");
2073++ addr = (u32 *)&(lwtbl[29*4]);
2074++ dw_value = *addr;
2075++ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2076++ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2077++ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2078++ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2079++ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2080++
2081++ //DW30
2082++ seq_printf(s, "LWTBL DW 30\n\t");
2083++ addr = (u32 *)&(lwtbl[30*4]);
2084++ dw_value = *addr;
2085++ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2086++ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2087++ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2088++ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2089++
2090++ //DW31
2091++ seq_printf(s, "LWTBL DW 31\n\t");
2092++ addr = (u32 *)&(lwtbl[31*4]);
2093++ dw_value = *addr;
2094++ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2095++ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2096++ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2097++ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2098++
2099++ return 0;
2100++}
2101++
2102++static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2103++{
2104++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2105++ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2106++ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2107++ int x;
2108++ u32 *addr = 0;
2109++ u32 dw_value = 0;
2110++ u32 amsdu_len = 0;
2111++ u32 u2SN = 0;
2112++ u16 keyloc0, keyloc1;
2113++
2114++ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2115++ UWTBL_LEN_IN_DW, uwtbl);
2116++ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2117++ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2118++ MT_DBG_WTBLON_TOP_WDUCR,
2119++ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2120++ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2121++ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2122++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2123++ x,
2124++ uwtbl[x * 4 + 3],
2125++ uwtbl[x * 4 + 2],
2126++ uwtbl[x * 4 + 1],
2127++ uwtbl[x * 4]);
2128++ }
2129++
2130++ /* UMAC WTBL DW 0 */
2131++ seq_printf(s, "\nUWTBL PN\n\t");
2132++ addr = (u32 *)&(uwtbl[0]);
2133++ dw_value = *addr;
2134++ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2135++ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2136++ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2137++ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2138++
2139++ addr = (u32 *)&(uwtbl[1 * 4]);
2140++ dw_value = *addr;
2141++ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2142++ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2143++
2144++ /* UMAC WTBL DW SN part */
2145++ seq_printf(s, "\nUWTBL SN\n");
2146++ addr = (u32 *)&(uwtbl[2 * 4]);
2147++ dw_value = *addr;
2148++ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2149++ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2150++
2151++ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2152++ addr = (u32 *)&(uwtbl[3 * 4]);
2153++ dw_value = *addr;
2154++ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2155++ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2156++ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2157++ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2158++
2159++ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2160++ addr = (u32 *)&(uwtbl[4 * 4]);
2161++ dw_value = *addr;
2162++ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2163++ seq_printf(s, "TID5_SN:%u\n", u2SN);
2164++ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2165++ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2166++
2167++ addr = (u32 *)&(uwtbl[1 * 4]);
2168++ dw_value = *addr;
2169++ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2170++
2171++ /* UMAC WTBL DW 0 */
2172++ seq_printf(s, "\nUWTBL others\n");
2173++
2174++ addr = (u32 *)&(uwtbl[5 * 4]);
2175++ dw_value = *addr;
2176++ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2177++ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2178++ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2179++ FIELD_GET(GENMASK(10, 0), dw_value),
2180++ FIELD_GET(GENMASK(26, 16), dw_value));
2181++ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2182++ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2183++
2184++ addr = (u32 *)&(uwtbl[6*4]);
2185++ dw_value = *addr;
2186++ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2187++
2188++ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2189++ if (amsdu_len == 0)
2190++ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2191++ else if (amsdu_len == 1)
2192++ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2193++ 1,
2194++ 255,
2195++ amsdu_len);
2196++ else
2197++ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2198++ 256 * (amsdu_len - 1),
2199++ 256 * (amsdu_len - 1) + 255,
2200++ amsdu_len
2201++ );
2202++ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2203++ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2204++ FIELD_GET(GENMASK(8, 6), dw_value));
2205++
2206++ /* Parse KEY link */
2207++ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2208++ if(keyloc0 != GENMASK(10, 0)) {
2209++ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2210++ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2211++ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2212++ MT_DBG_WTBLON_TOP_WDUCR,
2213++ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2214++ KEYTBL_IDX2BASE(keyloc0, 0));
2215++
2216++ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2217++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2218++ x,
2219++ keytbl[x * 4 + 3],
2220++ keytbl[x * 4 + 2],
2221++ keytbl[x * 4 + 1],
2222++ keytbl[x * 4]);
2223++ }
2224++ }
2225++
2226++ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2227++ if(keyloc1 != GENMASK(26, 16)) {
2228++ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2229++ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2230++ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2231++ MT_DBG_WTBLON_TOP_WDUCR,
2232++ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2233++ KEYTBL_IDX2BASE(keyloc1, 0));
2234++
2235++ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2236++ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2237++ x,
2238++ keytbl[x * 4 + 3],
2239++ keytbl[x * 4 + 2],
2240++ keytbl[x * 4 + 1],
2241++ keytbl[x * 4]);
2242++ }
2243++ }
2244++ return 0;
2245++}
2246++
2247++static void
2248++dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2249++{
2250++ u32 base, cnt, cidx, didx, queue_cnt;
2251++
2252++ base= mt76_rr(dev, ring_base);
2253++ cnt = mt76_rr(dev, ring_base + 4);
2254++ cidx = mt76_rr(dev, ring_base + 8);
2255++ didx = mt76_rr(dev, ring_base + 12);
2256++ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2257++
2258++ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2259++}
2260++
2261++static void
2262++dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2263++{
2264++ u32 base, cnt, cidx, didx, queue_cnt;
2265++
2266++ base= mt76_rr(dev, ring_base);
2267++ cnt = mt76_rr(dev, ring_base + 4);
2268++ cidx = mt76_rr(dev, ring_base + 8);
2269++ didx = mt76_rr(dev, ring_base + 12);
2270++ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2271++
2272++ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2273++}
2274++
2275++static void
2276++mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2277++{
2278++ u32 sys_ctrl[10] = {};
2279++
2280++ /* HOST DMA */
2281++ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2282++ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2283++ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2284++ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2285++ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2286++ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2287++ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2288++ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2289++ seq_printf(s, "HOST_DMA Configuration\n");
2290++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2291++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2292++ seq_printf(s, "%10s %10x %10x\n",
2293++ "Merge", sys_ctrl[0], sys_ctrl[1]);
2294++ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2295++ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2296++ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2297++ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2298++ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2299++ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2300++
2301++ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2302++ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2303++ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2304++ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2305++ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2306++ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2307++
2308++ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2309++ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2310++ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2311++ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2312++ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2313++ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2314++ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2315++ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2316++ seq_printf(s, "%10s %10x %10x\n",
2317++ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2318++ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2319++ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2320++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2321++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2322++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2323++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2324++ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2325++ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2326++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2327++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2328++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2329++ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2330++
2331++ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2332++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2333++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2334++ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2335++ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2336++
2337++ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2338++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2339++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2340++ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2341++
2342++ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2343++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2344++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2345++ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2346++ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
2347++ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2348++ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2349++ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2350++ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
2351++ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
2352++ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2353++
2354++ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2355++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2356++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2357++ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2358++ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2359++}
2360++
2361++static void
2362++mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2363++{
2364++ u32 sys_ctrl[9] = {};
2365++
2366++ /* MCU DMA information */
2367++ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2368++ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2369++ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2370++
2371++ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2372++ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2373++ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2374++ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2375++ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2376++ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2377++
2378++ seq_printf(s, "MCU_DMA Configuration\n");
2379++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2380++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2381++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2382++ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2383++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2384++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2385++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2386++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2387++
2388++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2389++ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2390++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2391++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2392++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2393++ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2394++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2395++ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2396++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2397++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2398++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2399++ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2400++
2401++ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2402++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2403++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2404++ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2405++ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2406++ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2407++ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2408++ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2409++ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2410++ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2411++ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2412++
2413++ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2414++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2415++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2416++ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2417++ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2418++ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2419++ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2420++ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2421++ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2422++ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2423++ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2424++
2425++ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2426++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2427++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2428++ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2429++ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2430++}
2431++
2432++static void
2433++mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2434++{
2435++ u32 sys_ctrl[5] = {};
2436++
2437++ /* HOST DMA */
2438++ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2439++ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2440++ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2441++ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2442++ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2443++
2444++ seq_printf(s, "HOST_DMA Configuration\n");
2445++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2446++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2447++ seq_printf(s, "%10s %10x %10x\n",
2448++ "Merge", sys_ctrl[0], sys_ctrl[1]);
2449++ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2450++ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2451++ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2452++ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2453++ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2454++ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2455++
2456++
2457++ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2458++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2459++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2460++ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2461++ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
2462++ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2463++ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2464++ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2465++ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2466++ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
2467++ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2468++ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2469++ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2470++ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2471++}
2472++
2473++static void
2474++mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2475++{
2476++ u32 sys_ctrl[3] = {};
2477++
2478++ /* MCU DMA information */
2479++ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2480++ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2481++ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2482++
2483++ seq_printf(s, "MCU_DMA Configuration\n");
2484++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2485++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2486++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2487++ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2488++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2489++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2490++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2491++ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2492++
2493++ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2494++ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2495++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2496++ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2497++ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2498++ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2499++ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2500++ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2501++ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2502++ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2503++ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2504++ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2505++ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2506++ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2507++ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2508++ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2509++ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2510++ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2511++ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2512++ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2513++
2514++}
2515++
2516++static void
2517++mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2518++{
2519++ u32 sys_ctrl[10] = {};
2520++
2521++ if(is_mt7915(&dev->mt76)) {
2522++ mt7915_show_host_dma_info(s, dev);
2523++ mt7915_show_mcu_dma_info(s, dev);
2524++ } else {
2525++ mt7986_show_host_dma_info(s, dev);
2526++ mt7986_show_mcu_dma_info(s, dev);
2527++ }
2528++
2529++ /* MEM DMA information */
2530++ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2531++ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2532++ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2533++
2534++ seq_printf(s, "MEM_DMA Configuration\n");
2535++ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2536++ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2537++ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2538++ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2539++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2540++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2541++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2542++ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2543++
2544++ seq_printf(s, "MEM_DMA Ring Configuration\n");
2545++ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2546++ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2547++ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2548++ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2549++ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2550++ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2551++}
2552++
2553++static int mt7915_trinfo_read(struct seq_file *s, void *data)
2554++{
2555++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2556++ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2557++ const struct hif_pci_rx_ring_desc *rx_ring_layout;
2558++ u32 tx_ring_num, rx_ring_num;
2559++ u32 tbase[5], tcnt[5];
2560++ u32 tcidx[5], tdidx[5];
2561++ u32 rbase[6], rcnt[6];
2562++ u32 rcidx[6], rdidx[6];
2563++ int idx;
2564++
2565++ if(is_mt7915(&dev->mt76)) {
2566++ tx_ring_layout = &mt7915_tx_ring_layout[0];
2567++ rx_ring_layout = &mt7915_rx_ring_layout[0];
2568++ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2569++ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2570++ } else {
2571++ tx_ring_layout = &mt7986_tx_ring_layout[0];
2572++ rx_ring_layout = &mt7986_rx_ring_layout[0];
2573++ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2574++ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2575++ }
2576++
2577++ for (idx = 0; idx < tx_ring_num; idx++) {
2578++ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2579++ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2580++ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2581++ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);
2582++ }
2583++
2584++ for (idx = 0; idx < rx_ring_num; idx++) {
2585++ if (idx < 2) {
2586++ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2587++ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2588++ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2589++ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2590++ } else {
2591++ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2592++ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2593++ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2594++ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2595++ }
2596++ }
2597++
2598++ seq_printf(s, "=================================================\n");
2599++ seq_printf(s, "TxRing Configuration\n");
2600++ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2601++ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2602++ "QCnt");
2603++ for (idx = 0; idx < tx_ring_num; idx++) {
2604++ u32 queue_cnt;
2605++
2606++ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2607++ (tcidx[idx] - tdidx[idx]) :
2608++ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2609++ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2610++ idx, tx_ring_layout[idx].ring_info,
2611++ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2612++ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2613++ }
2614++
2615++ seq_printf(s, "RxRing Configuration\n");
2616++ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2617++ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2618++ "QCnt");
2619++
2620++ for (idx = 0; idx < rx_ring_num; idx++) {
2621++ u32 queue_cnt;
2622++
2623++ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2624++ (rdidx[idx] - rcidx[idx] - 1) :
2625++ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2626++ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2627++ idx, rx_ring_layout[idx].ring_info,
2628++ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2629++ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2630++ }
2631++
2632++ mt7915_show_dma_info(s, dev);
2633++ return 0;
2634++}
2635++
2636++static int mt7915_drr_info(struct seq_file *s, void *data)
2637++{
2638++#define DL_AC_START 0x00
2639++#define DL_AC_END 0x0F
2640++#define UL_AC_START 0x10
2641++#define UL_AC_END 0x1F
2642++
2643++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2644++ u32 drr_sta_status[16];
2645++ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
2646++ bool is_show = false;
2647++ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
2648++ seq_printf(s, "DRR Table STA Info:\n");
2649++
2650++ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2651++ is_show = true;
2652++ drr_ctrl_val = (drr_ctrl_def_val | idx);
2653++ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2654++ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2655++ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2656++ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2657++ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2658++ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2659++ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2660++ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2661++ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2662++
2663++ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2664++ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2665++ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2666++ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2667++ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2668++ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2669++ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2670++ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2671++ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2672++ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2673++ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2674++ }
2675++ if (!is_mt7915(&dev->mt76))
2676++ max_sta_line = 8;
2677++
2678++ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2679++ if (drr_sta_status[sta_line] > 0) {
2680++ for (sta_no = 0; sta_no < 32; sta_no++) {
2681++ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2682++ if (is_show) {
2683++ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
2684++ is_show = false;
2685++ }
2686++ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2687++ }
2688++ }
2689++ }
2690++ }
2691++ }
2692++
2693++ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
2694++ is_show = true;
2695++ drr_ctrl_val = (drr_ctrl_def_val | idx);
2696++ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2697++ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2698++ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2699++ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2700++ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2701++ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2702++ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2703++ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2704++ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2705++
2706++ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2707++ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2708++ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2709++ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2710++ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2711++ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2712++ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2713++ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2714++ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2715++ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2716++ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2717++ }
2718++
2719++ if (!is_mt7915(&dev->mt76))
2720++ max_sta_line = 8;
2721++
2722++ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2723++ if (drr_sta_status[sta_line] > 0) {
2724++ for (sta_no = 0; sta_no < 32; sta_no++) {
2725++ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2726++ if (is_show) {
2727++ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
2728++ is_show = false;
2729++ }
2730++ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2731++ }
2732++ }
2733++ }
2734++ }
2735++ }
2736++
2737++ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2738++ drr_ctrl_def_val = 0x80420000;
2739++ drr_ctrl_val = (drr_ctrl_def_val | idx);
2740++ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2741++ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2742++ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2743++ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2744++ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2745++ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2746++ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2747++ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2748++ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2749++
2750++ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2751++ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
2752++ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2753++ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2754++ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2755++ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2756++ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2757++ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2758++ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2759++ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2760++ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2761++ }
2762++
2763++ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
2764++ if (!is_mt7915(&dev->mt76))
2765++ max_sta_line = 8;
2766++
2767++ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2768++ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
2769++
2770++ if ((sta_line % 4) == 3)
2771++ seq_printf(s, "\n");
2772++ }
2773++ }
2774++
2775++ return 0;
2776++}
2777++
2778++#define CR_NUM_OF_AC 9
2779++
2780++typedef enum _ENUM_UMAC_PORT_T {
2781++ ENUM_UMAC_HIF_PORT_0 = 0,
2782++ ENUM_UMAC_CPU_PORT_1 = 1,
2783++ ENUM_UMAC_LMAC_PORT_2 = 2,
2784++ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
2785++ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
2786++} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
2787++
2788++/* N9 MCU QUEUE LIST */
2789++typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
2790++ ENUM_UMAC_CTX_Q_0 = 0,
2791++ ENUM_UMAC_CTX_Q_1 = 1,
2792++ ENUM_UMAC_CTX_Q_2 = 2,
2793++ ENUM_UMAC_CTX_Q_3 = 3,
2794++ ENUM_UMAC_CRX = 0,
2795++ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
2796++} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
2797++
2798++/* LMAC PLE TX QUEUE LIST */
2799++typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
2800++ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
2801++ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
2802++ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
2803++ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
2804++
2805++ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
2806++ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
2807++ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
2808++ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
2809++
2810++ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
2811++ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
2812++ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
2813++ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
2814++
2815++ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
2816++ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
2817++ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
2818++ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
2819++
2820++ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
2821++ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
2822++ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
2823++ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
2824++
2825++ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
2826++ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
2827++ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
2828++ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
2829++ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
2830++ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
2831++ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
2832++ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
2833++
2834++} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
2835++
2836++typedef struct _EMPTY_QUEUE_INFO_T {
2837++ char *QueueName;
2838++ u32 Portid;
2839++ u32 Queueid;
2840++} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
2841++
2842++static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
2843++ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
2844++ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
2845++ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
2846++ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
2847++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
2848++ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
2849++ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
2850++ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
2851++ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
2852++ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
2853++ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
2854++ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
2855++ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
2856++ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
2857++ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
2858++ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
2859++ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
2860++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
2861++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
2862++ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
2863++ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
2864++};
2865++
2866++static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
2867++ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
2868++ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
2869++ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
2870++ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
2871++ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
2872++ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
2873++ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
2874++ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
2875++ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
2876++ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
2877++ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
2878++ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
2879++ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
2880++ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
2881++ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
2882++ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
2883++ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
2884++ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
2885++ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
2886++ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
2887++ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
2888++ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
2889++ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
2890++ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
2891++ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
2892++ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
2893++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
2894++};
2895++
2896++
2897++
2898++static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
2899++static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
2900++ u32 *sta_pause, u32 *dis_sta_map,
2901++ u32 dumptxd)
2902++{
2903++ int i, j;
2904++ u32 total_nonempty_cnt = 0;
2905++ u32 ac_num = 9, all_ac_num;
2906++
2907++ /* TDO: ac_num = 16 for mt7986 */
2908++ /* if (!is_mt7915(&dev->mt76))
2909++ ac_num = 16;
2910++ */
2911++
2912++ all_ac_num = ac_num * 4;
2913++
2914++ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
2915++ for (i = 0; i < 32; i++) {
2916++ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
2917++ u32 hfid, tfid, pktcnt, ac_num = j / ac_num, ctrl = 0;
2918++ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
2919++ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
2920++ u32 wmmidx = 0;
2921++ struct mt7915_sta *msta;
2922++ struct mt76_wcid *wcid;
2923++ struct ieee80211_sta *sta = NULL;
2924++
2925++ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
2926++ sta = wcid_to_sta(wcid);
2927++ if (!sta) {
2928++ printk("ERROR!! no found STA wcid=%d\n", sta_num);
2929++ return 0;
2930++ }
2931++ msta = container_of(wcid, struct mt7915_sta, wcid);
2932++ wmmidx = msta->vif->mt76.wmm_idx;
2933++
2934++ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_num);
2935++
2936++ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
2937++ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
2938++ fl_que_ctrl[0] |= (ac_num << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
2939++ fl_que_ctrl[0] |= sta_num;
2940++ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
2941++ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
2942++ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
2943++ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
2944++ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
2945++ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
2946++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
2947++ tfid, hfid, pktcnt);
2948++
2949++ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
2950++ ctrl = 2;
2951++
2952++ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
2953++ ctrl = 1;
2954++
2955++ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
2956++ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
2957++
2958++ total_nonempty_cnt++;
2959++
2960++ // TODO
2961++ //if (pktcnt > 0 && dumptxd > 0)
2962++ // ShowTXDInfo(pAd, hfid);
2963++ }
2964++ }
2965++ }
2966++
2967++ return total_nonempty_cnt;
2968++}
2969++
2970++static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
2971++{
2972++ int i;
2973++
2974++ seq_printf(s, "Nonempty TXCMD Q info:\n");
2975++ for (i = 0; i < 31; i++) {
2976++ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
2977++ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
2978++
2979++ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
2980++ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
2981++ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
2982++ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
2983++ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
2984++ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
2985++ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
2986++ } else
2987++ continue;
2988++
2989++ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
2990++ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
2991++ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
2992++ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
2993++ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
2994++ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
2995++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
2996++ tfid, hfid, pktcnt);
2997++ }
2998++ }
2999++}
3000++
3001++static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3002++{
3003++ int i;
3004++ int cr_num = 9, all_cr_num;
3005++ u32 ac , index;
3006++
3007++ /* TDO: cr_num = 16 for mt7986 */
3008++ /*
3009++ if(!is_mt7915(&dev->mt76))
3010++ cr_num = 16;
3011++ */
3012++ all_cr_num = cr_num * 4;
3013++
3014++ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3015++
3016++ for(i = 0; i < all_cr_num; i++) {
3017++ ac = i / cr_num;
3018++ index = i % cr_num;
3019++ ple_stat[i + 1] =
3020++ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3021++
3022++ }
3023++}
3024++
3025++static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3026++{
3027++ int i;
3028++
3029++ for(i = 0; i < CR_NUM_OF_AC; i++) {
3030++ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3031++ }
3032++}
3033++
3034++static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3035++{
3036++ int i;
3037++
3038++ for(i = 0; i < CR_NUM_OF_AC; i++) {
3039++ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3040++ }
3041++}
3042++
3043++static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3044++{
3045++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3046++ u32 ple_buf_ctrl, pg_sz, pg_num;
3047++ u32 ple_stat[65] = {0}, pg_flow_ctrl[8] = {0};
3048++ u32 ple_native_txcmd_stat;
3049++ u32 ple_txcmd_stat;
3050++ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3051++ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3052++ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3053++ int i, j;
3054++ u32 ac_num = 9, all_ac_num;
3055++
3056++ /* TDO: ac_num = 16 for mt7986 */
3057++ /* if (!is_mt7915(&dev->mt76))
3058++ ac_num = 16;
3059++ */
3060++
3061++ all_ac_num = ac_num * 4;
3062++
3063++ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3064++ chip_get_ple_acq_stat(dev, ple_stat);
3065++ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3066++ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3067++ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3068++ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3069++ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3070++ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3071++ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3072++ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3073++ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3074++ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3075++ chip_get_dis_sta_map(dev, dis_sta_map);
3076++ chip_get_sta_pause(dev, sta_pause);
3077++
3078++ seq_printf(s, "PLE Configuration Info:\n");
3079++ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3080++ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3081++
3082++ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3083++ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3084++ pg_sz, (pg_sz == 1 ? 128 : 64));
3085++ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3086++ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3087++
3088++ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3089++ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3090++
3091++ /* Page Flow Control */
3092++ seq_printf(s, "PLE Page Flow Control:\n");
3093++ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3094++ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3095++ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3096++
3097++ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3098++ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3099++
3100++ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3101++ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3102++ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3103++
3104++ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3105++ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3106++ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3107++ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3108++ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3109++ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3110++ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3111++
3112++ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3113++ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3114++ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3115++
3116++ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3117++ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3118++ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3119++
3120++ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3121++ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3122++ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3123++ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3124++ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3125++ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3126++ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3127++
3128++ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3129++ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3130++ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3131++
3132++ seq_printf(s, "\tReserved page counter of CPU group(0x820c0150): 0x%08x\n", pg_flow_ctrl[4]);
3133++ seq_printf(s, "\tCPU group page status(0x820c0154): 0x%08x\n", pg_flow_ctrl[5]);
3134++ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3135++ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3136++ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3137++
3138++ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3139++ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3140++ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3141++
3142++ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3143++ for (j = 0; j < all_ac_num; j++) {
3144++ if (j % ac_num == 0) {
3145++ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3146++ }
3147++
3148++ for (i = 0; i < all_ac_num; i++) {
3149++ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3150++ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3151++ }
3152++ }
3153++ }
3154++
3155++ seq_printf(s, "\n");
3156++ }
3157++
3158++ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3159++
3160++ seq_printf(s, "Nonempty Q info:\n");
3161++
3162++ for (i = 0; i < all_ac_num; i++) {
3163++ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3164++ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3165++
3166++ if (ple_queue_empty_info[i].QueueName != NULL) {
3167++ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3168++ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3169++ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3170++ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3171++ } else
3172++ continue;
3173++
3174++ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3175++ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3176++ /* band0 set TGID 0, bit31 = 0 */
3177++ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3178++ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3179++ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3180++ /* band1 set TGID 1, bit31 = 1 */
3181++ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3182++
3183++ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3184++ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3185++ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3186++ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3187++ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3188++ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3189++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3190++ tfid, hfid, pktcnt);
3191++
3192++ /* TODO */
3193++ //if (pktcnt > 0 && dumptxd > 0)
3194++ // ShowTXDInfo(pAd, hfid);
3195++ }
3196++ }
3197++
3198++ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3199++ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3200++
3201++ return 0;
3202++}
3203++
3204++typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3205++ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3206++ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3207++ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3208++} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3209++
3210++static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3211++ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3212++ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3213++ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3214++ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3215++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3216++ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3217++ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3218++ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3219++ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3220++ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3221++ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3222++ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3223++ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3224++ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3225++ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3226++ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3227++ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3228++ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3229++ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3230++ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3231++ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3232++ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3233++};
3234++
3235++static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3236++{
3237++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3238++ u32 pse_buf_ctrl, pg_sz, pg_num;
3239++ u32 pse_stat, pg_flow_ctrl[22] = {0};
3240++ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3241++ u32 max_q, min_q, rsv_pg, used_pg;
3242++ int i;
3243++
3244++ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3245++ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3246++ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3247++ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3248++ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3249++ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3250++ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3251++ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3252++ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3253++ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3254++ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3255++ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3256++ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3257++ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3258++ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3259++ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3260++ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3261++ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3262++ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3263++ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3264++ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3265++ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3266++ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3267++ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3268++
3269++ /* Configuration Info */
3270++ seq_printf(s, "PSE Configuration Info:\n");
3271++ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3272++ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3273++
3274++ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3275++ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3276++ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3277++ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3278++
3279++ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3280++
3281++ /* Page Flow Control */
3282++ seq_printf(s, "PSE Page Flow Control:\n");
3283++ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3284++ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3285++ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3286++
3287++ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3288++ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3289++
3290++ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3291++ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3292++
3293++ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3294++ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3295++ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3296++ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3297++ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3298++ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3299++ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3300++ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3301++ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3302++ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3303++ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3304++ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3305++ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3306++ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3307++ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3308++ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3309++ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3310++
3311++ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3312++ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3313++ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3314++ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3315++ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3316++ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3317++ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3318++ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3319++ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3320++ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3321++ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3322++ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3323++ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3324++ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3325++ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3326++ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3327++ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3328++ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3329++ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3330++ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3331++ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3332++ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3333++ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3334++ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3335++ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3336++ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3337++ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3338++ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3339++ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3340++ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3341++ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3342++ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3343++ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3344++
3345++ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3346++ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3347++ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3348++ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3349++ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3350++ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3351++ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3352++ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3353++
3354++ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3355++ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3356++ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3357++ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3358++ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3359++ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3360++ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3361++ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3362++
3363++ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3364++ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3365++ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3366++ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3367++ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3368++ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3369++ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3370++ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3371++
3372++ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3373++ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3374++ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3375++ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3376++ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3377++ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3378++ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3379++ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3380++
3381++ /* Queue Empty Status */
3382++ seq_printf(s, "PSE Queue Empty Status:\n");
3383++ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3384++ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3385++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3386++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3387++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3388++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3389++
3390++ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3391++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3392++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3393++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3394++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3395++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3396++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3397++
3398++ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3399++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3400++ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3401++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3402++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3403++ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3404++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3405++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3406++ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3407++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3408++ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3409++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3410++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3411++ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3412++ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3413++ seq_printf(s, "Nonempty Q info:\n");
3414++
3415++ for (i = 0; i < 31; i++) {
3416++ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3417++ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3418++
3419++ if (pse_queue_empty_info[i].QueueName != NULL) {
3420++ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3421++ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3422++ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3423++ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3424++ } else
3425++ continue;
3426++
3427++ fl_que_ctrl[0] |= (0x1 << 31);
3428++
3429++ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3430++ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3431++ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3432++
3433++ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3434++ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3435++ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3436++ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3437++ tfid, hfid, pktcnt);
3438++ }
3439++ }
3440++
3441++ return 0;
3442++}
3443++
3444++static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3445++{
3446++#define BSS_NUM 4
3447++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3448++ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3449++ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3450++ u32 mbxsdr[BSS_NUM][7];
3451++ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3452++ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3453++ u32 mu_cnt[5];
3454++ u32 ampdu_cnt[3];
3455++ unsigned long per;
3456++
3457++ seq_printf(s, "Band %d MIB Status\n", band_idx);
3458++ seq_printf(s, "===============================\n");
3459++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3460++ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3461++ if (is_mt7915(&dev->mt76)) {
3462++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3463++ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3464++ }
3465++
3466++ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3467++ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3468++ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3469++ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3470++ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3471++ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3472++ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3473++ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3474++ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3475++ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3476++ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3477++ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3478++ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3479++ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3480++ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3481++ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3482++
3483++ seq_printf(s, "===Phy/Timing Related Counters===\n");
3484++ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3485++ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3486++ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3487++ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3488++ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3489++ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3490++ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3491++ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3492++ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3493++ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3494++
3495++ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3496++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3497++ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3498++ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3499++ dev->dbg.bcn_total_cnt[band_idx] = 0;
3500++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3501++ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3502++ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3503++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3504++ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3505++ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3506++ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3507++ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3508++ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3509++ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3510++ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3511++
3512++ seq_printf(s, "===MU Related Counters===\n");
3513++ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3514++ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3515++ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3516++ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3517++ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3518++ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3519++ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3520++ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3521++ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3522++ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3523++
3524++ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3525++ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3526++ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3527++
3528++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3529++ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3530++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3531++ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3532++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3533++ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3534++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3535++ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3536++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3537++ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3538++ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3539++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3540++ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3541++
3542++ if (is_mt7915(&dev->mt76)) {
3543++ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3544++ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3545++ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3546++
3547++ for (idx = 0; idx < BSS_NUM; idx++) {
3548++ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3549++ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3550++ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3551++ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3552++ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3553++ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3554++ }
3555++
3556++ for (idx = 0; idx < BSS_NUM; idx++) {
3557++ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3558++ idx, btcr[idx], btdcr[idx], btbcr[idx],
3559++ brcr[idx], brdcr[idx], brbcr[idx]);
3560++ }
3561++
3562++ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3563++ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3564++ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3565++
3566++ for (idx = 0; idx < BSS_NUM; idx++) {
3567++ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3568++ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3569++ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3570++ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3571++ }
3572++
3573++ for (idx = 0; idx < BSS_NUM; idx++) {
3574++ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3575++ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3576++ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3577++ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3578++ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3579++ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3580++ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3581++ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3582++ }
3583++
3584++ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3585++ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3586++ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3587++
3588++ for (idx = 0; idx < 16; idx++) {
3589++ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3590++ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3591++ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3592++ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3593++ }
3594++
3595++ for (idx = 0; idx < 16; idx++) {
3596++ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3597++ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3598++ }
3599++ return 0;
3600++ } else {
3601++ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3602++ u8 bss_nums = BSS_NUM;
3603++
3604++ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3605++ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3606++ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3607++
3608++ for (idx = 0; idx < BSS_NUM; idx++) {
3609++ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3610++ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3611++ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3612++ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3613++ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3614++ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3615++
3616++ if ((idx % 2) == 0) {
3617++ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3618++ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3619++ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3620++ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3621++ } else {
3622++ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3623++ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3624++ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3625++ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3626++ }
3627++ }
3628++
3629++ for (idx = 0; idx < BSS_NUM; idx++) {
3630++ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3631++ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
3632++ }
3633++
3634++ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3635++ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3636++ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3637++
3638++ for (idx = 0; idx < BSS_NUM; idx++) {
3639++ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
3640++ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
3641++ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
3642++ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
3643++ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
3644++ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
3645++ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
3646++
3647++ if ((idx % 2) == 0) {
3648++ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
3649++ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
3650++ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
3651++ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
3652++ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
3653++ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
3654++ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
3655++ } else {
3656++ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
3657++ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
3658++ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
3659++ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
3660++ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
3661++ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
3662++ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
3663++ }
3664++ }
3665++
3666++ for (idx = 0; idx < BSS_NUM; idx++) {
3667++ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3668++ idx,
3669++ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
3670++ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
3671++ }
3672++
3673++ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3674++ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3675++ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3676++
3677++ for (idx = 0; idx < 16; idx++) {
3678++ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3679++ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3680++ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3681++ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3682++
3683++ if ((idx % 2) == 0) {
3684++ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3685++ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3686++ } else {
3687++ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3688++ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3689++ }
3690++ }
3691++
3692++ for (idx = 0; idx < 16; idx++) {
3693++ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3694++ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3695++ }
3696++ }
3697++
3698++ seq_printf(s, "===Dummy delimiter insertion result===\n");
3699++ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3700++ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
3701++ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
3702++ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3703++ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
3704++ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
3705++ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
3706++ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
3707++ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
3708++
3709++ return 0;
3710++}
3711++
3712++static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
3713++{
3714++ mt7915_mibinfo_read_per_band(s, 0);
3715++ return 0;
3716++}
3717++
3718++static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
3719++{
3720++ mt7915_mibinfo_read_per_band(s, 1);
3721++ return 0;
3722++}
3723++
3724++static int mt7915_token_read(struct seq_file *s, void *data)
3725++{
3726++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3727++ int id, count = 0;
3728++ struct mt76_txwi_cache *txwi;
3729++
3730++ seq_printf(s, "Cut through token:\n");
3731++ spin_lock_bh(&dev->mt76.token_lock);
3732++ idr_for_each_entry(&dev->mt76.token, txwi, id) {
3733++ seq_printf(s, "%4d ", id);
3734++ count++;
3735++ if (count % 8 == 0)
3736++ seq_printf(s, "\n");
3737++ }
3738++ spin_unlock_bh(&dev->mt76.token_lock);
3739++ seq_printf(s, "\n");
3740++
3741++ return 0;
3742++}
3743++
3744++struct txd_l {
3745++ u32 txd_0;
3746++ u32 txd_1;
3747++ u32 txd_2;
3748++ u32 txd_3;
3749++ u32 txd_4;
3750++ u32 txd_5;
3751++ u32 txd_6;
3752++ u32 txd_7;
3753++} __packed;
3754++
3755++char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
3756++char *hdr_fmt_str[] = {
3757++ "Non-80211-Frame",
3758++ "Command-Frame",
3759++ "Normal-80211-Frame",
3760++ "enhanced-80211-Frame",
3761++};
3762++/* TMAC_TXD_1.hdr_format */
3763++#define TMI_HDR_FT_NON_80211 0x0
3764++#define TMI_HDR_FT_CMD 0x1
3765++#define TMI_HDR_FT_NOR_80211 0x2
3766++#define TMI_HDR_FT_ENH_80211 0x3
3767++
3768++void mt7915_dump_tmac_info(u8 *tmac_info)
3769++{
3770++ struct txd_l *txd = (struct txd_l *)tmac_info;
3771++
3772++ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
3773++ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
3774++
3775++ printk("TMAC_TXD Fields:\n");
3776++ printk("\tTMAC_TXD_0:\n");
3777++
3778++ /* DW0 */
3779++ /* TX Byte Count [15:0] */
3780++ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
3781++
3782++ /* PKT_FT: Packet Format [24:23] */
3783++ printk("\t\tpkt_ft = %ld(%s)\n",
3784++ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
3785++ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
3786++
3787++ /* Q_IDX [31:25] */
3788++ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
3789++
3790++ printk("\tTMAC_TXD_1:\n");
3791++
3792++ /* DW1 */
3793++ /* WLAN Indec [9:0] */
3794++ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
3795++
3796++ /* VTA [10] */
3797++ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
3798++
3799++ /* HF: Header Format [17:16] */
3800++ printk("\t\tHdrFmt = %ld(%s)\n",
3801++ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
3802++ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
3803++ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
3804++
3805++ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
3806++ case TMI_HDR_FT_NON_80211:
3807++ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
3808++ printk("\t\t\tMRD = %d, EOSP = %d,\
3809++ RMVL = %d, VLAN = %d, ETYP = %d\n",
3810++ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
3811++ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
3812++ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
3813++ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
3814++ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
3815++ break;
3816++ case TMI_HDR_FT_NOR_80211:
3817++ /* HEADER_LENGTH [15:11] */
3818++ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
3819++ break;
3820++
3821++ case TMI_HDR_FT_ENH_80211:
3822++ /* EOSP [12], AMS [13] */
3823++ printk("\t\t\tEOSP = %d, AMS = %d\n",
3824++ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
3825++ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
3826++ break;
3827++ }
3828++
3829++ /* Header Padding [19:18] */
3830++ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
3831++
3832++ /* TID [22:20] */
3833++ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
3834++
3835++
3836++ /* UtxB/AMSDU_C/AMSDU [23] */
3837++ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
3838++
3839++ /* OM [29:24] */
3840++ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
3841++
3842++
3843++ /* TGID [30] */
3844++ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
3845++
3846++
3847++ /* FT [31] */
3848++ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
3849++
3850++ printk("\tTMAC_TXD_2:\n");
3851++ /* DW2 */
3852++ /* Subtype [3:0] */
3853++ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
3854++
3855++ /* Type[5:4] */
3856++ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
3857++
3858++ /* NDP [6] */
3859++ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
3860++
3861++ /* NDPA [7] */
3862++ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
3863++
3864++ /* SD [8] */
3865++ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
3866++
3867++ /* RTS [9] */
3868++ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
3869++
3870++ /* BM [10] */
3871++ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
3872++
3873++ /* B [11] */
3874++ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
3875++
3876++ /* DU [12] */
3877++ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
3878++
3879++ /* HE [13] */
3880++ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
3881++
3882++ /* FRAG [15:14] */
3883++ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
3884++
3885++
3886++ /* Remaining Life Time [23:16]*/
3887++ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
3888++ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
3889++
3890++ /* Power Offset [29:24] */
3891++ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
3892++
3893++ /* FRM [30] */
3894++ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
3895++
3896++ /* FR[31] */
3897++ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
3898++
3899++
3900++ printk("\tTMAC_TXD_3:\n");
3901++
3902++ /* DW3 */
3903++ /* NA [0] */
3904++ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
3905++
3906++ /* PF [1] */
3907++ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
3908++
3909++ /* EMRD [2] */
3910++ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
3911++
3912++ /* EEOSP [3] */
3913++ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
3914++
3915++ /* DAS [4] */
3916++ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
3917++
3918++ /* TM [5] */
3919++ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
3920++
3921++ /* TX Count [10:6] */
3922++ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
3923++
3924++ /* Remaining TX Count [15:11] */
3925++ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
3926++
3927++ /* SN [27:16] */
3928++ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
3929++
3930++ /* BA_DIS [28] */
3931++ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
3932++
3933++ /* Power Management [29] */
3934++ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
3935++
3936++ /* PN_VLD [30] */
3937++ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
3938++
3939++ /* SN_VLD [31] */
3940++ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
3941++
3942++
3943++ /* DW4 */
3944++ printk("\tTMAC_TXD_4:\n");
3945++
3946++ /* PN_LOW [31:0] */
3947++ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
3948++
3949++
3950++ /* DW5 */
3951++ printk("\tTMAC_TXD_5:\n");
3952++
3953++ /* PID [7:0] */
3954++ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
3955++
3956++ /* TXSFM [8] */
3957++ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
3958++
3959++ /* TXS2M [9] */
3960++ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
3961++
3962++ /* TXS2H [10] */
3963++ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
3964++
3965++ /* ADD_BA [14] */
3966++ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
3967++
3968++ /* MD [15] */
3969++ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
3970++
3971++ /* PN_HIGH [31:16] */
3972++ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
3973++
3974++ /* DW6 */
3975++ printk("\tTMAC_TXD_6:\n");
3976++
3977++ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
3978++ /* Fixed BandWidth mode [2:0] */
3979++ printk("\t\tbw = %ld\n", FIELD_GET(MT_TXD6_BW, txd->txd_6));
3980++
3981++ /* DYN_BW [3] */
3982++ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
3983++
3984++ /* ANT_ID [7:4] */
3985++ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
3986++
3987++ /* SPE_IDX_SEL [10] */
3988++ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
3989++
3990++ /* LDPC [11] */
3991++ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
3992++
3993++ /* HELTF Type[13:12] */
3994++ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
3995++
3996++ /* GI Type [15:14] */
3997++ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
3998++
3999++ /* Rate to be Fixed [29:16] */
4000++ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4001++ }
4002++
4003++ /* TXEBF [30] */
4004++ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4005++
4006++ /* TXIBF [31] */
4007++ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4008++
4009++ /* DW7 */
4010++ printk("\tTMAC_TXD_7:\n");
4011++
4012++ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4013++ /* SW Tx Time [9:0] */
4014++ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4015++ } else {
4016++ /* TXD Arrival Time [9:0] */
4017++ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4018++ }
4019++
4020++ /* HW_AMSDU_CAP [10] */
4021++ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4022++
4023++ /* SPE_IDX [15:11] */
4024++ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4025++ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4026++ }
4027++
4028++ /* PSE_FID [27:16] */
4029++ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4030++
4031++ /* Subtype [19:16] */
4032++ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4033++
4034++ /* Type [21:20] */
4035++ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4036++
4037++ /* CTXD_CNT [25:23] */
4038++ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4039++
4040++ /* CTXD [26] */
4041++ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4042++
4043++ /* I [28] */
4044++ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4045++
4046++ /* UT [29] */
4047++ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4048++
4049++ /* TXDLEN [31:30] */
4050++ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4051++}
4052++
4053++
4054++static int mt7915_token_txd_read(struct seq_file *s, void *data)
4055++{
4056++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4057++ struct mt76_txwi_cache *t;
4058++ u8* txwi;
4059++
4060++ seq_printf(s, "\n");
4061++ spin_lock_bh(&dev->mt76.token_lock);
4062++
4063++ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4064++
4065++ spin_unlock_bh(&dev->mt76.token_lock);
4066++ if (t != NULL) {
4067++ struct mt76_dev *mdev = &dev->mt76;
4068++ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4069++ mt7915_dump_tmac_info((u8*) txwi);
4070++ seq_printf(s, "\n");
4071++ printk("[SKB]\n");
4072++ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4073++ seq_printf(s, "\n");
4074++ }
4075++ return 0;
4076++}
4077++
4078++static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4079++{
4080++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4081++ u32 ple_stat[8] = {0}, total_amsdu = 0;
4082++ u8 i;
4083++
4084++ for (i = 0; i < 8; i++)
4085++ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4086++
4087++ seq_printf(s, "TXD counter status of MSDU:\n");
4088++
4089++ for (i = 0; i < 8; i++)
4090++ total_amsdu += ple_stat[i];
4091++
4092++ for (i = 0; i < 8; i++) {
4093++ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4094++ if (total_amsdu != 0)
4095++ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4096++ else
4097++ seq_printf(s, "\n");
4098++ }
4099++
4100++ return 0;
4101++
4102++}
4103++
4104++static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4105++{
4106++ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4107++ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4108++
4109++ seq_printf(s, "Band %d AGG Status\n", band_idx);
4110++ seq_printf(s, "===============================\n");
4111++ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4112++ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4113++ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4114++ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4115++ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4116++
4117++ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4118++ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4119++ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4120++ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4121++ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4122++
4123++ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4124++ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4125++ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4126++ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4127++ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4128++
4129++ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4130++ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4131++ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4132++ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4133++ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4134++
4135++ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4136++ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4137++
4138++ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4139++ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4140++ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4141++ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4142++ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4143++
4144++ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4145++ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4146++ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4147++ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4148++ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4149++
4150++ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4151++ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4152++ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4153++ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4154++ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4155++
4156++
4157++ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4158++ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4159++ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4160++ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4161++
4162++ seq_printf(s, "===AMPDU Related Counters===\n");
4163++
4164++ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4165++ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4166++ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4167++ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4168++ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4169++
4170++ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4171++ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4172++ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4173++ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4174++ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4175++
4176++ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4177++ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4178++ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4179++ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4180++ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4181++
4182++ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4183++ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4184++ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4185++ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4186++
4187++ /* Need to add 1 after read from AGG_RANG_SEL CR */
4188++ for (idx = 0; idx < 15; idx++)
4189++ agg_rang_sel[idx]++;
4190++
4191++ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4192++ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4193++ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4194++ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4195++ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4196++ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4197++ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4198++ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4199++
4200++ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4201++ agg_rang_sel[0],
4202++ agg_rang_sel[0] + 1, agg_rang_sel[1],
4203++ agg_rang_sel[1] + 1, agg_rang_sel[2],
4204++ agg_rang_sel[2] + 1, agg_rang_sel[3],
4205++ agg_rang_sel[3] + 1, agg_rang_sel[4],
4206++ agg_rang_sel[4] + 1, agg_rang_sel[5],
4207++ agg_rang_sel[5] + 1, agg_rang_sel[6],
4208++ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4209++
4210++#define BIT_0_to_15_MASK 0x0000FFFF
4211++#define BIT_15_to_31_MASK 0xFFFF0000
4212++#define SHFIT_16_BIT 16
4213++
4214++ for (idx = 3; idx < 11; idx++)
4215++ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4216++
4217++ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4218++ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4219++ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4220++ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4221++ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4222++ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4223++ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4224++ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4225++ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4226++
4227++ if (total_ampdu != 0) {
4228++ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4229++ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4230++ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4231++ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4232++ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4233++ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4234++ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4235++ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4236++ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4237++ }
4238++
4239++ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4240++ agg_rang_sel[7] + 1, agg_rang_sel[8],
4241++ agg_rang_sel[8] + 1, agg_rang_sel[9],
4242++ agg_rang_sel[9] + 1, agg_rang_sel[10],
4243++ agg_rang_sel[10] + 1, agg_rang_sel[11],
4244++ agg_rang_sel[11] + 1, agg_rang_sel[12],
4245++ agg_rang_sel[12] + 1, agg_rang_sel[13],
4246++ agg_rang_sel[13] + 1, agg_rang_sel[14],
4247++ agg_rang_sel[14] + 1);
4248++
4249++ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4250++ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4251++ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4252++ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4253++ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4254++ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4255++ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4256++ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4257++ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4258++
4259++ if (total_ampdu != 0) {
4260++ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4261++ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4262++ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4263++ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4264++ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4265++ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4266++ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4267++ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4268++ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4269++ }
4270++
4271++ return 0;
4272++}
4273++
4274++static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4275++{
4276++ mt7915_agginfo_read_per_band(s, 0);
4277++ return 0;
4278++}
4279++
4280++static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4281++{
4282++ mt7915_agginfo_read_per_band(s, 1);
4283++ return 0;
4284++}
4285++
4286++/*usage: <en> <num> <len>
4287++ en: BIT(16) 0: sw amsdu 1: hw amsdu
4288++ num: GENMASK(15, 8) range 1-8
4289++ len: GENMASK(7, 0) unit: 256 bytes */
4290++static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4291++{
4292++/* UWTBL DW 6 */
4293++#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4294++#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4295++#define WTBL_AMSDU_EN_MASK BIT(9)
4296++#define UWTBL_HW_AMSDU_DW 6
4297++
4298++ struct mt7915_dev *dev = data;
4299++ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4300++ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4301++ u32 uwtbl;
4302++
4303++ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4304++ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4305++
4306++ if (len) {
4307++ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4308++ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4309++ }
4310++
4311++ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4312++ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4313++
4314++ if (tx_amsdu & BIT(16))
4315++ uwtbl |= WTBL_AMSDU_EN_MASK;
4316++
4317++ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4318++ UWTBL_HW_AMSDU_DW, uwtbl);
4319++
4320++ return 0;
4321++}
4322++
4323++DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4324++ mt7915_sta_tx_amsdu_set, "%llx\n");
4325++
4326++static int mt7915_red_enable_set(void *data, u64 en)
4327++{
4328++ struct mt7915_dev *dev = data;
4329++
4330++ return mt7915_mcu_set_red(dev, en);
4331++}
4332++DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4333++ mt7915_red_enable_set, "%llx\n");
4334++
4335++static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4336++{
4337++ struct mt7915_dev *dev = data;
4338++
4339++ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4340++ MCU_WA_PARAM_RED_SHOW_STA,
4341++ wlan_idx, 0, true);
4342++
4343++ return 0;
4344++}
4345++DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4346++ mt7915_red_show_sta_set, "%llx\n");
4347++
4348++static int mt7915_red_target_dly_set(void *data, u64 delay)
4349++{
4350++ struct mt7915_dev *dev = data;
4351++
4352++ if (delay > 0 && delay <= 32767)
4353++ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4354++ MCU_WA_PARAM_RED_TARGET_DELAY,
4355++ delay, 0, true);
4356++
4357++ return 0;
4358++}
4359++DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4360++ mt7915_red_target_dly_set, "%llx\n");
4361++
4362++static int
4363++mt7915_txpower_level_set(void *data, u64 val)
4364++{
4365++ struct mt7915_dev *dev = data;
4366++ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4367++ mt7915_mcu_set_txpower_level(&dev->phy, val);
4368++ if (ext_phy)
4369++ mt7915_mcu_set_txpower_level(ext_phy, val);
4370++
4371++ return 0;
4372++}
4373++
4374++DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4375++ mt7915_txpower_level_set, "%lld\n");
4376++
4377++/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4378++static int
4379++mt7915_wa_set(void *data, u64 val)
4380++{
4381++ struct mt7915_dev *dev = data;
4382++ u32 arg1, arg2, arg3;
4383++
4384++ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4385++ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4386++ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4387++
4388++ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4389++
4390++ return 0;
4391++}
4392++
4393++DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4394++ "0x%llx\n");
4395++/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4396++static int
4397++mt7915_wa_query(void *data, u64 val)
4398++{
4399++ struct mt7915_dev *dev = data;
4400++ u32 arg1, arg2, arg3;
4401++
4402++ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4403++ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4404++ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4405++
4406++ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4407++
4408++ return 0;
4409++}
4410++
4411++DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4412++ "0x%llx\n");
4413++/* set wa debug level
4414++ usage:
4415++ echo 0x[arg] > fw_wa_debug
4416++ bit0 : DEBUG_WIFI_TX
4417++ bit1 : DEBUG_CMD_EVENT
4418++ bit2 : DEBUG_RED
4419++ bit3 : DEBUG_WARN
4420++ bit4 : DEBUG_WIFI_RX
4421++ bit5 : DEBUG_TIME_STAMP
4422++ bit6 : DEBUG_TX_FREE_DONE_EVENT
4423++ bit12 : DEBUG_WIFI_TXD */
4424++static int
4425++mt7915_wa_debug(void *data, u64 val)
4426++{
4427++ struct mt7915_dev *dev = data;
4428++ u32 arg;
4429++
4430++ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4431++
4432++ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4433++
4434++ return 0;
4435++}
4436++
4437++DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4438++ "0x%llx\n");
4439++
4440++int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4441++{
4442++ struct mt7915_dev *dev = phy->dev;
4443++ u32 device_id = (dev->mt76.rev) >> 16;
4444++ int i = 0;
4445++
4446++ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
4447++ if (device_id == dbg_reg_s[i].id) {
4448++ dev->dbg_reg = &dbg_reg_s[i];
4449++ break;
4450++ }
4451++ }
4452++
4453++ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4454++
4455++ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4456++ &fops_fw_debug_module);
4457++ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4458++ &fops_fw_debug_level);
4459++
4460++ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4461++ mt7915_wtbl_read);
4462++ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
4463++ mt7915_uwtbl_read);
4464++
4465++ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4466++ mt7915_trinfo_read);
4467++
4468++ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
4469++ mt7915_drr_info);
4470++
4471++ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
4472++ mt7915_pleinfo_read);
4473++
4474++ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
4475++ mt7915_pseinfo_read);
4476++
4477++ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4478++ mt7915_mibinfo_band0);
4479++ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4480++ mt7915_mibinfo_band1);
4481++
4482++ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
4483++ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
4484++ mt7915_token_read);
4485++ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
4486++ mt7915_token_txd_read);
4487++
4488++ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4489++ mt7915_amsduinfo_read);
4490++
4491++ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4492++ mt7915_agginfo_read_band0);
4493++ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4494++ mt7915_agginfo_read_band1);
4495++
4496++ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
4497++
4498++ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4499++ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4500++ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
4501++
4502++ debugfs_create_file("red_en", 0600, dir, dev,
4503++ &fops_red_en);
4504++ debugfs_create_file("red_show_sta", 0600, dir, dev,
4505++ &fops_red_show_sta);
4506++ debugfs_create_file("red_target_dly", 0600, dir, dev,
4507++ &fops_red_target_dly);
4508++
4509++ debugfs_create_file("txpower_level", 0400, dir, dev,
4510++ &fops_txpower_level);
4511++
4512++ return 0;
4513++}
4514++#endif
4515+diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
4516+new file mode 100644
4517+index 0000000..145fe78
4518+--- /dev/null
4519++++ b/mt7915/mtk_mcu.c
4520+@@ -0,0 +1,51 @@
4521++#include <linux/firmware.h>
4522++#include <linux/fs.h>
4523++#include<linux/inet.h>
4524++#include "mt7915.h"
4525++#include "mcu.h"
4526++#include "mac.h"
4527++
4528++int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
4529++{
4530++ struct mt7915_dev *dev = phy->dev;
4531++ struct mt7915_sku_val {
4532++ u8 format_id;
4533++ u8 val;
4534++ u8 band;
4535++ u8 _rsv;
4536++ } __packed req = {
4537++ .format_id = 1,
4538++ .band = phy->band_idx,
4539++ .val = !!drop_level,
4540++ };
4541++ int ret;
4542++
4543++ ret = mt76_mcu_send_msg(&dev->mt76,
4544++ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4545++ sizeof(req), true);
4546++ if (ret)
4547++ return ret;
4548++
4549++ req.format_id = 2;
4550++ if ((drop_level > 90 && drop_level < 100) || !drop_level)
4551++ req.val = 0;
4552++ else if (drop_level > 60 && drop_level <= 90)
4553++ /* reduce Pwr for 1 dB. */
4554++ req.val = 2;
4555++ else if (drop_level > 30 && drop_level <= 60)
4556++ /* reduce Pwr for 3 dB. */
4557++ req.val = 6;
4558++ else if (drop_level > 15 && drop_level <= 30)
4559++ /* reduce Pwr for 6 dB. */
4560++ req.val = 12;
4561++ else if (drop_level > 9 && drop_level <= 15)
4562++ /* reduce Pwr for 9 dB. */
4563++ req.val = 18;
4564++ else if (drop_level > 0 && drop_level <= 9)
4565++ /* reduce Pwr for 12 dB. */
4566++ req.val = 24;
4567++
4568++ return mt76_mcu_send_msg(&dev->mt76,
4569++ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4570++ sizeof(req), true);
4571++}
4572+diff --git a/tools/fwlog.c b/tools/fwlog.c
4573+index e5d4a10..58a976a 100644
4574+--- a/tools/fwlog.c
4575++++ b/tools/fwlog.c
4576+@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4577+ return path;
4578+ }
4579+
4580+-static int mt76_set_fwlog_en(const char *phyname, bool en)
4581++static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4582+ {
4583+ FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4584+
4585+@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4586+ return 1;
4587+ }
4588+
4589+- fprintf(f, "7");
4590++ if (en && val)
4591++ fprintf(f, "%s", val);
4592++ else if (en)
4593++ fprintf(f, "7");
4594++ else
4595++ fprintf(f, "0");
4596++
4597+ fclose(f);
4598+
4599+ return 0;
4600+@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4601+
4602+ int mt76_fwlog(const char *phyname, int argc, char **argv)
4603+ {
4604++#define BUF_SIZE 1504
4605+ struct sockaddr_in local = {
4606+ .sin_family = AF_INET,
4607+ .sin_addr.s_addr = INADDR_ANY,
4608+@@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4609+ .sin_family = AF_INET,
4610+ .sin_port = htons(55688),
4611+ };
4612+- char buf[1504];
4613++ char *buf = calloc(BUF_SIZE, sizeof(char));
4614+ int ret = 0;
4615+- int yes = 1;
4616++ /* int yes = 1; */
4617+ int s, fd;
4618+
4619+ if (argc < 1) {
4620+@@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4621+ return 1;
4622+ }
4623+
4624+- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4625++ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4626+ if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4627+ perror("bind");
4628+ return 1;
4629+ }
4630+
4631+- if (mt76_set_fwlog_en(phyname, true))
4632++ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4633+ return 1;
4634+
4635+ fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
4636+@@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4637+ if (!r)
4638+ continue;
4639+
4640+- if (len > sizeof(buf)) {
4641+- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4642++ if (len > BUF_SIZE) {
4643++ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4644+ ret = 1;
4645+ break;
4646+ }
4647+@@ -171,7 +178,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4648+ close(fd);
4649+
4650+ out:
4651+- mt76_set_fwlog_en(phyname, false);
4652++ mt76_set_fwlog_en(phyname, false, NULL);
4653++ free(buf);
4654+
4655+ return ret;
4656+ }
4657+--
4658+2.25.1
4659+
4660diff --git a/package/kernel/mt76/patches/1002-mt76-mt7915-csi-implement-csi-support.patch b/package/kernel/mt76/patches/1002-mt76-mt7915-csi-implement-csi-support.patch
4661new file mode 100644
4662index 00000000..eee76103
4663--- /dev/null
4664+++ b/package/kernel/mt76/patches/1002-mt76-mt7915-csi-implement-csi-support.patch
4665@@ -0,0 +1,919 @@
4666+From f8971f67f0bb2c83a0fa7efe15fb7aa0d843a9f9 Mon Sep 17 00:00:00 2001
4667+From: Shayne Chen <shayne.chen@mediatek.com>
4668+Date: Tue, 15 Feb 2022 11:02:22 +0800
4669+Subject: [PATCH 1002/1006] mt76: mt7915: csi: implement csi support
4670+
4671+---
4672+ .../wireless/mediatek/mt76/mt76_connac_mcu.h | 2 +
4673+ .../wireless/mediatek/mt76/mt7915/Makefile | 4 +-
4674+ .../net/wireless/mediatek/mt76/mt7915/init.c | 39 ++
4675+ .../net/wireless/mediatek/mt76/mt7915/mcu.c | 111 +++++
4676+ .../net/wireless/mediatek/mt76/mt7915/mcu.h | 76 +++
4677+ .../wireless/mediatek/mt76/mt7915/mt7915.h | 20 +
4678+ .../wireless/mediatek/mt76/mt7915/vendor.c | 452 ++++++++++++++++++
4679+ .../wireless/mediatek/mt76/mt7915/vendor.h | 60 +++
4680+ 8 files changed, 762 insertions(+), 2 deletions(-)
4681+ create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/vendor.c
4682+ create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/vendor.h
4683+
4684+diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
4685+index d4a56f3..e959d4c 100644
4686+--- a/mt76_connac_mcu.h
4687++++ b/mt76_connac_mcu.h
4688+@@ -820,6 +820,7 @@ enum {
4689+ MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
4690+ MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
4691+ MCU_EXT_EVENT_MURU_CTRL = 0x9f,
4692++ MCU_EXT_EVENT_CSI_REPORT = 0xc2,
4693+ };
4694+
4695+ enum {
4696+@@ -990,6 +991,7 @@ enum {
4697+ MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
4698+ MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
4699+ MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
4700++ MCU_EXT_CMD_CSI_CTRL = 0xc2,
4701+ };
4702+
4703+ enum {
4704+diff --git a/mt7915/Makefile b/mt7915/Makefile
4705+index a3474e2..e272c82 100644
4706+--- a/mt7915/Makefile
4707++++ b/mt7915/Makefile
4708+@@ -1,9 +1,9 @@
4709+ # SPDX-License-Identifier: ISC
4710+-
4711++EXTRA_CFLAGS += -DCONFIG_MTK_VENDOR
4712+ obj-$(CONFIG_MT7915E) += mt7915e.o
4713+
4714+ mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
4715+- debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
4716++ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o vendor.o
4717+
4718+ mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
4719+ mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
4720+\ No newline at end of file
4721+diff --git a/mt7915/init.c b/mt7915/init.c
4722+index 553d1f5..96a1bb4 100644
4723+--- a/mt7915/init.c
4724++++ b/mt7915/init.c
4725+@@ -532,6 +532,12 @@ static int mt7915_register_ext_phy(struct mt7915_dev *dev)
4726+ if (ret)
4727+ goto error;
4728+
4729++#ifdef CONFIG_MTK_VENDOR
4730++ INIT_LIST_HEAD(&phy->csi.csi_list);
4731++ spin_lock_init(&phy->csi.csi_lock);
4732++ mt7915_vendor_register(phy);
4733++#endif
4734++
4735+ ret = mt76_register_phy(mphy, true, mt76_rates,
4736+ ARRAY_SIZE(mt76_rates));
4737+ if (ret)
4738+@@ -994,6 +1000,25 @@ void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
4739+ }
4740+ }
4741+
4742++#ifdef CONFIG_MTK_VENDOR
4743++static int mt7915_unregister_features(struct mt7915_phy *phy)
4744++{
4745++ struct csi_data *c, *tmp_c;
4746++
4747++ spin_lock_bh(&phy->csi.csi_lock);
4748++ phy->csi.enable = 0;
4749++
4750++ list_for_each_entry_safe(c, tmp_c, &phy->csi.csi_list, node) {
4751++ list_del(&c->node);
4752++ kfree(c);
4753++ }
4754++ spin_unlock_bh(&phy->csi.csi_lock);
4755++
4756++
4757++ return 0;
4758++}
4759++#endif
4760++
4761+ static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
4762+ {
4763+ struct mt7915_phy *phy = mt7915_ext_phy(dev);
4764+@@ -1002,6 +1027,10 @@ static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
4765+ if (!phy)
4766+ return;
4767+
4768++#ifdef CONFIG_MTK_VENDOR
4769++ mt7915_unregister_features(phy);
4770++#endif
4771++
4772+ mt7915_unregister_thermal(phy);
4773+ mt76_unregister_phy(mphy);
4774+ ieee80211_free_hw(mphy->hw);
4775+@@ -1035,6 +1064,12 @@ int mt7915_register_device(struct mt7915_dev *dev)
4776+ dev->mt76.test_ops = &mt7915_testmode_ops;
4777+ #endif
4778+
4779++#ifdef CONFIG_MTK_VENDOR
4780++ INIT_LIST_HEAD(&dev->phy.csi.csi_list);
4781++ spin_lock_init(&dev->phy.csi.csi_lock);
4782++ mt7915_vendor_register(&dev->phy);
4783++#endif
4784++
4785+ /* init led callbacks */
4786+ if (IS_ENABLED(CONFIG_MT76_LEDS)) {
4787+ dev->mt76.led_cdev.brightness_set = mt7915_led_set_brightness;
4788+@@ -1069,6 +1104,10 @@ void mt7915_unregister_device(struct mt7915_dev *dev)
4789+ mt7915_dma_cleanup(dev);
4790+ tasklet_disable(&dev->irq_tasklet);
4791+
4792++#ifdef CONFIG_MTK_VENDOR
4793++ mt7915_unregister_features(&dev->phy);
4794++#endif
4795++
4796+ if (is_mt7986(&dev->mt76))
4797+ mt7986_wmac_disable(dev);
4798+
4799+diff --git a/mt7915/mcu.c b/mt7915/mcu.c
4800+index f9215f4..f6897bf 100644
4801+--- a/mt7915/mcu.c
4802++++ b/mt7915/mcu.c
4803+@@ -89,6 +89,10 @@ struct mt7915_fw_region {
4804+ #define HE_PHY(p, c) u8_get_bits(c, IEEE80211_HE_PHY_##p)
4805+ #define HE_MAC(m, c) u8_get_bits(c, IEEE80211_HE_MAC_##m)
4806+
4807++#ifdef CONFIG_MTK_VENDOR
4808++static int mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb);
4809++#endif
4810++
4811+ static u8
4812+ mt7915_mcu_get_sta_nss(u16 mcs_map)
4813+ {
4814+@@ -449,6 +453,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
4815+ case MCU_EXT_EVENT_FW_LOG_2_HOST:
4816+ mt7915_mcu_rx_log_message(dev, skb);
4817+ break;
4818++#ifdef CONFIG_MTK_VENDOR
4819++ case MCU_EXT_EVENT_CSI_REPORT:
4820++ mt7915_mcu_report_csi(dev, skb);
4821++ break;
4822++#endif
4823+ case MCU_EXT_EVENT_BCC_NOTIFY:
4824+ mt7915_mcu_rx_bcc_notify(dev, skb);
4825+ break;
4826+@@ -3594,6 +3603,108 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
4827+ &req, sizeof(req), true);
4828+ }
4829+
4830++#ifdef CONFIG_MTK_VENDOR
4831++int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
4832++ u8 cfg, u8 v1, u32 v2, u8 *mac_addr)
4833++{
4834++ struct mt7915_dev *dev = phy->dev;
4835++ struct mt7915_mcu_csi req = {
4836++ .band = phy != &dev->phy,
4837++ .mode = mode,
4838++ .cfg = cfg,
4839++ .v1 = v1,
4840++ .v2 = cpu_to_le32(v2),
4841++ };
4842++
4843++ if (is_valid_ether_addr(mac_addr))
4844++ ether_addr_copy(req.mac_addr, mac_addr);
4845++
4846++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CSI_CTRL), &req,
4847++ sizeof(req), false);
4848++}
4849++
4850++static int
4851++mt7915_mcu_report_csi(struct mt7915_dev *dev, struct sk_buff *skb)
4852++{
4853++ struct mt7915_mcu_rxd *rxd = (struct mt7915_mcu_rxd *)skb->data;
4854++ struct mt7915_phy *phy = &dev->phy;
4855++ struct mt7915_mcu_csi_report *cr;
4856++ struct csi_data *csi;
4857++ int len, i;
4858++
4859++ skb_pull(skb, sizeof(struct mt7915_mcu_rxd));
4860++
4861++ len = le16_to_cpu(rxd->len) - sizeof(struct mt7915_mcu_rxd) + 24;
4862++ if (len < sizeof(*cr))
4863++ return -EINVAL;
4864++
4865++ cr = (struct mt7915_mcu_csi_report *)skb->data;
4866++
4867++ if (phy->csi.interval &&
4868++ le32_to_cpu(cr->ts) < phy->csi.last_record + phy->csi.interval)
4869++ return 0;
4870++
4871++ csi = kzalloc(sizeof(*csi), GFP_KERNEL);
4872++ if (!csi)
4873++ return -ENOMEM;
4874++
4875++#define SET_CSI_DATA(_field) csi->_field = le32_to_cpu(cr->_field)
4876++ SET_CSI_DATA(ch_bw);
4877++ SET_CSI_DATA(rssi);
4878++ SET_CSI_DATA(snr);
4879++ SET_CSI_DATA(data_num);
4880++ SET_CSI_DATA(data_bw);
4881++ SET_CSI_DATA(pri_ch_idx);
4882++ SET_CSI_DATA(info);
4883++ SET_CSI_DATA(rx_mode);
4884++ SET_CSI_DATA(h_idx);
4885++ SET_CSI_DATA(ts);
4886++
4887++ SET_CSI_DATA(band);
4888++ if (csi->band && !phy->band_idx)
4889++ phy = mt7915_ext_phy(dev);
4890++#undef SET_CSI_DATA
4891++
4892++ for (i = 0; i < csi->data_num; i++) {
4893++ csi->data_i[i] = le16_to_cpu(cr->data_i[i]);
4894++ csi->data_q[i] = le16_to_cpu(cr->data_q[i]);
4895++ }
4896++
4897++ memcpy(csi->ta, cr->ta, ETH_ALEN);
4898++ csi->tx_idx = le32_get_bits(cr->trx_idx, GENMASK(31, 16));
4899++ csi->rx_idx = le32_get_bits(cr->trx_idx, GENMASK(15, 0));
4900++
4901++ INIT_LIST_HEAD(&csi->node);
4902++ spin_lock_bh(&phy->csi.csi_lock);
4903++
4904++ if (!phy->csi.enable) {
4905++ kfree(csi);
4906++ spin_unlock_bh(&phy->csi.csi_lock);
4907++ return 0;
4908++ }
4909++
4910++ list_add_tail(&csi->node, &phy->csi.csi_list);
4911++ phy->csi.count++;
4912++
4913++ if (phy->csi.count > CSI_MAX_BUF_NUM) {
4914++ struct csi_data *old;
4915++
4916++ old = list_first_entry(&phy->csi.csi_list,
4917++ struct csi_data, node);
4918++
4919++ list_del(&old->node);
4920++ kfree(old);
4921++ phy->csi.count--;
4922++ }
4923++
4924++ if (csi->h_idx & BIT(15)) /* last chain */
4925++ phy->csi.last_record = csi->ts;
4926++ spin_unlock_bh(&phy->csi.csi_lock);
4927++
4928++ return 0;
4929++}
4930++#endif
4931++
4932+ #ifdef MTK_DEBUG
4933+ int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
4934+ {
4935+diff --git a/mt7915/mcu.h b/mt7915/mcu.h
4936+index f1fd983..372125a 100644
4937+--- a/mt7915/mcu.h
4938++++ b/mt7915/mcu.h
4939+@@ -492,4 +492,80 @@ enum {
4940+ sizeof(struct bss_info_bcn_mbss) + \
4941+ sizeof(struct bss_info_bcn_cont))
4942+
4943++#ifdef CONFIG_MTK_VENDOR
4944++struct mt7915_mcu_csi {
4945++ u8 band;
4946++ u8 mode;
4947++ u8 cfg;
4948++ u8 v1;
4949++ __le32 v2;
4950++ u8 mac_addr[ETH_ALEN];
4951++ u8 _rsv[34];
4952++} __packed;
4953++
4954++struct csi_tlv {
4955++ __le32 tag;
4956++ __le32 len;
4957++} __packed;
4958++
4959++#define CSI_MAX_COUNT 256
4960++#define CSI_MAX_BUF_NUM 3000
4961++
4962++struct mt7915_mcu_csi_report {
4963++ struct csi_tlv _t0;
4964++ __le32 ver;
4965++ struct csi_tlv _t1;
4966++ __le32 ch_bw;
4967++ struct csi_tlv _t2;
4968++ __le32 rssi;
4969++ struct csi_tlv _t3;
4970++ __le32 snr;
4971++ struct csi_tlv _t4;
4972++ __le32 band;
4973++ struct csi_tlv _t5;
4974++ __le32 data_num;
4975++ struct csi_tlv _t6;
4976++ __le16 data_i[CSI_MAX_COUNT];
4977++ struct csi_tlv _t7;
4978++ __le16 data_q[CSI_MAX_COUNT];
4979++ struct csi_tlv _t8;
4980++ __le32 data_bw;
4981++ struct csi_tlv _t9;
4982++ __le32 pri_ch_idx;
4983++ struct csi_tlv _t10;
4984++ u8 ta[8];
4985++ struct csi_tlv _t11;
4986++ __le32 info;
4987++ struct csi_tlv _t12;
4988++ __le32 rx_mode;
4989++ struct csi_tlv _t17;
4990++ __le32 h_idx;
4991++ struct csi_tlv _t18;
4992++ __le32 trx_idx;
4993++ struct csi_tlv _t19;
4994++ __le32 ts;
4995++} __packed;
4996++
4997++struct csi_data {
4998++ u8 ch_bw;
4999++ u16 data_num;
5000++ s16 data_i[CSI_MAX_COUNT];
5001++ s16 data_q[CSI_MAX_COUNT];
5002++ u8 band;
5003++ s8 rssi;
5004++ u8 snr;
5005++ u32 ts;
5006++ u8 data_bw;
5007++ u8 pri_ch_idx;
5008++ u8 ta[ETH_ALEN];
5009++ u32 info;
5010++ u8 rx_mode;
5011++ u32 h_idx;
5012++ u16 tx_idx;
5013++ u16 rx_idx;
5014++
5015++ struct list_head node;
5016++};
5017++#endif
5018++
5019+ #endif
5020+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
5021+index 85c7e5d..477ed43 100644
5022+--- a/mt7915/mt7915.h
5023++++ b/mt7915/mt7915.h
5024+@@ -265,6 +265,20 @@ struct mt7915_phy {
5025+ u8 spe_idx;
5026+ } test;
5027+ #endif
5028++
5029++#ifdef CONFIG_MTK_VENDOR
5030++ struct {
5031++ struct list_head csi_list;
5032++ spinlock_t csi_lock;
5033++ u32 count;
5034++ bool mask;
5035++ bool reorder;
5036++ bool enable;
5037++
5038++ u32 interval;
5039++ u32 last_record;
5040++ } csi;
5041++#endif
5042+ };
5043+
5044+ struct mt7915_dev {
5045+@@ -608,6 +622,12 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5046+ struct ieee80211_sta *sta, struct dentry *dir);
5047+ #endif
5048+
5049++#ifdef CONFIG_MTK_VENDOR
5050++void mt7915_vendor_register(struct mt7915_phy *phy);
5051++int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
5052++ u8 cfg, u8 v1, u32 v2, u8 *mac_addr);
5053++#endif
5054++
5055+ #ifdef MTK_DEBUG
5056+ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
5057+ int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
5058+diff --git a/mt7915/vendor.c b/mt7915/vendor.c
5059+new file mode 100644
5060+index 0000000..98fd9c2
5061+--- /dev/null
5062++++ b/mt7915/vendor.c
5063+@@ -0,0 +1,452 @@
5064++// SPDX-License-Identifier: ISC
5065++/*
5066++ * Copyright (C) 2020, MediaTek Inc. All rights reserved.
5067++ */
5068++
5069++#include <net/netlink.h>
5070++
5071++#include "mt7915.h"
5072++#include "mcu.h"
5073++#include "vendor.h"
5074++
5075++static const struct nla_policy
5076++csi_ctrl_policy[NUM_MTK_VENDOR_ATTRS_CSI_CTRL] = {
5077++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG] = {.type = NLA_NESTED },
5078++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE] = { .type = NLA_U8 },
5079++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE] = { .type = NLA_U8 },
5080++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1] = { .type = NLA_U8 },
5081++ [MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2] = { .type = NLA_U8 },
5082++ [MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR] = { .type = NLA_NESTED },
5083++ [MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL] = { .type = NLA_U32 },
5084++ [MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM] = { .type = NLA_U16 },
5085++ [MTK_VENDOR_ATTR_CSI_CTRL_DATA] = { .type = NLA_NESTED },
5086++};
5087++
5088++struct csi_null_tone {
5089++ u8 start;
5090++ u8 end;
5091++};
5092++
5093++struct csi_reorder{
5094++ u8 dest;
5095++ u8 start;
5096++ u8 end;
5097++};
5098++
5099++struct csi_mask {
5100++ struct csi_null_tone null[10];
5101++ u8 pilot[8];
5102++ struct csi_reorder ro[3];
5103++};
5104++
5105++static const struct csi_mask csi_mask_groups[] = {
5106++ /* OFDM */
5107++ { .null = { { 0 }, { 27, 37 } },
5108++ .ro = { {0, 0, 63} },
5109++ },
5110++ { .null = { { 0, 69 }, { 96 }, { 123, 127 } },
5111++ .ro = { { 0, 96 }, { 38, 70, 95 }, { 1, 97, 122 } },
5112++ },
5113++ { .null = { { 0, 5 }, { 32 }, { 59, 127 } },
5114++ .ro = { { 0, 32 }, { 38, 6, 31 }, { 1, 33, 58 } },
5115++ },
5116++ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 127 } },
5117++ .ro = { { 0, 0, 127 } },
5118++ },
5119++ { .null = { { 0, 133 }, { 160 }, { 187, 255 } },
5120++ .ro = { { 0, 160 }, { 1, 161, 186 }, { 38, 134, 159 } },
5121++ },
5122++ { .null = { { 0, 197 }, { 224 }, { 251, 255 } },
5123++ .ro = { { 0, 224 }, { 1, 225, 250 }, { 38, 198, 223 } },
5124++ },
5125++ { .null = { { 0, 5 }, { 32 }, { 59, 255 } },
5126++ .ro = { { 0, 32 }, { 1, 33, 58 }, { 38, 6, 31 } },
5127++ },
5128++ { .null = { { 0, 69 }, { 96 }, { 123, 255 } },
5129++ .ro = { { 0, 96 }, { 1, 97, 122 }, { 38, 70, 95 } },
5130++ },
5131++ { .null = { { 0, 133 }, { 160 }, { 187, 197 }, { 224 }, { 251, 255 } },
5132++ .ro = { { 0, 192 }, { 2, 198, 250 }, { 74, 134, 186 } },
5133++ },
5134++ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 255 } },
5135++ .ro = { { 0, 64 }, { 2, 70, 122 }, { 74, 6, 58 } },
5136++ },
5137++ { .null = { { 0, 5 }, { 32 }, { 59, 69 }, { 96 }, { 123, 133 },
5138++ { 160 }, { 187, 197 }, { 224 }, { 251, 255 } },
5139++ .ro = { { 0, 0, 255 } },
5140++ },
5141++
5142++ /* HT/VHT */
5143++ { .null = { { 0 }, { 29, 35 } },
5144++ .pilot = { 7, 21, 43, 57 },
5145++ .ro = { { 0, 0, 63 } },
5146++ },
5147++ { .null = { { 0, 67 }, { 96 }, { 125, 127 } },
5148++ .pilot = { 75, 89, 103, 117 },
5149++ .ro = { { 0, 96 }, { 36, 68, 95 }, { 1, 97, 124 } },
5150++ },
5151++ { .null = { { 0, 3 }, { 32 }, { 61, 127 } },
5152++ .pilot = { 11, 25, 39, 53 },
5153++ .ro = { { 0, 32 }, { 36, 4, 31 }, { 1, 33, 60 } },
5154++ },
5155++ { .null = { { 0, 1 }, { 59, 69 }, { 127 } },
5156++ .pilot = { 11, 25, 53, 75, 103, 117 },
5157++ .ro = { { 0, 0, 127 } },
5158++ },
5159++ { .null = { { 0, 131 }, { 160 }, { 189, 255 } },
5160++ .pilot = { 139, 153, 167, 181 },
5161++ .ro = { { 0, 160 }, { 1, 161, 188 }, { 36, 132, 159 } },
5162++ },
5163++ { .null = { { 0, 195 }, { 224 }, { 253 }, { 255 } },
5164++ .pilot = { 203, 217, 231, 245 },
5165++ .ro = { { 0, 224 }, { 1, 225, 252 }, { 36, 196, 223 } },
5166++ },
5167++ { .null = { { 0, 3 }, { 32 }, { 61, 255 } },
5168++ .pilot = { 11, 25, 39, 53 },
5169++ .ro = { { 0, 32 }, { 1, 33, 60 }, { 36, 4, 31 } },
5170++ },
5171++ { .null = { { 0, 67 }, { 96 }, { 125, 255 } },
5172++ .pilot = { 75, 89, 103, 117 },
5173++ .ro = { { 0, 96 }, { 1, 97, 124 }, { 36, 68, 95 } },
5174++ },
5175++ { .null = { { 0, 133 }, { 191, 193 }, { 251, 255 } },
5176++ .pilot = { 139, 167, 181, 203, 217, 245 },
5177++ .ro = { { 0, 192 }, { 2, 194, 250 }, { 70, 134, 190 } },
5178++ },
5179++ { .null = { { 0, 5 }, { 63, 65 }, { 123, 127 } },
5180++ .pilot = { 11, 39, 53, 75, 89, 117 },
5181++ .ro = { { 0, 64 }, { 2, 66, 122 }, { 70, 6, 62 } },
5182++ },
5183++ { .null = { { 0, 1 }, { 123, 133 }, { 255 } },
5184++ .pilot = { 11, 39, 75, 103, 153, 181, 217, 245 },
5185++ .ro = { { 0, 0, 255 } },
5186++ },
5187++
5188++ /* HE */
5189++ { .null = { { 0 }, { 31, 33 } },
5190++ .pilot = { 12, 29, 35, 52 },
5191++ .ro = { { 0, 0, 63 } },
5192++ },
5193++ { .null = { { 30, 34 }, { 96 } },
5194++ .pilot = { 4, 21, 43, 60, 70, 87, 105, 122 },
5195++ .ro = { { 0, 96 }, { 34, 66, 95 }, { 1, 97, 126 } },
5196++ },
5197++ { .null = { { 32 }, { 94, 98 } },
5198++ .pilot = { 6, 23, 41, 58, 68, 85, 107, 124 },
5199++ .ro = { { 0, 32 }, { 34, 2, 31 }, { 1, 31, 62 } },
5200++ },
5201++ { .null = { { 0 }, { 62, 66 } },
5202++ .pilot = { 9, 26, 36, 53, 75, 92, 102, 119 },
5203++ .ro = { { 0, 0, 127 } },
5204++ },
5205++ { .null = { { 30, 34 }, { 160 } },
5206++ .pilot = { 4, 21, 43, 60, 137, 154, 166, 183 },
5207++ .ro = { { 0, 160 }, { 1, 161, 190 }, { 34, 130, 159 } },
5208++ },
5209++ { .null = { { 94, 98 }, { 224 } },
5210++ .pilot = { 68, 85, 107, 124, 201, 218, 230, 247 },
5211++ .ro = { { 0, 224 }, { 1, 225, 254 }, { 34, 194, 223 } },
5212++ },
5213++ { .null = { { 32 }, { 158, 162 } },
5214++ .pilot = { 9, 26, 38, 55, 132, 149, 171, 188 },
5215++ .ro = { { 0, 32 }, { 1, 33, 62 }, { 34, 2, 31 } },
5216++ },
5217++ { .null = { { 96 }, { 222, 226 } },
5218++ .pilot = { 73, 90, 102, 119, 196, 213, 235, 252 },
5219++ .ro = { { 0, 96 }, { 1, 97, 126 }, { 34, 66, 95 } },
5220++ },
5221++ { .null = { { 62, 66 }, { 192 } },
5222++ .pilot = { 36, 53, 75, 92, 169, 186, 198, 215 },
5223++ .ro = { { 0, 192 }, { 1, 193, 253 }, { 67, 131, 191 } },
5224++ },
5225++ { .null = { { 64 }, { 190, 194 } },
5226++ .pilot = { 41, 58, 70, 87, 164, 181, 203, 220 },
5227++ .ro = { { 0, 64 }, { 1, 65, 125 }, { 67, 3, 63 } },
5228++ },
5229++ { .null = { { 0 }, { 126, 130 } },
5230++ .pilot = { 6, 23, 100, 117, 139, 156, 233, 250 },
5231++ .ro = { { 0, 0, 255 } },
5232++ },
5233++};
5234++
5235++static inline u8 csi_group_idx(u8 mode, u8 ch_bw, u8 data_bw, u8 pri_ch_idx)
5236++{
5237++ if (ch_bw < 2 || data_bw < 1)
5238++ return mode * 11 + ch_bw * ch_bw + pri_ch_idx;
5239++ else
5240++ return mode * 11 + ch_bw * ch_bw + (data_bw + 1) * 2 + pri_ch_idx;
5241++}
5242++
5243++static int mt7915_vendor_csi_ctrl(struct wiphy *wiphy,
5244++ struct wireless_dev *wdev,
5245++ const void *data,
5246++ int data_len)
5247++{
5248++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
5249++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
5250++ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_CSI_CTRL];
5251++ int err;
5252++
5253++ err = nla_parse(tb, MTK_VENDOR_ATTR_CSI_CTRL_MAX, data, data_len,
5254++ csi_ctrl_policy, NULL);
5255++ if (err)
5256++ return err;
5257++
5258++ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_CFG]) {
5259++ u8 mode = 0, type = 0, v1 = 0, v2 = 0;
5260++ u8 mac_addr[ETH_ALEN] = {};
5261++ struct nlattr *cur;
5262++ int rem;
5263++
5264++ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_CSI_CTRL_CFG], rem) {
5265++ switch(nla_type(cur)) {
5266++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE:
5267++ mode = nla_get_u8(cur);
5268++ break;
5269++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE:
5270++ type = nla_get_u8(cur);
5271++ break;
5272++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1:
5273++ v1 = nla_get_u8(cur);
5274++ break;
5275++ case MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2:
5276++ v2 = nla_get_u8(cur);
5277++ break;
5278++ default:
5279++ return -EINVAL;
5280++ };
5281++ }
5282++
5283++ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR]) {
5284++ int idx = 0;
5285++
5286++ nla_for_each_nested(cur, tb[MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR], rem) {
5287++ mac_addr[idx++] = nla_get_u8(cur);
5288++ }
5289++ }
5290++
5291++ mt7915_mcu_set_csi(phy, mode, type, v1, v2, mac_addr);
5292++
5293++ spin_lock_bh(&phy->csi.csi_lock);
5294++
5295++ phy->csi.enable = !!mode;
5296++
5297++ if (mode == 2 && type == 5) {
5298++ if (v1 >= 1)
5299++ phy->csi.mask = 1;
5300++ if (v1 == 2)
5301++ phy->csi.reorder = 1;
5302++ }
5303++
5304++ /* clean up old csi stats */
5305++ if ((mode == 0 || mode == 2) && !list_empty(&phy->csi.csi_list)) {
5306++ struct csi_data *c, *tmp_c;
5307++
5308++ list_for_each_entry_safe(c, tmp_c, &phy->csi.csi_list,
5309++ node) {
5310++ list_del(&c->node);
5311++ kfree(c);
5312++ phy->csi.count--;
5313++ }
5314++ } else if (mode == 1) {
5315++ phy->csi.last_record = 0;
5316++ }
5317++
5318++ spin_unlock_bh(&phy->csi.csi_lock);
5319++ }
5320++
5321++ if (tb[MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL])
5322++ phy->csi.interval = nla_get_u32(tb[MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL]);
5323++
5324++ return 0;
5325++}
5326++
5327++static void
5328++mt7915_vendor_csi_tone_mask(struct mt7915_phy *phy, struct csi_data *csi)
5329++{
5330++ static const u8 mode_map[] = {
5331++ [MT_PHY_TYPE_OFDM] = 0,
5332++ [MT_PHY_TYPE_HT] = 1,
5333++ [MT_PHY_TYPE_VHT] = 1,
5334++ [MT_PHY_TYPE_HE_SU] = 2,
5335++ };
5336++ const struct csi_mask *cmask;
5337++ int i;
5338++
5339++ if (csi->rx_mode == MT_PHY_TYPE_CCK || !phy->csi.mask)
5340++ return;
5341++
5342++ if (csi->data_bw == IEEE80211_STA_RX_BW_40)
5343++ csi->pri_ch_idx /= 2;
5344++
5345++ cmask = &csi_mask_groups[csi_group_idx(mode_map[csi->rx_mode],
5346++ csi->ch_bw,
5347++ csi->data_bw,
5348++ csi->pri_ch_idx)];
5349++
5350++ for (i = 0; i < 10; i++) {
5351++ const struct csi_null_tone *ntone = &cmask->null[i];
5352++ u8 start = ntone->start;
5353++ u8 end = ntone->end;
5354++ int j;
5355++
5356++ if (!start && !end && i > 0)
5357++ break;
5358++
5359++ if (!end)
5360++ end = start;
5361++
5362++ for (j = start; j <= end; j++) {
5363++ csi->data_i[j] = 0;
5364++ csi->data_q[j] = 0;
5365++ }
5366++ }
5367++
5368++ for (i = 0; i < 8; i++) {
5369++ u8 pilot = cmask->pilot[i];
5370++
5371++ if (!pilot)
5372++ break;
5373++
5374++ csi->data_i[pilot] = 0;
5375++ csi->data_q[pilot] = 0;
5376++ }
5377++
5378++ if (!phy->csi.reorder)
5379++ return;
5380++
5381++ for (i = 0; i < 3; i++) {
5382++ const struct csi_reorder *ro = &cmask->ro[i];
5383++ u8 dest = ro->dest;
5384++ u8 start = ro->start;
5385++ u8 end = ro->end;
5386++
5387++ if (!dest && !start && !end)
5388++ break;
5389++
5390++ if (dest == start)
5391++ continue;
5392++
5393++ if (end) {
5394++ memmove(&csi->data_i[dest], &csi->data_i[start],
5395++ end - start + 1);
5396++ memmove(&csi->data_q[dest], &csi->data_q[start],
5397++ end - start + 1);
5398++ } else {
5399++ csi->data_i[dest] = csi->data_i[start];
5400++ csi->data_q[dest] = csi->data_q[start];
5401++ }
5402++ }
5403++}
5404++
5405++static int
5406++mt7915_vendor_csi_ctrl_dump(struct wiphy *wiphy, struct wireless_dev *wdev,
5407++ struct sk_buff *skb, const void *data, int data_len,
5408++ unsigned long *storage)
5409++{
5410++#define RESERVED_SET BIT(31)
5411++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
5412++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
5413++ struct nlattr *tb[NUM_MTK_VENDOR_ATTRS_CSI_CTRL];
5414++ int err = 0;
5415++
5416++ if (*storage & RESERVED_SET) {
5417++ if ((*storage & GENMASK(15, 0)) == 0)
5418++ return -ENOENT;
5419++ (*storage)--;
5420++ }
5421++
5422++ if (data) {
5423++ err = nla_parse(tb, MTK_VENDOR_ATTR_CSI_CTRL_MAX, data, data_len,
5424++ csi_ctrl_policy, NULL);
5425++ if (err)
5426++ return err;
5427++ }
5428++
5429++ if (!(*storage & RESERVED_SET) && tb[MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM]) {
5430++ *storage = nla_get_u16(tb[MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM]);
5431++ *storage |= RESERVED_SET;
5432++ }
5433++
5434++ spin_lock_bh(&phy->csi.csi_lock);
5435++
5436++ if (!list_empty(&phy->csi.csi_list)) {
5437++ struct csi_data *csi;
5438++ void *a, *b;
5439++ int i;
5440++
5441++ csi = list_first_entry(&phy->csi.csi_list, struct csi_data, node);
5442++
5443++ mt7915_vendor_csi_tone_mask(phy, csi);
5444++
5445++ a = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_CTRL_DATA);
5446++
5447++ if (nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_VER, 1) ||
5448++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_RSSI, csi->rssi) ||
5449++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_SNR, csi->snr) ||
5450++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_BW, csi->data_bw) ||
5451++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_CH_IDX, csi->pri_ch_idx) ||
5452++ nla_put_u8(skb, MTK_VENDOR_ATTR_CSI_DATA_MODE, csi->rx_mode))
5453++ goto out;
5454++
5455++ if (nla_put_u16(skb, MTK_VENDOR_ATTR_CSI_DATA_TX_ANT, csi->tx_idx) ||
5456++ nla_put_u16(skb, MTK_VENDOR_ATTR_CSI_DATA_RX_ANT, csi->rx_idx))
5457++ goto out;
5458++
5459++ if (nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_INFO, csi->info) ||
5460++ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_H_IDX, csi->h_idx) ||
5461++ nla_put_u32(skb, MTK_VENDOR_ATTR_CSI_DATA_TS, csi->ts))
5462++ goto out;
5463++
5464++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_TA);
5465++ for (i = 0; i < ARRAY_SIZE(csi->ta); i++)
5466++ if (nla_put_u8(skb, i, csi->ta[i]))
5467++ goto out;
5468++ nla_nest_end(skb, b);
5469++
5470++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_I);
5471++ for (i = 0; i < ARRAY_SIZE(csi->data_i); i++)
5472++ if (nla_put_u16(skb, i, csi->data_i[i]))
5473++ goto out;
5474++ nla_nest_end(skb, b);
5475++
5476++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_CSI_DATA_Q);
5477++ for (i = 0; i < ARRAY_SIZE(csi->data_q); i++)
5478++ if (nla_put_u16(skb, i, csi->data_q[i]))
5479++ goto out;
5480++ nla_nest_end(skb, b);
5481++
5482++ nla_nest_end(skb, a);
5483++
5484++ list_del(&csi->node);
5485++ kfree(csi);
5486++ phy->csi.count--;
5487++
5488++ err = phy->csi.count;
5489++ }
5490++out:
5491++ spin_unlock_bh(&phy->csi.csi_lock);
5492++
5493++ return err;
5494++}
5495++
5496++static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
5497++ {
5498++ .info = {
5499++ .vendor_id = MTK_NL80211_VENDOR_ID,
5500++ .subcmd = MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL,
5501++ },
5502++ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
5503++ WIPHY_VENDOR_CMD_NEED_RUNNING,
5504++ .doit = mt7915_vendor_csi_ctrl,
5505++ .dumpit = mt7915_vendor_csi_ctrl_dump,
5506++ .policy = csi_ctrl_policy,
5507++ .maxattr = MTK_VENDOR_ATTR_CSI_CTRL_MAX,
5508++ }
5509++};
5510++
5511++void mt7915_vendor_register(struct mt7915_phy *phy)
5512++{
5513++ phy->mt76->hw->wiphy->vendor_commands = mt7915_vendor_commands;
5514++ phy->mt76->hw->wiphy->n_vendor_commands = ARRAY_SIZE(mt7915_vendor_commands);
5515++}
5516+diff --git a/mt7915/vendor.h b/mt7915/vendor.h
5517+new file mode 100644
5518+index 0000000..9d3db2a
5519+--- /dev/null
5520++++ b/mt7915/vendor.h
5521+@@ -0,0 +1,60 @@
5522++#ifndef __MT7915_VENDOR_H
5523++#define __MT7915_VENDOR_H
5524++
5525++#define MTK_NL80211_VENDOR_ID 0x0ce7
5526++
5527++enum mtk_nl80211_vendor_subcmds {
5528++ MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL = 0xc2,
5529++};
5530++
5531++enum mtk_vendor_attr_csi_ctrl {
5532++ MTK_VENDOR_ATTR_CSI_CTRL_UNSPEC,
5533++
5534++ MTK_VENDOR_ATTR_CSI_CTRL_CFG,
5535++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_MODE,
5536++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_TYPE,
5537++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL1,
5538++ MTK_VENDOR_ATTR_CSI_CTRL_CFG_VAL2,
5539++ MTK_VENDOR_ATTR_CSI_CTRL_MAC_ADDR,
5540++ MTK_VENDOR_ATTR_CSI_CTRL_INTERVAL,
5541++
5542++ MTK_VENDOR_ATTR_CSI_CTRL_DUMP_NUM,
5543++
5544++ MTK_VENDOR_ATTR_CSI_CTRL_DATA,
5545++
5546++ /* keep last */
5547++ NUM_MTK_VENDOR_ATTRS_CSI_CTRL,
5548++ MTK_VENDOR_ATTR_CSI_CTRL_MAX =
5549++ NUM_MTK_VENDOR_ATTRS_CSI_CTRL - 1
5550++};
5551++
5552++enum mtk_vendor_attr_csi_data {
5553++ MTK_VENDOR_ATTR_CSI_DATA_UNSPEC,
5554++ MTK_VENDOR_ATTR_CSI_DATA_PAD,
5555++
5556++ MTK_VENDOR_ATTR_CSI_DATA_VER,
5557++ MTK_VENDOR_ATTR_CSI_DATA_TS,
5558++ MTK_VENDOR_ATTR_CSI_DATA_RSSI,
5559++ MTK_VENDOR_ATTR_CSI_DATA_SNR,
5560++ MTK_VENDOR_ATTR_CSI_DATA_BW,
5561++ MTK_VENDOR_ATTR_CSI_DATA_CH_IDX,
5562++ MTK_VENDOR_ATTR_CSI_DATA_TA,
5563++ MTK_VENDOR_ATTR_CSI_DATA_I,
5564++ MTK_VENDOR_ATTR_CSI_DATA_Q,
5565++ MTK_VENDOR_ATTR_CSI_DATA_INFO,
5566++ MTK_VENDOR_ATTR_CSI_DATA_RSVD1,
5567++ MTK_VENDOR_ATTR_CSI_DATA_RSVD2,
5568++ MTK_VENDOR_ATTR_CSI_DATA_RSVD3,
5569++ MTK_VENDOR_ATTR_CSI_DATA_RSVD4,
5570++ MTK_VENDOR_ATTR_CSI_DATA_TX_ANT,
5571++ MTK_VENDOR_ATTR_CSI_DATA_RX_ANT,
5572++ MTK_VENDOR_ATTR_CSI_DATA_MODE,
5573++ MTK_VENDOR_ATTR_CSI_DATA_H_IDX,
5574++
5575++ /* keep last */
5576++ NUM_MTK_VENDOR_ATTRS_CSI_DATA,
5577++ MTK_VENDOR_ATTR_CSI_DATA_MAX =
5578++ NUM_MTK_VENDOR_ATTRS_CSI_DATA - 1
5579++};
5580++
5581++#endif
5582+--
5583+2.25.1
5584+
5585diff --git a/package/kernel/mt76/patches/1003-mt76-mt7915-air-monitor-support.patch b/package/kernel/mt76/patches/1003-mt76-mt7915-air-monitor-support.patch
5586new file mode 100644
5587index 00000000..2666a0c0
5588--- /dev/null
5589+++ b/package/kernel/mt76/patches/1003-mt76-mt7915-air-monitor-support.patch
5590@@ -0,0 +1,549 @@
5591+From 5dfe20c80a41f6d665e5f911f4254aec5ac311f3 Mon Sep 17 00:00:00 2001
5592+From: Peter Chiu <chui-hao.chiu@mediatek.com>
5593+Date: Tue, 11 Jan 2022 12:03:23 +0800
5594+Subject: [PATCH 1003/1006] mt76: mt7915: air monitor support
5595+
5596+---
5597+ .../wireless/mediatek/mt76/mt76_connac_mcu.h | 2 +
5598+ .../net/wireless/mediatek/mt76/mt7915/mac.c | 4 +
5599+ .../net/wireless/mediatek/mt76/mt7915/main.c | 3 +
5600+ .../wireless/mediatek/mt76/mt7915/mt7915.h | 34 ++
5601+ .../wireless/mediatek/mt76/mt7915/vendor.c | 359 ++++++++++++++++++
5602+ .../wireless/mediatek/mt76/mt7915/vendor.h | 38 ++
5603+ 6 files changed, 440 insertions(+)
5604+
5605+diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
5606+index e959d4c..2173682 100644
5607+--- a/mt76_connac_mcu.h
5608++++ b/mt76_connac_mcu.h
5609+@@ -991,6 +991,8 @@ enum {
5610+ MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
5611+ MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
5612+ MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
5613++ /* for vendor csi and air monitor */
5614++ MCU_EXT_CMD_SMESH_CTRL = 0xae,
5615+ MCU_EXT_CMD_CSI_CTRL = 0xc2,
5616+ };
5617+
5618+diff --git a/mt7915/mac.c b/mt7915/mac.c
5619+index 06186c0..9f595ca 100644
5620+--- a/mt7915/mac.c
5621++++ b/mt7915/mac.c
5622+@@ -825,6 +825,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
5623+ seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
5624+ qos_ctl = *ieee80211_get_qos_ctl(hdr);
5625+ }
5626++#ifdef CONFIG_MTK_VENDOR
5627++ if (phy->amnt_ctrl.enable)
5628++ mt7915_vendor_amnt_fill_rx(phy, skb);
5629++#endif
5630+ } else {
5631+ status->flag |= RX_FLAG_8023;
5632+ }
5633+diff --git a/mt7915/main.c b/mt7915/main.c
5634+index c3f44d8..1beadd8 100644
5635+--- a/mt7915/main.c
5636++++ b/mt7915/main.c
5637+@@ -677,6 +677,9 @@ int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
5638+ if (ret)
5639+ return ret;
5640+
5641++#ifdef CONFIG_MTK_VENDOR
5642++ mt7915_vendor_amnt_sta_remove(mvif->phy, sta);
5643++#endif
5644+ return mt7915_mcu_add_rate_ctrl(dev, vif, sta, false);
5645+ }
5646+
5647+diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
5648+index 477ed43..85d05f7 100644
5649+--- a/mt7915/mt7915.h
5650++++ b/mt7915/mt7915.h
5651+@@ -222,6 +222,35 @@ struct mt7915_hif {
5652+ int irq;
5653+ };
5654+
5655++#ifdef CONFIG_MTK_VENDOR
5656++#define MT7915_AIR_MONITOR_MAX_ENTRY 16
5657++#define MT7915_AIR_MONITOR_MAX_GROUP MT7915_AIR_MONITOR_MAX_ENTRY >> 2
5658++
5659++struct mt7915_air_monitor_group {
5660++ bool enable;
5661++ bool used[2];
5662++};
5663++
5664++struct mt7915_air_monitor_entry {
5665++ bool enable;
5666++
5667++ u8 group_idx;
5668++ u8 group_used_idx;
5669++ u8 muar_idx;
5670++ u8 addr[ETH_ALEN];
5671++ unsigned int last_seen;
5672++ s8 rssi[4];
5673++ struct ieee80211_sta *sta;
5674++};
5675++
5676++struct mt7915_air_monitor_ctrl {
5677++ u8 enable;
5678++
5679++ struct mt7915_air_monitor_group group[MT7915_AIR_MONITOR_MAX_GROUP];
5680++ struct mt7915_air_monitor_entry entry[MT7915_AIR_MONITOR_MAX_ENTRY];
5681++};
5682++#endif
5683++
5684+ struct mt7915_phy {
5685+ struct mt76_phy *mt76;
5686+ struct mt7915_dev *dev;
5687+@@ -278,6 +307,8 @@ struct mt7915_phy {
5688+ u32 interval;
5689+ u32 last_record;
5690+ } csi;
5691++
5692++ struct mt7915_air_monitor_ctrl amnt_ctrl;
5693+ #endif
5694+ };
5695+
5696+@@ -626,6 +657,9 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5697+ void mt7915_vendor_register(struct mt7915_phy *phy);
5698+ int mt7915_mcu_set_csi(struct mt7915_phy *phy, u8 mode,
5699+ u8 cfg, u8 v1, u32 v2, u8 *mac_addr);
5700++void mt7915_vendor_amnt_fill_rx(struct mt7915_phy *phy, struct sk_buff *skb);
5701++int mt7915_vendor_amnt_sta_remove(struct mt7915_phy *phy,
5702++ struct ieee80211_sta *sta);
5703+ #endif
5704+
5705+ #ifdef MTK_DEBUG
5706+diff --git a/mt7915/vendor.c b/mt7915/vendor.c
5707+index 98fd9c2..b94d787 100644
5708+--- a/mt7915/vendor.c
5709++++ b/mt7915/vendor.c
5710+@@ -430,6 +430,353 @@ out:
5711+ return err;
5712+ }
5713+
5714++static const struct nla_policy
5715++amnt_ctrl_policy[NUM_MTK_VENDOR_ATTRS_AMNT_CTRL] = {
5716++ [MTK_VENDOR_ATTR_AMNT_CTRL_SET] = {.type = NLA_NESTED },
5717++ [MTK_VENDOR_ATTR_AMNT_CTRL_DUMP] = { .type = NLA_NESTED },
5718++};
5719++
5720++static const struct nla_policy
5721++amnt_set_policy[NUM_MTK_VENDOR_ATTRS_AMNT_SET] = {
5722++ [MTK_VENDOR_ATTR_AMNT_SET_INDEX] = {.type = NLA_U8 },
5723++ [MTK_VENDOR_ATTR_AMNT_SET_MACADDR] = { .type = NLA_NESTED },
5724++};
5725++
5726++static const struct nla_policy
5727++amnt_dump_policy[NUM_MTK_VENDOR_ATTRS_AMNT_DUMP] = {
5728++ [MTK_VENDOR_ATTR_AMNT_DUMP_INDEX] = {.type = NLA_U8 },
5729++ [MTK_VENDOR_ATTR_AMNT_DUMP_LEN] = { .type = NLA_U8 },
5730++ [MTK_VENDOR_ATTR_AMNT_DUMP_RESULT] = { .type = NLA_NESTED },
5731++};
5732++
5733++struct mt7915_amnt_data {
5734++ u8 idx;
5735++ u8 addr[ETH_ALEN];
5736++ s8 rssi[4];
5737++ u32 last_seen;
5738++};
5739++
5740++struct mt7915_smesh {
5741++ u8 band;
5742++ u8 write;
5743++ u8 enable;
5744++ bool a2;
5745++ bool a1;
5746++ bool data;
5747++ bool mgnt;
5748++ bool ctrl;
5749++} __packed;
5750++
5751++struct mt7915_smesh_event {
5752++ u8 band;
5753++ __le32 value;
5754++} __packed;
5755++
5756++static int
5757++mt7915_vendor_smesh_ctrl(struct mt7915_phy *phy, u8 write,
5758++ u8 enable, u32 *value)
5759++{
5760++ struct mt7915_dev *dev = phy->dev;
5761++ struct mt7915_smesh req = {
5762++ .band = phy != &dev->phy,
5763++ .write = write,
5764++ .enable = enable,
5765++ .a2 = 1,
5766++ .a1 = 1,
5767++ .data = 1,
5768++ };
5769++ struct mt7915_smesh_event *res;
5770++ struct sk_buff *skb;
5771++ int ret = 0;
5772++
5773++ ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_EXT_CMD(SMESH_CTRL),
5774++ &req, sizeof(req), !write, &skb);
5775++
5776++ if (ret || write)
5777++ return ret;
5778++
5779++ res = (struct mt7915_smesh_event *) skb->data;
5780++
5781++ if (!value)
5782++ return -EINVAL;
5783++
5784++ *value = res->value;
5785++
5786++ dev_kfree_skb(skb);
5787++
5788++ return 0;
5789++}
5790++
5791++static int
5792++mt7915_vendor_amnt_muar(struct mt7915_phy *phy, u8 muar_idx, u8 *addr)
5793++{
5794++ struct mt7915_dev *dev = phy->dev;
5795++ struct {
5796++ u8 mode;
5797++ u8 force_clear;
5798++ u8 clear_bitmap[8];
5799++ u8 entry_count;
5800++ u8 write;
5801++ u8 band;
5802++
5803++ u8 index;
5804++ u8 bssid;
5805++ u8 addr[ETH_ALEN];
5806++ } __packed req = {
5807++ .entry_count = 1,
5808++ .write = 1,
5809++ .band = phy != &dev->phy,
5810++ .index = muar_idx,
5811++ };
5812++
5813++ ether_addr_copy(req.addr, addr);
5814++
5815++ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MUAR_UPDATE), &req,
5816++ sizeof(req), true);
5817++}
5818++
5819++static int
5820++mt7915_vendor_amnt_set_en(struct mt7915_phy *phy, u8 enable)
5821++{
5822++ u32 status;
5823++ int ret;
5824++
5825++ ret = mt7915_vendor_smesh_ctrl(phy, 0, enable, &status);
5826++ if (ret)
5827++ return ret;
5828++
5829++ status = status & 0xff;
5830++
5831++ if (status == enable)
5832++ return 0;
5833++
5834++ ret = mt7915_vendor_smesh_ctrl(phy, 1, enable, &status);
5835++ if (ret)
5836++ return ret;
5837++
5838++ return 0;
5839++}
5840++
5841++static int
5842++mt7915_vendor_amnt_set_addr(struct mt7915_phy *phy, u8 index, u8 *addr)
5843++{
5844++ struct mt7915_air_monitor_ctrl *amnt_ctrl = &phy->amnt_ctrl;
5845++ struct mt7915_air_monitor_group *group;
5846++ struct mt7915_air_monitor_entry *entry = &amnt_ctrl->entry[index];
5847++ const u8 zero_addr[ETH_ALEN] = {};
5848++ int enable = !ether_addr_equal(addr, zero_addr);
5849++ int ret, i, j;
5850++
5851++ if (enable == 1 && entry->enable == 1) {
5852++ ether_addr_copy(entry->addr, addr);
5853++ } else if (enable == 1 && entry->enable == 0){
5854++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_GROUP; i++) {
5855++ group = &(amnt_ctrl->group[i]);
5856++ if (group->used[0] == 0)
5857++ j = 0;
5858++ else
5859++ j = 1;
5860++
5861++ group->enable = 1;
5862++ group->used[j] = 1;
5863++ entry->enable = 1;
5864++ entry->group_idx = i;
5865++ entry->group_used_idx = j;
5866++ entry->muar_idx = 32 + 2 * i + 2 * i + 2 * j;
5867++ ether_addr_copy(entry->addr, addr);
5868++ break;
5869++ }
5870++ } else {
5871++ group = &(amnt_ctrl->group[entry->group_idx]);
5872++
5873++ group->used[entry->group_used_idx] = 0;
5874++ if (group->used[0] == 0 && group->used[1] == 0)
5875++ group->enable = 0;
5876++
5877++ entry->enable = 0;
5878++ ether_addr_copy(entry->addr, addr);
5879++ }
5880++
5881++ amnt_ctrl->enable &= ~(1 << entry->group_idx);
5882++ amnt_ctrl->enable |= entry->enable << entry->group_idx;
5883++ ret = mt7915_vendor_amnt_muar(phy, entry->muar_idx, addr);
5884++ if (ret)
5885++ return ret;
5886++
5887++ return mt7915_vendor_amnt_set_en(phy, amnt_ctrl->enable);
5888++}
5889++
5890++void mt7915_vendor_amnt_fill_rx(struct mt7915_phy *phy, struct sk_buff *skb)
5891++{
5892++ struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
5893++ struct mt7915_air_monitor_ctrl *ctrl = &phy->amnt_ctrl;
5894++ struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb);
5895++ __le16 fc = hdr->frame_control;
5896++ u8 addr[ETH_ALEN];
5897++ int i;
5898++
5899++ if (!ieee80211_has_fromds(fc))
5900++ ether_addr_copy(addr, hdr->addr2);
5901++ else if (ieee80211_has_tods(fc))
5902++ ether_addr_copy(addr, hdr->addr4);
5903++ else
5904++ ether_addr_copy(addr, hdr->addr3);
5905++
5906++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_ENTRY; i++) {
5907++ struct mt7915_air_monitor_entry *entry;
5908++
5909++ if (ether_addr_equal(addr, ctrl->entry[i].addr)) {
5910++ entry = &ctrl->entry[i];
5911++ entry->rssi[0] = status->chain_signal[0];
5912++ entry->rssi[1] = status->chain_signal[1];
5913++ entry->rssi[2] = status->chain_signal[2];
5914++ entry->rssi[3] = status->chain_signal[3];
5915++ entry->last_seen = jiffies;
5916++ }
5917++ }
5918++
5919++ if (ieee80211_has_tods(fc) &&
5920++ !ether_addr_equal(hdr->addr3, phy->mt76->macaddr))
5921++ return;
5922++ else if (!ether_addr_equal(hdr->addr1, phy->mt76->macaddr))
5923++ return;
5924++}
5925++
5926++int mt7915_vendor_amnt_sta_remove(struct mt7915_phy *phy,
5927++ struct ieee80211_sta *sta)
5928++{
5929++ u8 zero[ETH_ALEN] = {};
5930++ int i;
5931++
5932++ if (!phy->amnt_ctrl.enable)
5933++ return 0;
5934++
5935++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_ENTRY; i++)
5936++ if (ether_addr_equal(sta->addr, phy->amnt_ctrl.entry[i].addr))
5937++ return mt7915_vendor_amnt_set_addr(phy, i, zero);
5938++
5939++ return 0;
5940++}
5941++
5942++static int
5943++mt7915_vendor_amnt_ctrl(struct wiphy *wiphy, struct wireless_dev *wdev,
5944++ const void *data, int data_len)
5945++{
5946++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
5947++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
5948++ struct nlattr *tb1[NUM_MTK_VENDOR_ATTRS_AMNT_CTRL];
5949++ struct nlattr *tb2[NUM_MTK_VENDOR_ATTRS_AMNT_SET];
5950++ struct nlattr *cur;
5951++ u8 index = 0, i = 0;
5952++ u8 mac_addr[ETH_ALEN] = {};
5953++ int err, rem;
5954++
5955++ err = nla_parse(tb1, MTK_VENDOR_ATTR_AMNT_CTRL_MAX, data, data_len,
5956++ amnt_ctrl_policy, NULL);
5957++ if (err)
5958++ return err;
5959++
5960++ if (!tb1[MTK_VENDOR_ATTR_AMNT_CTRL_SET])
5961++ return -EINVAL;
5962++
5963++ err = nla_parse_nested(tb2, MTK_VENDOR_ATTR_AMNT_SET_MAX,
5964++ tb1[MTK_VENDOR_ATTR_AMNT_CTRL_SET], amnt_set_policy, NULL);
5965++
5966++ if (!tb2[MTK_VENDOR_ATTR_AMNT_SET_INDEX] ||
5967++ !tb2[MTK_VENDOR_ATTR_AMNT_SET_MACADDR])
5968++ return -EINVAL;
5969++
5970++ index = nla_get_u8(tb2[MTK_VENDOR_ATTR_AMNT_SET_INDEX]);
5971++ nla_for_each_nested(cur, tb2[MTK_VENDOR_ATTR_AMNT_SET_MACADDR], rem) {
5972++ mac_addr[i++] = nla_get_u8(cur);
5973++ }
5974++
5975++ return mt7915_vendor_amnt_set_addr(phy, index, mac_addr);
5976++}
5977++
5978++static int
5979++mt7915_amnt_dump(struct mt7915_phy *phy, struct sk_buff *skb,
5980++ u8 amnt_idx, int *attrtype)
5981++{
5982++ struct mt7915_air_monitor_entry *entry =
5983++ &phy->amnt_ctrl.entry[amnt_idx];
5984++ struct mt7915_amnt_data data;
5985++ u32 last_seen = 0;
5986++
5987++ if (entry->enable == 0)
5988++ return 0;
5989++
5990++ last_seen = jiffies_to_msecs(jiffies - entry->last_seen);
5991++
5992++ data.idx = amnt_idx;
5993++ ether_addr_copy(data.addr, entry->addr);
5994++ data.rssi[0] = entry->rssi[0];
5995++ data.rssi[1] = entry->rssi[1];
5996++ data.rssi[2] = entry->rssi[2];
5997++ data.rssi[3] = entry->rssi[3];
5998++ data.last_seen = last_seen;
5999++
6000++ nla_put(skb, (*attrtype)++, sizeof(struct mt7915_amnt_data), &data);
6001++
6002++ return 1;
6003++}
6004++
6005++static int
6006++mt7915_vendor_amnt_ctrl_dump(struct wiphy *wiphy, struct wireless_dev *wdev,
6007++ struct sk_buff *skb, const void *data, int data_len,
6008++ unsigned long *storage)
6009++{
6010++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
6011++ struct mt7915_phy *phy = mt7915_hw_phy(hw);
6012++ struct nlattr *tb1[NUM_MTK_VENDOR_ATTRS_AMNT_CTRL];
6013++ struct nlattr *tb2[NUM_MTK_VENDOR_ATTRS_AMNT_DUMP];
6014++ void *a, *b;
6015++ int err = 0, attrtype = 0, i, len = 0;
6016++ u8 amnt_idx;
6017++
6018++ if (*storage == 1)
6019++ return -ENOENT;
6020++ *storage = 1;
6021++
6022++ err = nla_parse(tb1, MTK_VENDOR_ATTR_AMNT_CTRL_MAX, data, data_len,
6023++ amnt_ctrl_policy, NULL);
6024++ if (err)
6025++ return err;
6026++
6027++ if (!tb1[MTK_VENDOR_ATTR_AMNT_CTRL_DUMP])
6028++ return -EINVAL;
6029++
6030++ err = nla_parse_nested(tb2, MTK_VENDOR_ATTR_AMNT_DUMP_MAX,
6031++ tb1[MTK_VENDOR_ATTR_AMNT_CTRL_DUMP],
6032++ amnt_dump_policy, NULL);
6033++ if (err)
6034++ return err;
6035++
6036++ if (!tb2[MTK_VENDOR_ATTR_AMNT_DUMP_INDEX])
6037++ return -EINVAL;
6038++
6039++ amnt_idx = nla_get_u8(tb2[MTK_VENDOR_ATTR_AMNT_DUMP_INDEX]);
6040++
6041++ a = nla_nest_start(skb, MTK_VENDOR_ATTR_AMNT_CTRL_DUMP);
6042++ b = nla_nest_start(skb, MTK_VENDOR_ATTR_AMNT_DUMP_RESULT);
6043++
6044++ if (amnt_idx != 0xff) {
6045++ len += mt7915_amnt_dump(phy, skb, amnt_idx, &attrtype);
6046++ } else {
6047++ for (i = 0; i < MT7915_AIR_MONITOR_MAX_ENTRY; i++) {
6048++ len += mt7915_amnt_dump(phy, skb, i, &attrtype);
6049++ }
6050++ }
6051++
6052++ nla_nest_end(skb, b);
6053++
6054++ nla_put_u8(skb, MTK_VENDOR_ATTR_AMNT_DUMP_LEN, len);
6055++
6056++ nla_nest_end(skb, a);
6057++
6058++ return len + 1;
6059++}
6060++
6061+ static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
6062+ {
6063+ .info = {
6064+@@ -442,6 +789,18 @@ static const struct wiphy_vendor_command mt7915_vendor_commands[] = {
6065+ .dumpit = mt7915_vendor_csi_ctrl_dump,
6066+ .policy = csi_ctrl_policy,
6067+ .maxattr = MTK_VENDOR_ATTR_CSI_CTRL_MAX,
6068++ },
6069++ {
6070++ .info = {
6071++ .vendor_id = MTK_NL80211_VENDOR_ID,
6072++ .subcmd = MTK_NL80211_VENDOR_SUBCMD_AMNT_CTRL,
6073++ },
6074++ .flags = WIPHY_VENDOR_CMD_NEED_NETDEV |
6075++ WIPHY_VENDOR_CMD_NEED_RUNNING,
6076++ .doit = mt7915_vendor_amnt_ctrl,
6077++ .dumpit = mt7915_vendor_amnt_ctrl_dump,
6078++ .policy = amnt_ctrl_policy,
6079++ .maxattr = MTK_VENDOR_ATTR_AMNT_CTRL_MAX,
6080+ }
6081+ };
6082+
6083+diff --git a/mt7915/vendor.h b/mt7915/vendor.h
6084+index 9d3db2a..976817f 100644
6085+--- a/mt7915/vendor.h
6086++++ b/mt7915/vendor.h
6087+@@ -4,6 +4,7 @@
6088+ #define MTK_NL80211_VENDOR_ID 0x0ce7
6089+
6090+ enum mtk_nl80211_vendor_subcmds {
6091++ MTK_NL80211_VENDOR_SUBCMD_AMNT_CTRL = 0xae,
6092+ MTK_NL80211_VENDOR_SUBCMD_CSI_CTRL = 0xc2,
6093+ };
6094+
6095+@@ -57,4 +58,41 @@ enum mtk_vendor_attr_csi_data {
6096+ NUM_MTK_VENDOR_ATTRS_CSI_DATA - 1
6097+ };
6098+
6099++enum mtk_vendor_attr_mnt_ctrl {
6100++ MTK_VENDOR_ATTR_AMNT_CTRL_UNSPEC,
6101++
6102++ MTK_VENDOR_ATTR_AMNT_CTRL_SET,
6103++ MTK_VENDOR_ATTR_AMNT_CTRL_DUMP,
6104++
6105++ /* keep last */
6106++ NUM_MTK_VENDOR_ATTRS_AMNT_CTRL,
6107++ MTK_VENDOR_ATTR_AMNT_CTRL_MAX =
6108++ NUM_MTK_VENDOR_ATTRS_AMNT_CTRL - 1
6109++};
6110++
6111++enum mtk_vendor_attr_mnt_set {
6112++ MTK_VENDOR_ATTR_AMNT_SET_UNSPEC,
6113++
6114++ MTK_VENDOR_ATTR_AMNT_SET_INDEX,
6115++ MTK_VENDOR_ATTR_AMNT_SET_MACADDR,
6116++
6117++ /* keep last */
6118++ NUM_MTK_VENDOR_ATTRS_AMNT_SET,
6119++ MTK_VENDOR_ATTR_AMNT_SET_MAX =
6120++ NUM_MTK_VENDOR_ATTRS_AMNT_SET - 1
6121++};
6122++
6123++enum mtk_vendor_attr_mnt_dump {
6124++ MTK_VENDOR_ATTR_AMNT_DUMP_UNSPEC,
6125++
6126++ MTK_VENDOR_ATTR_AMNT_DUMP_INDEX,
6127++ MTK_VENDOR_ATTR_AMNT_DUMP_LEN,
6128++ MTK_VENDOR_ATTR_AMNT_DUMP_RESULT,
6129++
6130++ /* keep last */
6131++ NUM_MTK_VENDOR_ATTRS_AMNT_DUMP,
6132++ MTK_VENDOR_ATTR_AMNT_DUMP_MAX =
6133++ NUM_MTK_VENDOR_ATTRS_AMNT_DUMP - 1
6134++};
6135++
6136+ #endif
6137+--
6138+2.25.1
6139+