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developer8eb72a32023-03-30 08:32:07 +08001From d8f7b7ae8934a0107bf9f36c2c5199a767febad6 Mon Sep 17 00:00:00 2001
developerabdbf252023-02-06 16:02:21 +08002From: Bo Jiao <Bo.Jiao@mediatek.com>
developer483388c2023-03-08 13:52:15 +08003Date: Mon, 6 Feb 2023 11:34:51 +0800
developer1bc2ce22023-03-25 00:47:41 +08004Subject: [PATCH 14/29] wifi: mt76: mt7996: add 802.11s mesh amsdu/de-amsdu
developerabdbf252023-02-06 16:02:21 +08005 support
6
7Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
8---
9 mt7996/mac.c | 15 ++++++++++++++-
10 mt7996/mac.h | 2 ++
11 mt7996/mcu.c | 9 ++++++++-
12 mt7996/mcu.h | 2 +-
13 mt7996/mmio.c | 3 ++-
14 5 files changed, 27 insertions(+), 4 deletions(-)
developerabdbf252023-02-06 16:02:21 +080015
16diff --git a/mt7996/mac.c b/mt7996/mac.c
developer8eb72a32023-03-30 08:32:07 +080017index 40ef5e4..8dc3a62 100644
developerabdbf252023-02-06 16:02:21 +080018--- a/mt7996/mac.c
19+++ b/mt7996/mac.c
developer483388c2023-03-08 13:52:15 +080020@@ -633,6 +633,7 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb)
developerabdbf252023-02-06 16:02:21 +080021 u32 rxd4 = le32_to_cpu(rxd[4]);
22 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
23 u32 csum_status = *(u32 *)skb->cb;
24+ u32 mesh_mask = MT_RXD0_MESH | MT_RXD0_MHCP;
25 bool unicast, insert_ccmp_hdr = false;
26 u8 remove_pad, amsdu_info, band_idx;
27 u8 mode = 0, qos_ctl = 0;
developer483388c2023-03-08 13:52:15 +080028@@ -825,6 +826,9 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb)
developerabdbf252023-02-06 16:02:21 +080029
30 skb_pull(skb, hdr_gap);
31 if (!hdr_trans && status->amsdu) {
32+ if(ieee80211_has_a4(fc) && ((rxd0 & mesh_mask) == mesh_mask))
33+ pad_start = 0;
34+ else
35 pad_start = ieee80211_get_hdrlen_from_skb(skb);
36 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) {
37 /* When header translation failure is indicated,
developer483388c2023-03-08 13:52:15 +080038@@ -857,8 +861,17 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb)
developerabdbf252023-02-06 16:02:21 +080039 hdr = mt76_skb_get_hdr(skb);
40 fc = hdr->frame_control;
41 if (ieee80211_is_data_qos(fc)) {
42+ u8 *p = ieee80211_get_qos_ctl(hdr);
43+
44 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
45- qos_ctl = *ieee80211_get_qos_ctl(hdr);
46+ qos_ctl = *p;
47+
48+ /* the hardware support mesh de-amsdu by default,
49+ * so, clear amsdu present bit in the Qos Control field.
50+ */
51+ if (ieee80211_has_a4(fc) && status->amsdu &&
52+ ((rxd0 & mesh_mask) == mesh_mask))
53+ *p &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
54 }
55 } else {
56 status->flag |= RX_FLAG_8023;
57diff --git a/mt7996/mac.h b/mt7996/mac.h
developer8eb72a32023-03-30 08:32:07 +080058index 4914d3e..e48cc68 100644
developerabdbf252023-02-06 16:02:21 +080059--- a/mt7996/mac.h
60+++ b/mt7996/mac.h
61@@ -12,6 +12,8 @@
62 #define MT_RXD0_LENGTH GENMASK(15, 0)
63 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
64
65+#define MT_RXD0_MESH BIT(18)
66+#define MT_RXD0_MHCP BIT(19)
67 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
68 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
69 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
70diff --git a/mt7996/mcu.c b/mt7996/mcu.c
developer8eb72a32023-03-30 08:32:07 +080071index b332658..0dbe2e0 100644
developerabdbf252023-02-06 16:02:21 +080072--- a/mt7996/mcu.c
73+++ b/mt7996/mcu.c
developer483388c2023-03-08 13:52:15 +080074@@ -1054,7 +1054,8 @@ mt7996_mcu_sta_amsdu_tlv(struct mt7996_dev *dev, struct sk_buff *skb,
developerabdbf252023-02-06 16:02:21 +080075 struct tlv *tlv;
76
77 if (vif->type != NL80211_IFTYPE_STATION &&
78- vif->type != NL80211_IFTYPE_AP)
79+ vif->type != NL80211_IFTYPE_AP &&
80+ vif->type != NL80211_IFTYPE_MESH_POINT)
81 return;
82
83 if (!sta->deflink.agg.max_amsdu_len)
developer483388c2023-03-08 13:52:15 +080084@@ -1560,6 +1561,12 @@ mt7996_mcu_sta_hdr_trans_tlv(struct mt7996_dev *dev, struct sk_buff *skb,
developerabdbf252023-02-06 16:02:21 +080085 hdr_trans->to_ds = true;
86 hdr_trans->from_ds = true;
87 }
88+
89+ if (vif->type == NL80211_IFTYPE_MESH_POINT) {
90+ hdr_trans->to_ds = true;
91+ hdr_trans->from_ds = true;
92+ hdr_trans->mesh = true;
93+ }
94 }
95
96 static enum mcu_mmps_mode
97diff --git a/mt7996/mcu.h b/mt7996/mcu.h
developer8eb72a32023-03-30 08:32:07 +080098index 7fefc28..ad66a1f 100644
developerabdbf252023-02-06 16:02:21 +080099--- a/mt7996/mcu.h
100+++ b/mt7996/mcu.h
developer483388c2023-03-08 13:52:15 +0800101@@ -434,7 +434,7 @@ struct sta_rec_hdr_trans {
developerabdbf252023-02-06 16:02:21 +0800102 u8 from_ds;
103 u8 to_ds;
104 u8 dis_rx_hdr_tran;
105- u8 rsv;
106+ u8 mesh;
107 } __packed;
108
109 struct hdr_trans_en {
110diff --git a/mt7996/mmio.c b/mt7996/mmio.c
developer8eb72a32023-03-30 08:32:07 +0800111index 902370a..6610cc4 100644
developerabdbf252023-02-06 16:02:21 +0800112--- a/mt7996/mmio.c
113+++ b/mt7996/mmio.c
114@@ -320,7 +320,8 @@ struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
115 /* txwi_size = txd size + txp size */
developer483388c2023-03-08 13:52:15 +0800116 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
developerabdbf252023-02-06 16:02:21 +0800117 .drv_flags = MT_DRV_TXWI_NO_FREE |
118- MT_DRV_HW_MGMT_TXQ,
119+ MT_DRV_HW_MGMT_TXQ |
120+ MT_DRV_AMSDU_OFFLOAD,
121 .survey_flags = SURVEY_INFO_TIME_TX |
122 SURVEY_INFO_TIME_RX |
123 SURVEY_INFO_TIME_BSS_RX,
124--
developer8eb72a32023-03-30 08:32:07 +08001252.18.0
developerabdbf252023-02-06 16:02:21 +0800126