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developer20747c12022-09-16 14:09:40 +08001From a46e93efedae595b85fec8295e16641c2de183fb Mon Sep 17 00:00:00 2001
developer8cb3ac72022-07-04 10:55:14 +08002From: Sujuan Chen <sujuan.chen@mediatek.com>
3Date: Sun, 12 Jun 2022 16:38:45 +0800
developer20747c12022-09-16 14:09:40 +08004Subject: [PATCH 3001/3007] mt76 add wed tx support
developer8cb3ac72022-07-04 10:55:14 +08005
6Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
7---
developerbbca0f92022-07-26 17:26:12 +08008 mt76_connac.h | 1 +
9 mt7915/dma.c | 59 +++++++++++++++++++-------
developer8d18bff2022-09-26 17:39:49 +080010 mt7915/mac.c | 11 +++--
developerbbca0f92022-07-26 17:26:12 +080011 mt7915/main.c | 9 +++-
12 mt7915/mcu.c | 2 +-
13 mt7915/mmio.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++-
14 mt7915/mt7915.h | 2 +
developer20747c12022-09-16 14:09:40 +080015 mt7915/pci.c | 93 +---------------------------------------
developerbbca0f92022-07-26 17:26:12 +080016 mt7915/regs.h | 15 +++++++
17 mt7915/soc.c | 16 +++++--
developer20747c12022-09-16 14:09:40 +080018 10 files changed, 193 insertions(+), 118 deletions(-)
developer8cb3ac72022-07-04 10:55:14 +080019
20diff --git a/mt76_connac.h b/mt76_connac.h
developer20747c12022-09-16 14:09:40 +080021index 0915eb57..9a468878 100644
developer8cb3ac72022-07-04 10:55:14 +080022--- a/mt76_connac.h
23+++ b/mt76_connac.h
developer1d9fede2022-08-29 15:24:07 +080024@@ -116,6 +116,7 @@ struct mt76_connac_sta_key_conf {
developer8cb3ac72022-07-04 10:55:14 +080025 };
26
27 #define MT_TXP_MAX_BUF_NUM 6
28+#define MT_TXD_TXP_BUF_SIZE 128
29
30 struct mt76_connac_fw_txp {
31 __le16 flags;
32diff --git a/mt7915/dma.c b/mt7915/dma.c
developer20747c12022-09-16 14:09:40 +080033index 4b594a53..ac30698f 100644
developer8cb3ac72022-07-04 10:55:14 +080034--- a/mt7915/dma.c
35+++ b/mt7915/dma.c
developer1d9fede2022-08-29 15:24:07 +080036@@ -11,7 +11,10 @@ mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base
37 struct mt7915_dev *dev = phy->dev;
developer8cb3ac72022-07-04 10:55:14 +080038
39 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) {
40- ring_base = MT_WED_TX_RING_BASE;
41+ if(!is_mt7986(&dev->mt76))
42+ ring_base = MT_WED_TX_RING_BASE;
43+ else
44+ ring_base += MT_TXQ_ID(0) * MT_RING_SIZE;
45 idx -= MT_TXQ_ID(0);
46 }
47
developer1d9fede2022-08-29 15:24:07 +080048@@ -58,14 +61,23 @@ static void mt7915_dma_config(struct mt7915_dev *dev)
developer8cb3ac72022-07-04 10:55:14 +080049 MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA);
50 MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
51 } else {
52- RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0);
53+ if(is_mt7916(&dev->mt76) && (mtk_wed_device_active(&dev->mt76.mmio.wed))) {
54+ RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_WED_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0);
55+ RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916, MT7916_RXQ_MCU_WA);
developer1d9fede2022-08-29 15:24:07 +080056+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1);
developer8cb3ac72022-07-04 10:55:14 +080057+ RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN);
58+ TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0, MT7915_TXQ_BAND0);
59+ TXQ_CONFIG(1, WFDMA0, MT_INT_WED_TX_DONE_BAND1, MT7915_TXQ_BAND1);
60+ } else {
61+ RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0);
62+ RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA);
developer1d9fede2022-08-29 15:24:07 +080063+ RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1);
developer8cb3ac72022-07-04 10:55:14 +080064+ RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN);
65+ TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
66+ TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
67+ }
68 RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM);
69- RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA);
developer1d9fede2022-08-29 15:24:07 +080070- RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1);
71 RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT);
developer8cb3ac72022-07-04 10:55:14 +080072- RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN);
73- TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
74- TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
75 MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
76 MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA);
77 MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
developer1d9fede2022-08-29 15:24:07 +080078@@ -323,7 +335,9 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
developer8cb3ac72022-07-04 10:55:14 +080079 u32 wed_irq_mask = irq_mask;
80
81 wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
82- mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
83+ if (!is_mt7986(&dev->mt76))
84+ mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
85+ mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
86 mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
87 }
88
developer1d9fede2022-08-29 15:24:07 +080089@@ -348,15 +362,19 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +080090
91 mt7915_dma_disable(dev, true);
92
93- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
94+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) && !is_mt7986(mdev)) {
95 mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
96-
97+ if(is_mt7915(mdev)) {
98 mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
99 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
100 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
101 FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
102- } else {
103- mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
104+ } else {
105+ mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
106+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
107+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
108+ FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 2));
109+ }
110 }
111
112 /* init tx queue */
developer1d9fede2022-08-29 15:24:07 +0800113@@ -410,7 +428,7 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800114 return ret;
115
116 /* event from WA */
117- if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
118+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(mdev)) {
119 wa_rx_base = MT_WED_RX_RING_BASE;
120 wa_rx_idx = MT7915_RXQ_MCU_WA;
121 dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE;
developer1d9fede2022-08-29 15:24:07 +0800122@@ -437,11 +455,20 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
developer8cb3ac72022-07-04 10:55:14 +0800123
124 /* tx free notify event from WA for band0 */
125 if (!is_mt7915(mdev)) {
126+ wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA);
127+ wa_rx_idx = MT_RXQ_ID(MT_RXQ_MAIN_WA);
128+
129+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
130+ dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE;
131+ if (is_mt7916(mdev)) {
132+ wa_rx_base = MT_WED_RX_RING_BASE;
133+ wa_rx_idx = MT7915_RXQ_MCU_WA;
134+ }
135+ }
136 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
137- MT_RXQ_ID(MT_RXQ_MAIN_WA),
138+ wa_rx_idx,
139 MT7915_RX_MCU_RING_SIZE,
140- MT_RX_BUF_SIZE,
141- MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
142+ MT_RX_BUF_SIZE, wa_rx_base);
143 if (ret)
144 return ret;
145 }
146diff --git a/mt7915/mac.c b/mt7915/mac.c
developer20747c12022-09-16 14:09:40 +0800147index 0631ad2c..b1788fb8 100644
developer8cb3ac72022-07-04 10:55:14 +0800148--- a/mt7915/mac.c
149+++ b/mt7915/mac.c
developer1d9fede2022-08-29 15:24:07 +0800150@@ -826,9 +826,9 @@ u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id)
developer8cb3ac72022-07-04 10:55:14 +0800151
152 txp->token = cpu_to_le16(token_id);
153 txp->nbuf = 1;
154- txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp));
155+ txp->buf[0] = cpu_to_le32(phys + MT_TXD_TXP_BUF_SIZE);
156
157- return MT_TXD_SIZE + sizeof(*txp);
158+ return MT_TXD_TXP_BUF_SIZE;
159 }
160
161 static void
developer8d18bff2022-09-26 17:39:49 +0800162@@ -944,6 +944,7 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
163 LIST_HEAD(free_list);
164 void *end = data + len;
165 bool v3, wake = false;
166+ bool with_txwi = true;
167 u16 total, count = 0;
168 u32 txd = le32_to_cpu(free->txd);
169 __le32 *cur_info;
170@@ -997,12 +998,14 @@ mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len)
171 txwi = mt76_token_release(mdev, msdu, &wake);
172 if (!txwi)
173 continue;
174+ else
175+ with_txwi = false;
176
177 mt7915_txwi_free(dev, txwi, sta, &free_list);
178 }
179 }
180-
181- mt7915_mac_tx_free_done(dev, &free_list, wake);
182+ if (!with_txwi)
183+ mt7915_mac_tx_free_done(dev, &free_list, wake);
184 }
185
186 static void
developer8cb3ac72022-07-04 10:55:14 +0800187diff --git a/mt7915/main.c b/mt7915/main.c
developer20747c12022-09-16 14:09:40 +0800188index 192b0a9b..3a09f3f5 100644
developer8cb3ac72022-07-04 10:55:14 +0800189--- a/mt7915/main.c
190+++ b/mt7915/main.c
developer20747c12022-09-16 14:09:40 +0800191@@ -1456,14 +1456,19 @@ mt7915_net_fill_forward_path(struct ieee80211_hw *hw,
developer8cb3ac72022-07-04 10:55:14 +0800192 if (!mtk_wed_device_active(wed))
193 return -ENODEV;
194
195- if (msta->wcid.idx > 0xff)
196+ if (msta->wcid.idx > MT7915_WTBL_STA)
197 return -EIO;
198
199 path->type = DEV_PATH_MTK_WDMA;
200 path->dev = ctx->dev;
201 path->mtk_wdma.wdma_idx = wed->wdma_idx;
202 path->mtk_wdma.bss = mvif->mt76.idx;
203- path->mtk_wdma.wcid = msta->wcid.idx;
204+ /* fw will find the wcid by dest addr */
205+ if(is_mt7915(&dev->mt76))
206+ path->mtk_wdma.wcid = 0xff;
207+ else
208+ path->mtk_wdma.wcid = 0x3ff;
209+
210 path->mtk_wdma.queue = phy != &dev->phy;
211
212 ctx->dev = NULL;
213diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer20747c12022-09-16 14:09:40 +0800214index 8d74275d..f5caa326 100644
developer8cb3ac72022-07-04 10:55:14 +0800215--- a/mt7915/mcu.c
216+++ b/mt7915/mcu.c
developer20747c12022-09-16 14:09:40 +0800217@@ -2379,7 +2379,7 @@ int mt7915_run_firmware(struct mt7915_dev *dev)
developer8cb3ac72022-07-04 10:55:14 +0800218 if (ret)
219 return ret;
220
221- if (mtk_wed_device_active(&dev->mt76.mmio.wed))
222+ if (mtk_wed_device_active(&dev->mt76.mmio.wed) && is_mt7915(&dev->mt76))
223 mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), 0, 0, 0);
224
225 ret = mt7915_mcu_set_mwds(dev, 1);
226diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developer20747c12022-09-16 14:09:40 +0800227index 088c9f3e..11c90772 100644
developer8cb3ac72022-07-04 10:55:14 +0800228--- a/mt7915/mmio.c
229+++ b/mt7915/mmio.c
230@@ -10,6 +10,9 @@
231 #include "mac.h"
232 #include "../trace.h"
233
234+static bool wed_enable = true;
235+module_param(wed_enable, bool, 0644);
236+
237 static const u32 mt7915_reg[] = {
238 [INT_SOURCE_CSR] = 0xd7010,
239 [INT_MASK_CSR] = 0xd7014,
developer20747c12022-09-16 14:09:40 +0800240@@ -543,7 +546,11 @@ void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
developer8cb3ac72022-07-04 10:55:14 +0800241 mdev->mmio.irqmask |= set;
242
243 if (write_reg) {
244- mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
245+ if (mtk_wed_device_active(&mdev->mmio.wed))
246+ mtk_wed_device_irq_set_mask(&mdev->mmio.wed,
247+ mdev->mmio.irqmask);
248+ else
249+ mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
250 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
251 }
252
developer20747c12022-09-16 14:09:40 +0800253@@ -567,6 +574,8 @@ static void mt7915_irq_tasklet(struct tasklet_struct *t)
developer8cb3ac72022-07-04 10:55:14 +0800254
255 if (mtk_wed_device_active(wed)) {
256 mtk_wed_device_irq_set_mask(wed, 0);
257+ if (dev->hif2)
258+ mt76_wr(dev, MT_INT1_MASK_CSR, 0);
259 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
260 } else {
261 mt76_wr(dev, MT_INT_MASK_CSR, 0);
developer20747c12022-09-16 14:09:40 +0800262@@ -648,6 +657,105 @@ irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
developer8cb3ac72022-07-04 10:55:14 +0800263 return IRQ_HANDLED;
264 }
265
266+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
267+static int mt7915_wed_offload_enable(struct mtk_wed_device *wed)
268+{
269+ struct mt7915_dev *dev;
270+ int ret;
271+
272+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
273+
274+ spin_lock_bh(&dev->mt76.token_lock);
275+ dev->mt76.token_size = wed->wlan.token_start;
276+ spin_unlock_bh(&dev->mt76.token_lock);
277+
278+ ret = wait_event_timeout(dev->mt76.tx_wait,
279+ !dev->mt76.wed_token_count, HZ);
280+ if (!ret)
281+ return -EAGAIN;
282+
283+ return 0;
284+}
285+
286+static void mt7915_wed_offload_disable(struct mtk_wed_device *wed)
287+{
288+ struct mt7915_dev *dev;
289+
290+ dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
291+
292+ spin_lock_bh(&dev->mt76.token_lock);
293+ dev->mt76.token_size = wed->wlan.token_start;//MT7915_TOKEN_SIZE;
294+ spin_unlock_bh(&dev->mt76.token_lock);
295+}
296+#endif
297+
298+int
299+mt7915_pci_wed_init(struct mt7915_dev *dev, struct device *pdev, int *irq)
300+{
301+#ifdef CONFIG_NET_MEDIATEK_SOC_WED
302+ struct mt76_dev *mdev = &dev->mt76;
303+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
304+ u32 base;
305+ int ret;
306+
307+ if (!wed_enable)
308+ return 0;
309+
310+ if (dev_is_pci(pdev)) {
311+ struct pci_dev *pci_dev;
312+
313+ pci_dev = container_of(pdev, struct pci_dev, dev);
314+ base = pci_resource_start(pci_dev, 0);
315+ wed->wlan.base = (void __iomem *)ioremap(base, pci_resource_len(pci_dev, 0));
316+
317+ wed->wlan.pci_dev = pci_dev;
318+ wed->wlan.bus_type = MTK_BUS_TYPE_PCIE;
319+ wed->wlan.wpdma_int = base + MT_INT_WED_SOURCE_CSR;
320+ wed->wlan.wpdma_mask = base + MT_INT_WED_MASK_CSR;
321+ } else {
322+ struct platform_device *plat_dev;
323+ struct resource *res;
324+
325+ plat_dev = to_platform_device(pdev);
326+ res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
327+ base = res->start;
328+ wed->wlan.base = (void __iomem *)ioremap(base, resource_size(res));
329+ wed->wlan.bus_type = MTK_BUS_TYPE_AXI;
330+ wed->wlan.wpdma_int = base + MT_INT_SOURCE_CSR;
331+ wed->wlan.wpdma_mask = base + MT_INT_MASK_CSR;
332+ }
333+ wed->wlan.wpdma_tx = base + MT_TXQ_WED_RING_BASE;
334+ wed->wlan.wpdma_txfree = base + MT_RXQ_WED_RING_BASE;
335+
336+ wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
337+ wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
338+ wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
339+ wed->wlan.nbuf = 7168;
340+ wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
341+ wed->wlan.init_buf = mt7915_wed_init_buf;
342+ /* disable dynamic tx token */
343+ wed->wlan.offload_enable = mt7915_wed_offload_enable;
344+ wed->wlan.offload_disable = mt7915_wed_offload_disable;
345+
346+ if (mtk_wed_device_attach(wed) != 0)
347+ return 0;
348+
349+ if (wed->ver == MTK_WED_V1)
350+ wed->wlan.wpdma_phys = base + MT_WFDMA_EXT_CSR_BASE;
351+
352+ *irq = wed->irq;
353+ dev->mt76.dma_dev = wed->dev;
354+ mdev->token_size = wed->wlan.token_start;
355+ ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
356+ if (ret)
357+ return ret;
358+
359+ return 1;
360+#else
361+ return 0;
362+#endif
363+}
364+
365 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
366 void __iomem *mem_base, u32 device_id)
367 {
368diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer20747c12022-09-16 14:09:40 +0800369index 3fcedba5..1c78b882 100644
developer8cb3ac72022-07-04 10:55:14 +0800370--- a/mt7915/mt7915.h
371+++ b/mt7915/mt7915.h
developer20747c12022-09-16 14:09:40 +0800372@@ -534,6 +534,8 @@ static inline void mt7986_wmac_disable(struct mt7915_dev *dev)
developer8cb3ac72022-07-04 10:55:14 +0800373 {
374 }
375 #endif
376+int mt7915_pci_wed_init(struct mt7915_dev *dev,
377+ struct device *pdev, int *irq);
378 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
379 void __iomem *mem_base, u32 device_id);
380 void mt7915_wfsys_reset(struct mt7915_dev *dev);
381diff --git a/mt7915/pci.c b/mt7915/pci.c
developer20747c12022-09-16 14:09:40 +0800382index 728a879c..c5da01a9 100644
developer8cb3ac72022-07-04 10:55:14 +0800383--- a/mt7915/pci.c
384+++ b/mt7915/pci.c
385@@ -12,9 +12,6 @@
386 #include "mac.h"
387 #include "../trace.h"
388
389-static bool wed_enable = false;
390-module_param(wed_enable, bool, 0644);
391-
392 static LIST_HEAD(hif_list);
393 static DEFINE_SPINLOCK(hif_lock);
394 static u32 hif_idx;
developer20747c12022-09-16 14:09:40 +0800395@@ -95,94 +92,6 @@ static int mt7915_pci_hif2_probe(struct pci_dev *pdev)
developer8cb3ac72022-07-04 10:55:14 +0800396 return 0;
397 }
398
399-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
400-static int mt7915_wed_offload_enable(struct mtk_wed_device *wed)
401-{
402- struct mt7915_dev *dev;
developer20747c12022-09-16 14:09:40 +0800403- struct mt7915_phy *phy;
developer8cb3ac72022-07-04 10:55:14 +0800404- int ret;
405-
406- dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
407-
408- spin_lock_bh(&dev->mt76.token_lock);
409- dev->mt76.token_size = wed->wlan.token_start;
410- spin_unlock_bh(&dev->mt76.token_lock);
411-
412- ret = wait_event_timeout(dev->mt76.tx_wait,
413- !dev->mt76.wed_token_count, HZ);
414- if (!ret)
415- return -EAGAIN;
416-
developer20747c12022-09-16 14:09:40 +0800417- phy = &dev->phy;
418- mt76_set(dev, MT_AGG_ACR4(phy->band_idx), MT_AGG_ACR_PPDU_TXS2H);
419-
420- phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL;
421- if (phy)
422- mt76_set(dev, MT_AGG_ACR4(phy->band_idx),
423- MT_AGG_ACR_PPDU_TXS2H);
424-
developer8cb3ac72022-07-04 10:55:14 +0800425- return 0;
426-}
427-
428-static void mt7915_wed_offload_disable(struct mtk_wed_device *wed)
429-{
430- struct mt7915_dev *dev;
developer20747c12022-09-16 14:09:40 +0800431- struct mt7915_phy *phy;
developer8cb3ac72022-07-04 10:55:14 +0800432-
433- dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed);
434-
435- spin_lock_bh(&dev->mt76.token_lock);
436- dev->mt76.token_size = MT7915_TOKEN_SIZE;
437- spin_unlock_bh(&dev->mt76.token_lock);
developer20747c12022-09-16 14:09:40 +0800438-
439- /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
440- * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
441- */
442- phy = &dev->phy;
443- mt76_clear(dev, MT_AGG_ACR4(phy->band_idx), MT_AGG_ACR_PPDU_TXS2H);
444-
445- phy = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL;
446- if (phy)
447- mt76_clear(dev, MT_AGG_ACR4(phy->band_idx),
448- MT_AGG_ACR_PPDU_TXS2H);
developer8cb3ac72022-07-04 10:55:14 +0800449-}
450-#endif
451-
452-static int
453-mt7915_pci_wed_init(struct mt7915_dev *dev, struct pci_dev *pdev, int *irq)
454-{
455-#ifdef CONFIG_NET_MEDIATEK_SOC_WED
456- struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
457- int ret;
458-
459- if (!wed_enable)
460- return 0;
461-
462- wed->wlan.pci_dev = pdev;
463- wed->wlan.wpdma_phys = pci_resource_start(pdev, 0) +
464- MT_WFDMA_EXT_CSR_BASE;
465- wed->wlan.nbuf = 4096;
466- wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
467- wed->wlan.init_buf = mt7915_wed_init_buf;
468- wed->wlan.offload_enable = mt7915_wed_offload_enable;
469- wed->wlan.offload_disable = mt7915_wed_offload_disable;
470-
471- if (mtk_wed_device_attach(wed) != 0)
472- return 0;
473-
474- *irq = wed->irq;
475- dev->mt76.dma_dev = wed->dev;
476-
477- ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32));
478- if (ret)
479- return ret;
480-
481- return 1;
482-#else
483- return 0;
484-#endif
485-}
486-
487 static int mt7915_pci_probe(struct pci_dev *pdev,
488 const struct pci_device_id *id)
489 {
developer20747c12022-09-16 14:09:40 +0800490@@ -220,7 +129,7 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
developer8cb3ac72022-07-04 10:55:14 +0800491 mt7915_wfsys_reset(dev);
492 hif2 = mt7915_pci_init_hif2(pdev);
493
494- ret = mt7915_pci_wed_init(dev, pdev, &irq);
495+ ret = mt7915_pci_wed_init(dev, &pdev->dev, &irq);
496 if (ret < 0)
497 goto free_wed_or_irq_vector;
498
499diff --git a/mt7915/regs.h b/mt7915/regs.h
developer20747c12022-09-16 14:09:40 +0800500index d7f71033..51eb553c 100644
developer8cb3ac72022-07-04 10:55:14 +0800501--- a/mt7915/regs.h
502+++ b/mt7915/regs.h
developer20747c12022-09-16 14:09:40 +0800503@@ -621,6 +621,7 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +0800504 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
505 #define MT_PCIE_RECOG_ID_SEM BIT(31)
506
507+#define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200)
508 #define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204)
509
510 #define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300)
developer20747c12022-09-16 14:09:40 +0800511@@ -667,6 +668,13 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +0800512 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
513 MT_TXQ_ID(q)* 0x4)
514
515+#define MT_TXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7300 : 0x24420)
516+#define MT_RXQ_WED_RING_BASE (!is_mt7986(mdev)? 0xd7410 : 0x24520)
517+
518+#define MT_WED_TX_DONE_BAND0 (is_mt7915(mdev)? 4 : 30)
519+#define MT_WED_TX_DONE_BAND1 (is_mt7915(mdev)? 5 : 31)
520+#define MT_WED_TX_FREE_DONE (is_mt7915(mdev)? 1 : 2)
521+
522 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
523 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
524
developer20747c12022-09-16 14:09:40 +0800525@@ -685,6 +693,11 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +0800526 #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2)
527 #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3)
528
529+#define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18)
530+#define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19)
531+#define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1)
532+#define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17)
533+
534 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)])
535 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)])
536
developer20747c12022-09-16 14:09:40 +0800537@@ -708,6 +721,8 @@ enum offs_rev {
developer8cb3ac72022-07-04 10:55:14 +0800538 #define MT_INT_TX_DONE_BAND0 BIT(30)
539 #define MT_INT_TX_DONE_BAND1 BIT(31)
540 #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25)
541+#define MT_INT_WED_TX_DONE_BAND0 BIT(4)
542+#define MT_INT_WED_TX_DONE_BAND1 BIT(5)
543
544 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \
545 MT_INT_TX_MCU(MT_MCUQ_WM) | \
546diff --git a/mt7915/soc.c b/mt7915/soc.c
developer20747c12022-09-16 14:09:40 +0800547index 3618718d..8d0b2068 100644
developer8cb3ac72022-07-04 10:55:14 +0800548--- a/mt7915/soc.c
549+++ b/mt7915/soc.c
550@@ -1171,10 +1171,6 @@ static int mt7986_wmac_probe(struct platform_device *pdev)
551
552 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
553
554- irq = platform_get_irq(pdev, 0);
555- if (irq < 0)
556- return irq;
557-
558 mem_base = devm_platform_ioremap_resource(pdev, 0);
559 if (IS_ERR(mem_base)) {
560 dev_err(&pdev->dev, "Failed to get memory resource\n");
561@@ -1186,6 +1182,16 @@ static int mt7986_wmac_probe(struct platform_device *pdev)
562 return PTR_ERR(dev);
563
564 mdev = &dev->mt76;
565+ ret = mt7915_pci_wed_init(dev, &pdev->dev, &irq);
566+ if (ret < 0)
567+ goto free_device;
568+
569+ if (!ret) {
570+ irq = platform_get_irq(pdev, 0);
571+ if (irq < 0)
572+ return irq;;
573+ }
574+
575 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
576 IRQF_SHARED, KBUILD_MODNAME, dev);
577 if (ret)
578@@ -1207,6 +1213,8 @@ free_irq:
579 devm_free_irq(mdev->dev, irq, dev);
580
581 free_device:
582+ if (mtk_wed_device_active(&mdev->mmio.wed))
583+ mtk_wed_device_detach(&mdev->mmio.wed);
584 mt76_free_device(&dev->mt76);
585
586 return ret;
587--
developer20747c12022-09-16 14:09:40 +08005882.25.1
developer8cb3ac72022-07-04 10:55:14 +0800589